4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
19 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
20 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
21 - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
23 Copyright (C) 2013-2015 by the following authors:
24 - Rob Clark <robdclark@gmail.com> (robclark)
25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
27 Permission is hereby granted, free of charge, to any person obtaining
28 a copy of this software and associated documentation files (the
29 "Software"), to deal in the Software without restriction, including
30 without limitation the rights to use, copy, modify, merge, publish,
31 distribute, sublicense, and/or sell copies of the Software, and to
32 permit persons to whom the Software is furnished to do so, subject to
33 the following conditions:
35 The above copyright notice and this permission notice (including the
36 next paragraph) shall be included in all copies or substantial
37 portions of the Software.
39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
90 PACK_3D_FRAME_INT = 0,
91 PACK_3D_H_ROW_INT = 1,
92 PACK_3D_V_ROW_INT = 2,
96 enum mdp5_scale_filter {
97 SCALE_FILTER_NEAREST = 0,
99 SCALE_FILTER_PCMN = 2,
109 enum mdp5_cursor_format {
110 CURSOR_FMT_ARGB8888 = 0,
111 CURSOR_FMT_ARGB1555 = 2,
112 CURSOR_FMT_ARGB4444 = 4,
115 enum mdp5_cursor_alpha {
116 CURSOR_ALPHA_CONST = 0,
117 CURSOR_ALPHA_PER_PIXEL = 2,
127 enum mdp5_data_format {
132 enum mdp5_block_size {
137 enum mdp5_rotate_mode {
142 enum mdp5_chroma_downsample_method {
143 DS_MTHD_NO_PIXEL_DROP = 0,
144 DS_MTHD_PIXEL_DROP = 1,
147 #define MDP5_IRQ_WB_0_DONE 0x00000001
148 #define MDP5_IRQ_WB_1_DONE 0x00000002
149 #define MDP5_IRQ_WB_2_DONE 0x00000010
150 #define MDP5_IRQ_PING_PONG_0_DONE 0x00000100
151 #define MDP5_IRQ_PING_PONG_1_DONE 0x00000200
152 #define MDP5_IRQ_PING_PONG_2_DONE 0x00000400
153 #define MDP5_IRQ_PING_PONG_3_DONE 0x00000800
154 #define MDP5_IRQ_PING_PONG_0_RD_PTR 0x00001000
155 #define MDP5_IRQ_PING_PONG_1_RD_PTR 0x00002000
156 #define MDP5_IRQ_PING_PONG_2_RD_PTR 0x00004000
157 #define MDP5_IRQ_PING_PONG_3_RD_PTR 0x00008000
158 #define MDP5_IRQ_PING_PONG_0_WR_PTR 0x00010000
159 #define MDP5_IRQ_PING_PONG_1_WR_PTR 0x00020000
160 #define MDP5_IRQ_PING_PONG_2_WR_PTR 0x00040000
161 #define MDP5_IRQ_PING_PONG_3_WR_PTR 0x00080000
162 #define MDP5_IRQ_PING_PONG_0_AUTO_REF 0x00100000
163 #define MDP5_IRQ_PING_PONG_1_AUTO_REF 0x00200000
164 #define MDP5_IRQ_PING_PONG_2_AUTO_REF 0x00400000
165 #define MDP5_IRQ_PING_PONG_3_AUTO_REF 0x00800000
166 #define MDP5_IRQ_INTF0_UNDER_RUN 0x01000000
167 #define MDP5_IRQ_INTF0_VSYNC 0x02000000
168 #define MDP5_IRQ_INTF1_UNDER_RUN 0x04000000
169 #define MDP5_IRQ_INTF1_VSYNC 0x08000000
170 #define MDP5_IRQ_INTF2_UNDER_RUN 0x10000000
171 #define MDP5_IRQ_INTF2_VSYNC 0x20000000
172 #define MDP5_IRQ_INTF3_UNDER_RUN 0x40000000
173 #define MDP5_IRQ_INTF3_VSYNC 0x80000000
174 #define REG_MDSS_HW_VERSION 0x00000000
175 #define MDSS_HW_VERSION_STEP__MASK 0x0000ffff
176 #define MDSS_HW_VERSION_STEP__SHIFT 0
177 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val)
179 return ((val) << MDSS_HW_VERSION_STEP__SHIFT) & MDSS_HW_VERSION_STEP__MASK;
181 #define MDSS_HW_VERSION_MINOR__MASK 0x0fff0000
182 #define MDSS_HW_VERSION_MINOR__SHIFT 16
183 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val)
185 return ((val) << MDSS_HW_VERSION_MINOR__SHIFT) & MDSS_HW_VERSION_MINOR__MASK;
187 #define MDSS_HW_VERSION_MAJOR__MASK 0xf0000000
188 #define MDSS_HW_VERSION_MAJOR__SHIFT 28
189 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val)
191 return ((val) << MDSS_HW_VERSION_MAJOR__SHIFT) & MDSS_HW_VERSION_MAJOR__MASK;
194 #define REG_MDSS_HW_INTR_STATUS 0x00000010
195 #define MDSS_HW_INTR_STATUS_INTR_MDP 0x00000001
196 #define MDSS_HW_INTR_STATUS_INTR_DSI0 0x00000010
197 #define MDSS_HW_INTR_STATUS_INTR_DSI1 0x00000020
198 #define MDSS_HW_INTR_STATUS_INTR_HDMI 0x00000100
199 #define MDSS_HW_INTR_STATUS_INTR_EDP 0x00001000
201 static inline uint32_t __offset_MDP(uint32_t idx)
204 case 0: return (mdp5_cfg->mdp.base[0]);
205 default: return INVALID_IDX(idx);
208 static inline uint32_t REG_MDP5_MDP(uint32_t i0) { return 0x00000000 + __offset_MDP(i0); }
210 static inline uint32_t REG_MDP5_MDP_HW_VERSION(uint32_t i0) { return 0x00000000 + __offset_MDP(i0); }
211 #define MDP5_MDP_HW_VERSION_STEP__MASK 0x0000ffff
212 #define MDP5_MDP_HW_VERSION_STEP__SHIFT 0
213 static inline uint32_t MDP5_MDP_HW_VERSION_STEP(uint32_t val)
215 return ((val) << MDP5_MDP_HW_VERSION_STEP__SHIFT) & MDP5_MDP_HW_VERSION_STEP__MASK;
217 #define MDP5_MDP_HW_VERSION_MINOR__MASK 0x0fff0000
218 #define MDP5_MDP_HW_VERSION_MINOR__SHIFT 16
219 static inline uint32_t MDP5_MDP_HW_VERSION_MINOR(uint32_t val)
221 return ((val) << MDP5_MDP_HW_VERSION_MINOR__SHIFT) & MDP5_MDP_HW_VERSION_MINOR__MASK;
223 #define MDP5_MDP_HW_VERSION_MAJOR__MASK 0xf0000000
224 #define MDP5_MDP_HW_VERSION_MAJOR__SHIFT 28
225 static inline uint32_t MDP5_MDP_HW_VERSION_MAJOR(uint32_t val)
227 return ((val) << MDP5_MDP_HW_VERSION_MAJOR__SHIFT) & MDP5_MDP_HW_VERSION_MAJOR__MASK;
230 static inline uint32_t REG_MDP5_MDP_DISP_INTF_SEL(uint32_t i0) { return 0x00000004 + __offset_MDP(i0); }
231 #define MDP5_MDP_DISP_INTF_SEL_INTF0__MASK 0x000000ff
232 #define MDP5_MDP_DISP_INTF_SEL_INTF0__SHIFT 0
233 static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val)
235 return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF0__MASK;
237 #define MDP5_MDP_DISP_INTF_SEL_INTF1__MASK 0x0000ff00
238 #define MDP5_MDP_DISP_INTF_SEL_INTF1__SHIFT 8
239 static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val)
241 return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF1__MASK;
243 #define MDP5_MDP_DISP_INTF_SEL_INTF2__MASK 0x00ff0000
244 #define MDP5_MDP_DISP_INTF_SEL_INTF2__SHIFT 16
245 static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val)
247 return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF2__MASK;
249 #define MDP5_MDP_DISP_INTF_SEL_INTF3__MASK 0xff000000
250 #define MDP5_MDP_DISP_INTF_SEL_INTF3__SHIFT 24
251 static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val)
253 return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF3__MASK;
256 static inline uint32_t REG_MDP5_MDP_INTR_EN(uint32_t i0) { return 0x00000010 + __offset_MDP(i0); }
258 static inline uint32_t REG_MDP5_MDP_INTR_STATUS(uint32_t i0) { return 0x00000014 + __offset_MDP(i0); }
260 static inline uint32_t REG_MDP5_MDP_INTR_CLEAR(uint32_t i0) { return 0x00000018 + __offset_MDP(i0); }
262 static inline uint32_t REG_MDP5_MDP_HIST_INTR_EN(uint32_t i0) { return 0x0000001c + __offset_MDP(i0); }
264 static inline uint32_t REG_MDP5_MDP_HIST_INTR_STATUS(uint32_t i0) { return 0x00000020 + __offset_MDP(i0); }
266 static inline uint32_t REG_MDP5_MDP_HIST_INTR_CLEAR(uint32_t i0) { return 0x00000024 + __offset_MDP(i0); }
268 static inline uint32_t REG_MDP5_MDP_SPARE_0(uint32_t i0) { return 0x00000028 + __offset_MDP(i0); }
269 #define MDP5_MDP_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN 0x00000001
271 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_MDP(i0) + 0x4*i1; }
273 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W_REG(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_MDP(i0) + 0x4*i1; }
274 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK 0x000000ff
275 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__SHIFT 0
276 static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)
278 return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK;
280 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK 0x0000ff00
281 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__SHIFT 8
282 static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)
284 return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK;
286 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff0000
287 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__SHIFT 16
288 static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)
290 return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK;
293 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_MDP(i0) + 0x4*i1; }
295 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R_REG(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_MDP(i0) + 0x4*i1; }
296 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__MASK 0x000000ff
297 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__SHIFT 0
298 static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)
300 return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__MASK;
302 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__MASK 0x0000ff00
303 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__SHIFT 8
304 static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)
306 return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__MASK;
308 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff0000
309 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__SHIFT 16
310 static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)
312 return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__MASK;
315 static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)
318 case IGC_VIG: return 0x00000200;
319 case IGC_RGB: return 0x00000210;
320 case IGC_DMA: return 0x00000220;
321 case IGC_DSPP: return 0x00000300;
322 default: return INVALID_IDX(idx);
325 static inline uint32_t REG_MDP5_MDP_IGC(uint32_t i0, enum mdp5_igc_type i1) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1); }
327 static inline uint32_t REG_MDP5_MDP_IGC_LUT(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1) + 0x4*i2; }
329 static inline uint32_t REG_MDP5_MDP_IGC_LUT_REG(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1) + 0x4*i2; }
330 #define MDP5_MDP_IGC_LUT_REG_VAL__MASK 0x00000fff
331 #define MDP5_MDP_IGC_LUT_REG_VAL__SHIFT 0
332 static inline uint32_t MDP5_MDP_IGC_LUT_REG_VAL(uint32_t val)
334 return ((val) << MDP5_MDP_IGC_LUT_REG_VAL__SHIFT) & MDP5_MDP_IGC_LUT_REG_VAL__MASK;
336 #define MDP5_MDP_IGC_LUT_REG_INDEX_UPDATE 0x02000000
337 #define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_0 0x10000000
338 #define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000
339 #define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000
341 static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_EN(uint32_t i0) { return 0x000002f4 + __offset_MDP(i0); }
343 static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_UPPER(uint32_t i0) { return 0x000002f8 + __offset_MDP(i0); }
344 #define MDP5_MDP_SPLIT_DPL_UPPER_SMART_PANEL 0x00000002
345 #define MDP5_MDP_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN 0x00000004
346 #define MDP5_MDP_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX 0x00000010
347 #define MDP5_MDP_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX 0x00000100
349 static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_LOWER(uint32_t i0) { return 0x000003f0 + __offset_MDP(i0); }
350 #define MDP5_MDP_SPLIT_DPL_LOWER_SMART_PANEL 0x00000002
351 #define MDP5_MDP_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN 0x00000004
352 #define MDP5_MDP_SPLIT_DPL_LOWER_INTF1_TG_SYNC 0x00000010
353 #define MDP5_MDP_SPLIT_DPL_LOWER_INTF2_TG_SYNC 0x00000100
355 static inline uint32_t __offset_CTL(uint32_t idx)
358 case 0: return (mdp5_cfg->ctl.base[0]);
359 case 1: return (mdp5_cfg->ctl.base[1]);
360 case 2: return (mdp5_cfg->ctl.base[2]);
361 case 3: return (mdp5_cfg->ctl.base[3]);
362 case 4: return (mdp5_cfg->ctl.base[4]);
363 default: return INVALID_IDX(idx);
366 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }
368 static inline uint32_t __offset_LAYER(uint32_t idx)
371 case 0: return 0x00000000;
372 case 1: return 0x00000004;
373 case 2: return 0x00000008;
374 case 3: return 0x0000000c;
375 case 4: return 0x00000010;
376 case 5: return 0x00000024;
377 default: return INVALID_IDX(idx);
380 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
382 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
383 #define MDP5_CTL_LAYER_REG_VIG0__MASK 0x00000007
384 #define MDP5_CTL_LAYER_REG_VIG0__SHIFT 0
385 static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(uint32_t val)
387 return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK;
389 #define MDP5_CTL_LAYER_REG_VIG1__MASK 0x00000038
390 #define MDP5_CTL_LAYER_REG_VIG1__SHIFT 3
391 static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(uint32_t val)
393 return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK;
395 #define MDP5_CTL_LAYER_REG_VIG2__MASK 0x000001c0
396 #define MDP5_CTL_LAYER_REG_VIG2__SHIFT 6
397 static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(uint32_t val)
399 return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK;
401 #define MDP5_CTL_LAYER_REG_RGB0__MASK 0x00000e00
402 #define MDP5_CTL_LAYER_REG_RGB0__SHIFT 9
403 static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(uint32_t val)
405 return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK;
407 #define MDP5_CTL_LAYER_REG_RGB1__MASK 0x00007000
408 #define MDP5_CTL_LAYER_REG_RGB1__SHIFT 12
409 static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(uint32_t val)
411 return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK;
413 #define MDP5_CTL_LAYER_REG_RGB2__MASK 0x00038000
414 #define MDP5_CTL_LAYER_REG_RGB2__SHIFT 15
415 static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(uint32_t val)
417 return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK;
419 #define MDP5_CTL_LAYER_REG_DMA0__MASK 0x001c0000
420 #define MDP5_CTL_LAYER_REG_DMA0__SHIFT 18
421 static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(uint32_t val)
423 return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK;
425 #define MDP5_CTL_LAYER_REG_DMA1__MASK 0x00e00000
426 #define MDP5_CTL_LAYER_REG_DMA1__SHIFT 21
427 static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(uint32_t val)
429 return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK;
431 #define MDP5_CTL_LAYER_REG_BORDER_COLOR 0x01000000
432 #define MDP5_CTL_LAYER_REG_CURSOR_OUT 0x02000000
433 #define MDP5_CTL_LAYER_REG_VIG3__MASK 0x1c000000
434 #define MDP5_CTL_LAYER_REG_VIG3__SHIFT 26
435 static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(uint32_t val)
437 return ((val) << MDP5_CTL_LAYER_REG_VIG3__SHIFT) & MDP5_CTL_LAYER_REG_VIG3__MASK;
439 #define MDP5_CTL_LAYER_REG_RGB3__MASK 0xe0000000
440 #define MDP5_CTL_LAYER_REG_RGB3__SHIFT 29
441 static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(uint32_t val)
443 return ((val) << MDP5_CTL_LAYER_REG_RGB3__SHIFT) & MDP5_CTL_LAYER_REG_RGB3__MASK;
446 static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }
447 #define MDP5_CTL_OP_MODE__MASK 0x0000000f
448 #define MDP5_CTL_OP_MODE__SHIFT 0
449 static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)
451 return ((val) << MDP5_CTL_OP_MODE__SHIFT) & MDP5_CTL_OP_MODE__MASK;
453 #define MDP5_CTL_OP_INTF_NUM__MASK 0x00000070
454 #define MDP5_CTL_OP_INTF_NUM__SHIFT 4
455 static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)
457 return ((val) << MDP5_CTL_OP_INTF_NUM__SHIFT) & MDP5_CTL_OP_INTF_NUM__MASK;
459 #define MDP5_CTL_OP_CMD_MODE 0x00020000
460 #define MDP5_CTL_OP_PACK_3D_ENABLE 0x00080000
461 #define MDP5_CTL_OP_PACK_3D__MASK 0x00300000
462 #define MDP5_CTL_OP_PACK_3D__SHIFT 20
463 static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)
465 return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK;
468 static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }
469 #define MDP5_CTL_FLUSH_VIG0 0x00000001
470 #define MDP5_CTL_FLUSH_VIG1 0x00000002
471 #define MDP5_CTL_FLUSH_VIG2 0x00000004
472 #define MDP5_CTL_FLUSH_RGB0 0x00000008
473 #define MDP5_CTL_FLUSH_RGB1 0x00000010
474 #define MDP5_CTL_FLUSH_RGB2 0x00000020
475 #define MDP5_CTL_FLUSH_LM0 0x00000040
476 #define MDP5_CTL_FLUSH_LM1 0x00000080
477 #define MDP5_CTL_FLUSH_LM2 0x00000100
478 #define MDP5_CTL_FLUSH_LM3 0x00000200
479 #define MDP5_CTL_FLUSH_LM4 0x00000400
480 #define MDP5_CTL_FLUSH_DMA0 0x00000800
481 #define MDP5_CTL_FLUSH_DMA1 0x00001000
482 #define MDP5_CTL_FLUSH_DSPP0 0x00002000
483 #define MDP5_CTL_FLUSH_DSPP1 0x00004000
484 #define MDP5_CTL_FLUSH_DSPP2 0x00008000
485 #define MDP5_CTL_FLUSH_WB 0x00010000
486 #define MDP5_CTL_FLUSH_CTL 0x00020000
487 #define MDP5_CTL_FLUSH_VIG3 0x00040000
488 #define MDP5_CTL_FLUSH_RGB3 0x00080000
489 #define MDP5_CTL_FLUSH_LM5 0x00100000
490 #define MDP5_CTL_FLUSH_DSPP3 0x00200000
491 #define MDP5_CTL_FLUSH_CURSOR_0 0x00400000
492 #define MDP5_CTL_FLUSH_CURSOR_1 0x00800000
493 #define MDP5_CTL_FLUSH_CHROMADOWN_0 0x04000000
494 #define MDP5_CTL_FLUSH_TIMING_3 0x10000000
495 #define MDP5_CTL_FLUSH_TIMING_2 0x20000000
496 #define MDP5_CTL_FLUSH_TIMING_1 0x40000000
497 #define MDP5_CTL_FLUSH_TIMING_0 0x80000000
499 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }
501 static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }
503 static inline uint32_t __offset_LAYER_EXT(uint32_t idx)
506 case 0: return 0x00000040;
507 case 1: return 0x00000044;
508 case 2: return 0x00000048;
509 case 3: return 0x0000004c;
510 case 4: return 0x00000050;
511 case 5: return 0x00000054;
512 default: return INVALID_IDX(idx);
515 static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
517 static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
518 #define MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3 0x00000001
519 #define MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3 0x00000004
520 #define MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3 0x00000010
521 #define MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3 0x00000040
522 #define MDP5_CTL_LAYER_EXT_REG_RGB0_BIT3 0x00000100
523 #define MDP5_CTL_LAYER_EXT_REG_RGB1_BIT3 0x00000400
524 #define MDP5_CTL_LAYER_EXT_REG_RGB2_BIT3 0x00001000
525 #define MDP5_CTL_LAYER_EXT_REG_RGB3_BIT3 0x00004000
526 #define MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3 0x00010000
527 #define MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3 0x00040000
528 #define MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK 0x00f00000
529 #define MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT 20
530 static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val)
532 return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK;
534 #define MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK 0x3c000000
535 #define MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT 26
536 static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val)
538 return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK;
541 static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)
544 case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]);
545 case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]);
546 case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]);
547 case SSPP_RGB0: return (mdp5_cfg->pipe_rgb.base[0]);
548 case SSPP_RGB1: return (mdp5_cfg->pipe_rgb.base[1]);
549 case SSPP_RGB2: return (mdp5_cfg->pipe_rgb.base[2]);
550 case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]);
551 case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]);
552 case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]);
553 case SSPP_RGB3: return (mdp5_cfg->pipe_rgb.base[3]);
554 default: return INVALID_IDX(idx);
557 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
559 static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0); }
560 #define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00080000
561 #define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 19
562 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)
564 return ((val) << MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
566 #define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00040000
567 #define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 18
568 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)
570 return ((val) << MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
572 #define MDP5_PIPE_OP_MODE_CSC_1_EN 0x00020000
574 static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); }
576 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); }
578 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); }
580 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); }
581 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff
582 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT 0
583 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val)
585 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK;
587 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000
588 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT 16
589 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val)
591 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK;
594 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); }
595 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff
596 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT 0
597 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val)
599 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK;
601 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000
602 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT 16
603 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val)
605 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK;
608 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); }
609 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff
610 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT 0
611 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val)
613 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK;
615 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000
616 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT 16
617 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val)
619 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK;
622 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); }
623 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff
624 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT 0
625 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val)
627 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK;
629 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000
630 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT 16
631 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val)
633 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK;
636 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0); }
637 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff
638 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT 0
639 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val)
641 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK;
644 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
646 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
647 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK 0x000000ff
648 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT 0
649 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val)
651 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK;
653 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK 0x0000ff00
654 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT 8
655 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val)
657 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK;
660 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
662 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
663 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK 0x000000ff
664 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT 0
665 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val)
667 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK;
669 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK 0x0000ff00
670 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT 8
671 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val)
673 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK;
676 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
678 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
679 #define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK 0x000001ff
680 #define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT 0
681 static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val)
683 return ((val) << MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK;
686 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
688 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
689 #define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK 0x000001ff
690 #define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT 0
691 static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val)
693 return ((val) << MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK;
696 static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
697 #define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
698 #define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
699 static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
701 return ((val) << MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_SIZE_HEIGHT__MASK;
703 #define MDP5_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
704 #define MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT 0
705 static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)
707 return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK;
710 static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); }
711 #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK 0xffff0000
712 #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT 16
713 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)
715 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK;
717 #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK 0x0000ffff
718 #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT 0
719 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)
721 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK;
724 static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); }
725 #define MDP5_PIPE_SRC_XY_Y__MASK 0xffff0000
726 #define MDP5_PIPE_SRC_XY_Y__SHIFT 16
727 static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)
729 return ((val) << MDP5_PIPE_SRC_XY_Y__SHIFT) & MDP5_PIPE_SRC_XY_Y__MASK;
731 #define MDP5_PIPE_SRC_XY_X__MASK 0x0000ffff
732 #define MDP5_PIPE_SRC_XY_X__SHIFT 0
733 static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)
735 return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK;
738 static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); }
739 #define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK 0xffff0000
740 #define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT 16
741 static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)
743 return ((val) << MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_OUT_SIZE_HEIGHT__MASK;
745 #define MDP5_PIPE_OUT_SIZE_WIDTH__MASK 0x0000ffff
746 #define MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT 0
747 static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)
749 return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK;
752 static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); }
753 #define MDP5_PIPE_OUT_XY_Y__MASK 0xffff0000
754 #define MDP5_PIPE_OUT_XY_Y__SHIFT 16
755 static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)
757 return ((val) << MDP5_PIPE_OUT_XY_Y__SHIFT) & MDP5_PIPE_OUT_XY_Y__MASK;
759 #define MDP5_PIPE_OUT_XY_X__MASK 0x0000ffff
760 #define MDP5_PIPE_OUT_XY_X__SHIFT 0
761 static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)
763 return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK;
766 static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); }
768 static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); }
770 static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); }
772 static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); }
774 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); }
775 #define MDP5_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
776 #define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT 0
777 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)
779 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P0__MASK;
781 #define MDP5_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
782 #define MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT 16
783 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)
785 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK;
788 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); }
789 #define MDP5_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
790 #define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT 0
791 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)
793 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P2__MASK;
795 #define MDP5_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
796 #define MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT 16
797 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)
799 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK;
802 static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); }
804 static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); }
805 #define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
806 #define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
807 static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
809 return ((val) << MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_G_BPC__MASK;
811 #define MDP5_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
812 #define MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
813 static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
815 return ((val) << MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_B_BPC__MASK;
817 #define MDP5_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
818 #define MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
819 static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
821 return ((val) << MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_R_BPC__MASK;
823 #define MDP5_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
824 #define MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
825 static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
827 return ((val) << MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_A_BPC__MASK;
829 #define MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
830 #define MDP5_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
831 #define MDP5_PIPE_SRC_FORMAT_CPP__SHIFT 9
832 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)
834 return ((val) << MDP5_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CPP__MASK;
836 #define MDP5_PIPE_SRC_FORMAT_ROT90 0x00000800
837 #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00003000
838 #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 12
839 static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
841 return ((val) << MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
843 #define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
844 #define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
845 #define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK 0x00180000
846 #define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT 19
847 static inline uint32_t MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val)
849 return ((val) << MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT) & MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK;
851 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x01800000
852 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 23
853 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
855 return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
858 static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); }
859 #define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
860 #define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
861 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
863 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM0__MASK;
865 #define MDP5_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
866 #define MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
867 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
869 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM1__MASK;
871 #define MDP5_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
872 #define MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
873 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
875 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM2__MASK;
877 #define MDP5_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
878 #define MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
879 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
881 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK;
884 static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); }
885 #define MDP5_PIPE_SRC_OP_MODE_BWC_EN 0x00000001
886 #define MDP5_PIPE_SRC_OP_MODE_BWC__MASK 0x00000006
887 #define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT 1
888 static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)
890 return ((val) << MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT) & MDP5_PIPE_SRC_OP_MODE_BWC__MASK;
892 #define MDP5_PIPE_SRC_OP_MODE_FLIP_LR 0x00002000
893 #define MDP5_PIPE_SRC_OP_MODE_FLIP_UD 0x00004000
894 #define MDP5_PIPE_SRC_OP_MODE_IGC_EN 0x00010000
895 #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_0 0x00020000
896 #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1 0x00040000
897 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE 0x00400000
898 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD 0x00800000
899 #define MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE 0x80000000
901 static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); }
903 static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); }
905 static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); }
907 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); }
909 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); }
911 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); }
913 static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); }
915 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); }
917 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); }
919 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); }
921 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); }
923 static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); }
924 #define MDP5_PIPE_DECIMATION_VERT__MASK 0x000000ff
925 #define MDP5_PIPE_DECIMATION_VERT__SHIFT 0
926 static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)
928 return ((val) << MDP5_PIPE_DECIMATION_VERT__SHIFT) & MDP5_PIPE_DECIMATION_VERT__MASK;
930 #define MDP5_PIPE_DECIMATION_HORZ__MASK 0x0000ff00
931 #define MDP5_PIPE_DECIMATION_HORZ__SHIFT 8
932 static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)
934 return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK;
937 static inline uint32_t __offset_SW_PIX_EXT(enum mdp_component_type idx)
940 case COMP_0: return 0x00000100;
941 case COMP_1_2: return 0x00000110;
942 case COMP_3: return 0x00000120;
943 default: return INVALID_IDX(idx);
946 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
948 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
949 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK 0x000000ff
950 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT 0
951 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val)
953 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK;
955 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK 0x0000ff00
956 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT 8
957 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val)
959 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK;
961 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK 0x00ff0000
962 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT 16
963 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val)
965 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK;
967 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK 0xff000000
968 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT 24
969 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val)
971 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK;
974 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
975 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK 0x000000ff
976 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT 0
977 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val)
979 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK;
981 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK 0x0000ff00
982 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT 8
983 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val)
985 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK;
987 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK 0x00ff0000
988 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT 16
989 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val)
991 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK;
993 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK 0xff000000
994 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT 24
995 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val)
997 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK;
1000 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
1001 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK 0x0000ffff
1002 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT 0
1003 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val)
1005 return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK;
1007 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK 0xffff0000
1008 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT 16
1009 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val)
1011 return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK;
1014 static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); }
1015 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001
1016 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002
1017 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK 0x00000300
1018 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT 8
1019 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val)
1021 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK;
1023 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK 0x00000c00
1024 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT 10
1025 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val)
1027 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK;
1029 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK 0x00003000
1030 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT 12
1031 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val)
1033 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK;
1035 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK 0x0000c000
1036 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT 14
1037 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val)
1039 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK;
1041 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK 0x00030000
1042 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT 16
1043 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val)
1045 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK;
1047 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK 0x000c0000
1048 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT 18
1049 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val)
1051 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK;
1054 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); }
1056 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); }
1058 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0); }
1060 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0); }
1062 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); }
1064 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); }
1066 static inline uint32_t __offset_LM(uint32_t idx)
1069 case 0: return (mdp5_cfg->lm.base[0]);
1070 case 1: return (mdp5_cfg->lm.base[1]);
1071 case 2: return (mdp5_cfg->lm.base[2]);
1072 case 3: return (mdp5_cfg->lm.base[3]);
1073 case 4: return (mdp5_cfg->lm.base[4]);
1074 case 5: return (mdp5_cfg->lm.base[5]);
1075 default: return INVALID_IDX(idx);
1078 static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
1080 static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
1081 #define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA 0x00000002
1082 #define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA 0x00000004
1083 #define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA 0x00000008
1084 #define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA 0x00000010
1086 static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }
1087 #define MDP5_LM_OUT_SIZE_HEIGHT__MASK 0xffff0000
1088 #define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT 16
1089 static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)
1091 return ((val) << MDP5_LM_OUT_SIZE_HEIGHT__SHIFT) & MDP5_LM_OUT_SIZE_HEIGHT__MASK;
1093 #define MDP5_LM_OUT_SIZE_WIDTH__MASK 0x0000ffff
1094 #define MDP5_LM_OUT_SIZE_WIDTH__SHIFT 0
1095 static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)
1097 return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK;
1100 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0); }
1102 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); }
1104 static inline uint32_t __offset_BLEND(uint32_t idx)
1107 case 0: return 0x00000020;
1108 case 1: return 0x00000050;
1109 case 2: return 0x00000080;
1110 case 3: return 0x000000b0;
1111 case 4: return 0x00000230;
1112 case 5: return 0x00000260;
1113 case 6: return 0x00000290;
1114 default: return INVALID_IDX(idx);
1117 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
1119 static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
1120 #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK 0x00000003
1121 #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT 0
1122 static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)
1124 return ((val) << MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK;
1126 #define MDP5_LM_BLEND_OP_MODE_FG_INV_ALPHA 0x00000004
1127 #define MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA 0x00000008
1128 #define MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA 0x00000010
1129 #define MDP5_LM_BLEND_OP_MODE_FG_TRANSP_EN 0x00000020
1130 #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK 0x00000300
1131 #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT 8
1132 static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)
1134 return ((val) << MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK;
1136 #define MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA 0x00000400
1137 #define MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA 0x00000800
1138 #define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA 0x00001000
1139 #define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN 0x00002000
1141 static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_LM(i0) + __offset_BLEND(i1); }
1143 static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_LM(i0) + __offset_BLEND(i1); }
1145 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_LM(i0) + __offset_BLEND(i1); }
1147 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_LM(i0) + __offset_BLEND(i1); }
1149 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_LM(i0) + __offset_BLEND(i1); }
1151 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_LM(i0) + __offset_BLEND(i1); }
1153 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_LM(i0) + __offset_BLEND(i1); }
1155 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + __offset_BLEND(i1); }
1157 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + __offset_BLEND(i1); }
1159 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + __offset_BLEND(i1); }
1161 static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); }
1162 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK 0x0000ffff
1163 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT 0
1164 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)
1166 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK;
1168 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK 0xffff0000
1169 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT 16
1170 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)
1172 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK;
1175 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }
1176 #define MDP5_LM_CURSOR_SIZE_ROI_W__MASK 0x0000ffff
1177 #define MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT 0
1178 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)
1180 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_W__MASK;
1182 #define MDP5_LM_CURSOR_SIZE_ROI_H__MASK 0xffff0000
1183 #define MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT 16
1184 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)
1186 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_H__MASK;
1189 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }
1190 #define MDP5_LM_CURSOR_XY_SRC_X__MASK 0x0000ffff
1191 #define MDP5_LM_CURSOR_XY_SRC_X__SHIFT 0
1192 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)
1194 return ((val) << MDP5_LM_CURSOR_XY_SRC_X__SHIFT) & MDP5_LM_CURSOR_XY_SRC_X__MASK;
1196 #define MDP5_LM_CURSOR_XY_SRC_Y__MASK 0xffff0000
1197 #define MDP5_LM_CURSOR_XY_SRC_Y__SHIFT 16
1198 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)
1200 return ((val) << MDP5_LM_CURSOR_XY_SRC_Y__SHIFT) & MDP5_LM_CURSOR_XY_SRC_Y__MASK;
1203 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); }
1204 #define MDP5_LM_CURSOR_STRIDE_STRIDE__MASK 0x0000ffff
1205 #define MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT 0
1206 static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)
1208 return ((val) << MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT) & MDP5_LM_CURSOR_STRIDE_STRIDE__MASK;
1211 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); }
1212 #define MDP5_LM_CURSOR_FORMAT_FORMAT__MASK 0x00000007
1213 #define MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT 0
1214 static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)
1216 return ((val) << MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT) & MDP5_LM_CURSOR_FORMAT_FORMAT__MASK;
1219 static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); }
1221 static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); }
1222 #define MDP5_LM_CURSOR_START_XY_X_START__MASK 0x0000ffff
1223 #define MDP5_LM_CURSOR_START_XY_X_START__SHIFT 0
1224 static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)
1226 return ((val) << MDP5_LM_CURSOR_START_XY_X_START__SHIFT) & MDP5_LM_CURSOR_START_XY_X_START__MASK;
1228 #define MDP5_LM_CURSOR_START_XY_Y_START__MASK 0xffff0000
1229 #define MDP5_LM_CURSOR_START_XY_Y_START__SHIFT 16
1230 static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)
1232 return ((val) << MDP5_LM_CURSOR_START_XY_Y_START__SHIFT) & MDP5_LM_CURSOR_START_XY_Y_START__MASK;
1235 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); }
1236 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN 0x00000001
1237 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK 0x00000006
1238 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT 1
1239 static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)
1241 return ((val) << MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT) & MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK;
1243 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_TRANSP_EN 0x00000008
1245 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); }
1247 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0); }
1249 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0); }
1251 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0); }
1253 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0); }
1255 static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }
1257 static inline uint32_t __offset_DSPP(uint32_t idx)
1260 case 0: return (mdp5_cfg->dspp.base[0]);
1261 case 1: return (mdp5_cfg->dspp.base[1]);
1262 case 2: return (mdp5_cfg->dspp.base[2]);
1263 case 3: return (mdp5_cfg->dspp.base[3]);
1264 default: return INVALID_IDX(idx);
1267 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
1269 static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
1270 #define MDP5_DSPP_OP_MODE_IGC_LUT_EN 0x00000001
1271 #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK 0x0000000e
1272 #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT 1
1273 static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)
1275 return ((val) << MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT) & MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK;
1277 #define MDP5_DSPP_OP_MODE_PCC_EN 0x00000010
1278 #define MDP5_DSPP_OP_MODE_DITHER_EN 0x00000100
1279 #define MDP5_DSPP_OP_MODE_HIST_EN 0x00010000
1280 #define MDP5_DSPP_OP_MODE_AUTO_CLEAR 0x00020000
1281 #define MDP5_DSPP_OP_MODE_HIST_LUT_EN 0x00080000
1282 #define MDP5_DSPP_OP_MODE_PA_EN 0x00100000
1283 #define MDP5_DSPP_OP_MODE_GAMUT_EN 0x00800000
1284 #define MDP5_DSPP_OP_MODE_GAMUT_ORDER 0x01000000
1286 static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); }
1288 static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); }
1290 static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); }
1292 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); }
1294 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); }
1296 static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }
1298 static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); }
1300 static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }
1302 static inline uint32_t __offset_PP(uint32_t idx)
1305 case 0: return (mdp5_cfg->pp.base[0]);
1306 case 1: return (mdp5_cfg->pp.base[1]);
1307 case 2: return (mdp5_cfg->pp.base[2]);
1308 case 3: return (mdp5_cfg->pp.base[3]);
1309 default: return INVALID_IDX(idx);
1312 static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
1314 static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
1316 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP(i0); }
1317 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK 0x0007ffff
1318 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT 0
1319 static inline uint32_t MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val)
1321 return ((val) << MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT) & MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK;
1323 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNTER_EN 0x00080000
1324 #define MDP5_PP_SYNC_CONFIG_VSYNC_IN_EN 0x00100000
1326 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_PP(i0); }
1328 static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0); }
1329 #define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK 0x0000ffff
1330 #define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT 0
1331 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val)
1333 return ((val) << MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK;
1335 #define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK 0xffff0000
1336 #define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT 16
1337 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val)
1339 return ((val) << MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK;
1342 static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0); }
1344 static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0); }
1345 #define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK 0x0000ffff
1346 #define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT 0
1347 static inline uint32_t MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val)
1349 return ((val) << MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK;
1351 #define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK 0xffff0000
1352 #define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT 16
1353 static inline uint32_t MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val)
1355 return ((val) << MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK;
1358 static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); }
1359 #define MDP5_PP_SYNC_THRESH_START__MASK 0x0000ffff
1360 #define MDP5_PP_SYNC_THRESH_START__SHIFT 0
1361 static inline uint32_t MDP5_PP_SYNC_THRESH_START(uint32_t val)
1363 return ((val) << MDP5_PP_SYNC_THRESH_START__SHIFT) & MDP5_PP_SYNC_THRESH_START__MASK;
1365 #define MDP5_PP_SYNC_THRESH_CONTINUE__MASK 0xffff0000
1366 #define MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT 16
1367 static inline uint32_t MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val)
1369 return ((val) << MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT) & MDP5_PP_SYNC_THRESH_CONTINUE__MASK;
1372 static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); }
1374 static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); }
1376 static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); }
1378 static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0); }
1380 static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0); }
1382 static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_PP(i0); }
1384 static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); }
1386 static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0); }
1388 static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0); }
1390 static inline uint32_t __offset_WB(uint32_t idx)
1393 #if 0 /* TEMPORARY until patch that adds wb.base[] is merged */
1394 case 0: return (mdp5_cfg->wb.base[0]);
1395 case 1: return (mdp5_cfg->wb.base[1]);
1396 case 2: return (mdp5_cfg->wb.base[2]);
1397 case 3: return (mdp5_cfg->wb.base[3]);
1398 case 4: return (mdp5_cfg->wb.base[4]);
1400 default: return INVALID_IDX(idx);
1403 static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
1405 static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
1406 #define MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK 0x00000003
1407 #define MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT 0
1408 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val)
1410 return ((val) << MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK;
1412 #define MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK 0x0000000c
1413 #define MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT 2
1414 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val)
1416 return ((val) << MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK;
1418 #define MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK 0x00000030
1419 #define MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT 4
1420 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val)
1422 return ((val) << MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK;
1424 #define MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK 0x000000c0
1425 #define MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT 6
1426 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val)
1428 return ((val) << MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK;
1430 #define MDP5_WB_DST_FORMAT_DSTC3_EN 0x00000100
1431 #define MDP5_WB_DST_FORMAT_DST_BPP__MASK 0x00000600
1432 #define MDP5_WB_DST_FORMAT_DST_BPP__SHIFT 9
1433 static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val)
1435 return ((val) << MDP5_WB_DST_FORMAT_DST_BPP__SHIFT) & MDP5_WB_DST_FORMAT_DST_BPP__MASK;
1437 #define MDP5_WB_DST_FORMAT_PACK_COUNT__MASK 0x00003000
1438 #define MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT 12
1439 static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val)
1441 return ((val) << MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT) & MDP5_WB_DST_FORMAT_PACK_COUNT__MASK;
1443 #define MDP5_WB_DST_FORMAT_DST_ALPHA_X 0x00004000
1444 #define MDP5_WB_DST_FORMAT_PACK_TIGHT 0x00020000
1445 #define MDP5_WB_DST_FORMAT_PACK_ALIGN_MSB 0x00040000
1446 #define MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK 0x00180000
1447 #define MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT 19
1448 static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val)
1450 return ((val) << MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT) & MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK;
1452 #define MDP5_WB_DST_FORMAT_DST_DITHER_EN 0x00400000
1453 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK 0x03800000
1454 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT 23
1455 static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val)
1457 return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK;
1459 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK 0x3c000000
1460 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT 26
1461 static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val)
1463 return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK;
1465 #define MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK 0xc0000000
1466 #define MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT 30
1467 static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val)
1469 return ((val) << MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT) & MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK;
1472 static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); }
1473 #define MDP5_WB_DST_OP_MODE_BWC_ENC_EN 0x00000001
1474 #define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK 0x00000006
1475 #define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT 1
1476 static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val)
1478 return ((val) << MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT) & MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK;
1480 #define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK 0x00000010
1481 #define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT 4
1482 static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val)
1484 return ((val) << MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT) & MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK;
1486 #define MDP5_WB_DST_OP_MODE_ROT_MODE__MASK 0x00000020
1487 #define MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT 5
1488 static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val)
1490 return ((val) << MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT) & MDP5_WB_DST_OP_MODE_ROT_MODE__MASK;
1492 #define MDP5_WB_DST_OP_MODE_ROT_EN 0x00000040
1493 #define MDP5_WB_DST_OP_MODE_CSC_EN 0x00000100
1494 #define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00000200
1495 #define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 9
1496 static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val)
1498 return ((val) << MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
1500 #define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00000400
1501 #define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 10
1502 static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val)
1504 return ((val) << MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
1506 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_EN 0x00000800
1507 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK 0x00001000
1508 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT 12
1509 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val)
1511 return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK;
1513 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK 0x00002000
1514 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT 13
1515 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val)
1517 return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK;
1519 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK 0x00004000
1520 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT 14
1521 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val)
1523 return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK;
1526 static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(i0); }
1527 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK 0x00000003
1528 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT 0
1529 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val)
1531 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK;
1533 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK 0x00000300
1534 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT 8
1535 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val)
1537 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK;
1539 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK 0x00030000
1540 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT 16
1541 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val)
1543 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK;
1545 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK 0x03000000
1546 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT 24
1547 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val)
1549 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK;
1552 static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); }
1554 static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); }
1556 static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); }
1558 static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); }
1560 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0); }
1561 #define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK 0x0000ffff
1562 #define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT 0
1563 static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val)
1565 return ((val) << MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK;
1567 #define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK 0xffff0000
1568 #define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT 16
1569 static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val)
1571 return ((val) << MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK;
1574 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0); }
1575 #define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK 0x0000ffff
1576 #define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT 0
1577 static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val)
1579 return ((val) << MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK;
1581 #define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK 0xffff0000
1582 #define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT 16
1583 static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val)
1585 return ((val) << MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK;
1588 static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_WB(i0); }
1590 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_WB(i0); }
1592 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_WB(i0); }
1594 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_WB(i0); }
1596 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_WB(i0); }
1598 static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(i0); }
1600 static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB(i0); }
1602 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset_WB(i0); }
1604 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset_WB(i0); }
1606 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset_WB(i0); }
1608 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset_WB(i0); }
1610 static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); }
1611 #define MDP5_WB_OUT_SIZE_DST_W__MASK 0x0000ffff
1612 #define MDP5_WB_OUT_SIZE_DST_W__SHIFT 0
1613 static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val)
1615 return ((val) << MDP5_WB_OUT_SIZE_DST_W__SHIFT) & MDP5_WB_OUT_SIZE_DST_W__MASK;
1617 #define MDP5_WB_OUT_SIZE_DST_H__MASK 0xffff0000
1618 #define MDP5_WB_OUT_SIZE_DST_H__SHIFT 16
1619 static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val)
1621 return ((val) << MDP5_WB_OUT_SIZE_DST_H__SHIFT) & MDP5_WB_OUT_SIZE_DST_H__MASK;
1624 static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0); }
1626 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_WB(i0); }
1627 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff
1628 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT 0
1629 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val)
1631 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK;
1633 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000
1634 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT 16
1635 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val)
1637 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK;
1640 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_WB(i0); }
1641 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff
1642 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT 0
1643 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val)
1645 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK;
1647 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000
1648 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT 16
1649 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val)
1651 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK;
1654 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_WB(i0); }
1655 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff
1656 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT 0
1657 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val)
1659 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK;
1661 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000
1662 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT 16
1663 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val)
1665 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK;
1668 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_WB(i0); }
1669 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff
1670 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT 0
1671 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val)
1673 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK;
1675 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000
1676 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT 16
1677 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val)
1679 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK;
1682 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_WB(i0); }
1683 #define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff
1684 #define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT 0
1685 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val)
1687 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK;
1690 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
1692 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
1693 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK 0x000000ff
1694 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT 0
1695 static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val)
1697 return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK;
1699 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK 0x0000ff00
1700 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT 8
1701 static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val)
1703 return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK;
1706 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
1708 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
1709 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK 0x000000ff
1710 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT 0
1711 static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val)
1713 return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK;
1715 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK 0x0000ff00
1716 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT 8
1717 static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val)
1719 return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK;
1722 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
1724 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
1725 #define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK 0x000001ff
1726 #define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT 0
1727 static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val)
1729 return ((val) << MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK;
1732 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
1734 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
1735 #define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK 0x000001ff
1736 #define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT 0
1737 static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val)
1739 return ((val) << MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK;
1742 static inline uint32_t __offset_INTF(uint32_t idx)
1745 case 0: return (mdp5_cfg->intf.base[0]);
1746 case 1: return (mdp5_cfg->intf.base[1]);
1747 case 2: return (mdp5_cfg->intf.base[2]);
1748 case 3: return (mdp5_cfg->intf.base[3]);
1749 case 4: return (mdp5_cfg->intf.base[4]);
1750 default: return INVALID_IDX(idx);
1753 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
1755 static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
1757 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }
1759 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); }
1760 #define MDP5_INTF_HSYNC_CTL_PULSEW__MASK 0x0000ffff
1761 #define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT 0
1762 static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)
1764 return ((val) << MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT) & MDP5_INTF_HSYNC_CTL_PULSEW__MASK;
1766 #define MDP5_INTF_HSYNC_CTL_PERIOD__MASK 0xffff0000
1767 #define MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT 16
1768 static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)
1770 return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK;
1773 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); }
1775 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); }
1777 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); }
1779 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); }
1781 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); }
1783 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); }
1785 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); }
1787 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); }
1789 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); }
1790 #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK 0x7fffffff
1791 #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT 0
1792 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)
1794 return ((val) << MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK;
1796 #define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE 0x80000000
1798 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); }
1799 #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK 0x7fffffff
1800 #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT 0
1801 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)
1803 return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK;
1806 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); }
1808 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); }
1810 static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); }
1811 #define MDP5_INTF_DISPLAY_HCTL_START__MASK 0x0000ffff
1812 #define MDP5_INTF_DISPLAY_HCTL_START__SHIFT 0
1813 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)
1815 return ((val) << MDP5_INTF_DISPLAY_HCTL_START__SHIFT) & MDP5_INTF_DISPLAY_HCTL_START__MASK;
1817 #define MDP5_INTF_DISPLAY_HCTL_END__MASK 0xffff0000
1818 #define MDP5_INTF_DISPLAY_HCTL_END__SHIFT 16
1819 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)
1821 return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK;
1824 static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); }
1825 #define MDP5_INTF_ACTIVE_HCTL_START__MASK 0x00007fff
1826 #define MDP5_INTF_ACTIVE_HCTL_START__SHIFT 0
1827 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)
1829 return ((val) << MDP5_INTF_ACTIVE_HCTL_START__SHIFT) & MDP5_INTF_ACTIVE_HCTL_START__MASK;
1831 #define MDP5_INTF_ACTIVE_HCTL_END__MASK 0x7fff0000
1832 #define MDP5_INTF_ACTIVE_HCTL_END__SHIFT 16
1833 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)
1835 return ((val) << MDP5_INTF_ACTIVE_HCTL_END__SHIFT) & MDP5_INTF_ACTIVE_HCTL_END__MASK;
1837 #define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE 0x80000000
1839 static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); }
1841 static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); }
1843 static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); }
1845 static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); }
1846 #define MDP5_INTF_POLARITY_CTL_HSYNC_LOW 0x00000001
1847 #define MDP5_INTF_POLARITY_CTL_VSYNC_LOW 0x00000002
1848 #define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW 0x00000004
1850 static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); }
1852 static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); }
1854 static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); }
1856 static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); }
1858 static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); }
1860 static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); }
1862 static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); }
1864 static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); }
1866 static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); }
1868 static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); }
1870 static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); }
1872 static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); }
1874 static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); }
1876 static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); }
1878 static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); }
1880 static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); }
1882 static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); }
1884 static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); }
1886 static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); }
1888 static inline uint32_t __offset_AD(uint32_t idx)
1891 case 0: return (mdp5_cfg->ad.base[0]);
1892 case 1: return (mdp5_cfg->ad.base[1]);
1893 default: return INVALID_IDX(idx);
1896 static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1898 static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1900 static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }
1902 static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }
1904 static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }
1906 static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }
1908 static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }
1910 static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }
1912 static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }
1914 static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }
1916 static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }
1918 static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }
1920 static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }
1922 static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }
1924 static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }
1926 static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }
1928 static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }
1930 static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }
1932 static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }
1934 static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }
1936 static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }
1938 static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }
1940 static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }
1942 static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }
1944 static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }
1946 static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }
1948 static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }
1950 static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }
1952 static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }
1954 static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }
1956 static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }
1958 static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }
1960 static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }
1962 static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }
1964 static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }
1967 #endif /* MDP5_XML */