2 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/sort.h>
22 #include <drm/drm_mode.h>
24 #include "drm_crtc_helper.h"
25 #include "drm_flip_work.h"
27 #define CURSOR_WIDTH 64
28 #define CURSOR_HEIGHT 64
30 #define SSPP_MAX (SSPP_RGB3 + 1) /* TODO: Add SSPP_MAX in mdp5.xml.h */
38 /* layer mixer used for this CRTC (+ its lock): */
39 #define GET_LM_ID(crtc_id) ((crtc_id == 3) ? 5 : crtc_id)
41 spinlock_t lm_lock; /* protect REG_MDP5_LM_* registers */
43 /* CTL used for this CRTC: */
46 /* if there is a pending flip, these will be non-null: */
47 struct drm_pending_vblank_event *event;
49 /* Bits have been flushed at the last commit,
50 * used to decide if a vsync has happened since last commit.
54 #define PENDING_CURSOR 0x1
55 #define PENDING_FLIP 0x2
58 /* for unref'ing cursor bo's after scanout completes: */
59 struct drm_flip_work unref_cursor_work;
61 struct mdp_irq vblank;
63 struct mdp_irq pp_done;
65 struct completion pp_completion;
70 /* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/
73 /* current cursor being scanned out: */
74 struct drm_gem_object *scanout_bo;
75 uint32_t width, height;
79 #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
81 static struct mdp5_kms *get_kms(struct drm_crtc *crtc)
83 struct msm_drm_private *priv = crtc->dev->dev_private;
84 return to_mdp5_kms(to_mdp_kms(priv->kms));
87 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
89 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
91 atomic_or(pending, &mdp5_crtc->pending);
92 mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank);
95 static void request_pp_done_pending(struct drm_crtc *crtc)
97 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
98 reinit_completion(&mdp5_crtc->pp_completion);
101 static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
103 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
105 DBG("%s: flush=%08x", mdp5_crtc->name, flush_mask);
106 return mdp5_ctl_commit(mdp5_crtc->ctl, flush_mask);
110 * flush updates, to make sure hw is updated to new scanout fb,
111 * so that we can safely queue unref to current fb (ie. next
112 * vblank we know hw is done w/ previous scanout_fb).
114 static u32 crtc_flush_all(struct drm_crtc *crtc)
116 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
117 struct drm_plane *plane;
118 uint32_t flush_mask = 0;
120 /* this should not happen: */
121 if (WARN_ON(!mdp5_crtc->ctl))
124 drm_atomic_crtc_for_each_plane(plane, crtc) {
125 flush_mask |= mdp5_plane_get_flush(plane);
128 flush_mask |= mdp_ctl_flush_mask_lm(mdp5_crtc->lm);
130 return crtc_flush(crtc, flush_mask);
133 /* if file!=NULL, this is preclose potential cancel-flip path */
134 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
136 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
137 struct drm_device *dev = crtc->dev;
138 struct drm_pending_vblank_event *event;
139 struct drm_plane *plane;
142 spin_lock_irqsave(&dev->event_lock, flags);
143 event = mdp5_crtc->event;
145 /* if regular vblank case (!file) or if cancel-flip from
146 * preclose on file that requested flip, then send the
149 if (!file || (event->base.file_priv == file)) {
150 mdp5_crtc->event = NULL;
151 DBG("%s: send event: %p", mdp5_crtc->name, event);
152 drm_crtc_send_vblank_event(crtc, event);
155 spin_unlock_irqrestore(&dev->event_lock, flags);
157 drm_atomic_crtc_for_each_plane(plane, crtc) {
158 mdp5_plane_complete_flip(plane);
161 if (mdp5_crtc->ctl && !crtc->state->enable) {
162 /* set STAGE_UNUSED for all layers */
163 mdp5_ctl_blend(mdp5_crtc->ctl, NULL, 0, 0);
164 mdp5_crtc->ctl = NULL;
168 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
170 struct mdp5_crtc *mdp5_crtc =
171 container_of(work, struct mdp5_crtc, unref_cursor_work);
172 struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base);
174 msm_gem_put_iova(val, mdp5_kms->id);
175 drm_gem_object_unreference_unlocked(val);
178 static void mdp5_crtc_destroy(struct drm_crtc *crtc)
180 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
182 drm_crtc_cleanup(crtc);
183 drm_flip_work_cleanup(&mdp5_crtc->unref_cursor_work);
189 * blend_setup() - blend all the planes of a CRTC
191 * If no base layer is available, border will be enabled as the base layer.
192 * Otherwise all layers will be blended based on their stage calculated
193 * in mdp5_crtc_atomic_check.
195 static void blend_setup(struct drm_crtc *crtc)
197 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
198 struct mdp5_kms *mdp5_kms = get_kms(crtc);
199 struct drm_plane *plane;
200 const struct mdp5_cfg_hw *hw_cfg;
201 struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
202 const struct mdp_format *format;
203 uint32_t lm = mdp5_crtc->lm;
204 uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0;
206 uint8_t stage[STAGE_MAX + 1];
207 int i, plane_cnt = 0;
208 #define blender(stage) ((stage) - STAGE0)
210 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
212 spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
214 /* ctl could be released already when we are shutting down: */
218 /* Collect all plane information */
219 drm_atomic_crtc_for_each_plane(plane, crtc) {
220 pstate = to_mdp5_plane_state(plane->state);
221 pstates[pstate->stage] = pstate;
222 stage[pstate->stage] = mdp5_plane_pipe(plane);
227 * If there is no base layer, enable border color.
228 * Although it's not possbile in current blend logic,
229 * put it here as a reminder.
231 if (!pstates[STAGE_BASE] && plane_cnt) {
232 ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
233 DBG("Border Color is enabled");
236 /* The reset for blending */
237 for (i = STAGE0; i <= STAGE_MAX; i++) {
241 format = to_mdp_format(
242 msm_framebuffer_format(pstates[i]->base.fb));
243 plane = pstates[i]->base.plane;
244 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
245 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
246 fg_alpha = pstates[i]->alpha;
247 bg_alpha = 0xFF - pstates[i]->alpha;
248 DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha);
250 if (format->alpha_enable && pstates[i]->premultiplied) {
251 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
252 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
253 if (fg_alpha != 0xff) {
256 MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
257 MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
259 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
261 } else if (format->alpha_enable) {
262 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) |
263 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
264 if (fg_alpha != 0xff) {
267 MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA |
268 MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA |
269 MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
270 MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
272 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
276 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm,
277 blender(i)), blend_op);
278 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm,
279 blender(i)), fg_alpha);
280 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm,
281 blender(i)), bg_alpha);
284 mdp5_ctl_blend(mdp5_crtc->ctl, stage, plane_cnt, ctl_blend_flags);
287 spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
290 static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc)
292 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
293 struct mdp5_kms *mdp5_kms = get_kms(crtc);
295 struct drm_display_mode *mode;
297 if (WARN_ON(!crtc->state))
300 mode = &crtc->state->adjusted_mode;
302 DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
303 mdp5_crtc->name, mode->base.id, mode->name,
304 mode->vrefresh, mode->clock,
305 mode->hdisplay, mode->hsync_start,
306 mode->hsync_end, mode->htotal,
307 mode->vdisplay, mode->vsync_start,
308 mode->vsync_end, mode->vtotal,
309 mode->type, mode->flags);
311 spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
312 mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(mdp5_crtc->lm),
313 MDP5_LM_OUT_SIZE_WIDTH(mode->hdisplay) |
314 MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
315 spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
318 static void mdp5_crtc_disable(struct drm_crtc *crtc)
320 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
321 struct mdp5_kms *mdp5_kms = get_kms(crtc);
323 DBG("%s", mdp5_crtc->name);
325 if (WARN_ON(!mdp5_crtc->enabled))
328 if (mdp5_crtc->cmd_mode)
329 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done);
331 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err);
332 mdp5_disable(mdp5_kms);
334 mdp5_crtc->enabled = false;
337 static void mdp5_crtc_enable(struct drm_crtc *crtc)
339 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
340 struct mdp5_kms *mdp5_kms = get_kms(crtc);
342 DBG("%s", mdp5_crtc->name);
344 if (WARN_ON(mdp5_crtc->enabled))
347 mdp5_enable(mdp5_kms);
348 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);
350 if (mdp5_crtc->cmd_mode)
351 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done);
353 mdp5_crtc->enabled = true;
357 struct drm_plane *plane;
358 struct mdp5_plane_state *state;
361 static int pstate_cmp(const void *a, const void *b)
363 struct plane_state *pa = (struct plane_state *)a;
364 struct plane_state *pb = (struct plane_state *)b;
365 return pa->state->zpos - pb->state->zpos;
368 static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
369 struct drm_crtc_state *state)
371 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
372 struct mdp5_kms *mdp5_kms = get_kms(crtc);
373 struct drm_plane *plane;
374 struct drm_device *dev = crtc->dev;
375 struct plane_state pstates[STAGE_MAX + 1];
376 const struct mdp5_cfg_hw *hw_cfg;
379 DBG("%s: check", mdp5_crtc->name);
381 /* verify that there are not too many planes attached to crtc
382 * and that we don't have conflicting mixer stages:
384 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
385 drm_atomic_crtc_state_for_each_plane(plane, state) {
386 struct drm_plane_state *pstate;
387 if (cnt >= (hw_cfg->lm.nb_stages)) {
388 dev_err(dev->dev, "too many planes!\n");
392 pstate = state->state->plane_states[drm_plane_index(plane)];
394 /* plane might not have changed, in which case take
398 pstate = plane->state;
399 pstates[cnt].plane = plane;
400 pstates[cnt].state = to_mdp5_plane_state(pstate);
405 /* assign a stage based on sorted zpos property */
406 sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
408 for (i = 0; i < cnt; i++) {
409 pstates[i].state->stage = STAGE_BASE + i;
410 DBG("%s: assign pipe %s on stage=%d", mdp5_crtc->name,
411 pipe2name(mdp5_plane_pipe(pstates[i].plane)),
412 pstates[i].state->stage);
418 static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc,
419 struct drm_crtc_state *old_crtc_state)
421 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
422 DBG("%s: begin", mdp5_crtc->name);
425 static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc,
426 struct drm_crtc_state *old_crtc_state)
428 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
429 struct drm_device *dev = crtc->dev;
432 DBG("%s: event: %p", mdp5_crtc->name, crtc->state->event);
434 WARN_ON(mdp5_crtc->event);
436 spin_lock_irqsave(&dev->event_lock, flags);
437 mdp5_crtc->event = crtc->state->event;
438 spin_unlock_irqrestore(&dev->event_lock, flags);
441 * If no CTL has been allocated in mdp5_crtc_atomic_check(),
442 * it means we are trying to flush a CRTC whose state is disabled:
443 * nothing else needs to be done.
445 if (unlikely(!mdp5_crtc->ctl))
450 /* PP_DONE irq is only used by command mode for now.
451 * It is better to request pending before FLUSH and START trigger
452 * to make sure no pp_done irq missed.
453 * This is safe because no pp_done will happen before SW trigger
456 if (mdp5_crtc->cmd_mode)
457 request_pp_done_pending(crtc);
459 mdp5_crtc->flushed_mask = crtc_flush_all(crtc);
461 request_pending(crtc, PENDING_FLIP);
464 static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h)
466 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
467 uint32_t xres = crtc->mode.hdisplay;
468 uint32_t yres = crtc->mode.vdisplay;
471 * Cursor Region Of Interest (ROI) is a plane read from cursor
472 * buffer to render. The ROI region is determined by the visibility of
473 * the cursor point. In the default Cursor image the cursor point will
474 * be at the top left of the cursor image, unless it is specified
475 * otherwise using hotspot feature.
477 * If the cursor point reaches the right (xres - x < cursor.width) or
478 * bottom (yres - y < cursor.height) boundary of the screen, then ROI
479 * width and ROI height need to be evaluated to crop the cursor image
481 * (xres-x) will be new cursor width when x > (xres - cursor.width)
482 * (yres-y) will be new cursor height when y > (yres - cursor.height)
484 *roi_w = min(mdp5_crtc->cursor.width, xres -
485 mdp5_crtc->cursor.x);
486 *roi_h = min(mdp5_crtc->cursor.height, yres -
487 mdp5_crtc->cursor.y);
490 static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
491 struct drm_file *file, uint32_t handle,
492 uint32_t width, uint32_t height)
494 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
495 struct drm_device *dev = crtc->dev;
496 struct mdp5_kms *mdp5_kms = get_kms(crtc);
497 struct drm_gem_object *cursor_bo, *old_bo = NULL;
498 uint32_t blendcfg, cursor_addr, stride;
501 enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
502 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
503 uint32_t roi_w, roi_h;
504 bool cursor_enable = true;
507 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
508 dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
512 if (NULL == mdp5_crtc->ctl)
517 cursor_enable = false;
521 cursor_bo = drm_gem_object_lookup(file, handle);
525 ret = msm_gem_get_iova(cursor_bo, mdp5_kms->id, &cursor_addr);
530 drm_fb_get_bpp_depth(DRM_FORMAT_ARGB8888, &depth, &bpp);
531 stride = width * (bpp >> 3);
533 spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
534 old_bo = mdp5_crtc->cursor.scanout_bo;
536 mdp5_crtc->cursor.scanout_bo = cursor_bo;
537 mdp5_crtc->cursor.width = width;
538 mdp5_crtc->cursor.height = height;
540 get_roi(crtc, &roi_w, &roi_h);
542 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
543 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
544 MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888));
545 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),
546 MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) |
547 MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width));
548 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
549 MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
550 MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
551 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm), cursor_addr);
553 blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN;
554 blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha);
555 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);
557 spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
560 ret = mdp5_ctl_set_cursor(mdp5_crtc->ctl, 0, cursor_enable);
562 dev_err(dev->dev, "failed to %sable cursor: %d\n",
563 cursor_enable ? "en" : "dis", ret);
567 crtc_flush(crtc, flush_mask);
571 drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo);
572 /* enable vblank to complete cursor work: */
573 request_pending(crtc, PENDING_CURSOR);
578 static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
580 struct mdp5_kms *mdp5_kms = get_kms(crtc);
581 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
582 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
587 /* In case the CRTC is disabled, just drop the cursor update */
588 if (unlikely(!crtc->state->enable))
591 mdp5_crtc->cursor.x = x = max(x, 0);
592 mdp5_crtc->cursor.y = y = max(y, 0);
594 get_roi(crtc, &roi_w, &roi_h);
596 spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
597 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(mdp5_crtc->lm),
598 MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
599 MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
600 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(mdp5_crtc->lm),
601 MDP5_LM_CURSOR_START_XY_Y_START(y) |
602 MDP5_LM_CURSOR_START_XY_X_START(x));
603 spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
605 crtc_flush(crtc, flush_mask);
610 static const struct drm_crtc_funcs mdp5_crtc_funcs = {
611 .set_config = drm_atomic_helper_set_config,
612 .destroy = mdp5_crtc_destroy,
613 .page_flip = drm_atomic_helper_page_flip,
614 .set_property = drm_atomic_helper_crtc_set_property,
615 .reset = drm_atomic_helper_crtc_reset,
616 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
617 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
618 .cursor_set = mdp5_crtc_cursor_set,
619 .cursor_move = mdp5_crtc_cursor_move,
622 static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = {
623 .mode_set_nofb = mdp5_crtc_mode_set_nofb,
624 .disable = mdp5_crtc_disable,
625 .enable = mdp5_crtc_enable,
626 .atomic_check = mdp5_crtc_atomic_check,
627 .atomic_begin = mdp5_crtc_atomic_begin,
628 .atomic_flush = mdp5_crtc_atomic_flush,
631 static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
633 struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, vblank);
634 struct drm_crtc *crtc = &mdp5_crtc->base;
635 struct msm_drm_private *priv = crtc->dev->dev_private;
638 mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank);
640 pending = atomic_xchg(&mdp5_crtc->pending, 0);
642 if (pending & PENDING_FLIP) {
643 complete_flip(crtc, NULL);
646 if (pending & PENDING_CURSOR)
647 drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->wq);
650 static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
652 struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err);
654 DBG("%s: error: %08x", mdp5_crtc->name, irqstatus);
657 static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus)
659 struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc,
662 complete(&mdp5_crtc->pp_completion);
665 static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc)
667 struct drm_device *dev = crtc->dev;
668 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
671 ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
672 msecs_to_jiffies(50));
674 dev_warn(dev->dev, "pp done time out, lm=%d\n", mdp5_crtc->lm);
677 static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)
679 struct drm_device *dev = crtc->dev;
680 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
683 /* Should not call this function if crtc is disabled. */
687 ret = drm_crtc_vblank_get(crtc);
691 ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
692 ((mdp5_ctl_get_commit_status(mdp5_crtc->ctl) &
693 mdp5_crtc->flushed_mask) == 0),
694 msecs_to_jiffies(50));
696 dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp5_crtc->id);
698 mdp5_crtc->flushed_mask = 0;
700 drm_crtc_vblank_put(crtc);
703 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc)
705 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
706 return mdp5_crtc->vblank.irqmask;
709 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc,
710 struct mdp5_interface *intf, struct mdp5_ctl *ctl)
712 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
713 struct mdp5_kms *mdp5_kms = get_kms(crtc);
714 int lm = mdp5_crtc_get_lm(crtc);
716 /* now that we know what irq's we want: */
717 mdp5_crtc->err.irqmask = intf2err(intf->num);
718 mdp5_crtc->vblank.irqmask = intf2vblank(lm, intf);
720 if ((intf->type == INTF_DSI) &&
721 (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) {
722 mdp5_crtc->pp_done.irqmask = lm2ppdone(lm);
723 mdp5_crtc->pp_done.irq = mdp5_crtc_pp_done_irq;
724 mdp5_crtc->cmd_mode = true;
726 mdp5_crtc->pp_done.irqmask = 0;
727 mdp5_crtc->pp_done.irq = NULL;
728 mdp5_crtc->cmd_mode = false;
731 mdp_irq_update(&mdp5_kms->base);
733 mdp5_crtc->ctl = ctl;
734 mdp5_ctl_set_pipeline(ctl, intf, lm);
737 int mdp5_crtc_get_lm(struct drm_crtc *crtc)
739 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
740 return WARN_ON(!crtc) ? -EINVAL : mdp5_crtc->lm;
743 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc)
745 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
747 if (mdp5_crtc->cmd_mode)
748 mdp5_crtc_wait_for_pp_done(crtc);
750 mdp5_crtc_wait_for_flush_done(crtc);
753 /* initialize crtc */
754 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
755 struct drm_plane *plane, int id)
757 struct drm_crtc *crtc = NULL;
758 struct mdp5_crtc *mdp5_crtc;
760 mdp5_crtc = kzalloc(sizeof(*mdp5_crtc), GFP_KERNEL);
762 return ERR_PTR(-ENOMEM);
764 crtc = &mdp5_crtc->base;
767 mdp5_crtc->lm = GET_LM_ID(id);
769 spin_lock_init(&mdp5_crtc->lm_lock);
770 spin_lock_init(&mdp5_crtc->cursor.lock);
771 init_completion(&mdp5_crtc->pp_completion);
773 mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq;
774 mdp5_crtc->err.irq = mdp5_crtc_err_irq;
776 snprintf(mdp5_crtc->name, sizeof(mdp5_crtc->name), "%s:%d",
777 pipe2name(mdp5_plane_pipe(plane)), id);
779 drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp5_crtc_funcs,
782 drm_flip_work_init(&mdp5_crtc->unref_cursor_work,
783 "unref cursor", unref_cursor_worker);
785 drm_crtc_helper_add(crtc, &mdp5_crtc_helper_funcs);