drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include <engine/fifo.h>
  25
  26 #include <core/client.h>
  27 #include <core/engctx.h>
  28 #include <core/enum.h>
  29 #include <core/handle.h>
  30 #include <subdev/bar.h>
  31 #include <subdev/fb.h>
  32 #include <subdev/mmu.h>
  33 #include <subdev/timer.h>
  34
  35 #include <nvif/class.h>
  36 #include <nvif/unpack.h>
  37
  38 struct gf100_fifo {
  39         struct nvkm_fifo base;
  40
  41         struct work_struct fault;
  42         u64 mask;
  43
  44         struct {
  45                 struct nvkm_gpuobj *mem[2];
  46                 int active;
  47                 wait_queue_head_t wait;
  48         } runlist;
  49
  50         struct {
  51                 struct nvkm_gpuobj *mem;
  52                 struct nvkm_vma bar;
  53         } user;
  54         int spoon_nr;
  55 };
  56
  57 struct gf100_fifo_base {
  58         struct nvkm_fifo_base base;
  59         struct nvkm_gpuobj *pgd;
  60         struct nvkm_vm *vm;
  61 };
  62
  63 struct gf100_fifo_chan {
  64         struct nvkm_fifo_chan base;
  65         enum {
  66                 STOPPED,
  67                 RUNNING,
  68                 KILLED
  69         } state;
  70 };
  71
  72 /*******************************************************************************
  73  * FIFO channel objects
  74  ******************************************************************************/
  75
  76 static void
  77 gf100_fifo_runlist_update(struct gf100_fifo *fifo)
  78 {
  79         struct nvkm_device *device = fifo->base.engine.subdev.device;
  80         struct nvkm_bar *bar = device->bar;
  81         struct nvkm_gpuobj *cur;
  82         int i, p;
  83
  84         mutex_lock(&nv_subdev(fifo)->mutex);
  85         cur = fifo->runlist.mem[fifo->runlist.active];
  86         fifo->runlist.active = !fifo->runlist.active;
  87
  88         for (i = 0, p = 0; i < 128; i++) {
  89                 struct gf100_fifo_chan *chan = (void *)fifo->base.channel[i];
  90                 if (chan && chan->state == RUNNING) {
  91                         nv_wo32(cur, p + 0, i);
  92                         nv_wo32(cur, p + 4, 0x00000004);
  93                         p += 8;
  94                 }
  95         }
  96         bar->flush(bar);
  97
  98         nvkm_wr32(device, 0x002270, cur->addr >> 12);
  99         nvkm_wr32(device, 0x002274, 0x01f00000 | (p >> 3));
 100
 101         if (wait_event_timeout(fifo->runlist.wait,
 102                                !(nvkm_rd32(device, 0x00227c) & 0x00100000),
 103                                msecs_to_jiffies(2000)) == 0)
 104                 nv_error(fifo, "runlist update timeout\n");
 105         mutex_unlock(&nv_subdev(fifo)->mutex);
 106 }
 107
 108 static int
 109 gf100_fifo_context_attach(struct nvkm_object *parent,
 110                           struct nvkm_object *object)
 111 {
 112         struct nvkm_bar *bar = nvkm_bar(parent);
 113         struct gf100_fifo_base *base = (void *)parent->parent;
 114         struct nvkm_engctx *ectx = (void *)object;
 115         u32 addr;
 116         int ret;
 117
 118         switch (nv_engidx(object->engine)) {
 119         case NVDEV_ENGINE_SW    : return 0;
 120         case NVDEV_ENGINE_GR    : addr = 0x0210; break;
 121         case NVDEV_ENGINE_CE0   : addr = 0x0230; break;
 122         case NVDEV_ENGINE_CE1   : addr = 0x0240; break;
 123         case NVDEV_ENGINE_MSVLD : addr = 0x0270; break;
 124         case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break;
 125         case NVDEV_ENGINE_MSPPP : addr = 0x0260; break;
 126         default:
 127                 return -EINVAL;
 128         }
 129
 130         if (!ectx->vma.node) {
 131                 ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
 132                                          NV_MEM_ACCESS_RW, &ectx->vma);
 133                 if (ret)
 134                         return ret;
 135
 136                 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
 137         }
 138
 139         nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
 140         nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));
 141         bar->flush(bar);
 142         return 0;
 143 }
 144
 145 static int
 146 gf100_fifo_context_detach(struct nvkm_object *parent, bool suspend,
 147                           struct nvkm_object *object)
 148 {
 149         struct gf100_fifo *fifo = (void *)parent->engine;
 150         struct gf100_fifo_base *base = (void *)parent->parent;
 151         struct gf100_fifo_chan *chan = (void *)parent;
 152         struct nvkm_device *device = fifo->base.engine.subdev.device;
 153         struct nvkm_bar *bar = device->bar;
 154         u32 addr;
 155
 156         switch (nv_engidx(object->engine)) {
 157         case NVDEV_ENGINE_SW    : return 0;
 158         case NVDEV_ENGINE_GR    : addr = 0x0210; break;
 159         case NVDEV_ENGINE_CE0   : addr = 0x0230; break;
 160         case NVDEV_ENGINE_CE1   : addr = 0x0240; break;
 161         case NVDEV_ENGINE_MSVLD : addr = 0x0270; break;
 162         case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break;
 163         case NVDEV_ENGINE_MSPPP : addr = 0x0260; break;
 164         default:
 165                 return -EINVAL;
 166         }
 167
 168         nvkm_wr32(device, 0x002634, chan->base.chid);
 169         if (nvkm_msec(device, 2000,
 170                 if (nvkm_rd32(device, 0x002634) == chan->base.chid)
 171                         break;
 172         ) < 0) {
 173                 nv_error(fifo, "channel %d [%s] kick timeout\n",
 174                          chan->base.chid, nvkm_client_name(chan));
 175                 if (suspend)
 176                         return -EBUSY;
 177         }
 178
 179         nv_wo32(base, addr + 0x00, 0x00000000);
 180         nv_wo32(base, addr + 0x04, 0x00000000);
 181         bar->flush(bar);
 182         return 0;
 183 }
 184
 185 static int
 186 gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 187                      struct nvkm_oclass *oclass, void *data, u32 size,
 188                      struct nvkm_object **pobject)
 189 {
 190         union {
 191                 struct nv50_channel_gpfifo_v0 v0;
 192         } *args = data;
 193         struct nvkm_bar *bar = nvkm_bar(parent);
 194         struct gf100_fifo *fifo = (void *)engine;
 195         struct gf100_fifo_base *base = (void *)parent;
 196         struct gf100_fifo_chan *chan;
 197         u64 usermem, ioffset, ilength;
 198         int ret, i;
 199
 200         nv_ioctl(parent, "create channel gpfifo size %d\n", size);
 201         if (nvif_unpack(args->v0, 0, 0, false)) {
 202                 nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x "
 203                                  "ioffset %016llx ilength %08x\n",
 204                          args->v0.version, args->v0.pushbuf, args->v0.ioffset,
 205                          args->v0.ilength);
 206         } else
 207                 return ret;
 208
 209         ret = nvkm_fifo_channel_create(parent, engine, oclass, 1,
 210                                        fifo->user.bar.offset, 0x1000,
 211                                        args->v0.pushbuf,
 212                                        (1ULL << NVDEV_ENGINE_SW) |
 213                                        (1ULL << NVDEV_ENGINE_GR) |
 214                                        (1ULL << NVDEV_ENGINE_CE0) |
 215                                        (1ULL << NVDEV_ENGINE_CE1) |
 216                                        (1ULL << NVDEV_ENGINE_MSVLD) |
 217                                        (1ULL << NVDEV_ENGINE_MSPDEC) |
 218                                        (1ULL << NVDEV_ENGINE_MSPPP), &chan);
 219         *pobject = nv_object(chan);
 220         if (ret)
 221                 return ret;
 222
 223         args->v0.chid = chan->base.chid;
 224
 225         nv_parent(chan)->context_attach = gf100_fifo_context_attach;
 226         nv_parent(chan)->context_detach = gf100_fifo_context_detach;
 227
 228         usermem = chan->base.chid * 0x1000;
 229         ioffset = args->v0.ioffset;
 230         ilength = order_base_2(args->v0.ilength / 8);
 231
 232         for (i = 0; i < 0x1000; i += 4)
 233                 nv_wo32(fifo->user.mem, usermem + i, 0x00000000);
 234
 235         nv_wo32(base, 0x08, lower_32_bits(fifo->user.mem->addr + usermem));
 236         nv_wo32(base, 0x0c, upper_32_bits(fifo->user.mem->addr + usermem));
 237         nv_wo32(base, 0x10, 0x0000face);
 238         nv_wo32(base, 0x30, 0xfffff902);
 239         nv_wo32(base, 0x48, lower_32_bits(ioffset));
 240         nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));
 241         nv_wo32(base, 0x54, 0x00000002);
 242         nv_wo32(base, 0x84, 0x20400000);
 243         nv_wo32(base, 0x94, 0x30000001);
 244         nv_wo32(base, 0x9c, 0x00000100);
 245         nv_wo32(base, 0xa4, 0x1f1f1f1f);
 246         nv_wo32(base, 0xa8, 0x1f1f1f1f);
 247         nv_wo32(base, 0xac, 0x0000001f);
 248         nv_wo32(base, 0xb8, 0xf8000000);
 249         nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */
 250         nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */
 251         bar->flush(bar);
 252         return 0;
 253 }
 254
 255 static int
 256 gf100_fifo_chan_init(struct nvkm_object *object)
 257 {
 258         struct nvkm_gpuobj *base = nv_gpuobj(object->parent);
 259         struct gf100_fifo *fifo = (void *)object->engine;
 260         struct gf100_fifo_chan *chan = (void *)object;
 261         struct nvkm_device *device = fifo->base.engine.subdev.device;
 262         u32 chid = chan->base.chid;
 263         int ret;
 264
 265         ret = nvkm_fifo_channel_init(&chan->base);
 266         if (ret)
 267                 return ret;
 268
 269         nvkm_wr32(device, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12);
 270
 271         if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) {
 272                 nvkm_wr32(device, 0x003004 + (chid * 8), 0x001f0001);
 273                 gf100_fifo_runlist_update(fifo);
 274         }
 275
 276         return 0;
 277 }
 278
 279 static void gf100_fifo_intr_engine(struct gf100_fifo *fifo);
 280
 281 static int
 282 gf100_fifo_chan_fini(struct nvkm_object *object, bool suspend)
 283 {
 284         struct gf100_fifo *fifo = (void *)object->engine;
 285         struct gf100_fifo_chan *chan = (void *)object;
 286         struct nvkm_device *device = fifo->base.engine.subdev.device;
 287         u32 chid = chan->base.chid;
 288
 289         if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) {
 290                 nvkm_mask(device, 0x003004 + (chid * 8), 0x00000001, 0x00000000);
 291                 gf100_fifo_runlist_update(fifo);
 292         }
 293
 294         gf100_fifo_intr_engine(fifo);
 295
 296         nvkm_wr32(device, 0x003000 + (chid * 8), 0x00000000);
 297         return nvkm_fifo_channel_fini(&chan->base, suspend);
 298 }
 299
 300 static struct nvkm_ofuncs
 301 gf100_fifo_ofuncs = {
 302         .ctor = gf100_fifo_chan_ctor,
 303         .dtor = _nvkm_fifo_channel_dtor,
 304         .init = gf100_fifo_chan_init,
 305         .fini = gf100_fifo_chan_fini,
 306         .map  = _nvkm_fifo_channel_map,
 307         .rd32 = _nvkm_fifo_channel_rd32,
 308         .wr32 = _nvkm_fifo_channel_wr32,
 309         .ntfy = _nvkm_fifo_channel_ntfy
 310 };
 311
 312 static struct nvkm_oclass
 313 gf100_fifo_sclass[] = {
 314         { FERMI_CHANNEL_GPFIFO, &gf100_fifo_ofuncs },
 315         {}
 316 };
 317
 318 /*******************************************************************************
 319  * FIFO context - instmem heap and vm setup
 320  ******************************************************************************/
 321
 322 static int
 323 gf100_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 324                         struct nvkm_oclass *oclass, void *data, u32 size,
 325                         struct nvkm_object **pobject)
 326 {
 327         struct gf100_fifo_base *base;
 328         int ret;
 329
 330         ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
 331                                        0x1000, NVOBJ_FLAG_ZERO_ALLOC |
 332                                        NVOBJ_FLAG_HEAP, &base);
 333         *pobject = nv_object(base);
 334         if (ret)
 335                 return ret;
 336
 337         ret = nvkm_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
 338                               &base->pgd);
 339         if (ret)
 340                 return ret;
 341
 342         nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
 343         nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
 344         nv_wo32(base, 0x0208, 0xffffffff);
 345         nv_wo32(base, 0x020c, 0x000000ff);
 346
 347         ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd);
 348         if (ret)
 349                 return ret;
 350
 351         return 0;
 352 }
 353
 354 static void
 355 gf100_fifo_context_dtor(struct nvkm_object *object)
 356 {
 357         struct gf100_fifo_base *base = (void *)object;
 358         nvkm_vm_ref(NULL, &base->vm, base->pgd);
 359         nvkm_gpuobj_ref(NULL, &base->pgd);
 360         nvkm_fifo_context_destroy(&base->base);
 361 }
 362
 363 static struct nvkm_oclass
 364 gf100_fifo_cclass = {
 365         .handle = NV_ENGCTX(FIFO, 0xc0),
 366         .ofuncs = &(struct nvkm_ofuncs) {
 367                 .ctor = gf100_fifo_context_ctor,
 368                 .dtor = gf100_fifo_context_dtor,
 369                 .init = _nvkm_fifo_context_init,
 370                 .fini = _nvkm_fifo_context_fini,
 371                 .rd32 = _nvkm_fifo_context_rd32,
 372                 .wr32 = _nvkm_fifo_context_wr32,
 373         },
 374 };
 375
 376 /*******************************************************************************
 377  * PFIFO engine
 378  ******************************************************************************/
 379
 380 static inline int
 381 gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn)
 382 {
 383         switch (engn) {
 384         case NVDEV_ENGINE_GR    : engn = 0; break;
 385         case NVDEV_ENGINE_MSVLD : engn = 1; break;
 386         case NVDEV_ENGINE_MSPPP : engn = 2; break;
 387         case NVDEV_ENGINE_MSPDEC: engn = 3; break;
 388         case NVDEV_ENGINE_CE0   : engn = 4; break;
 389         case NVDEV_ENGINE_CE1   : engn = 5; break;
 390         default:
 391                 return -1;
 392         }
 393
 394         return engn;
 395 }
 396
 397 static inline struct nvkm_engine *
 398 gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn)
 399 {
 400         switch (engn) {
 401         case 0: engn = NVDEV_ENGINE_GR; break;
 402         case 1: engn = NVDEV_ENGINE_MSVLD; break;
 403         case 2: engn = NVDEV_ENGINE_MSPPP; break;
 404         case 3: engn = NVDEV_ENGINE_MSPDEC; break;
 405         case 4: engn = NVDEV_ENGINE_CE0; break;
 406         case 5: engn = NVDEV_ENGINE_CE1; break;
 407         default:
 408                 return NULL;
 409         }
 410
 411         return nvkm_engine(fifo, engn);
 412 }
 413
 414 static void
 415 gf100_fifo_recover_work(struct work_struct *work)
 416 {
 417         struct gf100_fifo *fifo = container_of(work, typeof(*fifo), fault);
 418         struct nvkm_device *device = fifo->base.engine.subdev.device;
 419         struct nvkm_object *engine;
 420         unsigned long flags;
 421         u32 engn, engm = 0;
 422         u64 mask, todo;
 423
 424         spin_lock_irqsave(&fifo->base.lock, flags);
 425         mask = fifo->mask;
 426         fifo->mask = 0ULL;
 427         spin_unlock_irqrestore(&fifo->base.lock, flags);
 428
 429         for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn))
 430                 engm |= 1 << gf100_fifo_engidx(fifo, engn);
 431         nvkm_mask(device, 0x002630, engm, engm);
 432
 433         for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) {
 434                 if ((engine = (void *)nvkm_engine(fifo, engn))) {
 435                         nv_ofuncs(engine)->fini(engine, false);
 436                         WARN_ON(nv_ofuncs(engine)->init(engine));
 437                 }
 438         }
 439
 440         gf100_fifo_runlist_update(fifo);
 441         nvkm_wr32(device, 0x00262c, engm);
 442         nvkm_mask(device, 0x002630, engm, 0x00000000);
 443 }
 444
 445 static void
 446 gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine,
 447                    struct gf100_fifo_chan *chan)
 448 {
 449         struct nvkm_device *device = fifo->base.engine.subdev.device;
 450         u32 chid = chan->base.chid;
 451         unsigned long flags;
 452
 453         nv_error(fifo, "%s engine fault on channel %d, recovering...\n",
 454                        nv_subdev(engine)->name, chid);
 455
 456         nvkm_mask(device, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000);
 457         chan->state = KILLED;
 458
 459         spin_lock_irqsave(&fifo->base.lock, flags);
 460         fifo->mask |= 1ULL << nv_engidx(engine);
 461         spin_unlock_irqrestore(&fifo->base.lock, flags);
 462         schedule_work(&fifo->fault);
 463 }
 464
 465 static int
 466 gf100_fifo_swmthd(struct gf100_fifo *fifo, u32 chid, u32 mthd, u32 data)
 467 {
 468         struct gf100_fifo_chan *chan = NULL;
 469         struct nvkm_handle *bind;
 470         unsigned long flags;
 471         int ret = -EINVAL;
 472
 473         spin_lock_irqsave(&fifo->base.lock, flags);
 474         if (likely(chid >= fifo->base.min && chid <= fifo->base.max))
 475                 chan = (void *)fifo->base.channel[chid];
 476         if (unlikely(!chan))
 477                 goto out;
 478
 479         bind = nvkm_namedb_get_class(nv_namedb(chan), 0x906e);
 480         if (likely(bind)) {
 481                 if (!mthd || !nv_call(bind->object, mthd, data))
 482                         ret = 0;
 483                 nvkm_namedb_put(bind);
 484         }
 485
 486 out:
 487         spin_unlock_irqrestore(&fifo->base.lock, flags);
 488         return ret;
 489 }
 490
 491 static const struct nvkm_enum
 492 gf100_fifo_sched_reason[] = {
 493         { 0x0a, "CTXSW_TIMEOUT" },
 494         {}
 495 };
 496
 497 static void
 498 gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo)
 499 {
 500         struct nvkm_device *device = fifo->base.engine.subdev.device;
 501         struct nvkm_engine *engine;
 502         struct gf100_fifo_chan *chan;
 503         u32 engn;
 504
 505         for (engn = 0; engn < 6; engn++) {
 506                 u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04));
 507                 u32 busy = (stat & 0x80000000);
 508                 u32 save = (stat & 0x00100000); /* maybe? */
 509                 u32 unk0 = (stat & 0x00040000);
 510                 u32 unk1 = (stat & 0x00001000);
 511                 u32 chid = (stat & 0x0000007f);
 512                 (void)save;
 513
 514                 if (busy && unk0 && unk1) {
 515                         if (!(chan = (void *)fifo->base.channel[chid]))
 516                                 continue;
 517                         if (!(engine = gf100_fifo_engine(fifo, engn)))
 518                                 continue;
 519                         gf100_fifo_recover(fifo, engine, chan);
 520                 }
 521         }
 522 }
 523
 524 static void
 525 gf100_fifo_intr_sched(struct gf100_fifo *fifo)
 526 {
 527         struct nvkm_device *device = fifo->base.engine.subdev.device;
 528         u32 intr = nvkm_rd32(device, 0x00254c);
 529         u32 code = intr & 0x000000ff;
 530         const struct nvkm_enum *en;
 531         char enunk[6] = "";
 532
 533         en = nvkm_enum_find(gf100_fifo_sched_reason, code);
 534         if (!en)
 535                 snprintf(enunk, sizeof(enunk), "UNK%02x", code);
 536
 537         nv_error(fifo, "SCHED_ERROR [ %s ]\n", en ? en->name : enunk);
 538
 539         switch (code) {
 540         case 0x0a:
 541                 gf100_fifo_intr_sched_ctxsw(fifo);
 542                 break;
 543         default:
 544                 break;
 545         }
 546 }
 547
 548 static const struct nvkm_enum
 549 gf100_fifo_fault_engine[] = {
 550         { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR },
 551         { 0x03, "PEEPHOLE", NULL, NVDEV_ENGINE_IFB },
 552         { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR },
 553         { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
 554         { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
 555         { 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD },
 556         { 0x11, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP },
 557         { 0x13, "PCOUNTER" },
 558         { 0x14, "PMSPDEC", NULL, NVDEV_ENGINE_MSPDEC },
 559         { 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 },
 560         { 0x16, "PCE1", NULL, NVDEV_ENGINE_CE1 },
 561         { 0x17, "PDAEMON" },
 562         {}
 563 };
 564
 565 static const struct nvkm_enum
 566 gf100_fifo_fault_reason[] = {
 567         { 0x00, "PT_NOT_PRESENT" },
 568         { 0x01, "PT_TOO_SHORT" },
 569         { 0x02, "PAGE_NOT_PRESENT" },
 570         { 0x03, "VM_LIMIT_EXCEEDED" },
 571         { 0x04, "NO_CHANNEL" },
 572         { 0x05, "PAGE_SYSTEM_ONLY" },
 573         { 0x06, "PAGE_READ_ONLY" },
 574         { 0x0a, "COMPRESSED_SYSRAM" },
 575         { 0x0c, "INVALID_STORAGE_TYPE" },
 576         {}
 577 };
 578
 579 static const struct nvkm_enum
 580 gf100_fifo_fault_hubclient[] = {
 581         { 0x01, "PCOPY0" },
 582         { 0x02, "PCOPY1" },
 583         { 0x04, "DISPATCH" },
 584         { 0x05, "CTXCTL" },
 585         { 0x06, "PFIFO" },
 586         { 0x07, "BAR_READ" },
 587         { 0x08, "BAR_WRITE" },
 588         { 0x0b, "PVP" },
 589         { 0x0c, "PMSPPP" },
 590         { 0x0d, "PMSVLD" },
 591         { 0x11, "PCOUNTER" },
 592         { 0x12, "PDAEMON" },
 593         { 0x14, "CCACHE" },
 594         { 0x15, "CCACHE_POST" },
 595         {}
 596 };
 597
 598 static const struct nvkm_enum
 599 gf100_fifo_fault_gpcclient[] = {
 600         { 0x01, "TEX" },
 601         { 0x0c, "ESETUP" },
 602         { 0x0e, "CTXCTL" },
 603         { 0x0f, "PROP" },
 604         {}
 605 };
 606
 607 static void
 608 gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit)
 609 {
 610         struct nvkm_device *device = fifo->base.engine.subdev.device;
 611         u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
 612         u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
 613         u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
 614         u32 stat = nvkm_rd32(device, 0x00280c + (unit * 0x10));
 615         u32 gpc    = (stat & 0x1f000000) >> 24;
 616         u32 client = (stat & 0x00001f00) >> 8;
 617         u32 write  = (stat & 0x00000080);
 618         u32 hub    = (stat & 0x00000040);
 619         u32 reason = (stat & 0x0000000f);
 620         struct nvkm_object *engctx = NULL, *object;
 621         struct nvkm_engine *engine = NULL;
 622         const struct nvkm_enum *er, *eu, *ec;
 623         char erunk[6] = "";
 624         char euunk[6] = "";
 625         char ecunk[6] = "";
 626         char gpcid[3] = "";
 627
 628         er = nvkm_enum_find(gf100_fifo_fault_reason, reason);
 629         if (!er)
 630                 snprintf(erunk, sizeof(erunk), "UNK%02X", reason);
 631
 632         eu = nvkm_enum_find(gf100_fifo_fault_engine, unit);
 633         if (eu) {
 634                 switch (eu->data2) {
 635                 case NVDEV_SUBDEV_BAR:
 636                         nvkm_mask(device, 0x001704, 0x00000000, 0x00000000);
 637                         break;
 638                 case NVDEV_SUBDEV_INSTMEM:
 639                         nvkm_mask(device, 0x001714, 0x00000000, 0x00000000);
 640                         break;
 641                 case NVDEV_ENGINE_IFB:
 642                         nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
 643                         break;
 644                 default:
 645                         engine = nvkm_engine(fifo, eu->data2);
 646                         if (engine)
 647                                 engctx = nvkm_engctx_get(engine, inst);
 648                         break;
 649                 }
 650         } else {
 651                 snprintf(euunk, sizeof(euunk), "UNK%02x", unit);
 652         }
 653
 654         if (hub) {
 655                 ec = nvkm_enum_find(gf100_fifo_fault_hubclient, client);
 656         } else {
 657                 ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, client);
 658                 snprintf(gpcid, sizeof(gpcid), "%d", gpc);
 659         }
 660
 661         if (!ec)
 662                 snprintf(ecunk, sizeof(ecunk), "UNK%02x", client);
 663
 664         nv_error(fifo, "%s fault at 0x%010llx [%s] from %s/%s%s%s%s on "
 665                        "channel 0x%010llx [%s]\n", write ? "write" : "read",
 666                  (u64)vahi << 32 | valo, er ? er->name : erunk,
 667                  eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/",
 668                  ec ? ec->name : ecunk, (u64)inst << 12,
 669                  nvkm_client_name(engctx));
 670
 671         object = engctx;
 672         while (object) {
 673                 switch (nv_mclass(object)) {
 674                 case FERMI_CHANNEL_GPFIFO:
 675                         gf100_fifo_recover(fifo, engine, (void *)object);
 676                         break;
 677                 }
 678                 object = object->parent;
 679         }
 680
 681         nvkm_engctx_put(engctx);
 682 }
 683
 684 static const struct nvkm_bitfield
 685 gf100_fifo_pbdma_intr[] = {
 686 /*      { 0x00008000, "" }      seen with null ib push */
 687         { 0x00200000, "ILLEGAL_MTHD" },
 688         { 0x00800000, "EMPTY_SUBC" },
 689         {}
 690 };
 691
 692 static void
 693 gf100_fifo_intr_pbdma(struct gf100_fifo *fifo, int unit)
 694 {
 695         struct nvkm_device *device = fifo->base.engine.subdev.device;
 696         u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000));
 697         u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000));
 698         u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000));
 699         u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0x7f;
 700         u32 subc = (addr & 0x00070000) >> 16;
 701         u32 mthd = (addr & 0x00003ffc);
 702         u32 show = stat;
 703
 704         if (stat & 0x00800000) {
 705                 if (!gf100_fifo_swmthd(fifo, chid, mthd, data))
 706                         show &= ~0x00800000;
 707         }
 708
 709         if (show) {
 710                 nv_error(fifo, "PBDMA%d:", unit);
 711                 nvkm_bitfield_print(gf100_fifo_pbdma_intr, show);
 712                 pr_cont("\n");
 713                 nv_error(fifo,
 714                          "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
 715                          unit, chid,
 716                          nvkm_client_name_for_fifo_chid(&fifo->base, chid),
 717                          subc, mthd, data);
 718         }
 719
 720         nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008);
 721         nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat);
 722 }
 723
 724 static void
 725 gf100_fifo_intr_runlist(struct gf100_fifo *fifo)
 726 {
 727         struct nvkm_device *device = fifo->base.engine.subdev.device;
 728         u32 intr = nvkm_rd32(device, 0x002a00);
 729
 730         if (intr & 0x10000000) {
 731                 wake_up(&fifo->runlist.wait);
 732                 nvkm_wr32(device, 0x002a00, 0x10000000);
 733                 intr &= ~0x10000000;
 734         }
 735
 736         if (intr) {
 737                 nv_error(fifo, "RUNLIST 0x%08x\n", intr);
 738                 nvkm_wr32(device, 0x002a00, intr);
 739         }
 740 }
 741
 742 static void
 743 gf100_fifo_intr_engine_unit(struct gf100_fifo *fifo, int engn)
 744 {
 745         struct nvkm_device *device = fifo->base.engine.subdev.device;
 746         u32 intr = nvkm_rd32(device, 0x0025a8 + (engn * 0x04));
 747         u32 inte = nvkm_rd32(device, 0x002628);
 748         u32 unkn;
 749
 750         nvkm_wr32(device, 0x0025a8 + (engn * 0x04), intr);
 751
 752         for (unkn = 0; unkn < 8; unkn++) {
 753                 u32 ints = (intr >> (unkn * 0x04)) & inte;
 754                 if (ints & 0x1) {
 755                         nvkm_fifo_uevent(&fifo->base);
 756                         ints &= ~1;
 757                 }
 758                 if (ints) {
 759                         nv_error(fifo, "ENGINE %d %d %01x", engn, unkn, ints);
 760                         nvkm_mask(device, 0x002628, ints, 0);
 761                 }
 762         }
 763 }
 764
 765 static void
 766 gf100_fifo_intr_engine(struct gf100_fifo *fifo)
 767 {
 768         struct nvkm_device *device = fifo->base.engine.subdev.device;
 769         u32 mask = nvkm_rd32(device, 0x0025a4);
 770         while (mask) {
 771                 u32 unit = __ffs(mask);
 772                 gf100_fifo_intr_engine_unit(fifo, unit);
 773                 mask &= ~(1 << unit);
 774         }
 775 }
 776
 777 static void
 778 gf100_fifo_intr(struct nvkm_subdev *subdev)
 779 {
 780         struct gf100_fifo *fifo = (void *)subdev;
 781         struct nvkm_device *device = fifo->base.engine.subdev.device;
 782         u32 mask = nvkm_rd32(device, 0x002140);
 783         u32 stat = nvkm_rd32(device, 0x002100) & mask;
 784
 785         if (stat & 0x00000001) {
 786                 u32 intr = nvkm_rd32(device, 0x00252c);
 787                 nv_warn(fifo, "INTR 0x00000001: 0x%08x\n", intr);
 788                 nvkm_wr32(device, 0x002100, 0x00000001);
 789                 stat &= ~0x00000001;
 790         }
 791
 792         if (stat & 0x00000100) {
 793                 gf100_fifo_intr_sched(fifo);
 794                 nvkm_wr32(device, 0x002100, 0x00000100);
 795                 stat &= ~0x00000100;
 796         }
 797
 798         if (stat & 0x00010000) {
 799                 u32 intr = nvkm_rd32(device, 0x00256c);
 800                 nv_warn(fifo, "INTR 0x00010000: 0x%08x\n", intr);
 801                 nvkm_wr32(device, 0x002100, 0x00010000);
 802                 stat &= ~0x00010000;
 803         }
 804
 805         if (stat & 0x01000000) {
 806                 u32 intr = nvkm_rd32(device, 0x00258c);
 807                 nv_warn(fifo, "INTR 0x01000000: 0x%08x\n", intr);
 808                 nvkm_wr32(device, 0x002100, 0x01000000);
 809                 stat &= ~0x01000000;
 810         }
 811
 812         if (stat & 0x10000000) {
 813                 u32 mask = nvkm_rd32(device, 0x00259c);
 814                 while (mask) {
 815                         u32 unit = __ffs(mask);
 816                         gf100_fifo_intr_fault(fifo, unit);
 817                         nvkm_wr32(device, 0x00259c, (1 << unit));
 818                         mask &= ~(1 << unit);
 819                 }
 820                 stat &= ~0x10000000;
 821         }
 822
 823         if (stat & 0x20000000) {
 824                 u32 mask = nvkm_rd32(device, 0x0025a0);
 825                 while (mask) {
 826                         u32 unit = __ffs(mask);
 827                         gf100_fifo_intr_pbdma(fifo, unit);
 828                         nvkm_wr32(device, 0x0025a0, (1 << unit));
 829                         mask &= ~(1 << unit);
 830                 }
 831                 stat &= ~0x20000000;
 832         }
 833
 834         if (stat & 0x40000000) {
 835                 gf100_fifo_intr_runlist(fifo);
 836                 stat &= ~0x40000000;
 837         }
 838
 839         if (stat & 0x80000000) {
 840                 gf100_fifo_intr_engine(fifo);
 841                 stat &= ~0x80000000;
 842         }
 843
 844         if (stat) {
 845                 nv_error(fifo, "INTR 0x%08x\n", stat);
 846                 nvkm_mask(device, 0x002140, stat, 0x00000000);
 847                 nvkm_wr32(device, 0x002100, stat);
 848         }
 849 }
 850
 851 static void
 852 gf100_fifo_uevent_init(struct nvkm_event *event, int type, int index)
 853 {
 854         struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
 855         struct nvkm_device *device = fifo->engine.subdev.device;
 856         nvkm_mask(device, 0x002140, 0x80000000, 0x80000000);
 857 }
 858
 859 static void
 860 gf100_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
 861 {
 862         struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
 863         struct nvkm_device *device = fifo->engine.subdev.device;
 864         nvkm_mask(device, 0x002140, 0x80000000, 0x00000000);
 865 }
 866
 867 static const struct nvkm_event_func
 868 gf100_fifo_uevent_func = {
 869         .ctor = nvkm_fifo_uevent_ctor,
 870         .init = gf100_fifo_uevent_init,
 871         .fini = gf100_fifo_uevent_fini,
 872 };
 873
 874 static int
 875 gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 876                 struct nvkm_oclass *oclass, void *data, u32 size,
 877                 struct nvkm_object **pobject)
 878 {
 879         struct gf100_fifo *fifo;
 880         int ret;
 881
 882         ret = nvkm_fifo_create(parent, engine, oclass, 0, 127, &fifo);
 883         *pobject = nv_object(fifo);
 884         if (ret)
 885                 return ret;
 886
 887         INIT_WORK(&fifo->fault, gf100_fifo_recover_work);
 888
 889         ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 0x1000, 0x1000, 0,
 890                               &fifo->runlist.mem[0]);
 891         if (ret)
 892                 return ret;
 893
 894         ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 0x1000, 0x1000, 0,
 895                               &fifo->runlist.mem[1]);
 896         if (ret)
 897                 return ret;
 898
 899         init_waitqueue_head(&fifo->runlist.wait);
 900
 901         ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 128 * 0x1000, 0x1000, 0,
 902                               &fifo->user.mem);
 903         if (ret)
 904                 return ret;
 905
 906         ret = nvkm_gpuobj_map(fifo->user.mem, NV_MEM_ACCESS_RW,
 907                               &fifo->user.bar);
 908         if (ret)
 909                 return ret;
 910
 911         ret = nvkm_event_init(&gf100_fifo_uevent_func, 1, 1, &fifo->base.uevent);
 912         if (ret)
 913                 return ret;
 914
 915         nv_subdev(fifo)->unit = 0x00000100;
 916         nv_subdev(fifo)->intr = gf100_fifo_intr;
 917         nv_engine(fifo)->cclass = &gf100_fifo_cclass;
 918         nv_engine(fifo)->sclass = gf100_fifo_sclass;
 919         return 0;
 920 }
 921
 922 static void
 923 gf100_fifo_dtor(struct nvkm_object *object)
 924 {
 925         struct gf100_fifo *fifo = (void *)object;
 926
 927         nvkm_gpuobj_unmap(&fifo->user.bar);
 928         nvkm_gpuobj_ref(NULL, &fifo->user.mem);
 929         nvkm_gpuobj_ref(NULL, &fifo->runlist.mem[0]);
 930         nvkm_gpuobj_ref(NULL, &fifo->runlist.mem[1]);
 931
 932         nvkm_fifo_destroy(&fifo->base);
 933 }
 934
 935 static int
 936 gf100_fifo_init(struct nvkm_object *object)
 937 {
 938         struct gf100_fifo *fifo = (void *)object;
 939         struct nvkm_device *device = fifo->base.engine.subdev.device;
 940         int ret, i;
 941
 942         ret = nvkm_fifo_init(&fifo->base);
 943         if (ret)
 944                 return ret;
 945
 946         nvkm_wr32(device, 0x000204, 0xffffffff);
 947         nvkm_wr32(device, 0x002204, 0xffffffff);
 948
 949         fifo->spoon_nr = hweight32(nvkm_rd32(device, 0x002204));
 950         nv_debug(fifo, "%d PBDMA unit(s)\n", fifo->spoon_nr);
 951
 952         /* assign engines to PBDMAs */
 953         if (fifo->spoon_nr >= 3) {
 954                 nvkm_wr32(device, 0x002208, ~(1 << 0)); /* PGRAPH */
 955                 nvkm_wr32(device, 0x00220c, ~(1 << 1)); /* PVP */
 956                 nvkm_wr32(device, 0x002210, ~(1 << 1)); /* PMSPP */
 957                 nvkm_wr32(device, 0x002214, ~(1 << 1)); /* PMSVLD */
 958                 nvkm_wr32(device, 0x002218, ~(1 << 2)); /* PCE0 */
 959                 nvkm_wr32(device, 0x00221c, ~(1 << 1)); /* PCE1 */
 960         }
 961
 962         /* PBDMA[n] */
 963         for (i = 0; i < fifo->spoon_nr; i++) {
 964                 nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
 965                 nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
 966                 nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
 967         }
 968
 969         nvkm_mask(device, 0x002200, 0x00000001, 0x00000001);
 970         nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12);
 971
 972         nvkm_wr32(device, 0x002100, 0xffffffff);
 973         nvkm_wr32(device, 0x002140, 0x7fffffff);
 974         nvkm_wr32(device, 0x002628, 0x00000001); /* ENGINE_INTR_EN */
 975         return 0;
 976 }
 977
 978 struct nvkm_oclass *
 979 gf100_fifo_oclass = &(struct nvkm_oclass) {
 980         .handle = NV_ENGINE(FIFO, 0xc0),
 981         .ofuncs = &(struct nvkm_ofuncs) {
 982                 .ctor = gf100_fifo_ctor,
 983                 .dtor = gf100_fifo_dtor,
 984                 .init = gf100_fifo_init,
 985                 .fini = _nvkm_fifo_fini,
 986         },
 987 };