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11 * The above copyright notice and this permission notice shall be included in
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20 * DEALINGS IN THE SOFTWARE.
25 #include <subdev/timer.h>
27 #include <nvif/class.h>
30 gk20a_gr_init_dtor(struct gf100_gr_pack *pack)
41 static struct gf100_gr_pack *
42 gk20a_gr_av_to_init(struct gf100_gr_fuc *fuc)
44 struct gf100_gr_init *init;
45 struct gf100_gr_pack *pack;
46 const int nent = (fuc->size / sizeof(struct gk20a_fw_av));
49 pack = vzalloc((sizeof(*pack) * 2) + (sizeof(*init) * (nent + 1)));
51 return ERR_PTR(-ENOMEM);
53 init = (void *)(pack + 2);
57 for (i = 0; i < nent; i++) {
58 struct gf100_gr_init *ent = &init[i];
59 struct gk20a_fw_av *av = &((struct gk20a_fw_av *)fuc->data)[i];
77 static struct gf100_gr_pack *
78 gk20a_gr_aiv_to_init(struct gf100_gr_fuc *fuc)
80 struct gf100_gr_init *init;
81 struct gf100_gr_pack *pack;
82 const int nent = (fuc->size / sizeof(struct gk20a_fw_aiv));
85 pack = vzalloc((sizeof(*pack) * 2) + (sizeof(*init) * (nent + 1)));
87 return ERR_PTR(-ENOMEM);
89 init = (void *)(pack + 2);
93 for (i = 0; i < nent; i++) {
94 struct gf100_gr_init *ent = &init[i];
95 struct gk20a_fw_aiv *av = &((struct gk20a_fw_aiv *)fuc->data)[i];
106 static struct gf100_gr_pack *
107 gk20a_gr_av_to_method(struct gf100_gr_fuc *fuc)
109 struct gf100_gr_init *init;
110 struct gf100_gr_pack *pack;
111 /* We don't suppose we will initialize more than 16 classes here... */
112 static const unsigned int max_classes = 16;
113 const int nent = (fuc->size / sizeof(struct gk20a_fw_av));
117 pack = vzalloc((sizeof(*pack) * max_classes) +
118 (sizeof(*init) * (nent + 1)));
120 return ERR_PTR(-ENOMEM);
122 init = (void *)(pack + max_classes);
124 for (i = 0; i < nent; i++) {
125 struct gf100_gr_init *ent = &init[i];
126 struct gk20a_fw_av *av = &((struct gk20a_fw_av *)fuc->data)[i];
127 u32 class = av->addr & 0xffff;
128 u32 addr = (av->addr & 0xffff0000) >> 14;
130 if (prevclass != class) {
131 pack[classidx].init = ent;
132 pack[classidx].type = class;
134 if (++classidx >= max_classes) {
136 return ERR_PTR(-ENOSPC);
141 ent->data = av->data;
150 gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr)
152 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
153 struct nvkm_device *device = subdev->device;
155 if (nvkm_msec(device, 2000,
156 if (!(nvkm_rd32(device, 0x40910c) & 0x00000006))
159 nvkm_error(subdev, "FECS mem scrubbing timeout\n");
163 if (nvkm_msec(device, 2000,
164 if (!(nvkm_rd32(device, 0x41a10c) & 0x00000006))
167 nvkm_error(subdev, "GPCCS mem scrubbing timeout\n");
175 gk20a_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
177 struct nvkm_device *device = gr->base.engine.subdev.device;
178 nvkm_wr32(device, 0x419e44, 0x1ffffe);
179 nvkm_wr32(device, 0x419e4c, 0x7f);
183 gk20a_gr_init(struct gf100_gr *gr)
185 struct nvkm_device *device = gr->base.engine.subdev.device;
186 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
187 u32 data[TPC_MAX / 8] = {};
193 nvkm_wr32(device, 0x40802c, 0x1);
195 gf100_gr_mmio(gr, gr->fuc_sw_nonctx);
197 ret = gk20a_gr_wait_mem_scrubbing(gr);
201 ret = gf100_gr_wait_idle(gr);
205 /* MMU debug buffer */
206 nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(gr->unk4188b4) >> 8);
207 nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(gr->unk4188b8) >> 8);
209 if (gr->func->init_gpc_mmu)
210 gr->func->init_gpc_mmu(gr);
212 /* Set the PE as stream master */
213 nvkm_mask(device, 0x503018, 0x1, 0x1);
216 memset(data, 0x00, sizeof(data));
217 memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
218 for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
220 gpc = (gpc + 1) % gr->gpc_nr;
221 } while (!tpcnr[gpc]);
222 tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
224 data[i / 8] |= tpc << ((i % 8) * 4);
227 nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
228 nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
229 nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
230 nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
232 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
233 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
234 gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
235 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
237 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
240 nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
242 /* Enable FIFO access */
243 nvkm_wr32(device, 0x400500, 0x00010001);
245 /* Enable interrupts */
246 nvkm_wr32(device, 0x400100, 0xffffffff);
247 nvkm_wr32(device, 0x40013c, 0xffffffff);
249 /* Enable FECS error interrupts */
250 nvkm_wr32(device, 0x409c24, 0x000f0000);
252 /* Enable hardware warning exceptions */
253 nvkm_wr32(device, 0x404000, 0xc0000000);
254 nvkm_wr32(device, 0x404600, 0xc0000000);
256 if (gr->func->set_hww_esr_report_mask)
257 gr->func->set_hww_esr_report_mask(gr);
259 /* Enable TPC exceptions per GPC */
260 nvkm_wr32(device, 0x419d0c, 0x2);
261 nvkm_wr32(device, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16);
263 /* Reset and enable all exceptions */
264 nvkm_wr32(device, 0x400108, 0xffffffff);
265 nvkm_wr32(device, 0x400138, 0xffffffff);
266 nvkm_wr32(device, 0x400118, 0xffffffff);
267 nvkm_wr32(device, 0x400130, 0xffffffff);
268 nvkm_wr32(device, 0x40011c, 0xffffffff);
269 nvkm_wr32(device, 0x400134, 0xffffffff);
271 gf100_gr_zbc_init(gr);
273 return gf100_gr_init_ctxctl(gr);
277 gk20a_gr_dtor(struct gf100_gr *gr)
279 gk20a_gr_init_dtor(gr->fuc_method);
280 gk20a_gr_init_dtor(gr->fuc_bundle);
281 gk20a_gr_init_dtor(gr->fuc_sw_ctx);
282 gk20a_gr_init_dtor(gr->fuc_sw_nonctx);
286 gk20a_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device,
287 int index, struct nvkm_gr **pgr)
289 struct gf100_gr_fuc fuc;
293 if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
297 ret = gf100_gr_ctor(func, device, index, gr);
301 ret = gf100_gr_ctor_fw(gr, "sw_nonctx", &fuc);
304 gr->fuc_sw_nonctx = gk20a_gr_av_to_init(&fuc);
305 gf100_gr_dtor_fw(&fuc);
306 if (IS_ERR(gr->fuc_sw_nonctx))
307 return PTR_ERR(gr->fuc_sw_nonctx);
309 ret = gf100_gr_ctor_fw(gr, "sw_ctx", &fuc);
312 gr->fuc_sw_ctx = gk20a_gr_aiv_to_init(&fuc);
313 gf100_gr_dtor_fw(&fuc);
314 if (IS_ERR(gr->fuc_sw_ctx))
315 return PTR_ERR(gr->fuc_sw_ctx);
317 ret = gf100_gr_ctor_fw(gr, "sw_bundle_init", &fuc);
320 gr->fuc_bundle = gk20a_gr_av_to_init(&fuc);
321 gf100_gr_dtor_fw(&fuc);
322 if (IS_ERR(gr->fuc_bundle))
323 return PTR_ERR(gr->fuc_bundle);
325 ret = gf100_gr_ctor_fw(gr, "sw_method_init", &fuc);
328 gr->fuc_method = gk20a_gr_av_to_method(&fuc);
329 gf100_gr_dtor_fw(&fuc);
330 if (IS_ERR(gr->fuc_method))
331 return PTR_ERR(gr->fuc_method);
336 static const struct gf100_gr_func
338 .dtor = gk20a_gr_dtor,
339 .init = gk20a_gr_init,
340 .set_hww_esr_report_mask = gk20a_gr_set_hww_esr_report_mask,
342 .grctx = &gk20a_grctx,
344 { -1, -1, FERMI_TWOD_A },
345 { -1, -1, KEPLER_INLINE_TO_MEMORY_A },
346 { -1, -1, KEPLER_C, &gf100_fermi },
347 { -1, -1, KEPLER_COMPUTE_A },
353 gk20a_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
355 return gk20a_gr_new_(&gk20a_gr, device, index, pgr);