drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c

   1 /*
   2  * Copyright 2015 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs <bskeggs@redhat.com>
  23  */
  24 #include "gf100.h"
  25 #include "ctxgf100.h"
  26
  27 #include <subdev/secboot.h>
  28
  29 #include <nvif/class.h>
  30
  31 /*******************************************************************************
  32  * PGRAPH engine/subdev functions
  33  ******************************************************************************/
  34
  35 static void
  36 gm200_gr_init_gpc_mmu(struct gf100_gr *gr)
  37 {
  38         struct nvkm_device *device = gr->base.engine.subdev.device;
  39
  40         nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf0001fff);
  41         nvkm_wr32(device, 0x418890, 0x00000000);
  42         nvkm_wr32(device, 0x418894, 0x00000000);
  43
  44         nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));
  45         nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));
  46         nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));
  47 }
  48
  49 int
  50 gm200_gr_init(struct gf100_gr *gr)
  51 {
  52         struct nvkm_device *device = gr->base.engine.subdev.device;
  53         const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
  54         u32 data[TPC_MAX / 8] = {};
  55         u8  tpcnr[GPC_MAX];
  56         int gpc, tpc, ppc, rop;
  57         int i;
  58
  59         /*XXX: belongs in fb */
  60         nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(gr->unk4188b4) >> 8);
  61         nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(gr->unk4188b8) >> 8);
  62         nvkm_mask(device, 0x100cc4, 0x00040000, 0x00040000);
  63         gr->func->init_gpc_mmu(gr);
  64
  65         gf100_gr_mmio(gr, gr->fuc_sw_nonctx);
  66
  67         gm107_gr_init_bios(gr);
  68
  69         nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001);
  70
  71         memset(data, 0x00, sizeof(data));
  72         memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
  73         for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
  74                 do {
  75                         gpc = (gpc + 1) % gr->gpc_nr;
  76                 } while (!tpcnr[gpc]);
  77                 tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
  78
  79                 data[i / 8] |= tpc << ((i % 8) * 4);
  80         }
  81
  82         nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
  83         nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
  84         nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
  85         nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
  86
  87         for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
  88                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
  89                           gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
  90                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
  91                                                          gr->tpc_total);
  92                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
  93         }
  94
  95         nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
  96         nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
  97         nvkm_wr32(device, GPC_BCAST(0x033c), nvkm_rd32(device, 0x100804));
  98
  99         nvkm_wr32(device, 0x400500, 0x00010001);
 100         nvkm_wr32(device, 0x400100, 0xffffffff);
 101         nvkm_wr32(device, 0x40013c, 0xffffffff);
 102         nvkm_wr32(device, 0x400124, 0x00000002);
 103         nvkm_wr32(device, 0x409c24, 0x000e0000);
 104         nvkm_wr32(device, 0x405848, 0xc0000000);
 105         nvkm_wr32(device, 0x40584c, 0x00000001);
 106         nvkm_wr32(device, 0x404000, 0xc0000000);
 107         nvkm_wr32(device, 0x404600, 0xc0000000);
 108         nvkm_wr32(device, 0x408030, 0xc0000000);
 109         nvkm_wr32(device, 0x404490, 0xc0000000);
 110         nvkm_wr32(device, 0x406018, 0xc0000000);
 111         nvkm_wr32(device, 0x407020, 0x40000000);
 112         nvkm_wr32(device, 0x405840, 0xc0000000);
 113         nvkm_wr32(device, 0x405844, 0x00ffffff);
 114         nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
 115
 116         for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
 117                 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++)
 118                         nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);
 119                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
 120                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
 121                 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
 122                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
 123                 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
 124                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
 125                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
 126                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
 127                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
 128                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
 129                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
 130                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
 131                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005);
 132                 }
 133                 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
 134                 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
 135         }
 136
 137         for (rop = 0; rop < gr->rop_nr; rop++) {
 138                 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000);
 139                 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000);
 140                 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
 141                 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
 142         }
 143
 144         nvkm_wr32(device, 0x400108, 0xffffffff);
 145         nvkm_wr32(device, 0x400138, 0xffffffff);
 146         nvkm_wr32(device, 0x400118, 0xffffffff);
 147         nvkm_wr32(device, 0x400130, 0xffffffff);
 148         nvkm_wr32(device, 0x40011c, 0xffffffff);
 149         nvkm_wr32(device, 0x400134, 0xffffffff);
 150
 151         nvkm_wr32(device, 0x400054, 0x2c350f63);
 152
 153         gf100_gr_zbc_init(gr);
 154
 155         return gf100_gr_init_ctxctl(gr);
 156 }
 157
 158 int
 159 gm200_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device,
 160               int index, struct nvkm_gr **pgr)
 161 {
 162         struct gf100_gr *gr;
 163         int ret;
 164
 165         if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
 166                 return -ENOMEM;
 167         *pgr = &gr->base;
 168
 169         ret = gf100_gr_ctor(func, device, index, gr);
 170         if (ret)
 171                 return ret;
 172
 173         /* Load firmwares for non-secure falcons */
 174         if (!nvkm_secboot_is_managed(device->secboot,
 175                                      NVKM_SECBOOT_FALCON_FECS)) {
 176                 if ((ret = gf100_gr_ctor_fw(gr, "gr/fecs_inst", &gr->fuc409c)) ||
 177                     (ret = gf100_gr_ctor_fw(gr, "gr/fecs_data", &gr->fuc409d)))
 178                         return ret;
 179         }
 180         if (!nvkm_secboot_is_managed(device->secboot,
 181                                      NVKM_SECBOOT_FALCON_GPCCS)) {
 182                 if ((ret = gf100_gr_ctor_fw(gr, "gr/gpccs_inst", &gr->fuc41ac)) ||
 183                     (ret = gf100_gr_ctor_fw(gr, "gr/gpccs_data", &gr->fuc41ad)))
 184                         return ret;
 185         }
 186
 187         if ((ret = gk20a_gr_av_to_init(gr, "gr/sw_nonctx", &gr->fuc_sw_nonctx)) ||
 188             (ret = gk20a_gr_aiv_to_init(gr, "gr/sw_ctx", &gr->fuc_sw_ctx)) ||
 189             (ret = gk20a_gr_av_to_init(gr, "gr/sw_bundle_init", &gr->fuc_bundle)) ||
 190             (ret = gk20a_gr_av_to_method(gr, "gr/sw_method_init", &gr->fuc_method)))
 191                 return ret;
 192
 193         return 0;
 194 }
 195
 196 static const struct gf100_gr_func
 197 gm200_gr = {
 198         .init = gm200_gr_init,
 199         .init_gpc_mmu = gm200_gr_init_gpc_mmu,
 200         .rops = gf100_gr_rops,
 201         .ppc_nr = 2,
 202         .grctx = &gm200_grctx,
 203         .sclass = {
 204                 { -1, -1, FERMI_TWOD_A },
 205                 { -1, -1, KEPLER_INLINE_TO_MEMORY_B },
 206                 { -1, -1, MAXWELL_B, &gf100_fermi },
 207                 { -1, -1, MAXWELL_COMPUTE_B },
 208                 {}
 209         }
 210 };
 211
 212 int
 213 gm200_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
 214 {
 215         return gm200_gr_new_(&gm200_gr, device, index, pgr);
 216 }