drivers/gpu/drm/omapdrm/dss/dss.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DSS"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/io.h>
  28 #include <linux/export.h>
  29 #include <linux/err.h>
  30 #include <linux/delay.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/clk.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/gfp.h>
  36 #include <linux/sizes.h>
  37 #include <linux/mfd/syscon.h>
  38 #include <linux/regmap.h>
  39 #include <linux/of.h>
  40 #include <linux/regulator/consumer.h>
  41 #include <linux/suspend.h>
  42 #include <linux/component.h>
  43
  44 #include "omapdss.h"
  45 #include "dss.h"
  46 #include "dss_features.h"
  47
  48 #define DSS_SZ_REGS                     SZ_512
  49
  50 struct dss_reg {
  51         u16 idx;
  52 };
  53
  54 #define DSS_REG(idx)                    ((const struct dss_reg) { idx })
  55
  56 #define DSS_REVISION                    DSS_REG(0x0000)
  57 #define DSS_SYSCONFIG                   DSS_REG(0x0010)
  58 #define DSS_SYSSTATUS                   DSS_REG(0x0014)
  59 #define DSS_CONTROL                     DSS_REG(0x0040)
  60 #define DSS_SDI_CONTROL                 DSS_REG(0x0044)
  61 #define DSS_PLL_CONTROL                 DSS_REG(0x0048)
  62 #define DSS_SDI_STATUS                  DSS_REG(0x005C)
  63
  64 #define REG_GET(idx, start, end) \
  65         FLD_GET(dss_read_reg(idx), start, end)
  66
  67 #define REG_FLD_MOD(idx, val, start, end) \
  68         dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
  69
  70 struct dss_features {
  71         u8 fck_div_max;
  72         u8 dss_fck_multiplier;
  73         const char *parent_clk_name;
  74         const enum omap_display_type *ports;
  75         int num_ports;
  76         int (*dpi_select_source)(int port, enum omap_channel channel);
  77 };
  78
  79 static struct {
  80         struct platform_device *pdev;
  81         void __iomem    *base;
  82         struct regmap   *syscon_pll_ctrl;
  83         u32             syscon_pll_ctrl_offset;
  84
  85         struct clk      *parent_clk;
  86         struct clk      *dss_clk;
  87         unsigned long   dss_clk_rate;
  88
  89         unsigned long   cache_req_pck;
  90         unsigned long   cache_prate;
  91         struct dispc_clock_info cache_dispc_cinfo;
  92
  93         enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
  94         enum omap_dss_clk_source dispc_clk_source;
  95         enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
  96
  97         bool            ctx_valid;
  98         u32             ctx[DSS_SZ_REGS / sizeof(u32)];
  99
 100         const struct dss_features *feat;
 101
 102         struct dss_pll  *video1_pll;
 103         struct dss_pll  *video2_pll;
 104 } dss;
 105
 106 static const char * const dss_generic_clk_source_names[] = {
 107         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]  = "DSI_PLL_HSDIV_DISPC",
 108         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]    = "DSI_PLL_HSDIV_DSI",
 109         [OMAP_DSS_CLK_SRC_FCK]                  = "DSS_FCK",
 110         [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DSI_PLL2_HSDIV_DISPC",
 111         [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI]   = "DSI_PLL2_HSDIV_DSI",
 112 };
 113
 114 static bool dss_initialized;
 115
 116 bool omapdss_is_initialized(void)
 117 {
 118         return dss_initialized;
 119 }
 120 EXPORT_SYMBOL(omapdss_is_initialized);
 121
 122 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
 123 {
 124         __raw_writel(val, dss.base + idx.idx);
 125 }
 126
 127 static inline u32 dss_read_reg(const struct dss_reg idx)
 128 {
 129         return __raw_readl(dss.base + idx.idx);
 130 }
 131
 132 #define SR(reg) \
 133         dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
 134 #define RR(reg) \
 135         dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
 136
 137 static void dss_save_context(void)
 138 {
 139         DSSDBG("dss_save_context\n");
 140
 141         SR(CONTROL);
 142
 143         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 144                         OMAP_DISPLAY_TYPE_SDI) {
 145                 SR(SDI_CONTROL);
 146                 SR(PLL_CONTROL);
 147         }
 148
 149         dss.ctx_valid = true;
 150
 151         DSSDBG("context saved\n");
 152 }
 153
 154 static void dss_restore_context(void)
 155 {
 156         DSSDBG("dss_restore_context\n");
 157
 158         if (!dss.ctx_valid)
 159                 return;
 160
 161         RR(CONTROL);
 162
 163         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 164                         OMAP_DISPLAY_TYPE_SDI) {
 165                 RR(SDI_CONTROL);
 166                 RR(PLL_CONTROL);
 167         }
 168
 169         DSSDBG("context restored\n");
 170 }
 171
 172 #undef SR
 173 #undef RR
 174
 175 void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable)
 176 {
 177         unsigned shift;
 178         unsigned val;
 179
 180         if (!dss.syscon_pll_ctrl)
 181                 return;
 182
 183         val = !enable;
 184
 185         switch (pll_id) {
 186         case DSS_PLL_VIDEO1:
 187                 shift = 0;
 188                 break;
 189         case DSS_PLL_VIDEO2:
 190                 shift = 1;
 191                 break;
 192         case DSS_PLL_HDMI:
 193                 shift = 2;
 194                 break;
 195         default:
 196                 DSSERR("illegal DSS PLL ID %d\n", pll_id);
 197                 return;
 198         }
 199
 200         regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset,
 201                 1 << shift, val << shift);
 202 }
 203
 204 void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id,
 205         enum omap_channel channel)
 206 {
 207         unsigned shift, val;
 208
 209         if (!dss.syscon_pll_ctrl)
 210                 return;
 211
 212         switch (channel) {
 213         case OMAP_DSS_CHANNEL_LCD:
 214                 shift = 3;
 215
 216                 switch (pll_id) {
 217                 case DSS_PLL_VIDEO1:
 218                         val = 0; break;
 219                 case DSS_PLL_HDMI:
 220                         val = 1; break;
 221                 default:
 222                         DSSERR("error in PLL mux config for LCD\n");
 223                         return;
 224                 }
 225
 226                 break;
 227         case OMAP_DSS_CHANNEL_LCD2:
 228                 shift = 5;
 229
 230                 switch (pll_id) {
 231                 case DSS_PLL_VIDEO1:
 232                         val = 0; break;
 233                 case DSS_PLL_VIDEO2:
 234                         val = 1; break;
 235                 case DSS_PLL_HDMI:
 236                         val = 2; break;
 237                 default:
 238                         DSSERR("error in PLL mux config for LCD2\n");
 239                         return;
 240                 }
 241
 242                 break;
 243         case OMAP_DSS_CHANNEL_LCD3:
 244                 shift = 7;
 245
 246                 switch (pll_id) {
 247                 case DSS_PLL_VIDEO1:
 248                         val = 1; break;
 249                 case DSS_PLL_VIDEO2:
 250                         val = 0; break;
 251                 case DSS_PLL_HDMI:
 252                         val = 2; break;
 253                 default:
 254                         DSSERR("error in PLL mux config for LCD3\n");
 255                         return;
 256                 }
 257
 258                 break;
 259         default:
 260                 DSSERR("error in PLL mux config\n");
 261                 return;
 262         }
 263
 264         regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset,
 265                 0x3 << shift, val << shift);
 266 }
 267
 268 void dss_sdi_init(int datapairs)
 269 {
 270         u32 l;
 271
 272         BUG_ON(datapairs > 3 || datapairs < 1);
 273
 274         l = dss_read_reg(DSS_SDI_CONTROL);
 275         l = FLD_MOD(l, 0xf, 19, 15);            /* SDI_PDIV */
 276         l = FLD_MOD(l, datapairs-1, 3, 2);      /* SDI_PRSEL */
 277         l = FLD_MOD(l, 2, 1, 0);                /* SDI_BWSEL */
 278         dss_write_reg(DSS_SDI_CONTROL, l);
 279
 280         l = dss_read_reg(DSS_PLL_CONTROL);
 281         l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
 282         l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
 283         l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
 284         dss_write_reg(DSS_PLL_CONTROL, l);
 285 }
 286
 287 int dss_sdi_enable(void)
 288 {
 289         unsigned long timeout;
 290
 291         dispc_pck_free_enable(1);
 292
 293         /* Reset SDI PLL */
 294         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
 295         udelay(1);      /* wait 2x PCLK */
 296
 297         /* Lock SDI PLL */
 298         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
 299
 300         /* Waiting for PLL lock request to complete */
 301         timeout = jiffies + msecs_to_jiffies(500);
 302         while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
 303                 if (time_after_eq(jiffies, timeout)) {
 304                         DSSERR("PLL lock request timed out\n");
 305                         goto err1;
 306                 }
 307         }
 308
 309         /* Clearing PLL_GO bit */
 310         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
 311
 312         /* Waiting for PLL to lock */
 313         timeout = jiffies + msecs_to_jiffies(500);
 314         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
 315                 if (time_after_eq(jiffies, timeout)) {
 316                         DSSERR("PLL lock timed out\n");
 317                         goto err1;
 318                 }
 319         }
 320
 321         dispc_lcd_enable_signal(1);
 322
 323         /* Waiting for SDI reset to complete */
 324         timeout = jiffies + msecs_to_jiffies(500);
 325         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
 326                 if (time_after_eq(jiffies, timeout)) {
 327                         DSSERR("SDI reset timed out\n");
 328                         goto err2;
 329                 }
 330         }
 331
 332         return 0;
 333
 334  err2:
 335         dispc_lcd_enable_signal(0);
 336  err1:
 337         /* Reset SDI PLL */
 338         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 339
 340         dispc_pck_free_enable(0);
 341
 342         return -ETIMEDOUT;
 343 }
 344
 345 void dss_sdi_disable(void)
 346 {
 347         dispc_lcd_enable_signal(0);
 348
 349         dispc_pck_free_enable(0);
 350
 351         /* Reset SDI PLL */
 352         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 353 }
 354
 355 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)
 356 {
 357         return dss_generic_clk_source_names[clk_src];
 358 }
 359
 360 void dss_dump_clocks(struct seq_file *s)
 361 {
 362         const char *fclk_name, *fclk_real_name;
 363         unsigned long fclk_rate;
 364
 365         if (dss_runtime_get())
 366                 return;
 367
 368         seq_printf(s, "- DSS -\n");
 369
 370         fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 371         fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 372         fclk_rate = clk_get_rate(dss.dss_clk);
 373
 374         seq_printf(s, "%s (%s) = %lu\n",
 375                         fclk_name, fclk_real_name,
 376                         fclk_rate);
 377
 378         dss_runtime_put();
 379 }
 380
 381 static void dss_dump_regs(struct seq_file *s)
 382 {
 383 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
 384
 385         if (dss_runtime_get())
 386                 return;
 387
 388         DUMPREG(DSS_REVISION);
 389         DUMPREG(DSS_SYSCONFIG);
 390         DUMPREG(DSS_SYSSTATUS);
 391         DUMPREG(DSS_CONTROL);
 392
 393         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 394                         OMAP_DISPLAY_TYPE_SDI) {
 395                 DUMPREG(DSS_SDI_CONTROL);
 396                 DUMPREG(DSS_PLL_CONTROL);
 397                 DUMPREG(DSS_SDI_STATUS);
 398         }
 399
 400         dss_runtime_put();
 401 #undef DUMPREG
 402 }
 403
 404 static void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
 405 {
 406         int b;
 407         u8 start, end;
 408
 409         switch (clk_src) {
 410         case OMAP_DSS_CLK_SRC_FCK:
 411                 b = 0;
 412                 break;
 413         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 414                 b = 1;
 415                 break;
 416         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 417                 b = 2;
 418                 break;
 419         default:
 420                 BUG();
 421                 return;
 422         }
 423
 424         dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
 425
 426         REG_FLD_MOD(DSS_CONTROL, b, start, end);        /* DISPC_CLK_SWITCH */
 427
 428         dss.dispc_clk_source = clk_src;
 429 }
 430
 431 void dss_select_dsi_clk_source(int dsi_module,
 432                 enum omap_dss_clk_source clk_src)
 433 {
 434         int b, pos;
 435
 436         switch (clk_src) {
 437         case OMAP_DSS_CLK_SRC_FCK:
 438                 b = 0;
 439                 break;
 440         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
 441                 BUG_ON(dsi_module != 0);
 442                 b = 1;
 443                 break;
 444         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
 445                 BUG_ON(dsi_module != 1);
 446                 b = 1;
 447                 break;
 448         default:
 449                 BUG();
 450                 return;
 451         }
 452
 453         pos = dsi_module == 0 ? 1 : 10;
 454         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* DSIx_CLK_SWITCH */
 455
 456         dss.dsi_clk_source[dsi_module] = clk_src;
 457 }
 458
 459 void dss_select_lcd_clk_source(enum omap_channel channel,
 460                 enum omap_dss_clk_source clk_src)
 461 {
 462         int b, ix, pos;
 463
 464         if (!dss_has_feature(FEAT_LCD_CLK_SRC)) {
 465                 dss_select_dispc_clk_source(clk_src);
 466                 return;
 467         }
 468
 469         switch (clk_src) {
 470         case OMAP_DSS_CLK_SRC_FCK:
 471                 b = 0;
 472                 break;
 473         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 474                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
 475                 b = 1;
 476                 break;
 477         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 478                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2 &&
 479                        channel != OMAP_DSS_CHANNEL_LCD3);
 480                 b = 1;
 481                 break;
 482         default:
 483                 BUG();
 484                 return;
 485         }
 486
 487         pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 488              (channel == OMAP_DSS_CHANNEL_LCD2 ? 12 : 19);
 489         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* LCDx_CLK_SWITCH */
 490
 491         ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 492             (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
 493         dss.lcd_clk_source[ix] = clk_src;
 494 }
 495
 496 enum omap_dss_clk_source dss_get_dispc_clk_source(void)
 497 {
 498         return dss.dispc_clk_source;
 499 }
 500
 501 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
 502 {
 503         return dss.dsi_clk_source[dsi_module];
 504 }
 505
 506 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
 507 {
 508         if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
 509                 int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 510                         (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
 511                 return dss.lcd_clk_source[ix];
 512         } else {
 513                 /* LCD_CLK source is the same as DISPC_FCLK source for
 514                  * OMAP2 and OMAP3 */
 515                 return dss.dispc_clk_source;
 516         }
 517 }
 518
 519 bool dss_div_calc(unsigned long pck, unsigned long fck_min,
 520                 dss_div_calc_func func, void *data)
 521 {
 522         int fckd, fckd_start, fckd_stop;
 523         unsigned long fck;
 524         unsigned long fck_hw_max;
 525         unsigned long fckd_hw_max;
 526         unsigned long prate;
 527         unsigned m;
 528
 529         fck_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
 530
 531         if (dss.parent_clk == NULL) {
 532                 unsigned pckd;
 533
 534                 pckd = fck_hw_max / pck;
 535
 536                 fck = pck * pckd;
 537
 538                 fck = clk_round_rate(dss.dss_clk, fck);
 539
 540                 return func(fck, data);
 541         }
 542
 543         fckd_hw_max = dss.feat->fck_div_max;
 544
 545         m = dss.feat->dss_fck_multiplier;
 546         prate = clk_get_rate(dss.parent_clk);
 547
 548         fck_min = fck_min ? fck_min : 1;
 549
 550         fckd_start = min(prate * m / fck_min, fckd_hw_max);
 551         fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul);
 552
 553         for (fckd = fckd_start; fckd >= fckd_stop; --fckd) {
 554                 fck = DIV_ROUND_UP(prate, fckd) * m;
 555
 556                 if (func(fck, data))
 557                         return true;
 558         }
 559
 560         return false;
 561 }
 562
 563 int dss_set_fck_rate(unsigned long rate)
 564 {
 565         int r;
 566
 567         DSSDBG("set fck to %lu\n", rate);
 568
 569         r = clk_set_rate(dss.dss_clk, rate);
 570         if (r)
 571                 return r;
 572
 573         dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
 574
 575         WARN_ONCE(dss.dss_clk_rate != rate,
 576                         "clk rate mismatch: %lu != %lu", dss.dss_clk_rate,
 577                         rate);
 578
 579         return 0;
 580 }
 581
 582 unsigned long dss_get_dispc_clk_rate(void)
 583 {
 584         return dss.dss_clk_rate;
 585 }
 586
 587 static int dss_setup_default_clock(void)
 588 {
 589         unsigned long max_dss_fck, prate;
 590         unsigned long fck;
 591         unsigned fck_div;
 592         int r;
 593
 594         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
 595
 596         if (dss.parent_clk == NULL) {
 597                 fck = clk_round_rate(dss.dss_clk, max_dss_fck);
 598         } else {
 599                 prate = clk_get_rate(dss.parent_clk);
 600
 601                 fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier,
 602                                 max_dss_fck);
 603                 fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier;
 604         }
 605
 606         r = dss_set_fck_rate(fck);
 607         if (r)
 608                 return r;
 609
 610         return 0;
 611 }
 612
 613 void dss_set_venc_output(enum omap_dss_venc_type type)
 614 {
 615         int l = 0;
 616
 617         if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 618                 l = 0;
 619         else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
 620                 l = 1;
 621         else
 622                 BUG();
 623
 624         /* venc out selection. 0 = comp, 1 = svideo */
 625         REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
 626 }
 627
 628 void dss_set_dac_pwrdn_bgz(bool enable)
 629 {
 630         REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
 631 }
 632
 633 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src)
 634 {
 635         enum omap_display_type dp;
 636         dp = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
 637
 638         /* Complain about invalid selections */
 639         WARN_ON((src == DSS_VENC_TV_CLK) && !(dp & OMAP_DISPLAY_TYPE_VENC));
 640         WARN_ON((src == DSS_HDMI_M_PCLK) && !(dp & OMAP_DISPLAY_TYPE_HDMI));
 641
 642         /* Select only if we have options */
 643         if ((dp & OMAP_DISPLAY_TYPE_VENC) && (dp & OMAP_DISPLAY_TYPE_HDMI))
 644                 REG_FLD_MOD(DSS_CONTROL, src, 15, 15);  /* VENC_HDMI_SWITCH */
 645 }
 646
 647 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
 648 {
 649         enum omap_display_type displays;
 650
 651         displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
 652         if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0)
 653                 return DSS_VENC_TV_CLK;
 654
 655         if ((displays & OMAP_DISPLAY_TYPE_VENC) == 0)
 656                 return DSS_HDMI_M_PCLK;
 657
 658         return REG_GET(DSS_CONTROL, 15, 15);
 659 }
 660
 661 static int dss_dpi_select_source_omap2_omap3(int port, enum omap_channel channel)
 662 {
 663         if (channel != OMAP_DSS_CHANNEL_LCD)
 664                 return -EINVAL;
 665
 666         return 0;
 667 }
 668
 669 static int dss_dpi_select_source_omap4(int port, enum omap_channel channel)
 670 {
 671         int val;
 672
 673         switch (channel) {
 674         case OMAP_DSS_CHANNEL_LCD2:
 675                 val = 0;
 676                 break;
 677         case OMAP_DSS_CHANNEL_DIGIT:
 678                 val = 1;
 679                 break;
 680         default:
 681                 return -EINVAL;
 682         }
 683
 684         REG_FLD_MOD(DSS_CONTROL, val, 17, 17);
 685
 686         return 0;
 687 }
 688
 689 static int dss_dpi_select_source_omap5(int port, enum omap_channel channel)
 690 {
 691         int val;
 692
 693         switch (channel) {
 694         case OMAP_DSS_CHANNEL_LCD:
 695                 val = 1;
 696                 break;
 697         case OMAP_DSS_CHANNEL_LCD2:
 698                 val = 2;
 699                 break;
 700         case OMAP_DSS_CHANNEL_LCD3:
 701                 val = 3;
 702                 break;
 703         case OMAP_DSS_CHANNEL_DIGIT:
 704                 val = 0;
 705                 break;
 706         default:
 707                 return -EINVAL;
 708         }
 709
 710         REG_FLD_MOD(DSS_CONTROL, val, 17, 16);
 711
 712         return 0;
 713 }
 714
 715 static int dss_dpi_select_source_dra7xx(int port, enum omap_channel channel)
 716 {
 717         switch (port) {
 718         case 0:
 719                 return dss_dpi_select_source_omap5(port, channel);
 720         case 1:
 721                 if (channel != OMAP_DSS_CHANNEL_LCD2)
 722                         return -EINVAL;
 723                 break;
 724         case 2:
 725                 if (channel != OMAP_DSS_CHANNEL_LCD3)
 726                         return -EINVAL;
 727                 break;
 728         default:
 729                 return -EINVAL;
 730         }
 731
 732         return 0;
 733 }
 734
 735 int dss_dpi_select_source(int port, enum omap_channel channel)
 736 {
 737         return dss.feat->dpi_select_source(port, channel);
 738 }
 739
 740 static int dss_get_clocks(void)
 741 {
 742         struct clk *clk;
 743
 744         clk = devm_clk_get(&dss.pdev->dev, "fck");
 745         if (IS_ERR(clk)) {
 746                 DSSERR("can't get clock fck\n");
 747                 return PTR_ERR(clk);
 748         }
 749
 750         dss.dss_clk = clk;
 751
 752         if (dss.feat->parent_clk_name) {
 753                 clk = clk_get(NULL, dss.feat->parent_clk_name);
 754                 if (IS_ERR(clk)) {
 755                         DSSERR("Failed to get %s\n", dss.feat->parent_clk_name);
 756                         return PTR_ERR(clk);
 757                 }
 758         } else {
 759                 clk = NULL;
 760         }
 761
 762         dss.parent_clk = clk;
 763
 764         return 0;
 765 }
 766
 767 static void dss_put_clocks(void)
 768 {
 769         if (dss.parent_clk)
 770                 clk_put(dss.parent_clk);
 771 }
 772
 773 int dss_runtime_get(void)
 774 {
 775         int r;
 776
 777         DSSDBG("dss_runtime_get\n");
 778
 779         r = pm_runtime_get_sync(&dss.pdev->dev);
 780         WARN_ON(r < 0);
 781         return r < 0 ? r : 0;
 782 }
 783
 784 void dss_runtime_put(void)
 785 {
 786         int r;
 787
 788         DSSDBG("dss_runtime_put\n");
 789
 790         r = pm_runtime_put_sync(&dss.pdev->dev);
 791         WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY);
 792 }
 793
 794 /* DEBUGFS */
 795 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
 796 void dss_debug_dump_clocks(struct seq_file *s)
 797 {
 798         dss_dump_clocks(s);
 799         dispc_dump_clocks(s);
 800 #ifdef CONFIG_OMAP2_DSS_DSI
 801         dsi_dump_clocks(s);
 802 #endif
 803 }
 804 #endif
 805
 806
 807 static const enum omap_display_type omap2plus_ports[] = {
 808         OMAP_DISPLAY_TYPE_DPI,
 809 };
 810
 811 static const enum omap_display_type omap34xx_ports[] = {
 812         OMAP_DISPLAY_TYPE_DPI,
 813         OMAP_DISPLAY_TYPE_SDI,
 814 };
 815
 816 static const enum omap_display_type dra7xx_ports[] = {
 817         OMAP_DISPLAY_TYPE_DPI,
 818         OMAP_DISPLAY_TYPE_DPI,
 819         OMAP_DISPLAY_TYPE_DPI,
 820 };
 821
 822 static const struct dss_features omap24xx_dss_feats = {
 823         /*
 824          * fck div max is really 16, but the divider range has gaps. The range
 825          * from 1 to 6 has no gaps, so let's use that as a max.
 826          */
 827         .fck_div_max            =       6,
 828         .dss_fck_multiplier     =       2,
 829         .parent_clk_name        =       "core_ck",
 830         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 831         .ports                  =       omap2plus_ports,
 832         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
 833 };
 834
 835 static const struct dss_features omap34xx_dss_feats = {
 836         .fck_div_max            =       16,
 837         .dss_fck_multiplier     =       2,
 838         .parent_clk_name        =       "dpll4_ck",
 839         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 840         .ports                  =       omap34xx_ports,
 841         .num_ports              =       ARRAY_SIZE(omap34xx_ports),
 842 };
 843
 844 static const struct dss_features omap3630_dss_feats = {
 845         .fck_div_max            =       32,
 846         .dss_fck_multiplier     =       1,
 847         .parent_clk_name        =       "dpll4_ck",
 848         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 849         .ports                  =       omap2plus_ports,
 850         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
 851 };
 852
 853 static const struct dss_features omap44xx_dss_feats = {
 854         .fck_div_max            =       32,
 855         .dss_fck_multiplier     =       1,
 856         .parent_clk_name        =       "dpll_per_x2_ck",
 857         .dpi_select_source      =       &dss_dpi_select_source_omap4,
 858         .ports                  =       omap2plus_ports,
 859         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
 860 };
 861
 862 static const struct dss_features omap54xx_dss_feats = {
 863         .fck_div_max            =       64,
 864         .dss_fck_multiplier     =       1,
 865         .parent_clk_name        =       "dpll_per_x2_ck",
 866         .dpi_select_source      =       &dss_dpi_select_source_omap5,
 867         .ports                  =       omap2plus_ports,
 868         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
 869 };
 870
 871 static const struct dss_features am43xx_dss_feats = {
 872         .fck_div_max            =       0,
 873         .dss_fck_multiplier     =       0,
 874         .parent_clk_name        =       NULL,
 875         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 876         .ports                  =       omap2plus_ports,
 877         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
 878 };
 879
 880 static const struct dss_features dra7xx_dss_feats = {
 881         .fck_div_max            =       64,
 882         .dss_fck_multiplier     =       1,
 883         .parent_clk_name        =       "dpll_per_x2_ck",
 884         .dpi_select_source      =       &dss_dpi_select_source_dra7xx,
 885         .ports                  =       dra7xx_ports,
 886         .num_ports              =       ARRAY_SIZE(dra7xx_ports),
 887 };
 888
 889 static int dss_init_features(struct platform_device *pdev)
 890 {
 891         const struct dss_features *src;
 892         struct dss_features *dst;
 893
 894         dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
 895         if (!dst) {
 896                 dev_err(&pdev->dev, "Failed to allocate local DSS Features\n");
 897                 return -ENOMEM;
 898         }
 899
 900         switch (omapdss_get_version()) {
 901         case OMAPDSS_VER_OMAP24xx:
 902                 src = &omap24xx_dss_feats;
 903                 break;
 904
 905         case OMAPDSS_VER_OMAP34xx_ES1:
 906         case OMAPDSS_VER_OMAP34xx_ES3:
 907         case OMAPDSS_VER_AM35xx:
 908                 src = &omap34xx_dss_feats;
 909                 break;
 910
 911         case OMAPDSS_VER_OMAP3630:
 912                 src = &omap3630_dss_feats;
 913                 break;
 914
 915         case OMAPDSS_VER_OMAP4430_ES1:
 916         case OMAPDSS_VER_OMAP4430_ES2:
 917         case OMAPDSS_VER_OMAP4:
 918                 src = &omap44xx_dss_feats;
 919                 break;
 920
 921         case OMAPDSS_VER_OMAP5:
 922                 src = &omap54xx_dss_feats;
 923                 break;
 924
 925         case OMAPDSS_VER_AM43xx:
 926                 src = &am43xx_dss_feats;
 927                 break;
 928
 929         case OMAPDSS_VER_DRA7xx:
 930                 src = &dra7xx_dss_feats;
 931                 break;
 932
 933         default:
 934                 return -ENODEV;
 935         }
 936
 937         memcpy(dst, src, sizeof(*dst));
 938         dss.feat = dst;
 939
 940         return 0;
 941 }
 942
 943 static int dss_init_ports(struct platform_device *pdev)
 944 {
 945         struct device_node *parent = pdev->dev.of_node;
 946         struct device_node *port;
 947         int r;
 948
 949         if (parent == NULL)
 950                 return 0;
 951
 952         port = omapdss_of_get_next_port(parent, NULL);
 953         if (!port)
 954                 return 0;
 955
 956         if (dss.feat->num_ports == 0)
 957                 return 0;
 958
 959         do {
 960                 enum omap_display_type port_type;
 961                 u32 reg;
 962
 963                 r = of_property_read_u32(port, "reg", &reg);
 964                 if (r)
 965                         reg = 0;
 966
 967                 if (reg >= dss.feat->num_ports)
 968                         continue;
 969
 970                 port_type = dss.feat->ports[reg];
 971
 972                 switch (port_type) {
 973                 case OMAP_DISPLAY_TYPE_DPI:
 974                         dpi_init_port(pdev, port);
 975                         break;
 976                 case OMAP_DISPLAY_TYPE_SDI:
 977                         sdi_init_port(pdev, port);
 978                         break;
 979                 default:
 980                         break;
 981                 }
 982         } while ((port = omapdss_of_get_next_port(parent, port)) != NULL);
 983
 984         return 0;
 985 }
 986
 987 static void dss_uninit_ports(struct platform_device *pdev)
 988 {
 989         struct device_node *parent = pdev->dev.of_node;
 990         struct device_node *port;
 991
 992         if (parent == NULL)
 993                 return;
 994
 995         port = omapdss_of_get_next_port(parent, NULL);
 996         if (!port)
 997                 return;
 998
 999         if (dss.feat->num_ports == 0)
1000                 return;
1001
1002         do {
1003                 enum omap_display_type port_type;
1004                 u32 reg;
1005                 int r;
1006
1007                 r = of_property_read_u32(port, "reg", &reg);
1008                 if (r)
1009                         reg = 0;
1010
1011                 if (reg >= dss.feat->num_ports)
1012                         continue;
1013
1014                 port_type = dss.feat->ports[reg];
1015
1016                 switch (port_type) {
1017                 case OMAP_DISPLAY_TYPE_DPI:
1018                         dpi_uninit_port(port);
1019                         break;
1020                 case OMAP_DISPLAY_TYPE_SDI:
1021                         sdi_uninit_port(port);
1022                         break;
1023                 default:
1024                         break;
1025                 }
1026         } while ((port = omapdss_of_get_next_port(parent, port)) != NULL);
1027 }
1028
1029 static int dss_video_pll_probe(struct platform_device *pdev)
1030 {
1031         struct device_node *np = pdev->dev.of_node;
1032         struct regulator *pll_regulator;
1033         int r;
1034
1035         if (!np)
1036                 return 0;
1037
1038         if (of_property_read_bool(np, "syscon-pll-ctrl")) {
1039                 dss.syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np,
1040                         "syscon-pll-ctrl");
1041                 if (IS_ERR(dss.syscon_pll_ctrl)) {
1042                         dev_err(&pdev->dev,
1043                                 "failed to get syscon-pll-ctrl regmap\n");
1044                         return PTR_ERR(dss.syscon_pll_ctrl);
1045                 }
1046
1047                 if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1,
1048                                 &dss.syscon_pll_ctrl_offset)) {
1049                         dev_err(&pdev->dev,
1050                                 "failed to get syscon-pll-ctrl offset\n");
1051                         return -EINVAL;
1052                 }
1053         }
1054
1055         pll_regulator = devm_regulator_get(&pdev->dev, "vdda_video");
1056         if (IS_ERR(pll_regulator)) {
1057                 r = PTR_ERR(pll_regulator);
1058
1059                 switch (r) {
1060                 case -ENOENT:
1061                         pll_regulator = NULL;
1062                         break;
1063
1064                 case -EPROBE_DEFER:
1065                         return -EPROBE_DEFER;
1066
1067                 default:
1068                         DSSERR("can't get DPLL VDDA regulator\n");
1069                         return r;
1070                 }
1071         }
1072
1073         if (of_property_match_string(np, "reg-names", "pll1") >= 0) {
1074                 dss.video1_pll = dss_video_pll_init(pdev, 0, pll_regulator);
1075                 if (IS_ERR(dss.video1_pll))
1076                         return PTR_ERR(dss.video1_pll);
1077         }
1078
1079         if (of_property_match_string(np, "reg-names", "pll2") >= 0) {
1080                 dss.video2_pll = dss_video_pll_init(pdev, 1, pll_regulator);
1081                 if (IS_ERR(dss.video2_pll)) {
1082                         dss_video_pll_uninit(dss.video1_pll);
1083                         return PTR_ERR(dss.video2_pll);
1084                 }
1085         }
1086
1087         return 0;
1088 }
1089
1090 /* DSS HW IP initialisation */
1091 static int dss_bind(struct device *dev)
1092 {
1093         struct platform_device *pdev = to_platform_device(dev);
1094         struct resource *dss_mem;
1095         u32 rev;
1096         int r;
1097
1098         dss.pdev = pdev;
1099
1100         r = dss_init_features(dss.pdev);
1101         if (r)
1102                 return r;
1103
1104         dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
1105         if (!dss_mem) {
1106                 DSSERR("can't get IORESOURCE_MEM DSS\n");
1107                 return -EINVAL;
1108         }
1109
1110         dss.base = devm_ioremap(&pdev->dev, dss_mem->start,
1111                                 resource_size(dss_mem));
1112         if (!dss.base) {
1113                 DSSERR("can't ioremap DSS\n");
1114                 return -ENOMEM;
1115         }
1116
1117         r = dss_get_clocks();
1118         if (r)
1119                 return r;
1120
1121         r = dss_setup_default_clock();
1122         if (r)
1123                 goto err_setup_clocks;
1124
1125         r = dss_video_pll_probe(pdev);
1126         if (r)
1127                 goto err_pll_init;
1128
1129         r = dss_init_ports(pdev);
1130         if (r)
1131                 goto err_init_ports;
1132
1133         pm_runtime_enable(&pdev->dev);
1134
1135         r = dss_runtime_get();
1136         if (r)
1137                 goto err_runtime_get;
1138
1139         dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
1140
1141         /* Select DPLL */
1142         REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
1143
1144         dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
1145
1146 #ifdef CONFIG_OMAP2_DSS_VENC
1147         REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);      /* venc dac demen */
1148         REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);      /* venc clock 4x enable */
1149         REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
1150 #endif
1151         dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
1152         dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
1153         dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
1154         dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
1155         dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
1156
1157         rev = dss_read_reg(DSS_REVISION);
1158         printk(KERN_INFO "OMAP DSS rev %d.%d\n",
1159                         FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
1160
1161         dss_runtime_put();
1162
1163         r = component_bind_all(&pdev->dev, NULL);
1164         if (r)
1165                 goto err_component;
1166
1167         dss_debugfs_create_file("dss", dss_dump_regs);
1168
1169         pm_set_vt_switch(0);
1170
1171         dss_initialized = true;
1172
1173         return 0;
1174
1175 err_component:
1176 err_runtime_get:
1177         pm_runtime_disable(&pdev->dev);
1178         dss_uninit_ports(pdev);
1179 err_init_ports:
1180         if (dss.video1_pll)
1181                 dss_video_pll_uninit(dss.video1_pll);
1182
1183         if (dss.video2_pll)
1184                 dss_video_pll_uninit(dss.video2_pll);
1185 err_pll_init:
1186 err_setup_clocks:
1187         dss_put_clocks();
1188         return r;
1189 }
1190
1191 static void dss_unbind(struct device *dev)
1192 {
1193         struct platform_device *pdev = to_platform_device(dev);
1194
1195         dss_initialized = false;
1196
1197         component_unbind_all(&pdev->dev, NULL);
1198
1199         if (dss.video1_pll)
1200                 dss_video_pll_uninit(dss.video1_pll);
1201
1202         if (dss.video2_pll)
1203                 dss_video_pll_uninit(dss.video2_pll);
1204
1205         dss_uninit_ports(pdev);
1206
1207         pm_runtime_disable(&pdev->dev);
1208
1209         dss_put_clocks();
1210 }
1211
1212 static const struct component_master_ops dss_component_ops = {
1213         .bind = dss_bind,
1214         .unbind = dss_unbind,
1215 };
1216
1217 static int dss_component_compare(struct device *dev, void *data)
1218 {
1219         struct device *child = data;
1220         return dev == child;
1221 }
1222
1223 static int dss_add_child_component(struct device *dev, void *data)
1224 {
1225         struct component_match **match = data;
1226
1227         /*
1228          * HACK
1229          * We don't have a working driver for rfbi, so skip it here always.
1230          * Otherwise dss will never get probed successfully, as it will wait
1231          * for rfbi to get probed.
1232          */
1233         if (strstr(dev_name(dev), "rfbi"))
1234                 return 0;
1235
1236         component_match_add(dev->parent, match, dss_component_compare, dev);
1237
1238         return 0;
1239 }
1240
1241 static int dss_probe(struct platform_device *pdev)
1242 {
1243         struct component_match *match = NULL;
1244         int r;
1245
1246         /* add all the child devices as components */
1247         device_for_each_child(&pdev->dev, &match, dss_add_child_component);
1248
1249         r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match);
1250         if (r)
1251                 return r;
1252
1253         return 0;
1254 }
1255
1256 static int dss_remove(struct platform_device *pdev)
1257 {
1258         component_master_del(&pdev->dev, &dss_component_ops);
1259         return 0;
1260 }
1261
1262 static int dss_runtime_suspend(struct device *dev)
1263 {
1264         dss_save_context();
1265         dss_set_min_bus_tput(dev, 0);
1266
1267         pinctrl_pm_select_sleep_state(dev);
1268
1269         return 0;
1270 }
1271
1272 static int dss_runtime_resume(struct device *dev)
1273 {
1274         int r;
1275
1276         pinctrl_pm_select_default_state(dev);
1277
1278         /*
1279          * Set an arbitrarily high tput request to ensure OPP100.
1280          * What we should really do is to make a request to stay in OPP100,
1281          * without any tput requirements, but that is not currently possible
1282          * via the PM layer.
1283          */
1284
1285         r = dss_set_min_bus_tput(dev, 1000000000);
1286         if (r)
1287                 return r;
1288
1289         dss_restore_context();
1290         return 0;
1291 }
1292
1293 static const struct dev_pm_ops dss_pm_ops = {
1294         .runtime_suspend = dss_runtime_suspend,
1295         .runtime_resume = dss_runtime_resume,
1296 };
1297
1298 static const struct of_device_id dss_of_match[] = {
1299         { .compatible = "ti,omap2-dss", },
1300         { .compatible = "ti,omap3-dss", },
1301         { .compatible = "ti,omap4-dss", },
1302         { .compatible = "ti,omap5-dss", },
1303         { .compatible = "ti,dra7-dss", },
1304         {},
1305 };
1306
1307 MODULE_DEVICE_TABLE(of, dss_of_match);
1308
1309 static struct platform_driver omap_dsshw_driver = {
1310         .probe          = dss_probe,
1311         .remove         = dss_remove,
1312         .driver         = {
1313                 .name   = "omapdss_dss",
1314                 .pm     = &dss_pm_ops,
1315                 .of_match_table = dss_of_match,
1316                 .suppress_bind_attrs = true,
1317         },
1318 };
1319
1320 int __init dss_init_platform_driver(void)
1321 {
1322         return platform_driver_register(&omap_dsshw_driver);
1323 }
1324
1325 void dss_uninit_platform_driver(void)
1326 {
1327         platform_driver_unregister(&omap_dsshw_driver);
1328 }