2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/backlight.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_panel.h>
36 #include <video/display_timing.h>
37 #include <video/videomode.h>
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
42 const struct display_timing *timings;
43 unsigned int num_timings;
48 * @width: width (in millimeters) of the panel's active display area
49 * @height: height (in millimeters) of the panel's active display area
57 * @prepare: the time (in milliseconds) that it takes for the panel to
58 * become ready and start receiving video data
59 * @enable: the time (in milliseconds) that it takes for the panel to
60 * display the first valid frame after starting to receive
62 * @disable: the time (in milliseconds) that it takes for the panel to
63 * turn the display off (no content is visible)
64 * @unprepare: the time (in milliseconds) that it takes for the panel
65 * to power itself down completely
71 unsigned int unprepare;
79 struct drm_panel base;
83 const struct panel_desc *desc;
85 struct backlight_device *backlight;
86 struct regulator *supply;
87 struct i2c_adapter *ddc;
89 struct gpio_desc *enable_gpio;
92 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
94 return container_of(panel, struct panel_simple, base);
97 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
99 struct drm_connector *connector = panel->base.connector;
100 struct drm_device *drm = panel->base.drm;
101 struct drm_display_mode *mode;
102 unsigned int i, num = 0;
107 for (i = 0; i < panel->desc->num_timings; i++) {
108 const struct display_timing *dt = &panel->desc->timings[i];
111 videomode_from_timing(dt, &vm);
112 mode = drm_mode_create(drm);
114 dev_err(drm->dev, "failed to add mode %ux%u\n",
115 dt->hactive.typ, dt->vactive.typ);
119 drm_display_mode_from_videomode(&vm, mode);
121 mode->type |= DRM_MODE_TYPE_DRIVER;
123 if (panel->desc->num_modes == 1)
124 mode->type |= DRM_MODE_TYPE_PREFERRED;
126 drm_mode_probed_add(connector, mode);
130 for (i = 0; i < panel->desc->num_modes; i++) {
131 const struct drm_display_mode *m = &panel->desc->modes[i];
133 mode = drm_mode_duplicate(drm, m);
135 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
136 m->hdisplay, m->vdisplay, m->vrefresh);
140 mode->type |= DRM_MODE_TYPE_DRIVER;
142 if (panel->desc->num_modes == 1)
143 mode->type |= DRM_MODE_TYPE_PREFERRED;
145 drm_mode_set_name(mode);
147 drm_mode_probed_add(connector, mode);
151 connector->display_info.bpc = panel->desc->bpc;
152 connector->display_info.width_mm = panel->desc->size.width;
153 connector->display_info.height_mm = panel->desc->size.height;
154 if (panel->desc->bus_format)
155 drm_display_info_set_bus_formats(&connector->display_info,
156 &panel->desc->bus_format, 1);
157 connector->display_info.bus_flags = panel->desc->bus_flags;
162 static int panel_simple_disable(struct drm_panel *panel)
164 struct panel_simple *p = to_panel_simple(panel);
170 p->backlight->props.power = FB_BLANK_POWERDOWN;
171 p->backlight->props.state |= BL_CORE_FBBLANK;
172 backlight_update_status(p->backlight);
175 if (p->desc->delay.disable)
176 msleep(p->desc->delay.disable);
183 static int panel_simple_unprepare(struct drm_panel *panel)
185 struct panel_simple *p = to_panel_simple(panel);
191 gpiod_set_value_cansleep(p->enable_gpio, 0);
193 regulator_disable(p->supply);
195 if (p->desc->delay.unprepare)
196 msleep(p->desc->delay.unprepare);
203 static int panel_simple_prepare(struct drm_panel *panel)
205 struct panel_simple *p = to_panel_simple(panel);
211 err = regulator_enable(p->supply);
213 dev_err(panel->dev, "failed to enable supply: %d\n", err);
218 gpiod_set_value_cansleep(p->enable_gpio, 1);
220 if (p->desc->delay.prepare)
221 msleep(p->desc->delay.prepare);
228 static int panel_simple_enable(struct drm_panel *panel)
230 struct panel_simple *p = to_panel_simple(panel);
235 if (p->desc->delay.enable)
236 msleep(p->desc->delay.enable);
239 p->backlight->props.state &= ~BL_CORE_FBBLANK;
240 p->backlight->props.power = FB_BLANK_UNBLANK;
241 backlight_update_status(p->backlight);
249 static int panel_simple_get_modes(struct drm_panel *panel)
251 struct panel_simple *p = to_panel_simple(panel);
254 /* probe EDID if a DDC bus is available */
256 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
257 drm_mode_connector_update_edid_property(panel->connector, edid);
259 num += drm_add_edid_modes(panel->connector, edid);
264 /* add hard-coded panel modes */
265 num += panel_simple_get_fixed_modes(p);
270 static int panel_simple_get_timings(struct drm_panel *panel,
271 unsigned int num_timings,
272 struct display_timing *timings)
274 struct panel_simple *p = to_panel_simple(panel);
277 if (p->desc->num_timings < num_timings)
278 num_timings = p->desc->num_timings;
281 for (i = 0; i < num_timings; i++)
282 timings[i] = p->desc->timings[i];
284 return p->desc->num_timings;
287 static const struct drm_panel_funcs panel_simple_funcs = {
288 .disable = panel_simple_disable,
289 .unprepare = panel_simple_unprepare,
290 .prepare = panel_simple_prepare,
291 .enable = panel_simple_enable,
292 .get_modes = panel_simple_get_modes,
293 .get_timings = panel_simple_get_timings,
296 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
298 struct device_node *backlight, *ddc;
299 struct panel_simple *panel;
302 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
306 panel->enabled = false;
307 panel->prepared = false;
310 panel->supply = devm_regulator_get(dev, "power");
311 if (IS_ERR(panel->supply))
312 return PTR_ERR(panel->supply);
314 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
316 if (IS_ERR(panel->enable_gpio)) {
317 err = PTR_ERR(panel->enable_gpio);
318 dev_err(dev, "failed to request GPIO: %d\n", err);
322 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
324 panel->backlight = of_find_backlight_by_node(backlight);
325 of_node_put(backlight);
327 if (!panel->backlight)
328 return -EPROBE_DEFER;
331 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
333 panel->ddc = of_find_i2c_adapter_by_node(ddc);
342 drm_panel_init(&panel->base);
343 panel->base.dev = dev;
344 panel->base.funcs = &panel_simple_funcs;
346 err = drm_panel_add(&panel->base);
350 dev_set_drvdata(dev, panel);
356 put_device(&panel->ddc->dev);
358 if (panel->backlight)
359 put_device(&panel->backlight->dev);
364 static int panel_simple_remove(struct device *dev)
366 struct panel_simple *panel = dev_get_drvdata(dev);
368 drm_panel_detach(&panel->base);
369 drm_panel_remove(&panel->base);
371 panel_simple_disable(&panel->base);
374 put_device(&panel->ddc->dev);
376 if (panel->backlight)
377 put_device(&panel->backlight->dev);
382 static void panel_simple_shutdown(struct device *dev)
384 struct panel_simple *panel = dev_get_drvdata(dev);
386 panel_simple_disable(&panel->base);
389 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
392 .hsync_start = 800 + 0,
393 .hsync_end = 800 + 0 + 255,
394 .htotal = 800 + 0 + 255 + 0,
396 .vsync_start = 480 + 2,
397 .vsync_end = 480 + 2 + 45,
398 .vtotal = 480 + 2 + 45 + 0,
400 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
403 static const struct panel_desc ampire_am800480r3tmqwa1h = {
404 .modes = &ire_am800480r3tmqwa1h_mode,
411 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
414 static const struct drm_display_mode auo_b101aw03_mode = {
417 .hsync_start = 1024 + 156,
418 .hsync_end = 1024 + 156 + 8,
419 .htotal = 1024 + 156 + 8 + 156,
421 .vsync_start = 600 + 16,
422 .vsync_end = 600 + 16 + 6,
423 .vtotal = 600 + 16 + 6 + 16,
427 static const struct panel_desc auo_b101aw03 = {
428 .modes = &auo_b101aw03_mode,
437 static const struct drm_display_mode auo_b101ean01_mode = {
440 .hsync_start = 1280 + 119,
441 .hsync_end = 1280 + 119 + 32,
442 .htotal = 1280 + 119 + 32 + 21,
444 .vsync_start = 800 + 4,
445 .vsync_end = 800 + 4 + 20,
446 .vtotal = 800 + 4 + 20 + 8,
450 static const struct panel_desc auo_b101ean01 = {
451 .modes = &auo_b101ean01_mode,
460 static const struct drm_display_mode auo_b101xtn01_mode = {
463 .hsync_start = 1366 + 20,
464 .hsync_end = 1366 + 20 + 70,
465 .htotal = 1366 + 20 + 70,
467 .vsync_start = 768 + 14,
468 .vsync_end = 768 + 14 + 42,
469 .vtotal = 768 + 14 + 42,
471 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
474 static const struct panel_desc auo_b101xtn01 = {
475 .modes = &auo_b101xtn01_mode,
484 static const struct drm_display_mode auo_b116xw03_mode = {
487 .hsync_start = 1366 + 40,
488 .hsync_end = 1366 + 40 + 40,
489 .htotal = 1366 + 40 + 40 + 32,
491 .vsync_start = 768 + 10,
492 .vsync_end = 768 + 10 + 12,
493 .vtotal = 768 + 10 + 12 + 6,
497 static const struct panel_desc auo_b116xw03 = {
498 .modes = &auo_b116xw03_mode,
507 static const struct drm_display_mode auo_b133xtn01_mode = {
510 .hsync_start = 1366 + 48,
511 .hsync_end = 1366 + 48 + 32,
512 .htotal = 1366 + 48 + 32 + 20,
514 .vsync_start = 768 + 3,
515 .vsync_end = 768 + 3 + 6,
516 .vtotal = 768 + 3 + 6 + 13,
520 static const struct panel_desc auo_b133xtn01 = {
521 .modes = &auo_b133xtn01_mode,
530 static const struct drm_display_mode auo_b133htn01_mode = {
533 .hsync_start = 1920 + 172,
534 .hsync_end = 1920 + 172 + 80,
535 .htotal = 1920 + 172 + 80 + 60,
537 .vsync_start = 1080 + 25,
538 .vsync_end = 1080 + 25 + 10,
539 .vtotal = 1080 + 25 + 10 + 10,
543 static const struct panel_desc auo_b133htn01 = {
544 .modes = &auo_b133htn01_mode,
558 static const struct drm_display_mode avic_tm070ddh03_mode = {
561 .hsync_start = 1024 + 160,
562 .hsync_end = 1024 + 160 + 4,
563 .htotal = 1024 + 160 + 4 + 156,
565 .vsync_start = 600 + 17,
566 .vsync_end = 600 + 17 + 1,
567 .vtotal = 600 + 17 + 1 + 17,
571 static const struct panel_desc avic_tm070ddh03 = {
572 .modes = &avic_tm070ddh03_mode,
586 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
589 .hsync_start = 1366 + 58,
590 .hsync_end = 1366 + 58 + 58,
591 .htotal = 1366 + 58 + 58 + 58,
593 .vsync_start = 768 + 4,
594 .vsync_end = 768 + 4 + 4,
595 .vtotal = 768 + 4 + 4 + 4,
599 static const struct panel_desc chunghwa_claa101wa01a = {
600 .modes = &chunghwa_claa101wa01a_mode,
609 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
612 .hsync_start = 1366 + 48,
613 .hsync_end = 1366 + 48 + 32,
614 .htotal = 1366 + 48 + 32 + 20,
616 .vsync_start = 768 + 16,
617 .vsync_end = 768 + 16 + 8,
618 .vtotal = 768 + 16 + 8 + 16,
622 static const struct panel_desc chunghwa_claa101wb01 = {
623 .modes = &chunghwa_claa101wb01_mode,
632 static const struct drm_display_mode edt_et057090dhu_mode = {
635 .hsync_start = 640 + 16,
636 .hsync_end = 640 + 16 + 30,
637 .htotal = 640 + 16 + 30 + 114,
639 .vsync_start = 480 + 10,
640 .vsync_end = 480 + 10 + 3,
641 .vtotal = 480 + 10 + 3 + 32,
643 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
646 static const struct panel_desc edt_et057090dhu = {
647 .modes = &edt_et057090dhu_mode,
656 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
659 .hsync_start = 800 + 40,
660 .hsync_end = 800 + 40 + 128,
661 .htotal = 800 + 40 + 128 + 88,
663 .vsync_start = 480 + 10,
664 .vsync_end = 480 + 10 + 2,
665 .vtotal = 480 + 10 + 2 + 33,
667 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
670 static const struct panel_desc edt_etm0700g0dh6 = {
671 .modes = &edt_etm0700g0dh6_mode,
680 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
683 .hsync_start = 800 + 168,
684 .hsync_end = 800 + 168 + 64,
685 .htotal = 800 + 168 + 64 + 88,
687 .vsync_start = 480 + 37,
688 .vsync_end = 480 + 37 + 2,
689 .vtotal = 480 + 37 + 2 + 8,
693 static const struct panel_desc foxlink_fl500wvr00_a0t = {
694 .modes = &foxlink_fl500wvr00_a0t_mode,
701 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
704 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
707 .hsync_start = 480 + 5,
708 .hsync_end = 480 + 5 + 1,
709 .htotal = 480 + 5 + 1 + 40,
711 .vsync_start = 272 + 8,
712 .vsync_end = 272 + 8 + 1,
713 .vtotal = 272 + 8 + 1 + 8,
717 static const struct panel_desc giantplus_gpg482739qs5 = {
718 .modes = &giantplus_gpg482739qs5_mode,
725 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
728 static const struct display_timing hannstar_hsd070pww1_timing = {
729 .pixelclock = { 64300000, 71100000, 82000000 },
730 .hactive = { 1280, 1280, 1280 },
731 .hfront_porch = { 1, 1, 10 },
732 .hback_porch = { 1, 1, 10 },
734 * According to the data sheet, the minimum horizontal blanking interval
735 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
736 * minimum working horizontal blanking interval to be 60 clocks.
738 .hsync_len = { 58, 158, 661 },
739 .vactive = { 800, 800, 800 },
740 .vfront_porch = { 1, 1, 10 },
741 .vback_porch = { 1, 1, 10 },
742 .vsync_len = { 1, 21, 203 },
743 .flags = DISPLAY_FLAGS_DE_HIGH,
746 static const struct panel_desc hannstar_hsd070pww1 = {
747 .timings = &hannstar_hsd070pww1_timing,
754 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
757 static const struct display_timing hannstar_hsd100pxn1_timing = {
758 .pixelclock = { 55000000, 65000000, 75000000 },
759 .hactive = { 1024, 1024, 1024 },
760 .hfront_porch = { 40, 40, 40 },
761 .hback_porch = { 220, 220, 220 },
762 .hsync_len = { 20, 60, 100 },
763 .vactive = { 768, 768, 768 },
764 .vfront_porch = { 7, 7, 7 },
765 .vback_porch = { 21, 21, 21 },
766 .vsync_len = { 10, 10, 10 },
767 .flags = DISPLAY_FLAGS_DE_HIGH,
770 static const struct panel_desc hannstar_hsd100pxn1 = {
771 .timings = &hannstar_hsd100pxn1_timing,
778 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
781 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
784 .hsync_start = 800 + 85,
785 .hsync_end = 800 + 85 + 86,
786 .htotal = 800 + 85 + 86 + 85,
788 .vsync_start = 480 + 16,
789 .vsync_end = 480 + 16 + 13,
790 .vtotal = 480 + 16 + 13 + 16,
794 static const struct panel_desc hitachi_tx23d38vm0caa = {
795 .modes = &hitachi_tx23d38vm0caa_mode,
804 static const struct drm_display_mode innolux_at043tn24_mode = {
807 .hsync_start = 480 + 2,
808 .hsync_end = 480 + 2 + 41,
809 .htotal = 480 + 2 + 41 + 2,
811 .vsync_start = 272 + 2,
812 .vsync_end = 272 + 2 + 11,
813 .vtotal = 272 + 2 + 11 + 2,
815 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
818 static const struct panel_desc innolux_at043tn24 = {
819 .modes = &innolux_at043tn24_mode,
826 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
829 static const struct drm_display_mode innolux_at070tn92_mode = {
832 .hsync_start = 800 + 210,
833 .hsync_end = 800 + 210 + 20,
834 .htotal = 800 + 210 + 20 + 46,
836 .vsync_start = 480 + 22,
837 .vsync_end = 480 + 22 + 10,
838 .vtotal = 480 + 22 + 23 + 10,
842 static const struct panel_desc innolux_at070tn92 = {
843 .modes = &innolux_at070tn92_mode,
849 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
852 static const struct drm_display_mode innolux_g121i1_l01_mode = {
855 .hsync_start = 1280 + 64,
856 .hsync_end = 1280 + 64 + 32,
857 .htotal = 1280 + 64 + 32 + 64,
859 .vsync_start = 800 + 9,
860 .vsync_end = 800 + 9 + 6,
861 .vtotal = 800 + 9 + 6 + 9,
865 static const struct panel_desc innolux_g121i1_l01 = {
866 .modes = &innolux_g121i1_l01_mode,
875 static const struct drm_display_mode innolux_g121x1_l03_mode = {
878 .hsync_start = 1024 + 0,
879 .hsync_end = 1024 + 1,
880 .htotal = 1024 + 0 + 1 + 320,
882 .vsync_start = 768 + 38,
883 .vsync_end = 768 + 38 + 1,
884 .vtotal = 768 + 38 + 1 + 0,
886 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
889 static const struct panel_desc innolux_g121x1_l03 = {
890 .modes = &innolux_g121x1_l03_mode,
904 static const struct drm_display_mode innolux_n116bge_mode = {
907 .hsync_start = 1366 + 136,
908 .hsync_end = 1366 + 136 + 30,
909 .htotal = 1366 + 136 + 30 + 60,
911 .vsync_start = 768 + 8,
912 .vsync_end = 768 + 8 + 12,
913 .vtotal = 768 + 8 + 12 + 12,
915 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
918 static const struct panel_desc innolux_n116bge = {
919 .modes = &innolux_n116bge_mode,
928 static const struct drm_display_mode innolux_n156bge_l21_mode = {
931 .hsync_start = 1366 + 16,
932 .hsync_end = 1366 + 16 + 34,
933 .htotal = 1366 + 16 + 34 + 50,
935 .vsync_start = 768 + 2,
936 .vsync_end = 768 + 2 + 6,
937 .vtotal = 768 + 2 + 6 + 12,
941 static const struct panel_desc innolux_n156bge_l21 = {
942 .modes = &innolux_n156bge_l21_mode,
951 static const struct drm_display_mode innolux_zj070na_01p_mode = {
954 .hsync_start = 1024 + 128,
955 .hsync_end = 1024 + 128 + 64,
956 .htotal = 1024 + 128 + 64 + 128,
958 .vsync_start = 600 + 16,
959 .vsync_end = 600 + 16 + 4,
960 .vtotal = 600 + 16 + 4 + 16,
964 static const struct panel_desc innolux_zj070na_01p = {
965 .modes = &innolux_zj070na_01p_mode,
974 static const struct display_timing kyo_tcg121xglp_timing = {
975 .pixelclock = { 52000000, 65000000, 71000000 },
976 .hactive = { 1024, 1024, 1024 },
977 .hfront_porch = { 2, 2, 2 },
978 .hback_porch = { 2, 2, 2 },
979 .hsync_len = { 86, 124, 244 },
980 .vactive = { 768, 768, 768 },
981 .vfront_porch = { 2, 2, 2 },
982 .vback_porch = { 2, 2, 2 },
983 .vsync_len = { 6, 34, 73 },
984 .flags = DISPLAY_FLAGS_DE_HIGH,
987 static const struct panel_desc kyo_tcg121xglp = {
988 .timings = &kyo_tcg121xglp_timing,
995 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
998 static const struct drm_display_mode lg_lb070wv8_mode = {
1001 .hsync_start = 800 + 88,
1002 .hsync_end = 800 + 88 + 80,
1003 .htotal = 800 + 88 + 80 + 88,
1005 .vsync_start = 480 + 10,
1006 .vsync_end = 480 + 10 + 25,
1007 .vtotal = 480 + 10 + 25 + 10,
1011 static const struct panel_desc lg_lb070wv8 = {
1012 .modes = &lg_lb070wv8_mode,
1019 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1022 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1025 .hsync_start = 1536 + 12,
1026 .hsync_end = 1536 + 12 + 16,
1027 .htotal = 1536 + 12 + 16 + 48,
1029 .vsync_start = 2048 + 8,
1030 .vsync_end = 2048 + 8 + 4,
1031 .vtotal = 2048 + 8 + 4 + 8,
1033 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1036 static const struct panel_desc lg_lp079qx1_sp0v = {
1037 .modes = &lg_lp079qx1_sp0v_mode,
1045 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1048 .hsync_start = 2048 + 150,
1049 .hsync_end = 2048 + 150 + 5,
1050 .htotal = 2048 + 150 + 5 + 5,
1052 .vsync_start = 1536 + 3,
1053 .vsync_end = 1536 + 3 + 1,
1054 .vtotal = 1536 + 3 + 1 + 9,
1058 static const struct panel_desc lg_lp097qx1_spa1 = {
1059 .modes = &lg_lp097qx1_spa1_mode,
1067 static const struct drm_display_mode lg_lp120up1_mode = {
1070 .hsync_start = 1920 + 40,
1071 .hsync_end = 1920 + 40 + 40,
1072 .htotal = 1920 + 40 + 40+ 80,
1074 .vsync_start = 1280 + 4,
1075 .vsync_end = 1280 + 4 + 4,
1076 .vtotal = 1280 + 4 + 4 + 12,
1080 static const struct panel_desc lg_lp120up1 = {
1081 .modes = &lg_lp120up1_mode,
1090 static const struct drm_display_mode lg_lp129qe_mode = {
1093 .hsync_start = 2560 + 48,
1094 .hsync_end = 2560 + 48 + 32,
1095 .htotal = 2560 + 48 + 32 + 80,
1097 .vsync_start = 1700 + 3,
1098 .vsync_end = 1700 + 3 + 10,
1099 .vtotal = 1700 + 3 + 10 + 36,
1103 static const struct panel_desc lg_lp129qe = {
1104 .modes = &lg_lp129qe_mode,
1113 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1116 .hsync_start = 480 + 2,
1117 .hsync_end = 480 + 2 + 41,
1118 .htotal = 480 + 2 + 41 + 2,
1120 .vsync_start = 272 + 2,
1121 .vsync_end = 272 + 2 + 4,
1122 .vtotal = 272 + 2 + 4 + 2,
1124 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1127 static const struct panel_desc nec_nl4827hc19_05b = {
1128 .modes = &nec_nl4827hc19_05b_mode,
1135 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1136 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1139 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1140 .pixelclock = { 30000000, 30000000, 40000000 },
1141 .hactive = { 800, 800, 800 },
1142 .hfront_porch = { 40, 40, 40 },
1143 .hback_porch = { 40, 40, 40 },
1144 .hsync_len = { 1, 48, 48 },
1145 .vactive = { 480, 480, 480 },
1146 .vfront_porch = { 13, 13, 13 },
1147 .vback_porch = { 29, 29, 29 },
1148 .vsync_len = { 3, 3, 3 },
1149 .flags = DISPLAY_FLAGS_DE_HIGH,
1152 static const struct panel_desc okaya_rs800480t_7x0gp = {
1153 .timings = &okaya_rs800480t_7x0gp_timing,
1166 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1169 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
1172 .hsync_start = 480 + 5,
1173 .hsync_end = 480 + 5 + 30,
1174 .htotal = 480 + 5 + 30 + 10,
1176 .vsync_start = 272 + 8,
1177 .vsync_end = 272 + 8 + 5,
1178 .vtotal = 272 + 8 + 5 + 3,
1182 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
1183 .modes = &olimex_lcd_olinuxino_43ts_mode,
1189 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1193 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
1194 * pixel clocks, but this is the timing that was being used in the Adafruit
1195 * installation instructions.
1197 static const struct drm_display_mode ontat_yx700wv03_mode = {
1208 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1213 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
1215 static const struct panel_desc ontat_yx700wv03 = {
1216 .modes = &ontat_yx700wv03_mode,
1223 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1226 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1229 .hsync_start = 480 + 10,
1230 .hsync_end = 480 + 10 + 10,
1231 .htotal = 480 + 10 + 10 + 15,
1233 .vsync_start = 800 + 3,
1234 .vsync_end = 800 + 3 + 3,
1235 .vtotal = 800 + 3 + 3 + 3,
1239 static const struct panel_desc ortustech_com43h4m85ulc = {
1240 .modes = &ortustech_com43h4m85ulc_mode,
1247 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1250 static const struct drm_display_mode qd43003c0_40_mode = {
1253 .hsync_start = 480 + 8,
1254 .hsync_end = 480 + 8 + 4,
1255 .htotal = 480 + 8 + 4 + 39,
1257 .vsync_start = 272 + 4,
1258 .vsync_end = 272 + 4 + 10,
1259 .vtotal = 272 + 4 + 10 + 2,
1263 static const struct panel_desc qd43003c0_40 = {
1264 .modes = &qd43003c0_40_mode,
1271 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1274 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1277 .hsync_start = 2560 + 48,
1278 .hsync_end = 2560 + 48 + 32,
1279 .htotal = 2560 + 48 + 32 + 80,
1281 .vsync_start = 1600 + 2,
1282 .vsync_end = 1600 + 2 + 5,
1283 .vtotal = 1600 + 2 + 5 + 57,
1287 static const struct panel_desc samsung_lsn122dl01_c01 = {
1288 .modes = &samsung_lsn122dl01_c01_mode,
1296 static const struct drm_display_mode samsung_ltn101nt05_mode = {
1299 .hsync_start = 1024 + 24,
1300 .hsync_end = 1024 + 24 + 136,
1301 .htotal = 1024 + 24 + 136 + 160,
1303 .vsync_start = 600 + 3,
1304 .vsync_end = 600 + 3 + 6,
1305 .vtotal = 600 + 3 + 6 + 61,
1309 static const struct panel_desc samsung_ltn101nt05 = {
1310 .modes = &samsung_ltn101nt05_mode,
1319 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1322 .hsync_start = 1366 + 64,
1323 .hsync_end = 1366 + 64 + 48,
1324 .htotal = 1366 + 64 + 48 + 128,
1326 .vsync_start = 768 + 2,
1327 .vsync_end = 768 + 2 + 5,
1328 .vtotal = 768 + 2 + 5 + 17,
1332 static const struct panel_desc samsung_ltn140at29_301 = {
1333 .modes = &samsung_ltn140at29_301_mode,
1342 static const struct display_timing sharp_lq101k1ly04_timing = {
1343 .pixelclock = { 60000000, 65000000, 80000000 },
1344 .hactive = { 1280, 1280, 1280 },
1345 .hfront_porch = { 20, 20, 20 },
1346 .hback_porch = { 20, 20, 20 },
1347 .hsync_len = { 10, 10, 10 },
1348 .vactive = { 800, 800, 800 },
1349 .vfront_porch = { 4, 4, 4 },
1350 .vback_porch = { 4, 4, 4 },
1351 .vsync_len = { 4, 4, 4 },
1352 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
1355 static const struct panel_desc sharp_lq101k1ly04 = {
1356 .timings = &sharp_lq101k1ly04_timing,
1363 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1366 static const struct drm_display_mode sharp_lq123p1jx31_mode = {
1369 .hsync_start = 2400 + 48,
1370 .hsync_end = 2400 + 48 + 32,
1371 .htotal = 2400 + 48 + 32 + 80,
1373 .vsync_start = 1600 + 3,
1374 .vsync_end = 1600 + 3 + 10,
1375 .vtotal = 1600 + 3 + 10 + 33,
1377 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1380 static const struct panel_desc sharp_lq123p1jx31 = {
1381 .modes = &sharp_lq123p1jx31_mode,
1389 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1392 .hsync_start = 800 + 1,
1393 .hsync_end = 800 + 1 + 64,
1394 .htotal = 800 + 1 + 64 + 64,
1396 .vsync_start = 480 + 1,
1397 .vsync_end = 480 + 1 + 23,
1398 .vtotal = 480 + 1 + 23 + 22,
1402 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1403 .modes = &shelly_sca07010_bfn_lnn_mode,
1409 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1412 static const struct drm_display_mode starry_kr122ea0sra_mode = {
1415 .hsync_start = 1920 + 16,
1416 .hsync_end = 1920 + 16 + 16,
1417 .htotal = 1920 + 16 + 16 + 32,
1419 .vsync_start = 1200 + 15,
1420 .vsync_end = 1200 + 15 + 2,
1421 .vtotal = 1200 + 15 + 2 + 18,
1423 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1426 static const struct panel_desc starry_kr122ea0sra = {
1427 .modes = &starry_kr122ea0sra_mode,
1435 static const struct drm_display_mode tpk_f07a_0102_mode = {
1438 .hsync_start = 800 + 40,
1439 .hsync_end = 800 + 40 + 128,
1440 .htotal = 800 + 40 + 128 + 88,
1442 .vsync_start = 480 + 10,
1443 .vsync_end = 480 + 10 + 2,
1444 .vtotal = 480 + 10 + 2 + 33,
1448 static const struct panel_desc tpk_f07a_0102 = {
1449 .modes = &tpk_f07a_0102_mode,
1455 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1458 static const struct drm_display_mode tpk_f10a_0102_mode = {
1461 .hsync_start = 1024 + 176,
1462 .hsync_end = 1024 + 176 + 5,
1463 .htotal = 1024 + 176 + 5 + 88,
1465 .vsync_start = 600 + 20,
1466 .vsync_end = 600 + 20 + 5,
1467 .vtotal = 600 + 20 + 5 + 25,
1471 static const struct panel_desc tpk_f10a_0102 = {
1472 .modes = &tpk_f10a_0102_mode,
1480 static const struct display_timing urt_umsh_8596md_timing = {
1481 .pixelclock = { 33260000, 33260000, 33260000 },
1482 .hactive = { 800, 800, 800 },
1483 .hfront_porch = { 41, 41, 41 },
1484 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
1485 .hsync_len = { 71, 128, 128 },
1486 .vactive = { 480, 480, 480 },
1487 .vfront_porch = { 10, 10, 10 },
1488 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
1489 .vsync_len = { 2, 2, 2 },
1490 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1491 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1494 static const struct panel_desc urt_umsh_8596md_lvds = {
1495 .timings = &urt_umsh_8596md_timing,
1502 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1505 static const struct panel_desc urt_umsh_8596md_parallel = {
1506 .timings = &urt_umsh_8596md_timing,
1513 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1516 static const struct of_device_id platform_of_match[] = {
1518 .compatible = "ampire,am800480r3tmqwa1h",
1519 .data = &ire_am800480r3tmqwa1h,
1521 .compatible = "auo,b101aw03",
1522 .data = &auo_b101aw03,
1524 .compatible = "auo,b101ean01",
1525 .data = &auo_b101ean01,
1527 .compatible = "auo,b101xtn01",
1528 .data = &auo_b101xtn01,
1530 .compatible = "auo,b116xw03",
1531 .data = &auo_b116xw03,
1533 .compatible = "auo,b133htn01",
1534 .data = &auo_b133htn01,
1536 .compatible = "auo,b133xtn01",
1537 .data = &auo_b133xtn01,
1539 .compatible = "avic,tm070ddh03",
1540 .data = &avic_tm070ddh03,
1542 .compatible = "chunghwa,claa101wa01a",
1543 .data = &chunghwa_claa101wa01a
1545 .compatible = "chunghwa,claa101wb01",
1546 .data = &chunghwa_claa101wb01
1548 .compatible = "edt,et057090dhu",
1549 .data = &edt_et057090dhu,
1551 .compatible = "edt,et070080dh6",
1552 .data = &edt_etm0700g0dh6,
1554 .compatible = "edt,etm0700g0dh6",
1555 .data = &edt_etm0700g0dh6,
1557 .compatible = "foxlink,fl500wvr00-a0t",
1558 .data = &foxlink_fl500wvr00_a0t,
1560 .compatible = "giantplus,gpg482739qs5",
1561 .data = &giantplus_gpg482739qs5
1563 .compatible = "hannstar,hsd070pww1",
1564 .data = &hannstar_hsd070pww1,
1566 .compatible = "hannstar,hsd100pxn1",
1567 .data = &hannstar_hsd100pxn1,
1569 .compatible = "hit,tx23d38vm0caa",
1570 .data = &hitachi_tx23d38vm0caa
1572 .compatible = "innolux,at043tn24",
1573 .data = &innolux_at043tn24,
1575 .compatible = "innolux,at070tn92",
1576 .data = &innolux_at070tn92,
1578 .compatible ="innolux,g121i1-l01",
1579 .data = &innolux_g121i1_l01
1581 .compatible = "innolux,g121x1-l03",
1582 .data = &innolux_g121x1_l03,
1584 .compatible = "innolux,n116bge",
1585 .data = &innolux_n116bge,
1587 .compatible = "innolux,n156bge-l21",
1588 .data = &innolux_n156bge_l21,
1590 .compatible = "innolux,zj070na-01p",
1591 .data = &innolux_zj070na_01p,
1593 .compatible = "kyo,tcg121xglp",
1594 .data = &kyo_tcg121xglp,
1596 .compatible = "lg,lb070wv8",
1597 .data = &lg_lb070wv8,
1599 .compatible = "lg,lp079qx1-sp0v",
1600 .data = &lg_lp079qx1_sp0v,
1602 .compatible = "lg,lp097qx1-spa1",
1603 .data = &lg_lp097qx1_spa1,
1605 .compatible = "lg,lp120up1",
1606 .data = &lg_lp120up1,
1608 .compatible = "lg,lp129qe",
1609 .data = &lg_lp129qe,
1611 .compatible = "nec,nl4827hc19-05b",
1612 .data = &nec_nl4827hc19_05b,
1614 .compatible = "okaya,rs800480t-7x0gp",
1615 .data = &okaya_rs800480t_7x0gp,
1617 .compatible = "olimex,lcd-olinuxino-43-ts",
1618 .data = &olimex_lcd_olinuxino_43ts,
1620 .compatible = "ontat,yx700wv03",
1621 .data = &ontat_yx700wv03,
1623 .compatible = "ortustech,com43h4m85ulc",
1624 .data = &ortustech_com43h4m85ulc,
1626 .compatible = "qiaodian,qd43003c0-40",
1627 .data = &qd43003c0_40,
1629 .compatible = "samsung,lsn122dl01-c01",
1630 .data = &samsung_lsn122dl01_c01,
1632 .compatible = "samsung,ltn101nt05",
1633 .data = &samsung_ltn101nt05,
1635 .compatible = "samsung,ltn140at29-301",
1636 .data = &samsung_ltn140at29_301,
1638 .compatible = "sharp,lq101k1ly04",
1639 .data = &sharp_lq101k1ly04,
1641 .compatible = "sharp,lq123p1jx31",
1642 .data = &sharp_lq123p1jx31,
1644 .compatible = "shelly,sca07010-bfn-lnn",
1645 .data = &shelly_sca07010_bfn_lnn,
1647 .compatible = "starry,kr122ea0sra",
1648 .data = &starry_kr122ea0sra,
1650 .compatible = "tpk,f07a-0102",
1651 .data = &tpk_f07a_0102,
1653 .compatible = "tpk,f10a-0102",
1654 .data = &tpk_f10a_0102,
1656 .compatible = "urt,umsh-8596md-t",
1657 .data = &urt_umsh_8596md_parallel,
1659 .compatible = "urt,umsh-8596md-1t",
1660 .data = &urt_umsh_8596md_parallel,
1662 .compatible = "urt,umsh-8596md-7t",
1663 .data = &urt_umsh_8596md_parallel,
1665 .compatible = "urt,umsh-8596md-11t",
1666 .data = &urt_umsh_8596md_lvds,
1668 .compatible = "urt,umsh-8596md-19t",
1669 .data = &urt_umsh_8596md_lvds,
1671 .compatible = "urt,umsh-8596md-20t",
1672 .data = &urt_umsh_8596md_parallel,
1677 MODULE_DEVICE_TABLE(of, platform_of_match);
1679 static int panel_simple_platform_probe(struct platform_device *pdev)
1681 const struct of_device_id *id;
1683 id = of_match_node(platform_of_match, pdev->dev.of_node);
1687 return panel_simple_probe(&pdev->dev, id->data);
1690 static int panel_simple_platform_remove(struct platform_device *pdev)
1692 return panel_simple_remove(&pdev->dev);
1695 static void panel_simple_platform_shutdown(struct platform_device *pdev)
1697 panel_simple_shutdown(&pdev->dev);
1700 static struct platform_driver panel_simple_platform_driver = {
1702 .name = "panel-simple",
1703 .of_match_table = platform_of_match,
1705 .probe = panel_simple_platform_probe,
1706 .remove = panel_simple_platform_remove,
1707 .shutdown = panel_simple_platform_shutdown,
1710 struct panel_desc_dsi {
1711 struct panel_desc desc;
1713 unsigned long flags;
1714 enum mipi_dsi_pixel_format format;
1718 static const struct drm_display_mode auo_b080uan01_mode = {
1721 .hsync_start = 1200 + 62,
1722 .hsync_end = 1200 + 62 + 4,
1723 .htotal = 1200 + 62 + 4 + 62,
1725 .vsync_start = 1920 + 9,
1726 .vsync_end = 1920 + 9 + 2,
1727 .vtotal = 1920 + 9 + 2 + 8,
1731 static const struct panel_desc_dsi auo_b080uan01 = {
1733 .modes = &auo_b080uan01_mode,
1741 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1742 .format = MIPI_DSI_FMT_RGB888,
1746 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
1749 .hsync_start = 1200 + 120,
1750 .hsync_end = 1200 + 120 + 20,
1751 .htotal = 1200 + 120 + 20 + 21,
1753 .vsync_start = 1920 + 21,
1754 .vsync_end = 1920 + 21 + 3,
1755 .vtotal = 1920 + 21 + 3 + 18,
1757 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1760 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1762 .modes = &boe_tv080wum_nl0_mode,
1769 .flags = MIPI_DSI_MODE_VIDEO |
1770 MIPI_DSI_MODE_VIDEO_BURST |
1771 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1772 .format = MIPI_DSI_FMT_RGB888,
1776 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1779 .hsync_start = 800 + 32,
1780 .hsync_end = 800 + 32 + 1,
1781 .htotal = 800 + 32 + 1 + 57,
1783 .vsync_start = 1280 + 28,
1784 .vsync_end = 1280 + 28 + 1,
1785 .vtotal = 1280 + 28 + 1 + 14,
1789 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1791 .modes = &lg_ld070wx3_sl01_mode,
1799 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1800 .format = MIPI_DSI_FMT_RGB888,
1804 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1807 .hsync_start = 720 + 12,
1808 .hsync_end = 720 + 12 + 4,
1809 .htotal = 720 + 12 + 4 + 112,
1811 .vsync_start = 1280 + 8,
1812 .vsync_end = 1280 + 8 + 4,
1813 .vtotal = 1280 + 8 + 4 + 12,
1817 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1819 .modes = &lg_lh500wx1_sd03_mode,
1827 .flags = MIPI_DSI_MODE_VIDEO,
1828 .format = MIPI_DSI_FMT_RGB888,
1832 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1835 .hsync_start = 1920 + 154,
1836 .hsync_end = 1920 + 154 + 16,
1837 .htotal = 1920 + 154 + 16 + 32,
1839 .vsync_start = 1200 + 17,
1840 .vsync_end = 1200 + 17 + 2,
1841 .vtotal = 1200 + 17 + 2 + 16,
1845 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1847 .modes = &panasonic_vvx10f004b00_mode,
1855 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1856 MIPI_DSI_CLOCK_NON_CONTINUOUS,
1857 .format = MIPI_DSI_FMT_RGB888,
1861 static const struct of_device_id dsi_of_match[] = {
1863 .compatible = "auo,b080uan01",
1864 .data = &auo_b080uan01
1866 .compatible = "boe,tv080wum-nl0",
1867 .data = &boe_tv080wum_nl0
1869 .compatible = "lg,ld070wx3-sl01",
1870 .data = &lg_ld070wx3_sl01
1872 .compatible = "lg,lh500wx1-sd03",
1873 .data = &lg_lh500wx1_sd03
1875 .compatible = "panasonic,vvx10f004b00",
1876 .data = &panasonic_vvx10f004b00
1881 MODULE_DEVICE_TABLE(of, dsi_of_match);
1883 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1885 const struct panel_desc_dsi *desc;
1886 const struct of_device_id *id;
1889 id = of_match_node(dsi_of_match, dsi->dev.of_node);
1895 err = panel_simple_probe(&dsi->dev, &desc->desc);
1899 dsi->mode_flags = desc->flags;
1900 dsi->format = desc->format;
1901 dsi->lanes = desc->lanes;
1903 return mipi_dsi_attach(dsi);
1906 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1910 err = mipi_dsi_detach(dsi);
1912 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1914 return panel_simple_remove(&dsi->dev);
1917 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1919 panel_simple_shutdown(&dsi->dev);
1922 static struct mipi_dsi_driver panel_simple_dsi_driver = {
1924 .name = "panel-simple-dsi",
1925 .of_match_table = dsi_of_match,
1927 .probe = panel_simple_dsi_probe,
1928 .remove = panel_simple_dsi_remove,
1929 .shutdown = panel_simple_dsi_shutdown,
1932 static int __init panel_simple_init(void)
1936 err = platform_driver_register(&panel_simple_platform_driver);
1940 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
1941 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
1948 module_init(panel_simple_init);
1950 static void __exit panel_simple_exit(void)
1952 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1953 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
1955 platform_driver_unregister(&panel_simple_platform_driver);
1957 module_exit(panel_simple_exit);
1959 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1960 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
1961 MODULE_LICENSE("GPL and additional rights");