drivers/gpu/drm/radeon/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include <drm/drm_fixed.h>
  30 #include "radeon.h"
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33
  34 static void atombios_overscan_setup(struct drm_crtc *crtc,
  35                                     struct drm_display_mode *mode,
  36                                     struct drm_display_mode *adjusted_mode)
  37 {
  38         struct drm_device *dev = crtc->dev;
  39         struct radeon_device *rdev = dev->dev_private;
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         SET_CRTC_OVERSCAN_PS_ALLOCATION args;
  42         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
  43         int a1, a2;
  44
  45         memset(&args, 0, sizeof(args));
  46
  47         args.ucCRTC = radeon_crtc->crtc_id;
  48
  49         switch (radeon_crtc->rmx_type) {
  50         case RMX_CENTER:
  51                 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
  52                 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
  53                 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
  54                 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
  55                 break;
  56         case RMX_ASPECT:
  57                 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
  58                 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
  59
  60                 if (a1 > a2) {
  61                         args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
  62                         args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
  63                 } else if (a2 > a1) {
  64                         args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
  65                         args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
  66                 }
  67                 break;
  68         case RMX_FULL:
  69         default:
  70                 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
  71                 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
  72                 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
  73                 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
  74                 break;
  75         }
  76         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  77 }
  78
  79 static void atombios_scaler_setup(struct drm_crtc *crtc)
  80 {
  81         struct drm_device *dev = crtc->dev;
  82         struct radeon_device *rdev = dev->dev_private;
  83         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  84         ENABLE_SCALER_PS_ALLOCATION args;
  85         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
  86         struct radeon_encoder *radeon_encoder =
  87                 to_radeon_encoder(radeon_crtc->encoder);
  88         /* fixme - fill in enc_priv for atom dac */
  89         enum radeon_tv_std tv_std = TV_STD_NTSC;
  90         bool is_tv = false, is_cv = false;
  91
  92         if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
  93                 return;
  94
  95         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
  96                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
  97                 tv_std = tv_dac->tv_std;
  98                 is_tv = true;
  99         }
 100
 101         memset(&args, 0, sizeof(args));
 102
 103         args.ucScaler = radeon_crtc->crtc_id;
 104
 105         if (is_tv) {
 106                 switch (tv_std) {
 107                 case TV_STD_NTSC:
 108                 default:
 109                         args.ucTVStandard = ATOM_TV_NTSC;
 110                         break;
 111                 case TV_STD_PAL:
 112                         args.ucTVStandard = ATOM_TV_PAL;
 113                         break;
 114                 case TV_STD_PAL_M:
 115                         args.ucTVStandard = ATOM_TV_PALM;
 116                         break;
 117                 case TV_STD_PAL_60:
 118                         args.ucTVStandard = ATOM_TV_PAL60;
 119                         break;
 120                 case TV_STD_NTSC_J:
 121                         args.ucTVStandard = ATOM_TV_NTSCJ;
 122                         break;
 123                 case TV_STD_SCART_PAL:
 124                         args.ucTVStandard = ATOM_TV_PAL; /* ??? */
 125                         break;
 126                 case TV_STD_SECAM:
 127                         args.ucTVStandard = ATOM_TV_SECAM;
 128                         break;
 129                 case TV_STD_PAL_CN:
 130                         args.ucTVStandard = ATOM_TV_PALCN;
 131                         break;
 132                 }
 133                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 134         } else if (is_cv) {
 135                 args.ucTVStandard = ATOM_TV_CV;
 136                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 137         } else {
 138                 switch (radeon_crtc->rmx_type) {
 139                 case RMX_FULL:
 140                         args.ucEnable = ATOM_SCALER_EXPANSION;
 141                         break;
 142                 case RMX_CENTER:
 143                         args.ucEnable = ATOM_SCALER_CENTER;
 144                         break;
 145                 case RMX_ASPECT:
 146                         args.ucEnable = ATOM_SCALER_EXPANSION;
 147                         break;
 148                 default:
 149                         if (ASIC_IS_AVIVO(rdev))
 150                                 args.ucEnable = ATOM_SCALER_DISABLE;
 151                         else
 152                                 args.ucEnable = ATOM_SCALER_CENTER;
 153                         break;
 154                 }
 155         }
 156         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 157         if ((is_tv || is_cv)
 158             && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
 159                 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
 160         }
 161 }
 162
 163 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
 164 {
 165         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 166         struct drm_device *dev = crtc->dev;
 167         struct radeon_device *rdev = dev->dev_private;
 168         int index =
 169             GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
 170         ENABLE_CRTC_PS_ALLOCATION args;
 171
 172         memset(&args, 0, sizeof(args));
 173
 174         args.ucCRTC = radeon_crtc->crtc_id;
 175         args.ucEnable = lock;
 176
 177         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 178 }
 179
 180 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
 181 {
 182         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 183         struct drm_device *dev = crtc->dev;
 184         struct radeon_device *rdev = dev->dev_private;
 185         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
 186         ENABLE_CRTC_PS_ALLOCATION args;
 187
 188         memset(&args, 0, sizeof(args));
 189
 190         args.ucCRTC = radeon_crtc->crtc_id;
 191         args.ucEnable = state;
 192
 193         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 194 }
 195
 196 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
 197 {
 198         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 199         struct drm_device *dev = crtc->dev;
 200         struct radeon_device *rdev = dev->dev_private;
 201         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
 202         ENABLE_CRTC_PS_ALLOCATION args;
 203
 204         memset(&args, 0, sizeof(args));
 205
 206         args.ucCRTC = radeon_crtc->crtc_id;
 207         args.ucEnable = state;
 208
 209         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 210 }
 211
 212 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
 213 {
 214         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 215         struct drm_device *dev = crtc->dev;
 216         struct radeon_device *rdev = dev->dev_private;
 217         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
 218         BLANK_CRTC_PS_ALLOCATION args;
 219
 220         memset(&args, 0, sizeof(args));
 221
 222         args.ucCRTC = radeon_crtc->crtc_id;
 223         args.ucBlanking = state;
 224
 225         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 226 }
 227
 228 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
 229 {
 230         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 231         struct drm_device *dev = crtc->dev;
 232         struct radeon_device *rdev = dev->dev_private;
 233         int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
 234         ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
 235
 236         memset(&args, 0, sizeof(args));
 237
 238         args.ucDispPipeId = radeon_crtc->crtc_id;
 239         args.ucEnable = state;
 240
 241         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 242 }
 243
 244 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 245 {
 246         struct drm_device *dev = crtc->dev;
 247         struct radeon_device *rdev = dev->dev_private;
 248         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 249
 250         switch (mode) {
 251         case DRM_MODE_DPMS_ON:
 252                 radeon_crtc->enabled = true;
 253                 /* adjust pm to dpms changes BEFORE enabling crtcs */
 254                 radeon_pm_compute_clocks(rdev);
 255                 atombios_enable_crtc(crtc, ATOM_ENABLE);
 256                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
 257                         atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
 258                 atombios_blank_crtc(crtc, ATOM_DISABLE);
 259                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 260                 radeon_crtc_load_lut(crtc);
 261                 break;
 262         case DRM_MODE_DPMS_STANDBY:
 263         case DRM_MODE_DPMS_SUSPEND:
 264         case DRM_MODE_DPMS_OFF:
 265                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 266                 if (radeon_crtc->enabled)
 267                         atombios_blank_crtc(crtc, ATOM_ENABLE);
 268                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
 269                         atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
 270                 atombios_enable_crtc(crtc, ATOM_DISABLE);
 271                 radeon_crtc->enabled = false;
 272                 /* adjust pm to dpms changes AFTER disabling crtcs */
 273                 radeon_pm_compute_clocks(rdev);
 274                 break;
 275         }
 276 }
 277
 278 static void
 279 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
 280                              struct drm_display_mode *mode)
 281 {
 282         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 283         struct drm_device *dev = crtc->dev;
 284         struct radeon_device *rdev = dev->dev_private;
 285         SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
 286         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
 287         u16 misc = 0;
 288
 289         memset(&args, 0, sizeof(args));
 290         args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
 291         args.usH_Blanking_Time =
 292                 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
 293         args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
 294         args.usV_Blanking_Time =
 295                 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
 296         args.usH_SyncOffset =
 297                 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
 298         args.usH_SyncWidth =
 299                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 300         args.usV_SyncOffset =
 301                 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
 302         args.usV_SyncWidth =
 303                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 304         args.ucH_Border = radeon_crtc->h_border;
 305         args.ucV_Border = radeon_crtc->v_border;
 306
 307         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 308                 misc |= ATOM_VSYNC_POLARITY;
 309         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 310                 misc |= ATOM_HSYNC_POLARITY;
 311         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 312                 misc |= ATOM_COMPOSITESYNC;
 313         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 314                 misc |= ATOM_INTERLACE;
 315         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 316                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 317
 318         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 319         args.ucCRTC = radeon_crtc->crtc_id;
 320
 321         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 322 }
 323
 324 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
 325                                      struct drm_display_mode *mode)
 326 {
 327         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 328         struct drm_device *dev = crtc->dev;
 329         struct radeon_device *rdev = dev->dev_private;
 330         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
 331         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 332         u16 misc = 0;
 333
 334         memset(&args, 0, sizeof(args));
 335         args.usH_Total = cpu_to_le16(mode->crtc_htotal);
 336         args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
 337         args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
 338         args.usH_SyncWidth =
 339                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 340         args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
 341         args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
 342         args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
 343         args.usV_SyncWidth =
 344                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 345
 346         args.ucOverscanRight = radeon_crtc->h_border;
 347         args.ucOverscanLeft = radeon_crtc->h_border;
 348         args.ucOverscanBottom = radeon_crtc->v_border;
 349         args.ucOverscanTop = radeon_crtc->v_border;
 350
 351         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 352                 misc |= ATOM_VSYNC_POLARITY;
 353         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 354                 misc |= ATOM_HSYNC_POLARITY;
 355         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 356                 misc |= ATOM_COMPOSITESYNC;
 357         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 358                 misc |= ATOM_INTERLACE;
 359         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 360                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 361
 362         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 363         args.ucCRTC = radeon_crtc->crtc_id;
 364
 365         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 366 }
 367
 368 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
 369 {
 370         u32 ss_cntl;
 371
 372         if (ASIC_IS_DCE4(rdev)) {
 373                 switch (pll_id) {
 374                 case ATOM_PPLL1:
 375                         ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
 376                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 377                         WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
 378                         break;
 379                 case ATOM_PPLL2:
 380                         ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
 381                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 382                         WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
 383                         break;
 384                 case ATOM_DCPLL:
 385                 case ATOM_PPLL_INVALID:
 386                         return;
 387                 }
 388         } else if (ASIC_IS_AVIVO(rdev)) {
 389                 switch (pll_id) {
 390                 case ATOM_PPLL1:
 391                         ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
 392                         ss_cntl &= ~1;
 393                         WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
 394                         break;
 395                 case ATOM_PPLL2:
 396                         ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
 397                         ss_cntl &= ~1;
 398                         WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
 399                         break;
 400                 case ATOM_DCPLL:
 401                 case ATOM_PPLL_INVALID:
 402                         return;
 403                 }
 404         }
 405 }
 406
 407
 408 union atom_enable_ss {
 409         ENABLE_LVDS_SS_PARAMETERS lvds_ss;
 410         ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
 411         ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
 412         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
 413         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
 414 };
 415
 416 static void atombios_crtc_program_ss(struct radeon_device *rdev,
 417                                      int enable,
 418                                      int pll_id,
 419                                      int crtc_id,
 420                                      struct radeon_atom_ss *ss)
 421 {
 422         unsigned i;
 423         int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
 424         union atom_enable_ss args;
 425
 426         if (enable) {
 427                 /* Don't mess with SS if percentage is 0 or external ss.
 428                  * SS is already disabled previously, and disabling it
 429                  * again can cause display problems if the pll is already
 430                  * programmed.
 431                  */
 432                 if (ss->percentage == 0)
 433                         return;
 434                 if (ss->type & ATOM_EXTERNAL_SS_MASK)
 435                         return;
 436         } else {
 437                 for (i = 0; i < rdev->num_crtc; i++) {
 438                         if (rdev->mode_info.crtcs[i] &&
 439                             rdev->mode_info.crtcs[i]->enabled &&
 440                             i != crtc_id &&
 441                             pll_id == rdev->mode_info.crtcs[i]->pll_id) {
 442                                 /* one other crtc is using this pll don't turn
 443                                  * off spread spectrum as it might turn off
 444                                  * display on active crtc
 445                                  */
 446                                 return;
 447                         }
 448                 }
 449         }
 450
 451         memset(&args, 0, sizeof(args));
 452
 453         if (ASIC_IS_DCE5(rdev)) {
 454                 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
 455                 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 456                 switch (pll_id) {
 457                 case ATOM_PPLL1:
 458                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
 459                         break;
 460                 case ATOM_PPLL2:
 461                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
 462                         break;
 463                 case ATOM_DCPLL:
 464                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
 465                         break;
 466                 case ATOM_PPLL_INVALID:
 467                         return;
 468                 }
 469                 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
 470                 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
 471                 args.v3.ucEnable = enable;
 472         } else if (ASIC_IS_DCE4(rdev)) {
 473                 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 474                 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 475                 switch (pll_id) {
 476                 case ATOM_PPLL1:
 477                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
 478                         break;
 479                 case ATOM_PPLL2:
 480                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
 481                         break;
 482                 case ATOM_DCPLL:
 483                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
 484                         break;
 485                 case ATOM_PPLL_INVALID:
 486                         return;
 487                 }
 488                 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
 489                 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
 490                 args.v2.ucEnable = enable;
 491         } else if (ASIC_IS_DCE3(rdev)) {
 492                 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 493                 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 494                 args.v1.ucSpreadSpectrumStep = ss->step;
 495                 args.v1.ucSpreadSpectrumDelay = ss->delay;
 496                 args.v1.ucSpreadSpectrumRange = ss->range;
 497                 args.v1.ucPpll = pll_id;
 498                 args.v1.ucEnable = enable;
 499         } else if (ASIC_IS_AVIVO(rdev)) {
 500                 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
 501                     (ss->type & ATOM_EXTERNAL_SS_MASK)) {
 502                         atombios_disable_ss(rdev, pll_id);
 503                         return;
 504                 }
 505                 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 506                 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 507                 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
 508                 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
 509                 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
 510                 args.lvds_ss_2.ucEnable = enable;
 511         } else {
 512                 if (enable == ATOM_DISABLE) {
 513                         atombios_disable_ss(rdev, pll_id);
 514                         return;
 515                 }
 516                 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 517                 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 518                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
 519                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
 520                 args.lvds_ss.ucEnable = enable;
 521         }
 522         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 523 }
 524
 525 union adjust_pixel_clock {
 526         ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
 527         ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
 528 };
 529
 530 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 531                                struct drm_display_mode *mode)
 532 {
 533         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 534         struct drm_device *dev = crtc->dev;
 535         struct radeon_device *rdev = dev->dev_private;
 536         struct drm_encoder *encoder = radeon_crtc->encoder;
 537         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 538         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 539         u32 adjusted_clock = mode->clock;
 540         int encoder_mode = atombios_get_encoder_mode(encoder);
 541         u32 dp_clock = mode->clock;
 542         int bpc = radeon_get_monitor_bpc(connector);
 543         bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
 544
 545         /* reset the pll flags */
 546         radeon_crtc->pll_flags = 0;
 547
 548         if (ASIC_IS_AVIVO(rdev)) {
 549                 if ((rdev->family == CHIP_RS600) ||
 550                     (rdev->family == CHIP_RS690) ||
 551                     (rdev->family == CHIP_RS740))
 552                         radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
 553                                 RADEON_PLL_PREFER_CLOSEST_LOWER);
 554
 555                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
 556                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 557                 else
 558                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 559
 560                 if (rdev->family < CHIP_RV770)
 561                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
 562                 /* use frac fb div on APUs */
 563                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
 564                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 565                 /* use frac fb div on RS780/RS880 */
 566                 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
 567                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 568                 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
 569                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 570         } else {
 571                 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
 572
 573                 if (mode->clock > 200000)       /* range limits??? */
 574                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 575                 else
 576                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 577         }
 578
 579         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 580             (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
 581                 if (connector) {
 582                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 583                         struct radeon_connector_atom_dig *dig_connector =
 584                                 radeon_connector->con_priv;
 585
 586                         dp_clock = dig_connector->dp_clock;
 587                 }
 588         }
 589
 590         /* use recommended ref_div for ss */
 591         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 592                 if (radeon_crtc->ss_enabled) {
 593                         if (radeon_crtc->ss.refdiv) {
 594                                 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 595                                 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
 596                                 if (ASIC_IS_AVIVO(rdev))
 597                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 598                         }
 599                 }
 600         }
 601
 602         if (ASIC_IS_AVIVO(rdev)) {
 603                 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
 604                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
 605                         adjusted_clock = mode->clock * 2;
 606                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 607                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
 608                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 609                         radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
 610         } else {
 611                 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 612                         radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 613                 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
 614                         radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 615         }
 616
 617         /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
 618          * accordingly based on the encoder/transmitter to work around
 619          * special hw requirements.
 620          */
 621         if (ASIC_IS_DCE3(rdev)) {
 622                 union adjust_pixel_clock args;
 623                 u8 frev, crev;
 624                 int index;
 625
 626                 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
 627                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 628                                            &crev))
 629                         return adjusted_clock;
 630
 631                 memset(&args, 0, sizeof(args));
 632
 633                 switch (frev) {
 634                 case 1:
 635                         switch (crev) {
 636                         case 1:
 637                         case 2:
 638                                 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
 639                                 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
 640                                 args.v1.ucEncodeMode = encoder_mode;
 641                                 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
 642                                         args.v1.ucConfig |=
 643                                                 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
 644
 645                                 atom_execute_table(rdev->mode_info.atom_context,
 646                                                    index, (uint32_t *)&args);
 647                                 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
 648                                 break;
 649                         case 3:
 650                                 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
 651                                 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
 652                                 args.v3.sInput.ucEncodeMode = encoder_mode;
 653                                 args.v3.sInput.ucDispPllConfig = 0;
 654                                 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
 655                                         args.v3.sInput.ucDispPllConfig |=
 656                                                 DISPPLL_CONFIG_SS_ENABLE;
 657                                 if (ENCODER_MODE_IS_DP(encoder_mode)) {
 658                                         args.v3.sInput.ucDispPllConfig |=
 659                                                 DISPPLL_CONFIG_COHERENT_MODE;
 660                                         /* 16200 or 27000 */
 661                                         args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
 662                                 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 663                                         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 664                                         if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
 665                                                 /* deep color support */
 666                                                 args.v3.sInput.usPixelClock =
 667                                                         cpu_to_le16((mode->clock * bpc / 8) / 10);
 668                                         if (dig->coherent_mode)
 669                                                 args.v3.sInput.ucDispPllConfig |=
 670                                                         DISPPLL_CONFIG_COHERENT_MODE;
 671                                         if (is_duallink)
 672                                                 args.v3.sInput.ucDispPllConfig |=
 673                                                         DISPPLL_CONFIG_DUAL_LINK;
 674                                 }
 675                                 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
 676                                     ENCODER_OBJECT_ID_NONE)
 677                                         args.v3.sInput.ucExtTransmitterID =
 678                                                 radeon_encoder_get_dp_bridge_encoder_id(encoder);
 679                                 else
 680                                         args.v3.sInput.ucExtTransmitterID = 0;
 681
 682                                 atom_execute_table(rdev->mode_info.atom_context,
 683                                                    index, (uint32_t *)&args);
 684                                 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
 685                                 if (args.v3.sOutput.ucRefDiv) {
 686                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 687                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 688                                         radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
 689                                 }
 690                                 if (args.v3.sOutput.ucPostDiv) {
 691                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 692                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
 693                                         radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
 694                                 }
 695                                 break;
 696                         default:
 697                                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 698                                 return adjusted_clock;
 699                         }
 700                         break;
 701                 default:
 702                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 703                         return adjusted_clock;
 704                 }
 705         }
 706         return adjusted_clock;
 707 }
 708
 709 union set_pixel_clock {
 710         SET_PIXEL_CLOCK_PS_ALLOCATION base;
 711         PIXEL_CLOCK_PARAMETERS v1;
 712         PIXEL_CLOCK_PARAMETERS_V2 v2;
 713         PIXEL_CLOCK_PARAMETERS_V3 v3;
 714         PIXEL_CLOCK_PARAMETERS_V5 v5;
 715         PIXEL_CLOCK_PARAMETERS_V6 v6;
 716 };
 717
 718 /* on DCE5, make sure the voltage is high enough to support the
 719  * required disp clk.
 720  */
 721 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
 722                                     u32 dispclk)
 723 {
 724         u8 frev, crev;
 725         int index;
 726         union set_pixel_clock args;
 727
 728         memset(&args, 0, sizeof(args));
 729
 730         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 731         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 732                                    &crev))
 733                 return;
 734
 735         switch (frev) {
 736         case 1:
 737                 switch (crev) {
 738                 case 5:
 739                         /* if the default dcpll clock is specified,
 740                          * SetPixelClock provides the dividers
 741                          */
 742                         args.v5.ucCRTC = ATOM_CRTC_INVALID;
 743                         args.v5.usPixelClock = cpu_to_le16(dispclk);
 744                         args.v5.ucPpll = ATOM_DCPLL;
 745                         break;
 746                 case 6:
 747                         /* if the default dcpll clock is specified,
 748                          * SetPixelClock provides the dividers
 749                          */
 750                         args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
 751                         if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
 752                                 args.v6.ucPpll = ATOM_EXT_PLL1;
 753                         else if (ASIC_IS_DCE6(rdev))
 754                                 args.v6.ucPpll = ATOM_PPLL0;
 755                         else
 756                                 args.v6.ucPpll = ATOM_DCPLL;
 757                         break;
 758                 default:
 759                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 760                         return;
 761                 }
 762                 break;
 763         default:
 764                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 765                 return;
 766         }
 767         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 768 }
 769
 770 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
 771                                       u32 crtc_id,
 772                                       int pll_id,
 773                                       u32 encoder_mode,
 774                                       u32 encoder_id,
 775                                       u32 clock,
 776                                       u32 ref_div,
 777                                       u32 fb_div,
 778                                       u32 frac_fb_div,
 779                                       u32 post_div,
 780                                       int bpc,
 781                                       bool ss_enabled,
 782                                       struct radeon_atom_ss *ss)
 783 {
 784         struct drm_device *dev = crtc->dev;
 785         struct radeon_device *rdev = dev->dev_private;
 786         u8 frev, crev;
 787         int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 788         union set_pixel_clock args;
 789
 790         memset(&args, 0, sizeof(args));
 791
 792         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 793                                    &crev))
 794                 return;
 795
 796         switch (frev) {
 797         case 1:
 798                 switch (crev) {
 799                 case 1:
 800                         if (clock == ATOM_DISABLE)
 801                                 return;
 802                         args.v1.usPixelClock = cpu_to_le16(clock / 10);
 803                         args.v1.usRefDiv = cpu_to_le16(ref_div);
 804                         args.v1.usFbDiv = cpu_to_le16(fb_div);
 805                         args.v1.ucFracFbDiv = frac_fb_div;
 806                         args.v1.ucPostDiv = post_div;
 807                         args.v1.ucPpll = pll_id;
 808                         args.v1.ucCRTC = crtc_id;
 809                         args.v1.ucRefDivSrc = 1;
 810                         break;
 811                 case 2:
 812                         args.v2.usPixelClock = cpu_to_le16(clock / 10);
 813                         args.v2.usRefDiv = cpu_to_le16(ref_div);
 814                         args.v2.usFbDiv = cpu_to_le16(fb_div);
 815                         args.v2.ucFracFbDiv = frac_fb_div;
 816                         args.v2.ucPostDiv = post_div;
 817                         args.v2.ucPpll = pll_id;
 818                         args.v2.ucCRTC = crtc_id;
 819                         args.v2.ucRefDivSrc = 1;
 820                         break;
 821                 case 3:
 822                         args.v3.usPixelClock = cpu_to_le16(clock / 10);
 823                         args.v3.usRefDiv = cpu_to_le16(ref_div);
 824                         args.v3.usFbDiv = cpu_to_le16(fb_div);
 825                         args.v3.ucFracFbDiv = frac_fb_div;
 826                         args.v3.ucPostDiv = post_div;
 827                         args.v3.ucPpll = pll_id;
 828                         if (crtc_id == ATOM_CRTC2)
 829                                 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
 830                         else
 831                                 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
 832                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 833                                 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
 834                         args.v3.ucTransmitterId = encoder_id;
 835                         args.v3.ucEncoderMode = encoder_mode;
 836                         break;
 837                 case 5:
 838                         args.v5.ucCRTC = crtc_id;
 839                         args.v5.usPixelClock = cpu_to_le16(clock / 10);
 840                         args.v5.ucRefDiv = ref_div;
 841                         args.v5.usFbDiv = cpu_to_le16(fb_div);
 842                         args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 843                         args.v5.ucPostDiv = post_div;
 844                         args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
 845                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 846                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
 847                         switch (bpc) {
 848                         case 8:
 849                         default:
 850                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
 851                                 break;
 852                         case 10:
 853                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
 854                                 break;
 855                         }
 856                         args.v5.ucTransmitterID = encoder_id;
 857                         args.v5.ucEncoderMode = encoder_mode;
 858                         args.v5.ucPpll = pll_id;
 859                         break;
 860                 case 6:
 861                         args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
 862                         args.v6.ucRefDiv = ref_div;
 863                         args.v6.usFbDiv = cpu_to_le16(fb_div);
 864                         args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 865                         args.v6.ucPostDiv = post_div;
 866                         args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
 867                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 868                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
 869                         switch (bpc) {
 870                         case 8:
 871                         default:
 872                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
 873                                 break;
 874                         case 10:
 875                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
 876                                 break;
 877                         case 12:
 878                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
 879                                 break;
 880                         case 16:
 881                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
 882                                 break;
 883                         }
 884                         args.v6.ucTransmitterID = encoder_id;
 885                         args.v6.ucEncoderMode = encoder_mode;
 886                         args.v6.ucPpll = pll_id;
 887                         break;
 888                 default:
 889                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 890                         return;
 891                 }
 892                 break;
 893         default:
 894                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 895                 return;
 896         }
 897
 898         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 899 }
 900
 901 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 902 {
 903         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 904         struct drm_device *dev = crtc->dev;
 905         struct radeon_device *rdev = dev->dev_private;
 906         struct radeon_encoder *radeon_encoder =
 907                 to_radeon_encoder(radeon_crtc->encoder);
 908         int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
 909
 910         radeon_crtc->bpc = 8;
 911         radeon_crtc->ss_enabled = false;
 912
 913         if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 914             (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
 915                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 916                 struct drm_connector *connector =
 917                         radeon_get_connector_for_encoder(radeon_crtc->encoder);
 918                 struct radeon_connector *radeon_connector =
 919                         to_radeon_connector(connector);
 920                 struct radeon_connector_atom_dig *dig_connector =
 921                         radeon_connector->con_priv;
 922                 int dp_clock;
 923                 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
 924
 925                 switch (encoder_mode) {
 926                 case ATOM_ENCODER_MODE_DP_MST:
 927                 case ATOM_ENCODER_MODE_DP:
 928                         /* DP/eDP */
 929                         dp_clock = dig_connector->dp_clock / 10;
 930                         if (ASIC_IS_DCE4(rdev))
 931                                 radeon_crtc->ss_enabled =
 932                                         radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
 933                                                                          ASIC_INTERNAL_SS_ON_DP,
 934                                                                          dp_clock);
 935                         else {
 936                                 if (dp_clock == 16200) {
 937                                         radeon_crtc->ss_enabled =
 938                                                 radeon_atombios_get_ppll_ss_info(rdev,
 939                                                                                  &radeon_crtc->ss,
 940                                                                                  ATOM_DP_SS_ID2);
 941                                         if (!radeon_crtc->ss_enabled)
 942                                                 radeon_crtc->ss_enabled =
 943                                                         radeon_atombios_get_ppll_ss_info(rdev,
 944                                                                                          &radeon_crtc->ss,
 945                                                                                          ATOM_DP_SS_ID1);
 946                                 } else {
 947                                         radeon_crtc->ss_enabled =
 948                                                 radeon_atombios_get_ppll_ss_info(rdev,
 949                                                                                  &radeon_crtc->ss,
 950                                                                                  ATOM_DP_SS_ID1);
 951                                 }
 952                                 /* disable spread spectrum on DCE3 DP */
 953                                 radeon_crtc->ss_enabled = false;
 954                         }
 955                         break;
 956                 case ATOM_ENCODER_MODE_LVDS:
 957                         if (ASIC_IS_DCE4(rdev))
 958                                 radeon_crtc->ss_enabled =
 959                                         radeon_atombios_get_asic_ss_info(rdev,
 960                                                                          &radeon_crtc->ss,
 961                                                                          dig->lcd_ss_id,
 962                                                                          mode->clock / 10);
 963                         else
 964                                 radeon_crtc->ss_enabled =
 965                                         radeon_atombios_get_ppll_ss_info(rdev,
 966                                                                          &radeon_crtc->ss,
 967                                                                          dig->lcd_ss_id);
 968                         break;
 969                 case ATOM_ENCODER_MODE_DVI:
 970                         if (ASIC_IS_DCE4(rdev))
 971                                 radeon_crtc->ss_enabled =
 972                                         radeon_atombios_get_asic_ss_info(rdev,
 973                                                                          &radeon_crtc->ss,
 974                                                                          ASIC_INTERNAL_SS_ON_TMDS,
 975                                                                          mode->clock / 10);
 976                         break;
 977                 case ATOM_ENCODER_MODE_HDMI:
 978                         if (ASIC_IS_DCE4(rdev))
 979                                 radeon_crtc->ss_enabled =
 980                                         radeon_atombios_get_asic_ss_info(rdev,
 981                                                                          &radeon_crtc->ss,
 982                                                                          ASIC_INTERNAL_SS_ON_HDMI,
 983                                                                          mode->clock / 10);
 984                         break;
 985                 default:
 986                         break;
 987                 }
 988         }
 989
 990         /* adjust pixel clock as needed */
 991         radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
 992
 993         return true;
 994 }
 995
 996 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 997 {
 998         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 999         struct drm_device *dev = crtc->dev;
1000         struct radeon_device *rdev = dev->dev_private;
1001         struct radeon_encoder *radeon_encoder =
1002                 to_radeon_encoder(radeon_crtc->encoder);
1003         u32 pll_clock = mode->clock;
1004         u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
1005         struct radeon_pll *pll;
1006         int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1007
1008         switch (radeon_crtc->pll_id) {
1009         case ATOM_PPLL1:
1010                 pll = &rdev->clock.p1pll;
1011                 break;
1012         case ATOM_PPLL2:
1013                 pll = &rdev->clock.p2pll;
1014                 break;
1015         case ATOM_DCPLL:
1016         case ATOM_PPLL_INVALID:
1017         default:
1018                 pll = &rdev->clock.dcpll;
1019                 break;
1020         }
1021
1022         /* update pll params */
1023         pll->flags = radeon_crtc->pll_flags;
1024         pll->reference_div = radeon_crtc->pll_reference_div;
1025         pll->post_div = radeon_crtc->pll_post_div;
1026
1027         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1028                 /* TV seems to prefer the legacy algo on some boards */
1029                 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1030                                           &fb_div, &frac_fb_div, &ref_div, &post_div);
1031         else if (ASIC_IS_AVIVO(rdev))
1032                 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1033                                          &fb_div, &frac_fb_div, &ref_div, &post_div);
1034         else
1035                 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1036                                           &fb_div, &frac_fb_div, &ref_div, &post_div);
1037
1038         atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1039                                  radeon_crtc->crtc_id, &radeon_crtc->ss);
1040
1041         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1042                                   encoder_mode, radeon_encoder->encoder_id, mode->clock,
1043                                   ref_div, fb_div, frac_fb_div, post_div,
1044                                   radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1045
1046         if (radeon_crtc->ss_enabled) {
1047                 /* calculate ss amount and step size */
1048                 if (ASIC_IS_DCE4(rdev)) {
1049                         u32 step_size;
1050                         u32 amount = (((fb_div * 10) + frac_fb_div) *
1051                                       (u32)radeon_crtc->ss.percentage) /
1052                                 (100 * (u32)radeon_crtc->ss.percentage_divider);
1053                         radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1054                         radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1055                                 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1056                         if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1057                                 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1058                                         (125 * 25 * pll->reference_freq / 100);
1059                         else
1060                                 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1061                                         (125 * 25 * pll->reference_freq / 100);
1062                         radeon_crtc->ss.step = step_size;
1063                 }
1064
1065                 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1066                                          radeon_crtc->crtc_id, &radeon_crtc->ss);
1067         }
1068 }
1069
1070 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1071                                  struct drm_framebuffer *fb,
1072                                  int x, int y, int atomic)
1073 {
1074         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1075         struct drm_device *dev = crtc->dev;
1076         struct radeon_device *rdev = dev->dev_private;
1077         struct radeon_framebuffer *radeon_fb;
1078         struct drm_framebuffer *target_fb;
1079         struct drm_gem_object *obj;
1080         struct radeon_bo *rbo;
1081         uint64_t fb_location;
1082         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1083         unsigned bankw, bankh, mtaspect, tile_split;
1084         u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1085         u32 tmp, viewport_w, viewport_h;
1086         int r;
1087
1088         /* no fb bound */
1089         if (!atomic && !crtc->fb) {
1090                 DRM_DEBUG_KMS("No FB bound\n");
1091                 return 0;
1092         }
1093
1094         if (atomic) {
1095                 radeon_fb = to_radeon_framebuffer(fb);
1096                 target_fb = fb;
1097         }
1098         else {
1099                 radeon_fb = to_radeon_framebuffer(crtc->fb);
1100                 target_fb = crtc->fb;
1101         }
1102
1103         /* If atomic, assume fb object is pinned & idle & fenced and
1104          * just update base pointers
1105          */
1106         obj = radeon_fb->obj;
1107         rbo = gem_to_radeon_bo(obj);
1108         r = radeon_bo_reserve(rbo, false);
1109         if (unlikely(r != 0))
1110                 return r;
1111
1112         if (atomic)
1113                 fb_location = radeon_bo_gpu_offset(rbo);
1114         else {
1115                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1116                 if (unlikely(r != 0)) {
1117                         radeon_bo_unreserve(rbo);
1118                         return -EINVAL;
1119                 }
1120         }
1121
1122         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1123         radeon_bo_unreserve(rbo);
1124
1125         switch (target_fb->bits_per_pixel) {
1126         case 8:
1127                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1128                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1129                 break;
1130         case 15:
1131                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1132                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1133                 break;
1134         case 16:
1135                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1136                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1137 #ifdef __BIG_ENDIAN
1138                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1139 #endif
1140                 break;
1141         case 24:
1142         case 32:
1143                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1144                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1145 #ifdef __BIG_ENDIAN
1146                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1147 #endif
1148                 break;
1149         default:
1150                 DRM_ERROR("Unsupported screen depth %d\n",
1151                           target_fb->bits_per_pixel);
1152                 return -EINVAL;
1153         }
1154
1155         if (tiling_flags & RADEON_TILING_MACRO) {
1156                 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1157
1158                 /* Set NUM_BANKS. */
1159                 if (rdev->family >= CHIP_BONAIRE) {
1160                         unsigned tileb, index, num_banks, tile_split_bytes;
1161
1162                         /* Calculate the macrotile mode index. */
1163                         tile_split_bytes = 64 << tile_split;
1164                         tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
1165                         tileb = min(tile_split_bytes, tileb);
1166
1167                         for (index = 0; tileb > 64; index++) {
1168                                 tileb >>= 1;
1169                         }
1170
1171                         if (index >= 16) {
1172                                 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1173                                           target_fb->bits_per_pixel, tile_split);
1174                                 return -EINVAL;
1175                         }
1176
1177                         num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1178                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1179                 } else {
1180                         /* SI and older. */
1181                         if (rdev->family >= CHIP_TAHITI)
1182                                 tmp = rdev->config.si.tile_config;
1183                         else if (rdev->family >= CHIP_CAYMAN)
1184                                 tmp = rdev->config.cayman.tile_config;
1185                         else
1186                                 tmp = rdev->config.evergreen.tile_config;
1187
1188                         switch ((tmp & 0xf0) >> 4) {
1189                         case 0: /* 4 banks */
1190                                 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1191                                 break;
1192                         case 1: /* 8 banks */
1193                         default:
1194                                 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1195                                 break;
1196                         case 2: /* 16 banks */
1197                                 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1198                                 break;
1199                         }
1200                 }
1201
1202                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1203                 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1204                 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1205                 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1206                 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1207                 if (rdev->family >= CHIP_BONAIRE) {
1208                         /* XXX need to know more about the surface tiling mode */
1209                         fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
1210                 }
1211         } else if (tiling_flags & RADEON_TILING_MICRO)
1212                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1213
1214         if (rdev->family >= CHIP_BONAIRE) {
1215                 /* Read the pipe config from the 2D TILED SCANOUT mode.
1216                  * It should be the same for the other modes too, but not all
1217                  * modes set the pipe config field. */
1218                 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
1219
1220                 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
1221         } else if ((rdev->family == CHIP_TAHITI) ||
1222                    (rdev->family == CHIP_PITCAIRN))
1223                 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1224         else if ((rdev->family == CHIP_VERDE) ||
1225                  (rdev->family == CHIP_OLAND) ||
1226                  (rdev->family == CHIP_HAINAN)) /* for completeness.  HAINAN has no display hw */
1227                 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1228
1229         switch (radeon_crtc->crtc_id) {
1230         case 0:
1231                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1232                 break;
1233         case 1:
1234                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1235                 break;
1236         case 2:
1237                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1238                 break;
1239         case 3:
1240                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1241                 break;
1242         case 4:
1243                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1244                 break;
1245         case 5:
1246                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1247                 break;
1248         default:
1249                 break;
1250         }
1251
1252         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1253                upper_32_bits(fb_location));
1254         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1255                upper_32_bits(fb_location));
1256         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1257                (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1258         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1259                (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1260         WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1261         WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1262
1263         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1264         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1265         WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1266         WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1267         WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1268         WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1269
1270         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1271         WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1272         WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1273
1274         if (rdev->family >= CHIP_BONAIRE)
1275                 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1276                        target_fb->height);
1277         else
1278                 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1279                        target_fb->height);
1280         x &= ~3;
1281         y &= ~1;
1282         WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1283                (x << 16) | y);
1284         viewport_w = crtc->mode.hdisplay;
1285         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1286         WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1287                (viewport_w << 16) | viewport_h);
1288
1289         /* pageflip setup */
1290         /* make sure flip is at vb rather than hb */
1291         tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1292         tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1293         WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1294
1295         /* set pageflip to happen anywhere in vblank interval */
1296         WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1297
1298         if (!atomic && fb && fb != crtc->fb) {
1299                 radeon_fb = to_radeon_framebuffer(fb);
1300                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1301                 r = radeon_bo_reserve(rbo, false);
1302                 if (unlikely(r != 0))
1303                         return r;
1304                 radeon_bo_unpin(rbo);
1305                 radeon_bo_unreserve(rbo);
1306         }
1307
1308         /* Bytes per pixel may have changed */
1309         radeon_bandwidth_update(rdev);
1310
1311         return 0;
1312 }
1313
1314 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1315                                   struct drm_framebuffer *fb,
1316                                   int x, int y, int atomic)
1317 {
1318         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1319         struct drm_device *dev = crtc->dev;
1320         struct radeon_device *rdev = dev->dev_private;
1321         struct radeon_framebuffer *radeon_fb;
1322         struct drm_gem_object *obj;
1323         struct radeon_bo *rbo;
1324         struct drm_framebuffer *target_fb;
1325         uint64_t fb_location;
1326         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1327         u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1328         u32 tmp, viewport_w, viewport_h;
1329         int r;
1330
1331         /* no fb bound */
1332         if (!atomic && !crtc->fb) {
1333                 DRM_DEBUG_KMS("No FB bound\n");
1334                 return 0;
1335         }
1336
1337         if (atomic) {
1338                 radeon_fb = to_radeon_framebuffer(fb);
1339                 target_fb = fb;
1340         }
1341         else {
1342                 radeon_fb = to_radeon_framebuffer(crtc->fb);
1343                 target_fb = crtc->fb;
1344         }
1345
1346         obj = radeon_fb->obj;
1347         rbo = gem_to_radeon_bo(obj);
1348         r = radeon_bo_reserve(rbo, false);
1349         if (unlikely(r != 0))
1350                 return r;
1351
1352         /* If atomic, assume fb object is pinned & idle & fenced and
1353          * just update base pointers
1354          */
1355         if (atomic)
1356                 fb_location = radeon_bo_gpu_offset(rbo);
1357         else {
1358                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1359                 if (unlikely(r != 0)) {
1360                         radeon_bo_unreserve(rbo);
1361                         return -EINVAL;
1362                 }
1363         }
1364         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1365         radeon_bo_unreserve(rbo);
1366
1367         switch (target_fb->bits_per_pixel) {
1368         case 8:
1369                 fb_format =
1370                     AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1371                     AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1372                 break;
1373         case 15:
1374                 fb_format =
1375                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1376                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1377                 break;
1378         case 16:
1379                 fb_format =
1380                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1381                     AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1382 #ifdef __BIG_ENDIAN
1383                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1384 #endif
1385                 break;
1386         case 24:
1387         case 32:
1388                 fb_format =
1389                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1390                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1391 #ifdef __BIG_ENDIAN
1392                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1393 #endif
1394                 break;
1395         default:
1396                 DRM_ERROR("Unsupported screen depth %d\n",
1397                           target_fb->bits_per_pixel);
1398                 return -EINVAL;
1399         }
1400
1401         if (rdev->family >= CHIP_R600) {
1402                 if (tiling_flags & RADEON_TILING_MACRO)
1403                         fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1404                 else if (tiling_flags & RADEON_TILING_MICRO)
1405                         fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1406         } else {
1407                 if (tiling_flags & RADEON_TILING_MACRO)
1408                         fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1409
1410                 if (tiling_flags & RADEON_TILING_MICRO)
1411                         fb_format |= AVIVO_D1GRPH_TILED;
1412         }
1413
1414         if (radeon_crtc->crtc_id == 0)
1415                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1416         else
1417                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1418
1419         if (rdev->family >= CHIP_RV770) {
1420                 if (radeon_crtc->crtc_id) {
1421                         WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1422                         WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1423                 } else {
1424                         WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1425                         WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1426                 }
1427         }
1428         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1429                (u32) fb_location);
1430         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1431                radeon_crtc->crtc_offset, (u32) fb_location);
1432         WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1433         if (rdev->family >= CHIP_R600)
1434                 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1435
1436         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1437         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1438         WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1439         WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1440         WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1441         WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1442
1443         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1444         WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1445         WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1446
1447         WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1448                target_fb->height);
1449         x &= ~3;
1450         y &= ~1;
1451         WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1452                (x << 16) | y);
1453         viewport_w = crtc->mode.hdisplay;
1454         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1455         WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1456                (viewport_w << 16) | viewport_h);
1457
1458         /* pageflip setup */
1459         /* make sure flip is at vb rather than hb */
1460         tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1461         tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1462         WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1463
1464         /* set pageflip to happen anywhere in vblank interval */
1465         WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1466
1467         if (!atomic && fb && fb != crtc->fb) {
1468                 radeon_fb = to_radeon_framebuffer(fb);
1469                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1470                 r = radeon_bo_reserve(rbo, false);
1471                 if (unlikely(r != 0))
1472                         return r;
1473                 radeon_bo_unpin(rbo);
1474                 radeon_bo_unreserve(rbo);
1475         }
1476
1477         /* Bytes per pixel may have changed */
1478         radeon_bandwidth_update(rdev);
1479
1480         return 0;
1481 }
1482
1483 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1484                            struct drm_framebuffer *old_fb)
1485 {
1486         struct drm_device *dev = crtc->dev;
1487         struct radeon_device *rdev = dev->dev_private;
1488
1489         if (ASIC_IS_DCE4(rdev))
1490                 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1491         else if (ASIC_IS_AVIVO(rdev))
1492                 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1493         else
1494                 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1495 }
1496
1497 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1498                                   struct drm_framebuffer *fb,
1499                                   int x, int y, enum mode_set_atomic state)
1500 {
1501        struct drm_device *dev = crtc->dev;
1502        struct radeon_device *rdev = dev->dev_private;
1503
1504         if (ASIC_IS_DCE4(rdev))
1505                 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1506         else if (ASIC_IS_AVIVO(rdev))
1507                 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1508         else
1509                 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1510 }
1511
1512 /* properly set additional regs when using atombios */
1513 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1514 {
1515         struct drm_device *dev = crtc->dev;
1516         struct radeon_device *rdev = dev->dev_private;
1517         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1518         u32 disp_merge_cntl;
1519
1520         switch (radeon_crtc->crtc_id) {
1521         case 0:
1522                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1523                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1524                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1525                 break;
1526         case 1:
1527                 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1528                 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1529                 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1530                 WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1531                 WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1532                 break;
1533         }
1534 }
1535
1536 /**
1537  * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1538  *
1539  * @crtc: drm crtc
1540  *
1541  * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1542  */
1543 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1544 {
1545         struct drm_device *dev = crtc->dev;
1546         struct drm_crtc *test_crtc;
1547         struct radeon_crtc *test_radeon_crtc;
1548         u32 pll_in_use = 0;
1549
1550         list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1551                 if (crtc == test_crtc)
1552                         continue;
1553
1554                 test_radeon_crtc = to_radeon_crtc(test_crtc);
1555                 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1556                         pll_in_use |= (1 << test_radeon_crtc->pll_id);
1557         }
1558         return pll_in_use;
1559 }
1560
1561 /**
1562  * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1563  *
1564  * @crtc: drm crtc
1565  *
1566  * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1567  * also in DP mode.  For DP, a single PPLL can be used for all DP
1568  * crtcs/encoders.
1569  */
1570 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1571 {
1572         struct drm_device *dev = crtc->dev;
1573         struct drm_crtc *test_crtc;
1574         struct radeon_crtc *test_radeon_crtc;
1575
1576         list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1577                 if (crtc == test_crtc)
1578                         continue;
1579                 test_radeon_crtc = to_radeon_crtc(test_crtc);
1580                 if (test_radeon_crtc->encoder &&
1581                     ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1582                         /* for DP use the same PLL for all */
1583                         if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1584                                 return test_radeon_crtc->pll_id;
1585                 }
1586         }
1587         return ATOM_PPLL_INVALID;
1588 }
1589
1590 /**
1591  * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1592  *
1593  * @crtc: drm crtc
1594  * @encoder: drm encoder
1595  *
1596  * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1597  * be shared (i.e., same clock).
1598  */
1599 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1600 {
1601         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1602         struct drm_device *dev = crtc->dev;
1603         struct drm_crtc *test_crtc;
1604         struct radeon_crtc *test_radeon_crtc;
1605         u32 adjusted_clock, test_adjusted_clock;
1606
1607         adjusted_clock = radeon_crtc->adjusted_clock;
1608
1609         if (adjusted_clock == 0)
1610                 return ATOM_PPLL_INVALID;
1611
1612         list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1613                 if (crtc == test_crtc)
1614                         continue;
1615                 test_radeon_crtc = to_radeon_crtc(test_crtc);
1616                 if (test_radeon_crtc->encoder &&
1617                     !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1618                         /* check if we are already driving this connector with another crtc */
1619                         if (test_radeon_crtc->connector == radeon_crtc->connector) {
1620                                 /* if we are, return that pll */
1621                                 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1622                                         return test_radeon_crtc->pll_id;
1623                         }
1624                         /* for non-DP check the clock */
1625                         test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1626                         if ((crtc->mode.clock == test_crtc->mode.clock) &&
1627                             (adjusted_clock == test_adjusted_clock) &&
1628                             (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1629                             (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1630                                 return test_radeon_crtc->pll_id;
1631                 }
1632         }
1633         return ATOM_PPLL_INVALID;
1634 }
1635
1636 /**
1637  * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1638  *
1639  * @crtc: drm crtc
1640  *
1641  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
1642  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
1643  * monitors a dedicated PPLL must be used.  If a particular board has
1644  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1645  * as there is no need to program the PLL itself.  If we are not able to
1646  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1647  * avoid messing up an existing monitor.
1648  *
1649  * Asic specific PLL information
1650  *
1651  * DCE 8.x
1652  * KB/KV
1653  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1654  * CI
1655  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1656  *
1657  * DCE 6.1
1658  * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1659  * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1660  *
1661  * DCE 6.0
1662  * - PPLL0 is available to all UNIPHY (DP only)
1663  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1664  *
1665  * DCE 5.0
1666  * - DCPLL is available to all UNIPHY (DP only)
1667  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1668  *
1669  * DCE 3.0/4.0/4.1
1670  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1671  *
1672  */
1673 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1674 {
1675         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1676         struct drm_device *dev = crtc->dev;
1677         struct radeon_device *rdev = dev->dev_private;
1678         struct radeon_encoder *radeon_encoder =
1679                 to_radeon_encoder(radeon_crtc->encoder);
1680         u32 pll_in_use;
1681         int pll;
1682
1683         if (ASIC_IS_DCE8(rdev)) {
1684                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1685                         if (rdev->clock.dp_extclk)
1686                                 /* skip PPLL programming if using ext clock */
1687                                 return ATOM_PPLL_INVALID;
1688                         else {
1689                                 /* use the same PPLL for all DP monitors */
1690                                 pll = radeon_get_shared_dp_ppll(crtc);
1691                                 if (pll != ATOM_PPLL_INVALID)
1692                                         return pll;
1693                         }
1694                 } else {
1695                         /* use the same PPLL for all monitors with the same clock */
1696                         pll = radeon_get_shared_nondp_ppll(crtc);
1697                         if (pll != ATOM_PPLL_INVALID)
1698                                 return pll;
1699                 }
1700                 /* otherwise, pick one of the plls */
1701                 if ((rdev->family == CHIP_KAVERI) ||
1702                     (rdev->family == CHIP_KABINI)) {
1703                         /* KB/KV has PPLL1 and PPLL2 */
1704                         pll_in_use = radeon_get_pll_use_mask(crtc);
1705                         if (!(pll_in_use & (1 << ATOM_PPLL2)))
1706                                 return ATOM_PPLL2;
1707                         if (!(pll_in_use & (1 << ATOM_PPLL1)))
1708                                 return ATOM_PPLL1;
1709                         DRM_ERROR("unable to allocate a PPLL\n");
1710                         return ATOM_PPLL_INVALID;
1711                 } else {
1712                         /* CI has PPLL0, PPLL1, and PPLL2 */
1713                         pll_in_use = radeon_get_pll_use_mask(crtc);
1714                         if (!(pll_in_use & (1 << ATOM_PPLL2)))
1715                                 return ATOM_PPLL2;
1716                         if (!(pll_in_use & (1 << ATOM_PPLL1)))
1717                                 return ATOM_PPLL1;
1718                         if (!(pll_in_use & (1 << ATOM_PPLL0)))
1719                                 return ATOM_PPLL0;
1720                         DRM_ERROR("unable to allocate a PPLL\n");
1721                         return ATOM_PPLL_INVALID;
1722                 }
1723         } else if (ASIC_IS_DCE61(rdev)) {
1724                 struct radeon_encoder_atom_dig *dig =
1725                         radeon_encoder->enc_priv;
1726
1727                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1728                     (dig->linkb == false))
1729                         /* UNIPHY A uses PPLL2 */
1730                         return ATOM_PPLL2;
1731                 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1732                         /* UNIPHY B/C/D/E/F */
1733                         if (rdev->clock.dp_extclk)
1734                                 /* skip PPLL programming if using ext clock */
1735                                 return ATOM_PPLL_INVALID;
1736                         else {
1737                                 /* use the same PPLL for all DP monitors */
1738                                 pll = radeon_get_shared_dp_ppll(crtc);
1739                                 if (pll != ATOM_PPLL_INVALID)
1740                                         return pll;
1741                         }
1742                 } else {
1743                         /* use the same PPLL for all monitors with the same clock */
1744                         pll = radeon_get_shared_nondp_ppll(crtc);
1745                         if (pll != ATOM_PPLL_INVALID)
1746                                 return pll;
1747                 }
1748                 /* UNIPHY B/C/D/E/F */
1749                 pll_in_use = radeon_get_pll_use_mask(crtc);
1750                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1751                         return ATOM_PPLL0;
1752                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1753                         return ATOM_PPLL1;
1754                 DRM_ERROR("unable to allocate a PPLL\n");
1755                 return ATOM_PPLL_INVALID;
1756         } else if (ASIC_IS_DCE4(rdev)) {
1757                 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1758                  * depending on the asic:
1759                  * DCE4: PPLL or ext clock
1760                  * DCE5: PPLL, DCPLL, or ext clock
1761                  * DCE6: PPLL, PPLL0, or ext clock
1762                  *
1763                  * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1764                  * PPLL/DCPLL programming and only program the DP DTO for the
1765                  * crtc virtual pixel clock.
1766                  */
1767                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1768                         if (rdev->clock.dp_extclk)
1769                                 /* skip PPLL programming if using ext clock */
1770                                 return ATOM_PPLL_INVALID;
1771                         else if (ASIC_IS_DCE6(rdev))
1772                                 /* use PPLL0 for all DP */
1773                                 return ATOM_PPLL0;
1774                         else if (ASIC_IS_DCE5(rdev))
1775                                 /* use DCPLL for all DP */
1776                                 return ATOM_DCPLL;
1777                         else {
1778                                 /* use the same PPLL for all DP monitors */
1779                                 pll = radeon_get_shared_dp_ppll(crtc);
1780                                 if (pll != ATOM_PPLL_INVALID)
1781                                         return pll;
1782                         }
1783                 } else if (!ASIC_IS_DCE41(rdev)) { /* Don't share PLLs on DCE4.1 chips */
1784                         /* use the same PPLL for all monitors with the same clock */
1785                         pll = radeon_get_shared_nondp_ppll(crtc);
1786                         if (pll != ATOM_PPLL_INVALID)
1787                                 return pll;
1788                 }
1789                 /* all other cases */
1790                 pll_in_use = radeon_get_pll_use_mask(crtc);
1791                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1792                         return ATOM_PPLL1;
1793                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1794                         return ATOM_PPLL2;
1795                 DRM_ERROR("unable to allocate a PPLL\n");
1796                 return ATOM_PPLL_INVALID;
1797         } else {
1798                 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1799                 /* some atombios (observed in some DCE2/DCE3) code have a bug,
1800                  * the matching btw pll and crtc is done through
1801                  * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
1802                  * pll (1 or 2) to select which register to write. ie if using
1803                  * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
1804                  * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
1805                  * choose which value to write. Which is reverse order from
1806                  * register logic. So only case that works is when pllid is
1807                  * same as crtcid or when both pll and crtc are enabled and
1808                  * both use same clock.
1809                  *
1810                  * So just return crtc id as if crtc and pll were hard linked
1811                  * together even if they aren't
1812                  */
1813                 return radeon_crtc->crtc_id;
1814         }
1815 }
1816
1817 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
1818 {
1819         /* always set DCPLL */
1820         if (ASIC_IS_DCE6(rdev))
1821                 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1822         else if (ASIC_IS_DCE4(rdev)) {
1823                 struct radeon_atom_ss ss;
1824                 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1825                                                                    ASIC_INTERNAL_SS_ON_DCPLL,
1826                                                                    rdev->clock.default_dispclk);
1827                 if (ss_enabled)
1828                         atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
1829                 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1830                 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1831                 if (ss_enabled)
1832                         atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
1833         }
1834
1835 }
1836
1837 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1838                            struct drm_display_mode *mode,
1839                            struct drm_display_mode *adjusted_mode,
1840                            int x, int y, struct drm_framebuffer *old_fb)
1841 {
1842         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1843         struct drm_device *dev = crtc->dev;
1844         struct radeon_device *rdev = dev->dev_private;
1845         struct radeon_encoder *radeon_encoder =
1846                 to_radeon_encoder(radeon_crtc->encoder);
1847         bool is_tvcv = false;
1848
1849         if (radeon_encoder->active_device &
1850             (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1851                 is_tvcv = true;
1852
1853         atombios_crtc_set_pll(crtc, adjusted_mode);
1854
1855         if (ASIC_IS_DCE4(rdev))
1856                 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1857         else if (ASIC_IS_AVIVO(rdev)) {
1858                 if (is_tvcv)
1859                         atombios_crtc_set_timing(crtc, adjusted_mode);
1860                 else
1861                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1862         } else {
1863                 atombios_crtc_set_timing(crtc, adjusted_mode);
1864                 if (radeon_crtc->crtc_id == 0)
1865                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1866                 radeon_legacy_atom_fixup(crtc);
1867         }
1868         atombios_crtc_set_base(crtc, x, y, old_fb);
1869         atombios_overscan_setup(crtc, mode, adjusted_mode);
1870         atombios_scaler_setup(crtc);
1871         /* update the hw version fpr dpm */
1872         radeon_crtc->hw_mode = *adjusted_mode;
1873
1874         return 0;
1875 }
1876
1877 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1878                                      const struct drm_display_mode *mode,
1879                                      struct drm_display_mode *adjusted_mode)
1880 {
1881         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1882         struct drm_device *dev = crtc->dev;
1883         struct drm_encoder *encoder;
1884
1885         /* assign the encoder to the radeon crtc to avoid repeated lookups later */
1886         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1887                 if (encoder->crtc == crtc) {
1888                         radeon_crtc->encoder = encoder;
1889                         radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
1890                         break;
1891                 }
1892         }
1893         if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
1894                 radeon_crtc->encoder = NULL;
1895                 radeon_crtc->connector = NULL;
1896                 return false;
1897         }
1898         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1899                 return false;
1900         if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
1901                 return false;
1902         /* pick pll */
1903         radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1904         /* if we can't get a PPLL for a non-DP encoder, fail */
1905         if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
1906             !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
1907                 return false;
1908
1909         return true;
1910 }
1911
1912 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1913 {
1914         struct drm_device *dev = crtc->dev;
1915         struct radeon_device *rdev = dev->dev_private;
1916
1917         /* disable crtc pair power gating before programming */
1918         if (ASIC_IS_DCE6(rdev))
1919                 atombios_powergate_crtc(crtc, ATOM_DISABLE);
1920
1921         atombios_lock_crtc(crtc, ATOM_ENABLE);
1922         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1923 }
1924
1925 static void atombios_crtc_commit(struct drm_crtc *crtc)
1926 {
1927         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1928         atombios_lock_crtc(crtc, ATOM_DISABLE);
1929 }
1930
1931 static void atombios_crtc_disable(struct drm_crtc *crtc)
1932 {
1933         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1934         struct drm_device *dev = crtc->dev;
1935         struct radeon_device *rdev = dev->dev_private;
1936         struct radeon_atom_ss ss;
1937         int i;
1938
1939         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1940         if (crtc->fb) {
1941                 int r;
1942                 struct radeon_framebuffer *radeon_fb;
1943                 struct radeon_bo *rbo;
1944
1945                 radeon_fb = to_radeon_framebuffer(crtc->fb);
1946                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1947                 r = radeon_bo_reserve(rbo, false);
1948                 if (unlikely(r))
1949                         DRM_ERROR("failed to reserve rbo before unpin\n");
1950                 else {
1951                         radeon_bo_unpin(rbo);
1952                         radeon_bo_unreserve(rbo);
1953                 }
1954         }
1955         /* disable the GRPH */
1956         if (ASIC_IS_DCE4(rdev))
1957                 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
1958         else if (ASIC_IS_AVIVO(rdev))
1959                 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
1960
1961         if (ASIC_IS_DCE6(rdev))
1962                 atombios_powergate_crtc(crtc, ATOM_ENABLE);
1963
1964         for (i = 0; i < rdev->num_crtc; i++) {
1965                 if (rdev->mode_info.crtcs[i] &&
1966                     rdev->mode_info.crtcs[i]->enabled &&
1967                     i != radeon_crtc->crtc_id &&
1968                     radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
1969                         /* one other crtc is using this pll don't turn
1970                          * off the pll
1971                          */
1972                         goto done;
1973                 }
1974         }
1975
1976         switch (radeon_crtc->pll_id) {
1977         case ATOM_PPLL1:
1978         case ATOM_PPLL2:
1979                 /* disable the ppll */
1980                 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1981                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1982                 break;
1983         case ATOM_PPLL0:
1984                 /* disable the ppll */
1985                 if ((rdev->family == CHIP_ARUBA) ||
1986                     (rdev->family == CHIP_BONAIRE) ||
1987                     (rdev->family == CHIP_HAWAII))
1988                         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1989                                                   0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1990                 break;
1991         default:
1992                 break;
1993         }
1994 done:
1995         radeon_crtc->pll_id = ATOM_PPLL_INVALID;
1996         radeon_crtc->adjusted_clock = 0;
1997         radeon_crtc->encoder = NULL;
1998         radeon_crtc->connector = NULL;
1999 }
2000
2001 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
2002         .dpms = atombios_crtc_dpms,
2003         .mode_fixup = atombios_crtc_mode_fixup,
2004         .mode_set = atombios_crtc_mode_set,
2005         .mode_set_base = atombios_crtc_set_base,
2006         .mode_set_base_atomic = atombios_crtc_set_base_atomic,
2007         .prepare = atombios_crtc_prepare,
2008         .commit = atombios_crtc_commit,
2009         .load_lut = radeon_crtc_load_lut,
2010         .disable = atombios_crtc_disable,
2011 };
2012
2013 void radeon_atombios_init_crtc(struct drm_device *dev,
2014                                struct radeon_crtc *radeon_crtc)
2015 {
2016         struct radeon_device *rdev = dev->dev_private;
2017
2018         if (ASIC_IS_DCE4(rdev)) {
2019                 switch (radeon_crtc->crtc_id) {
2020                 case 0:
2021                 default:
2022                         radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
2023                         break;
2024                 case 1:
2025                         radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
2026                         break;
2027                 case 2:
2028                         radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
2029                         break;
2030                 case 3:
2031                         radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
2032                         break;
2033                 case 4:
2034                         radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
2035                         break;
2036                 case 5:
2037                         radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
2038                         break;
2039                 }
2040         } else {
2041                 if (radeon_crtc->crtc_id == 1)
2042                         radeon_crtc->crtc_offset =
2043                                 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
2044                 else
2045                         radeon_crtc->crtc_offset = 0;
2046         }
2047         radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2048         radeon_crtc->adjusted_clock = 0;
2049         radeon_crtc->encoder = NULL;
2050         radeon_crtc->connector = NULL;
2051         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
2052 }