drivers/gpu/drm/radeon/atombios_dp.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  *          Jerome Glisse
  26  */
  27 #include <drm/drmP.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33 #include <drm/drm_dp_helper.h>
  34
  35 /* move these to drm_dp_helper.c/h */
  36 #define DP_LINK_CONFIGURATION_SIZE 9
  37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
  38
  39 static char *voltage_names[] = {
  40         "0.4V", "0.6V", "0.8V", "1.2V"
  41 };
  42 static char *pre_emph_names[] = {
  43         "0dB", "3.5dB", "6dB", "9.5dB"
  44 };
  45
  46 /***** radeon AUX functions *****/
  47
  48 /* Atom needs data in little endian format
  49  * so swap as appropriate when copying data to
  50  * or from atom. Note that atom operates on
  51  * dw units.
  52  */
  53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
  54 {
  55 #ifdef __BIG_ENDIAN
  56         u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
  57         u32 *dst32, *src32;
  58         int i;
  59
  60         memcpy(src_tmp, src, num_bytes);
  61         src32 = (u32 *)src_tmp;
  62         dst32 = (u32 *)dst_tmp;
  63         if (to_le) {
  64                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
  65                         dst32[i] = cpu_to_le32(src32[i]);
  66                 memcpy(dst, dst_tmp, num_bytes);
  67         } else {
  68                 u8 dws = num_bytes & ~3;
  69                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
  70                         dst32[i] = le32_to_cpu(src32[i]);
  71                 memcpy(dst, dst_tmp, dws);
  72                 if (num_bytes % 4) {
  73                         for (i = 0; i < (num_bytes % 4); i++)
  74                                 dst[dws+i] = dst_tmp[dws+i];
  75                 }
  76         }
  77 #else
  78         memcpy(dst, src, num_bytes);
  79 #endif
  80 }
  81
  82 union aux_channel_transaction {
  83         PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
  84         PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
  85 };
  86
  87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
  88                                  u8 *send, int send_bytes,
  89                                  u8 *recv, int recv_size,
  90                                  u8 delay, u8 *ack)
  91 {
  92         struct drm_device *dev = chan->dev;
  93         struct radeon_device *rdev = dev->dev_private;
  94         union aux_channel_transaction args;
  95         int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
  96         unsigned char *base;
  97         int recv_bytes;
  98         int r = 0;
  99
 100         memset(&args, 0, sizeof(args));
 101
 102         mutex_lock(&chan->mutex);
 103         mutex_lock(&rdev->mode_info.atom_context->scratch_mutex);
 104
 105         base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
 106
 107         radeon_atom_copy_swap(base, send, send_bytes, true);
 108
 109         args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
 110         args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
 111         args.v1.ucDataOutLen = 0;
 112         args.v1.ucChannelID = chan->rec.i2c_id;
 113         args.v1.ucDelay = delay / 10;
 114         if (ASIC_IS_DCE4(rdev))
 115                 args.v2.ucHPD_ID = chan->rec.hpd;
 116
 117         atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 118
 119         *ack = args.v1.ucReplyStatus;
 120
 121         /* timeout */
 122         if (args.v1.ucReplyStatus == 1) {
 123                 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
 124                 r = -ETIMEDOUT;
 125                 goto done;
 126         }
 127
 128         /* flags not zero */
 129         if (args.v1.ucReplyStatus == 2) {
 130                 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
 131                 r = -EIO;
 132                 goto done;
 133         }
 134
 135         /* error */
 136         if (args.v1.ucReplyStatus == 3) {
 137                 DRM_DEBUG_KMS("dp_aux_ch error\n");
 138                 r = -EIO;
 139                 goto done;
 140         }
 141
 142         recv_bytes = args.v1.ucDataOutLen;
 143         if (recv_bytes > recv_size)
 144                 recv_bytes = recv_size;
 145
 146         if (recv && recv_size)
 147                 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false);
 148
 149         r = recv_bytes;
 150 done:
 151         mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex);
 152         mutex_unlock(&chan->mutex);
 153
 154         return r;
 155 }
 156
 157 #define BARE_ADDRESS_SIZE 3
 158 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
 159
 160 static ssize_t
 161 radeon_dp_aux_transfer_atom(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 162 {
 163         struct radeon_i2c_chan *chan =
 164                 container_of(aux, struct radeon_i2c_chan, aux);
 165         int ret;
 166         u8 tx_buf[20];
 167         size_t tx_size;
 168         u8 ack, delay = 0;
 169
 170         if (WARN_ON(msg->size > 16))
 171                 return -E2BIG;
 172
 173         tx_buf[0] = msg->address & 0xff;
 174         tx_buf[1] = (msg->address >> 8) & 0xff;
 175         tx_buf[2] = (msg->request << 4) |
 176                 ((msg->address >> 16) & 0xf);
 177         tx_buf[3] = msg->size ? (msg->size - 1) : 0;
 178
 179         switch (msg->request & ~DP_AUX_I2C_MOT) {
 180         case DP_AUX_NATIVE_WRITE:
 181         case DP_AUX_I2C_WRITE:
 182         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
 183                 /* The atom implementation only supports writes with a max payload of
 184                  * 12 bytes since it uses 4 bits for the total count (header + payload)
 185                  * in the parameter space.  The atom interface supports 16 byte
 186                  * payloads for reads. The hw itself supports up to 16 bytes of payload.
 187                  */
 188                 if (WARN_ON_ONCE(msg->size > 12))
 189                         return -E2BIG;
 190                 /* tx_size needs to be 4 even for bare address packets since the atom
 191                  * table needs the info in tx_buf[3].
 192                  */
 193                 tx_size = HEADER_SIZE + msg->size;
 194                 if (msg->size == 0)
 195                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
 196                 else
 197                         tx_buf[3] |= tx_size << 4;
 198                 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
 199                 ret = radeon_process_aux_ch(chan,
 200                                             tx_buf, tx_size, NULL, 0, delay, &ack);
 201                 if (ret >= 0)
 202                         /* Return payload size. */
 203                         ret = msg->size;
 204                 break;
 205         case DP_AUX_NATIVE_READ:
 206         case DP_AUX_I2C_READ:
 207                 /* tx_size needs to be 4 even for bare address packets since the atom
 208                  * table needs the info in tx_buf[3].
 209                  */
 210                 tx_size = HEADER_SIZE;
 211                 if (msg->size == 0)
 212                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
 213                 else
 214                         tx_buf[3] |= tx_size << 4;
 215                 ret = radeon_process_aux_ch(chan,
 216                                             tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
 217                 break;
 218         default:
 219                 ret = -EINVAL;
 220                 break;
 221         }
 222
 223         if (ret >= 0)
 224                 msg->reply = ack >> 4;
 225
 226         return ret;
 227 }
 228
 229 void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
 230 {
 231         struct drm_device *dev = radeon_connector->base.dev;
 232         struct radeon_device *rdev = dev->dev_private;
 233         int ret;
 234
 235         radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
 236         radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
 237         if (ASIC_IS_DCE5(rdev)) {
 238                 if (radeon_auxch)
 239                         radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native;
 240                 else
 241                         radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
 242         } else {
 243                 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
 244         }
 245
 246         ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux);
 247         if (!ret)
 248                 radeon_connector->ddc_bus->has_aux = true;
 249
 250         WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret);
 251 }
 252
 253 /***** general DP utility functions *****/
 254
 255 #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_LEVEL_3
 256 #define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPH_LEVEL_3
 257
 258 static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],
 259                                 int lane_count,
 260                                 u8 train_set[4])
 261 {
 262         u8 v = 0;
 263         u8 p = 0;
 264         int lane;
 265
 266         for (lane = 0; lane < lane_count; lane++) {
 267                 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 268                 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
 269
 270                 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
 271                           lane,
 272                           voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 273                           pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 274
 275                 if (this_v > v)
 276                         v = this_v;
 277                 if (this_p > p)
 278                         p = this_p;
 279         }
 280
 281         if (v >= DP_VOLTAGE_MAX)
 282                 v |= DP_TRAIN_MAX_SWING_REACHED;
 283
 284         if (p >= DP_PRE_EMPHASIS_MAX)
 285                 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 286
 287         DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
 288                   voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 289                   pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 290
 291         for (lane = 0; lane < 4; lane++)
 292                 train_set[lane] = v | p;
 293 }
 294
 295 /* convert bits per color to bits per pixel */
 296 /* get bpc from the EDID */
 297 static int convert_bpc_to_bpp(int bpc)
 298 {
 299         if (bpc == 0)
 300                 return 24;
 301         else
 302                 return bpc * 3;
 303 }
 304
 305 /***** radeon specific DP functions *****/
 306
 307 int radeon_dp_get_dp_link_config(struct drm_connector *connector,
 308                                  const u8 dpcd[DP_DPCD_SIZE],
 309                                  unsigned pix_clock,
 310                                  unsigned *dp_lanes, unsigned *dp_rate)
 311 {
 312         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 313         static const unsigned link_rates[3] = { 162000, 270000, 540000 };
 314         unsigned max_link_rate = drm_dp_max_link_rate(dpcd);
 315         unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
 316         unsigned lane_num, i, max_pix_clock;
 317
 318         if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
 319             ENCODER_OBJECT_ID_NUTMEG) {
 320                 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
 321                         max_pix_clock = (lane_num * 270000 * 8) / bpp;
 322                         if (max_pix_clock >= pix_clock) {
 323                                 *dp_lanes = lane_num;
 324                                 *dp_rate = 270000;
 325                                 return 0;
 326                         }
 327                 }
 328         } else {
 329                 for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
 330                         for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
 331                                 max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
 332                                 if (max_pix_clock >= pix_clock) {
 333                                         *dp_lanes = lane_num;
 334                                         *dp_rate = link_rates[i];
 335                                         return 0;
 336                                 }
 337                         }
 338                 }
 339         }
 340
 341         return -EINVAL;
 342 }
 343
 344 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
 345                                     int action, int dp_clock,
 346                                     u8 ucconfig, u8 lane_num)
 347 {
 348         DP_ENCODER_SERVICE_PARAMETERS args;
 349         int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 350
 351         memset(&args, 0, sizeof(args));
 352         args.ucLinkClock = dp_clock / 10;
 353         args.ucConfig = ucconfig;
 354         args.ucAction = action;
 355         args.ucLaneNum = lane_num;
 356         args.ucStatus = 0;
 357
 358         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 359         return args.ucStatus;
 360 }
 361
 362 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
 363 {
 364         struct drm_device *dev = radeon_connector->base.dev;
 365         struct radeon_device *rdev = dev->dev_private;
 366
 367         return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
 368                                          radeon_connector->ddc_bus->rec.i2c_id, 0);
 369 }
 370
 371 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
 372 {
 373         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 374         u8 buf[3];
 375
 376         if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
 377                 return;
 378
 379         if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
 380                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
 381                               buf[0], buf[1], buf[2]);
 382
 383         if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
 384                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
 385                               buf[0], buf[1], buf[2]);
 386 }
 387
 388 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
 389 {
 390         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 391         u8 msg[DP_DPCD_SIZE];
 392         int ret;
 393
 394         ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
 395                                DP_DPCD_SIZE);
 396         if (ret == DP_DPCD_SIZE) {
 397                 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
 398
 399                 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
 400                               dig_connector->dpcd);
 401
 402                 radeon_dp_probe_oui(radeon_connector);
 403
 404                 return true;
 405         }
 406
 407         dig_connector->dpcd[0] = 0;
 408         return false;
 409 }
 410
 411 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
 412                              struct drm_connector *connector)
 413 {
 414         struct drm_device *dev = encoder->dev;
 415         struct radeon_device *rdev = dev->dev_private;
 416         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 417         struct radeon_connector_atom_dig *dig_connector;
 418         int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 419         u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
 420         u8 tmp;
 421
 422         if (!ASIC_IS_DCE4(rdev))
 423                 return panel_mode;
 424
 425         if (!radeon_connector->con_priv)
 426                 return panel_mode;
 427
 428         dig_connector = radeon_connector->con_priv;
 429
 430         if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
 431                 /* DP bridge chips */
 432                 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
 433                                       DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
 434                         if (tmp & 1)
 435                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 436                         else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
 437                                  (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
 438                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
 439                         else
 440                                 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 441                 }
 442         } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
 443                 /* eDP */
 444                 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
 445                                       DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
 446                         if (tmp & 1)
 447                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 448                 }
 449         }
 450
 451         return panel_mode;
 452 }
 453
 454 void radeon_dp_set_link_config(struct drm_connector *connector,
 455                                const struct drm_display_mode *mode)
 456 {
 457         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 458         struct radeon_connector_atom_dig *dig_connector;
 459         int ret;
 460
 461         if (!radeon_connector->con_priv)
 462                 return;
 463         dig_connector = radeon_connector->con_priv;
 464
 465         if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 466             (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 467                 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd,
 468                                                    mode->clock,
 469                                                    &dig_connector->dp_lane_count,
 470                                                    &dig_connector->dp_clock);
 471                 if (ret) {
 472                         dig_connector->dp_clock = 0;
 473                         dig_connector->dp_lane_count = 0;
 474                 }
 475         }
 476 }
 477
 478 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
 479                                 struct drm_display_mode *mode)
 480 {
 481         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 482         struct radeon_connector_atom_dig *dig_connector;
 483         unsigned dp_clock, dp_lanes;
 484         int ret;
 485
 486         if ((mode->clock > 340000) &&
 487             (!radeon_connector_is_dp12_capable(connector)))
 488                 return MODE_CLOCK_HIGH;
 489
 490         if (!radeon_connector->con_priv)
 491                 return MODE_CLOCK_HIGH;
 492         dig_connector = radeon_connector->con_priv;
 493
 494         ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd,
 495                                            mode->clock,
 496                                            &dp_lanes,
 497                                            &dp_clock);
 498         if (ret)
 499                 return MODE_CLOCK_HIGH;
 500
 501         if ((dp_clock == 540000) &&
 502             (!radeon_connector_is_dp12_capable(connector)))
 503                 return MODE_CLOCK_HIGH;
 504
 505         return MODE_OK;
 506 }
 507
 508 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
 509 {
 510         u8 link_status[DP_LINK_STATUS_SIZE];
 511         struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 512
 513         if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status)
 514             <= 0)
 515                 return false;
 516         if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
 517                 return false;
 518         return true;
 519 }
 520
 521 void radeon_dp_set_rx_power_state(struct drm_connector *connector,
 522                                   u8 power_state)
 523 {
 524         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 525         struct radeon_connector_atom_dig *dig_connector;
 526
 527         if (!radeon_connector->con_priv)
 528                 return;
 529
 530         dig_connector = radeon_connector->con_priv;
 531
 532         /* power up/down the sink */
 533         if (dig_connector->dpcd[0] >= 0x11) {
 534                 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux,
 535                                    DP_SET_POWER, power_state);
 536                 usleep_range(1000, 2000);
 537         }
 538 }
 539
 540
 541 struct radeon_dp_link_train_info {
 542         struct radeon_device *rdev;
 543         struct drm_encoder *encoder;
 544         struct drm_connector *connector;
 545         int enc_id;
 546         int dp_clock;
 547         int dp_lane_count;
 548         bool tp3_supported;
 549         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 550         u8 train_set[4];
 551         u8 link_status[DP_LINK_STATUS_SIZE];
 552         u8 tries;
 553         bool use_dpencoder;
 554         struct drm_dp_aux *aux;
 555 };
 556
 557 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
 558 {
 559         /* set the initial vs/emph on the source */
 560         atombios_dig_transmitter_setup(dp_info->encoder,
 561                                        ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
 562                                        0, dp_info->train_set[0]); /* sets all lanes at once */
 563
 564         /* set the vs/emph on the sink */
 565         drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
 566                           dp_info->train_set, dp_info->dp_lane_count);
 567 }
 568
 569 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
 570 {
 571         int rtp = 0;
 572
 573         /* set training pattern on the source */
 574         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
 575                 switch (tp) {
 576                 case DP_TRAINING_PATTERN_1:
 577                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
 578                         break;
 579                 case DP_TRAINING_PATTERN_2:
 580                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
 581                         break;
 582                 case DP_TRAINING_PATTERN_3:
 583                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
 584                         break;
 585                 }
 586                 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
 587         } else {
 588                 switch (tp) {
 589                 case DP_TRAINING_PATTERN_1:
 590                         rtp = 0;
 591                         break;
 592                 case DP_TRAINING_PATTERN_2:
 593                         rtp = 1;
 594                         break;
 595                 }
 596                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
 597                                           dp_info->dp_clock, dp_info->enc_id, rtp);
 598         }
 599
 600         /* enable training pattern on the sink */
 601         drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
 602 }
 603
 604 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
 605 {
 606         struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
 607         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 608         u8 tmp;
 609
 610         /* power up the sink */
 611         radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
 612
 613         /* possibly enable downspread on the sink */
 614         if (dp_info->dpcd[3] & 0x1)
 615                 drm_dp_dpcd_writeb(dp_info->aux,
 616                                    DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
 617         else
 618                 drm_dp_dpcd_writeb(dp_info->aux,
 619                                    DP_DOWNSPREAD_CTRL, 0);
 620
 621         if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
 622                 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
 623
 624         /* set the lane count on the sink */
 625         tmp = dp_info->dp_lane_count;
 626         if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
 627                 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 628         drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
 629
 630         /* set the link rate on the sink */
 631         tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
 632         drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
 633
 634         /* start training on the source */
 635         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 636                 atombios_dig_encoder_setup(dp_info->encoder,
 637                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
 638         else
 639                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
 640                                           dp_info->dp_clock, dp_info->enc_id, 0);
 641
 642         /* disable the training pattern on the sink */
 643         drm_dp_dpcd_writeb(dp_info->aux,
 644                            DP_TRAINING_PATTERN_SET,
 645                            DP_TRAINING_PATTERN_DISABLE);
 646
 647         return 0;
 648 }
 649
 650 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
 651 {
 652         udelay(400);
 653
 654         /* disable the training pattern on the sink */
 655         drm_dp_dpcd_writeb(dp_info->aux,
 656                            DP_TRAINING_PATTERN_SET,
 657                            DP_TRAINING_PATTERN_DISABLE);
 658
 659         /* disable the training pattern on the source */
 660         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 661                 atombios_dig_encoder_setup(dp_info->encoder,
 662                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
 663         else
 664                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
 665                                           dp_info->dp_clock, dp_info->enc_id, 0);
 666
 667         return 0;
 668 }
 669
 670 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
 671 {
 672         bool clock_recovery;
 673         u8 voltage;
 674         int i;
 675
 676         radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
 677         memset(dp_info->train_set, 0, 4);
 678         radeon_dp_update_vs_emph(dp_info);
 679
 680         udelay(400);
 681
 682         /* clock recovery loop */
 683         clock_recovery = false;
 684         dp_info->tries = 0;
 685         voltage = 0xff;
 686         while (1) {
 687                 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
 688
 689                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
 690                                                  dp_info->link_status) <= 0) {
 691                         DRM_ERROR("displayport link status failed\n");
 692                         break;
 693                 }
 694
 695                 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 696                         clock_recovery = true;
 697                         break;
 698                 }
 699
 700                 for (i = 0; i < dp_info->dp_lane_count; i++) {
 701                         if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
 702                                 break;
 703                 }
 704                 if (i == dp_info->dp_lane_count) {
 705                         DRM_ERROR("clock recovery reached max voltage\n");
 706                         break;
 707                 }
 708
 709                 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
 710                         ++dp_info->tries;
 711                         if (dp_info->tries == 5) {
 712                                 DRM_ERROR("clock recovery tried 5 times\n");
 713                                 break;
 714                         }
 715                 } else
 716                         dp_info->tries = 0;
 717
 718                 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 719
 720                 /* Compute new train_set as requested by sink */
 721                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 722
 723                 radeon_dp_update_vs_emph(dp_info);
 724         }
 725         if (!clock_recovery) {
 726                 DRM_ERROR("clock recovery failed\n");
 727                 return -1;
 728         } else {
 729                 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
 730                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 731                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
 732                           DP_TRAIN_PRE_EMPHASIS_SHIFT);
 733                 return 0;
 734         }
 735 }
 736
 737 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
 738 {
 739         bool channel_eq;
 740
 741         if (dp_info->tp3_supported)
 742                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
 743         else
 744                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
 745
 746         /* channel equalization loop */
 747         dp_info->tries = 0;
 748         channel_eq = false;
 749         while (1) {
 750                 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
 751
 752                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
 753                                                  dp_info->link_status) <= 0) {
 754                         DRM_ERROR("displayport link status failed\n");
 755                         break;
 756                 }
 757
 758                 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 759                         channel_eq = true;
 760                         break;
 761                 }
 762
 763                 /* Try 5 times */
 764                 if (dp_info->tries > 5) {
 765                         DRM_ERROR("channel eq failed: 5 tries\n");
 766                         break;
 767                 }
 768
 769                 /* Compute new train_set as requested by sink */
 770                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 771
 772                 radeon_dp_update_vs_emph(dp_info);
 773                 dp_info->tries++;
 774         }
 775
 776         if (!channel_eq) {
 777                 DRM_ERROR("channel eq failed\n");
 778                 return -1;
 779         } else {
 780                 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
 781                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 782                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
 783                           >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
 784                 return 0;
 785         }
 786 }
 787
 788 void radeon_dp_link_train(struct drm_encoder *encoder,
 789                           struct drm_connector *connector)
 790 {
 791         struct drm_device *dev = encoder->dev;
 792         struct radeon_device *rdev = dev->dev_private;
 793         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 794         struct radeon_encoder_atom_dig *dig;
 795         struct radeon_connector *radeon_connector;
 796         struct radeon_connector_atom_dig *dig_connector;
 797         struct radeon_dp_link_train_info dp_info;
 798         int index;
 799         u8 tmp, frev, crev;
 800
 801         if (!radeon_encoder->enc_priv)
 802                 return;
 803         dig = radeon_encoder->enc_priv;
 804
 805         radeon_connector = to_radeon_connector(connector);
 806         if (!radeon_connector->con_priv)
 807                 return;
 808         dig_connector = radeon_connector->con_priv;
 809
 810         if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
 811             (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
 812                 return;
 813
 814         /* DPEncoderService newer than 1.1 can't program properly the
 815          * training pattern. When facing such version use the
 816          * DIGXEncoderControl (X== 1 | 2)
 817          */
 818         dp_info.use_dpencoder = true;
 819         index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 820         if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
 821                 if (crev > 1) {
 822                         dp_info.use_dpencoder = false;
 823                 }
 824         }
 825
 826         dp_info.enc_id = 0;
 827         if (dig->dig_encoder)
 828                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
 829         else
 830                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
 831         if (dig->linkb)
 832                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
 833         else
 834                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
 835
 836         if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
 837             == 1) {
 838                 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
 839                         dp_info.tp3_supported = true;
 840                 else
 841                         dp_info.tp3_supported = false;
 842         } else {
 843                 dp_info.tp3_supported = false;
 844         }
 845
 846         memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
 847         dp_info.rdev = rdev;
 848         dp_info.encoder = encoder;
 849         dp_info.connector = connector;
 850         dp_info.dp_lane_count = dig_connector->dp_lane_count;
 851         dp_info.dp_clock = dig_connector->dp_clock;
 852         dp_info.aux = &radeon_connector->ddc_bus->aux;
 853
 854         if (radeon_dp_link_train_init(&dp_info))
 855                 goto done;
 856         if (radeon_dp_link_train_cr(&dp_info))
 857                 goto done;
 858         if (radeon_dp_link_train_ce(&dp_info))
 859                 goto done;
 860 done:
 861         if (radeon_dp_link_train_finish(&dp_info))
 862                 return;
 863 }