drivers/gpu/drm/radeon/atombios_encoders.c

   1 /*
   2  * Copyright 2007-11 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38
  39 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
  40 {
  41         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  42         switch (radeon_encoder->encoder_id) {
  43         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  44         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  45         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  46         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  47         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  48         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  49         case ENCODER_OBJECT_ID_INTERNAL_DDI:
  50         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  51         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  52         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  53         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  54                 return true;
  55         default:
  56                 return false;
  57         }
  58 }
  59
  60 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
  61                                    const struct drm_display_mode *mode,
  62                                    struct drm_display_mode *adjusted_mode)
  63 {
  64         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  65         struct drm_device *dev = encoder->dev;
  66         struct radeon_device *rdev = dev->dev_private;
  67
  68         /* set the active encoder to connector routing */
  69         radeon_encoder_set_active_device(encoder);
  70         drm_mode_set_crtcinfo(adjusted_mode, 0);
  71
  72         /* hw bug */
  73         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
  74             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
  75                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
  76
  77         /* get the native mode for LVDS */
  78         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
  79                 radeon_panel_mode_fixup(encoder, adjusted_mode);
  80
  81         /* get the native mode for TV */
  82         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
  83                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
  84                 if (tv_dac) {
  85                         if (tv_dac->tv_std == TV_STD_NTSC ||
  86                             tv_dac->tv_std == TV_STD_NTSC_J ||
  87                             tv_dac->tv_std == TV_STD_PAL_M)
  88                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
  89                         else
  90                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
  91                 }
  92         }
  93
  94         if (ASIC_IS_DCE3(rdev) &&
  95             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
  96              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
  97                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
  98                 radeon_dp_set_link_config(connector, mode);
  99         }
 100
 101         return true;
 102 }
 103
 104 static void
 105 atombios_dac_setup(struct drm_encoder *encoder, int action)
 106 {
 107         struct drm_device *dev = encoder->dev;
 108         struct radeon_device *rdev = dev->dev_private;
 109         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 110         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 111         int index = 0;
 112         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 113
 114         memset(&args, 0, sizeof(args));
 115
 116         switch (radeon_encoder->encoder_id) {
 117         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 118         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 119                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 120                 break;
 121         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 122         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 123                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 124                 break;
 125         }
 126
 127         args.ucAction = action;
 128
 129         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 130                 args.ucDacStandard = ATOM_DAC1_PS2;
 131         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 132                 args.ucDacStandard = ATOM_DAC1_CV;
 133         else {
 134                 switch (dac_info->tv_std) {
 135                 case TV_STD_PAL:
 136                 case TV_STD_PAL_M:
 137                 case TV_STD_SCART_PAL:
 138                 case TV_STD_SECAM:
 139                 case TV_STD_PAL_CN:
 140                         args.ucDacStandard = ATOM_DAC1_PAL;
 141                         break;
 142                 case TV_STD_NTSC:
 143                 case TV_STD_NTSC_J:
 144                 case TV_STD_PAL_60:
 145                 default:
 146                         args.ucDacStandard = ATOM_DAC1_NTSC;
 147                         break;
 148                 }
 149         }
 150         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 151
 152         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 153
 154 }
 155
 156 static void
 157 atombios_tv_setup(struct drm_encoder *encoder, int action)
 158 {
 159         struct drm_device *dev = encoder->dev;
 160         struct radeon_device *rdev = dev->dev_private;
 161         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 162         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 163         int index = 0;
 164         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 165
 166         memset(&args, 0, sizeof(args));
 167
 168         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 169
 170         args.sTVEncoder.ucAction = action;
 171
 172         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 173                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 174         else {
 175                 switch (dac_info->tv_std) {
 176                 case TV_STD_NTSC:
 177                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 178                         break;
 179                 case TV_STD_PAL:
 180                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 181                         break;
 182                 case TV_STD_PAL_M:
 183                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 184                         break;
 185                 case TV_STD_PAL_60:
 186                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 187                         break;
 188                 case TV_STD_NTSC_J:
 189                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 190                         break;
 191                 case TV_STD_SCART_PAL:
 192                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 193                         break;
 194                 case TV_STD_SECAM:
 195                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 196                         break;
 197                 case TV_STD_PAL_CN:
 198                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 199                         break;
 200                 default:
 201                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 202                         break;
 203                 }
 204         }
 205
 206         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 207
 208         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 209
 210 }
 211
 212 union dvo_encoder_control {
 213         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 214         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 215         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 216 };
 217
 218 void
 219 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 220 {
 221         struct drm_device *dev = encoder->dev;
 222         struct radeon_device *rdev = dev->dev_private;
 223         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 224         union dvo_encoder_control args;
 225         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 226         uint8_t frev, crev;
 227
 228         memset(&args, 0, sizeof(args));
 229
 230         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 231                 return;
 232
 233         /* some R4xx chips have the wrong frev */
 234         if (rdev->family <= CHIP_RV410)
 235                 frev = 1;
 236
 237         switch (frev) {
 238         case 1:
 239                 switch (crev) {
 240                 case 1:
 241                         /* R4xx, R5xx */
 242                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 243
 244                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 245                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 246
 247                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 248                         break;
 249                 case 2:
 250                         /* RS600/690/740 */
 251                         args.dvo.sDVOEncoder.ucAction = action;
 252                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 253                         /* DFP1, CRT1, TV1 depending on the type of port */
 254                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 255
 256                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 257                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 258                         break;
 259                 case 3:
 260                         /* R6xx */
 261                         args.dvo_v3.ucAction = action;
 262                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 263                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
 264                         break;
 265                 default:
 266                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 267                         break;
 268                 }
 269                 break;
 270         default:
 271                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 272                 break;
 273         }
 274
 275         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 276 }
 277
 278 union lvds_encoder_control {
 279         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 280         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 281 };
 282
 283 void
 284 atombios_digital_setup(struct drm_encoder *encoder, int action)
 285 {
 286         struct drm_device *dev = encoder->dev;
 287         struct radeon_device *rdev = dev->dev_private;
 288         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 289         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 290         union lvds_encoder_control args;
 291         int index = 0;
 292         int hdmi_detected = 0;
 293         uint8_t frev, crev;
 294
 295         if (!dig)
 296                 return;
 297
 298         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 299                 hdmi_detected = 1;
 300
 301         memset(&args, 0, sizeof(args));
 302
 303         switch (radeon_encoder->encoder_id) {
 304         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 305                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 306                 break;
 307         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 308         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 309                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 310                 break;
 311         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 312                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 313                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 314                 else
 315                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 316                 break;
 317         }
 318
 319         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 320                 return;
 321
 322         switch (frev) {
 323         case 1:
 324         case 2:
 325                 switch (crev) {
 326                 case 1:
 327                         args.v1.ucMisc = 0;
 328                         args.v1.ucAction = action;
 329                         if (hdmi_detected)
 330                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 331                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 332                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 333                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 334                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 335                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 336                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 337                         } else {
 338                                 if (dig->linkb)
 339                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 340                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 341                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 342                                 /*if (pScrn->rgbBits == 8) */
 343                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 344                         }
 345                         break;
 346                 case 2:
 347                 case 3:
 348                         args.v2.ucMisc = 0;
 349                         args.v2.ucAction = action;
 350                         if (crev == 3) {
 351                                 if (dig->coherent_mode)
 352                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 353                         }
 354                         if (hdmi_detected)
 355                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 356                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 357                         args.v2.ucTruncate = 0;
 358                         args.v2.ucSpatial = 0;
 359                         args.v2.ucTemporal = 0;
 360                         args.v2.ucFRC = 0;
 361                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 362                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 363                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 364                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 365                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 366                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 367                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 368                                 }
 369                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 370                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 371                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 372                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 373                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 374                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 375                                 }
 376                         } else {
 377                                 if (dig->linkb)
 378                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 379                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 380                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 381                         }
 382                         break;
 383                 default:
 384                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 385                         break;
 386                 }
 387                 break;
 388         default:
 389                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 390                 break;
 391         }
 392
 393         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 394 }
 395
 396 int
 397 atombios_get_encoder_mode(struct drm_encoder *encoder)
 398 {
 399         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 400         struct drm_connector *connector;
 401         struct radeon_connector *radeon_connector;
 402         struct radeon_connector_atom_dig *dig_connector;
 403
 404         /* dp bridges are always DP */
 405         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 406                 return ATOM_ENCODER_MODE_DP;
 407
 408         /* DVO is always DVO */
 409         if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
 410                 return ATOM_ENCODER_MODE_DVO;
 411
 412         connector = radeon_get_connector_for_encoder(encoder);
 413         /* if we don't have an active device yet, just use one of
 414          * the connectors tied to the encoder.
 415          */
 416         if (!connector)
 417                 connector = radeon_get_connector_for_encoder_init(encoder);
 418         radeon_connector = to_radeon_connector(connector);
 419
 420         switch (connector->connector_type) {
 421         case DRM_MODE_CONNECTOR_DVII:
 422         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 423                 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 424                     radeon_audio)
 425                         return ATOM_ENCODER_MODE_HDMI;
 426                 else if (radeon_connector->use_digital)
 427                         return ATOM_ENCODER_MODE_DVI;
 428                 else
 429                         return ATOM_ENCODER_MODE_CRT;
 430                 break;
 431         case DRM_MODE_CONNECTOR_DVID:
 432         case DRM_MODE_CONNECTOR_HDMIA:
 433         default:
 434                 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 435                     radeon_audio)
 436                         return ATOM_ENCODER_MODE_HDMI;
 437                 else
 438                         return ATOM_ENCODER_MODE_DVI;
 439                 break;
 440         case DRM_MODE_CONNECTOR_LVDS:
 441                 return ATOM_ENCODER_MODE_LVDS;
 442                 break;
 443         case DRM_MODE_CONNECTOR_DisplayPort:
 444                 dig_connector = radeon_connector->con_priv;
 445                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 446                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 447                         return ATOM_ENCODER_MODE_DP;
 448                 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 449                          radeon_audio)
 450                         return ATOM_ENCODER_MODE_HDMI;
 451                 else
 452                         return ATOM_ENCODER_MODE_DVI;
 453                 break;
 454         case DRM_MODE_CONNECTOR_eDP:
 455                 return ATOM_ENCODER_MODE_DP;
 456         case DRM_MODE_CONNECTOR_DVIA:
 457         case DRM_MODE_CONNECTOR_VGA:
 458                 return ATOM_ENCODER_MODE_CRT;
 459                 break;
 460         case DRM_MODE_CONNECTOR_Composite:
 461         case DRM_MODE_CONNECTOR_SVIDEO:
 462         case DRM_MODE_CONNECTOR_9PinDIN:
 463                 /* fix me */
 464                 return ATOM_ENCODER_MODE_TV;
 465                 /*return ATOM_ENCODER_MODE_CV;*/
 466                 break;
 467         }
 468 }
 469
 470 /*
 471  * DIG Encoder/Transmitter Setup
 472  *
 473  * DCE 3.0/3.1
 474  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 475  * Supports up to 3 digital outputs
 476  * - 2 DIG encoder blocks.
 477  * DIG1 can drive UNIPHY link A or link B
 478  * DIG2 can drive UNIPHY link B or LVTMA
 479  *
 480  * DCE 3.2
 481  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 482  * Supports up to 5 digital outputs
 483  * - 2 DIG encoder blocks.
 484  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 485  *
 486  * DCE 4.0/5.0/6.0
 487  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 488  * Supports up to 6 digital outputs
 489  * - 6 DIG encoder blocks.
 490  * - DIG to PHY mapping is hardcoded
 491  * DIG1 drives UNIPHY0 link A, A+B
 492  * DIG2 drives UNIPHY0 link B
 493  * DIG3 drives UNIPHY1 link A, A+B
 494  * DIG4 drives UNIPHY1 link B
 495  * DIG5 drives UNIPHY2 link A, A+B
 496  * DIG6 drives UNIPHY2 link B
 497  *
 498  * DCE 4.1
 499  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 500  * Supports up to 6 digital outputs
 501  * - 2 DIG encoder blocks.
 502  * llano
 503  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 504  * ontario
 505  * DIG1 drives UNIPHY0/1/2 link A
 506  * DIG2 drives UNIPHY0/1/2 link B
 507  *
 508  * Routing
 509  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 510  * Examples:
 511  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 512  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 513  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 514  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 515  */
 516
 517 union dig_encoder_control {
 518         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 519         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 520         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 521         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 522 };
 523
 524 void
 525 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 526 {
 527         struct drm_device *dev = encoder->dev;
 528         struct radeon_device *rdev = dev->dev_private;
 529         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 530         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 531         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 532         union dig_encoder_control args;
 533         int index = 0;
 534         uint8_t frev, crev;
 535         int dp_clock = 0;
 536         int dp_lane_count = 0;
 537         int hpd_id = RADEON_HPD_NONE;
 538         int bpc = 8;
 539
 540         if (connector) {
 541                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 542                 struct radeon_connector_atom_dig *dig_connector =
 543                         radeon_connector->con_priv;
 544
 545                 dp_clock = dig_connector->dp_clock;
 546                 dp_lane_count = dig_connector->dp_lane_count;
 547                 hpd_id = radeon_connector->hpd.hpd;
 548                 bpc = radeon_get_monitor_bpc(connector);
 549         }
 550
 551         /* no dig encoder assigned */
 552         if (dig->dig_encoder == -1)
 553                 return;
 554
 555         memset(&args, 0, sizeof(args));
 556
 557         if (ASIC_IS_DCE4(rdev))
 558                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 559         else {
 560                 if (dig->dig_encoder)
 561                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 562                 else
 563                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 564         }
 565
 566         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 567                 return;
 568
 569         switch (frev) {
 570         case 1:
 571                 switch (crev) {
 572                 case 1:
 573                         args.v1.ucAction = action;
 574                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 575                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 576                                 args.v3.ucPanelMode = panel_mode;
 577                         else
 578                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 579
 580                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 581                                 args.v1.ucLaneNum = dp_lane_count;
 582                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 583                                 args.v1.ucLaneNum = 8;
 584                         else
 585                                 args.v1.ucLaneNum = 4;
 586
 587                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 588                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 589                         switch (radeon_encoder->encoder_id) {
 590                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 591                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 592                                 break;
 593                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 594                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 595                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 596                                 break;
 597                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 598                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 599                                 break;
 600                         }
 601                         if (dig->linkb)
 602                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 603                         else
 604                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 605                         break;
 606                 case 2:
 607                 case 3:
 608                         args.v3.ucAction = action;
 609                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 610                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 611                                 args.v3.ucPanelMode = panel_mode;
 612                         else
 613                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 614
 615                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 616                                 args.v3.ucLaneNum = dp_lane_count;
 617                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 618                                 args.v3.ucLaneNum = 8;
 619                         else
 620                                 args.v3.ucLaneNum = 4;
 621
 622                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 623                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 624                         args.v3.acConfig.ucDigSel = dig->dig_encoder;
 625                         switch (bpc) {
 626                         case 0:
 627                                 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
 628                                 break;
 629                         case 6:
 630                                 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
 631                                 break;
 632                         case 8:
 633                         default:
 634                                 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 635                                 break;
 636                         case 10:
 637                                 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
 638                                 break;
 639                         case 12:
 640                                 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
 641                                 break;
 642                         case 16:
 643                                 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
 644                                 break;
 645                         }
 646                         break;
 647                 case 4:
 648                         args.v4.ucAction = action;
 649                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 650                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 651                                 args.v4.ucPanelMode = panel_mode;
 652                         else
 653                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
 654
 655                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 656                                 args.v4.ucLaneNum = dp_lane_count;
 657                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 658                                 args.v4.ucLaneNum = 8;
 659                         else
 660                                 args.v4.ucLaneNum = 4;
 661
 662                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
 663                                 if (dp_clock == 270000)
 664                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 665                                 else if (dp_clock == 540000)
 666                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 667                         }
 668                         args.v4.acConfig.ucDigSel = dig->dig_encoder;
 669                         switch (bpc) {
 670                         case 0:
 671                                 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
 672                                 break;
 673                         case 6:
 674                                 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
 675                                 break;
 676                         case 8:
 677                         default:
 678                                 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 679                                 break;
 680                         case 10:
 681                                 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
 682                                 break;
 683                         case 12:
 684                                 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
 685                                 break;
 686                         case 16:
 687                                 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
 688                                 break;
 689                         }
 690                         if (hpd_id == RADEON_HPD_NONE)
 691                                 args.v4.ucHPD_ID = 0;
 692                         else
 693                                 args.v4.ucHPD_ID = hpd_id + 1;
 694                         break;
 695                 default:
 696                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 697                         break;
 698                 }
 699                 break;
 700         default:
 701                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 702                 break;
 703         }
 704
 705         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 706
 707 }
 708
 709 union dig_transmitter_control {
 710         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 711         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 712         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 713         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
 714         DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
 715 };
 716
 717 void
 718 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 719 {
 720         struct drm_device *dev = encoder->dev;
 721         struct radeon_device *rdev = dev->dev_private;
 722         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 723         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 724         struct drm_connector *connector;
 725         union dig_transmitter_control args;
 726         int index = 0;
 727         uint8_t frev, crev;
 728         bool is_dp = false;
 729         int pll_id = 0;
 730         int dp_clock = 0;
 731         int dp_lane_count = 0;
 732         int connector_object_id = 0;
 733         int igp_lane_info = 0;
 734         int dig_encoder = dig->dig_encoder;
 735         int hpd_id = RADEON_HPD_NONE;
 736
 737         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 738                 connector = radeon_get_connector_for_encoder_init(encoder);
 739                 /* just needed to avoid bailing in the encoder check.  the encoder
 740                  * isn't used for init
 741                  */
 742                 dig_encoder = 0;
 743         } else
 744                 connector = radeon_get_connector_for_encoder(encoder);
 745
 746         if (connector) {
 747                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 748                 struct radeon_connector_atom_dig *dig_connector =
 749                         radeon_connector->con_priv;
 750
 751                 hpd_id = radeon_connector->hpd.hpd;
 752                 dp_clock = dig_connector->dp_clock;
 753                 dp_lane_count = dig_connector->dp_lane_count;
 754                 connector_object_id =
 755                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 756                 igp_lane_info = dig_connector->igp_lane_info;
 757         }
 758
 759         if (encoder->crtc) {
 760                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 761                 pll_id = radeon_crtc->pll_id;
 762         }
 763
 764         /* no dig encoder assigned */
 765         if (dig_encoder == -1)
 766                 return;
 767
 768         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
 769                 is_dp = true;
 770
 771         memset(&args, 0, sizeof(args));
 772
 773         switch (radeon_encoder->encoder_id) {
 774         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 775                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
 776                 break;
 777         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 778         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 779         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 780                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 781                 break;
 782         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 783                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
 784                 break;
 785         }
 786
 787         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 788                 return;
 789
 790         switch (frev) {
 791         case 1:
 792                 switch (crev) {
 793                 case 1:
 794                         args.v1.ucAction = action;
 795                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 796                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
 797                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 798                                 args.v1.asMode.ucLaneSel = lane_num;
 799                                 args.v1.asMode.ucLaneSet = lane_set;
 800                         } else {
 801                                 if (is_dp)
 802                                         args.v1.usPixelClock =
 803                                                 cpu_to_le16(dp_clock / 10);
 804                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 805                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 806                                 else
 807                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 808                         }
 809
 810                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 811
 812                         if (dig_encoder)
 813                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 814                         else
 815                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 816
 817                         if ((rdev->flags & RADEON_IS_IGP) &&
 818                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
 819                                 if (is_dp ||
 820                                     !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
 821                                         if (igp_lane_info & 0x1)
 822                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 823                                         else if (igp_lane_info & 0x2)
 824                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 825                                         else if (igp_lane_info & 0x4)
 826                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 827                                         else if (igp_lane_info & 0x8)
 828                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 829                                 } else {
 830                                         if (igp_lane_info & 0x3)
 831                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 832                                         else if (igp_lane_info & 0xc)
 833                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
 834                                 }
 835                         }
 836
 837                         if (dig->linkb)
 838                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
 839                         else
 840                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
 841
 842                         if (is_dp)
 843                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 844                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 845                                 if (dig->coherent_mode)
 846                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 847                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 848                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
 849                         }
 850                         break;
 851                 case 2:
 852                         args.v2.ucAction = action;
 853                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 854                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
 855                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 856                                 args.v2.asMode.ucLaneSel = lane_num;
 857                                 args.v2.asMode.ucLaneSet = lane_set;
 858                         } else {
 859                                 if (is_dp)
 860                                         args.v2.usPixelClock =
 861                                                 cpu_to_le16(dp_clock / 10);
 862                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 863                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 864                                 else
 865                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 866                         }
 867
 868                         args.v2.acConfig.ucEncoderSel = dig_encoder;
 869                         if (dig->linkb)
 870                                 args.v2.acConfig.ucLinkSel = 1;
 871
 872                         switch (radeon_encoder->encoder_id) {
 873                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 874                                 args.v2.acConfig.ucTransmitterSel = 0;
 875                                 break;
 876                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 877                                 args.v2.acConfig.ucTransmitterSel = 1;
 878                                 break;
 879                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 880                                 args.v2.acConfig.ucTransmitterSel = 2;
 881                                 break;
 882                         }
 883
 884                         if (is_dp) {
 885                                 args.v2.acConfig.fCoherentMode = 1;
 886                                 args.v2.acConfig.fDPConnector = 1;
 887                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 888                                 if (dig->coherent_mode)
 889                                         args.v2.acConfig.fCoherentMode = 1;
 890                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 891                                         args.v2.acConfig.fDualLinkConnector = 1;
 892                         }
 893                         break;
 894                 case 3:
 895                         args.v3.ucAction = action;
 896                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 897                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
 898                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 899                                 args.v3.asMode.ucLaneSel = lane_num;
 900                                 args.v3.asMode.ucLaneSet = lane_set;
 901                         } else {
 902                                 if (is_dp)
 903                                         args.v3.usPixelClock =
 904                                                 cpu_to_le16(dp_clock / 10);
 905                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 906                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 907                                 else
 908                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 909                         }
 910
 911                         if (is_dp)
 912                                 args.v3.ucLaneNum = dp_lane_count;
 913                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 914                                 args.v3.ucLaneNum = 8;
 915                         else
 916                                 args.v3.ucLaneNum = 4;
 917
 918                         if (dig->linkb)
 919                                 args.v3.acConfig.ucLinkSel = 1;
 920                         if (dig_encoder & 1)
 921                                 args.v3.acConfig.ucEncoderSel = 1;
 922
 923                         /* Select the PLL for the PHY
 924                          * DP PHY should be clocked from external src if there is
 925                          * one.
 926                          */
 927                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
 928                         if (is_dp && rdev->clock.dp_extclk)
 929                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
 930                         else
 931                                 args.v3.acConfig.ucRefClkSource = pll_id;
 932
 933                         switch (radeon_encoder->encoder_id) {
 934                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 935                                 args.v3.acConfig.ucTransmitterSel = 0;
 936                                 break;
 937                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 938                                 args.v3.acConfig.ucTransmitterSel = 1;
 939                                 break;
 940                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 941                                 args.v3.acConfig.ucTransmitterSel = 2;
 942                                 break;
 943                         }
 944
 945                         if (is_dp)
 946                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
 947                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 948                                 if (dig->coherent_mode)
 949                                         args.v3.acConfig.fCoherentMode = 1;
 950                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 951                                         args.v3.acConfig.fDualLinkConnector = 1;
 952                         }
 953                         break;
 954                 case 4:
 955                         args.v4.ucAction = action;
 956                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 957                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
 958                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 959                                 args.v4.asMode.ucLaneSel = lane_num;
 960                                 args.v4.asMode.ucLaneSet = lane_set;
 961                         } else {
 962                                 if (is_dp)
 963                                         args.v4.usPixelClock =
 964                                                 cpu_to_le16(dp_clock / 10);
 965                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 966                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 967                                 else
 968                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 969                         }
 970
 971                         if (is_dp)
 972                                 args.v4.ucLaneNum = dp_lane_count;
 973                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 974                                 args.v4.ucLaneNum = 8;
 975                         else
 976                                 args.v4.ucLaneNum = 4;
 977
 978                         if (dig->linkb)
 979                                 args.v4.acConfig.ucLinkSel = 1;
 980                         if (dig_encoder & 1)
 981                                 args.v4.acConfig.ucEncoderSel = 1;
 982
 983                         /* Select the PLL for the PHY
 984                          * DP PHY should be clocked from external src if there is
 985                          * one.
 986                          */
 987                         /* On DCE5 DCPLL usually generates the DP ref clock */
 988                         if (is_dp) {
 989                                 if (rdev->clock.dp_extclk)
 990                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
 991                                 else
 992                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
 993                         } else
 994                                 args.v4.acConfig.ucRefClkSource = pll_id;
 995
 996                         switch (radeon_encoder->encoder_id) {
 997                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 998                                 args.v4.acConfig.ucTransmitterSel = 0;
 999                                 break;
1000                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1001                                 args.v4.acConfig.ucTransmitterSel = 1;
1002                                 break;
1003                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1004                                 args.v4.acConfig.ucTransmitterSel = 2;
1005                                 break;
1006                         }
1007
1008                         if (is_dp)
1009                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1010                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1011                                 if (dig->coherent_mode)
1012                                         args.v4.acConfig.fCoherentMode = 1;
1013                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1014                                         args.v4.acConfig.fDualLinkConnector = 1;
1015                         }
1016                         break;
1017                 case 5:
1018                         args.v5.ucAction = action;
1019                         if (is_dp)
1020                                 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1021                         else
1022                                 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1023
1024                         switch (radeon_encoder->encoder_id) {
1025                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1026                                 if (dig->linkb)
1027                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1028                                 else
1029                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1030                                 break;
1031                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1032                                 if (dig->linkb)
1033                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1034                                 else
1035                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1036                                 break;
1037                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1038                                 if (dig->linkb)
1039                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1040                                 else
1041                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1042                                 break;
1043                         }
1044                         if (is_dp)
1045                                 args.v5.ucLaneNum = dp_lane_count;
1046                         else if (radeon_encoder->pixel_clock > 165000)
1047                                 args.v5.ucLaneNum = 8;
1048                         else
1049                                 args.v5.ucLaneNum = 4;
1050                         args.v5.ucConnObjId = connector_object_id;
1051                         args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1052
1053                         if (is_dp && rdev->clock.dp_extclk)
1054                                 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1055                         else
1056                                 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1057
1058                         if (is_dp)
1059                                 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1060                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1061                                 if (dig->coherent_mode)
1062                                         args.v5.asConfig.ucCoherentMode = 1;
1063                         }
1064                         if (hpd_id == RADEON_HPD_NONE)
1065                                 args.v5.asConfig.ucHPDSel = 0;
1066                         else
1067                                 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1068                         args.v5.ucDigEncoderSel = 1 << dig_encoder;
1069                         args.v5.ucDPLaneSet = lane_set;
1070                         break;
1071                 default:
1072                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1073                         break;
1074                 }
1075                 break;
1076         default:
1077                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1078                 break;
1079         }
1080
1081         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1082 }
1083
1084 bool
1085 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1086 {
1087         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1088         struct drm_device *dev = radeon_connector->base.dev;
1089         struct radeon_device *rdev = dev->dev_private;
1090         union dig_transmitter_control args;
1091         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1092         uint8_t frev, crev;
1093
1094         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1095                 goto done;
1096
1097         if (!ASIC_IS_DCE4(rdev))
1098                 goto done;
1099
1100         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1101             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1102                 goto done;
1103
1104         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1105                 goto done;
1106
1107         memset(&args, 0, sizeof(args));
1108
1109         args.v1.ucAction = action;
1110
1111         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1112
1113         /* wait for the panel to power up */
1114         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1115                 int i;
1116
1117                 for (i = 0; i < 300; i++) {
1118                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1119                                 return true;
1120                         mdelay(1);
1121                 }
1122                 return false;
1123         }
1124 done:
1125         return true;
1126 }
1127
1128 union external_encoder_control {
1129         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1130         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1131 };
1132
1133 static void
1134 atombios_external_encoder_setup(struct drm_encoder *encoder,
1135                                 struct drm_encoder *ext_encoder,
1136                                 int action)
1137 {
1138         struct drm_device *dev = encoder->dev;
1139         struct radeon_device *rdev = dev->dev_private;
1140         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1141         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1142         union external_encoder_control args;
1143         struct drm_connector *connector;
1144         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1145         u8 frev, crev;
1146         int dp_clock = 0;
1147         int dp_lane_count = 0;
1148         int connector_object_id = 0;
1149         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1150         int bpc = 8;
1151
1152         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1153                 connector = radeon_get_connector_for_encoder_init(encoder);
1154         else
1155                 connector = radeon_get_connector_for_encoder(encoder);
1156
1157         if (connector) {
1158                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1159                 struct radeon_connector_atom_dig *dig_connector =
1160                         radeon_connector->con_priv;
1161
1162                 dp_clock = dig_connector->dp_clock;
1163                 dp_lane_count = dig_connector->dp_lane_count;
1164                 connector_object_id =
1165                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1166                 bpc = radeon_get_monitor_bpc(connector);
1167         }
1168
1169         memset(&args, 0, sizeof(args));
1170
1171         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1172                 return;
1173
1174         switch (frev) {
1175         case 1:
1176                 /* no params on frev 1 */
1177                 break;
1178         case 2:
1179                 switch (crev) {
1180                 case 1:
1181                 case 2:
1182                         args.v1.sDigEncoder.ucAction = action;
1183                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1184                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1185
1186                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1187                                 if (dp_clock == 270000)
1188                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1189                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1190                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1191                                 args.v1.sDigEncoder.ucLaneNum = 8;
1192                         else
1193                                 args.v1.sDigEncoder.ucLaneNum = 4;
1194                         break;
1195                 case 3:
1196                         args.v3.sExtEncoder.ucAction = action;
1197                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1198                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1199                         else
1200                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1201                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1202
1203                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1204                                 if (dp_clock == 270000)
1205                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1206                                 else if (dp_clock == 540000)
1207                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1208                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1209                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1210                                 args.v3.sExtEncoder.ucLaneNum = 8;
1211                         else
1212                                 args.v3.sExtEncoder.ucLaneNum = 4;
1213                         switch (ext_enum) {
1214                         case GRAPH_OBJECT_ENUM_ID1:
1215                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1216                                 break;
1217                         case GRAPH_OBJECT_ENUM_ID2:
1218                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1219                                 break;
1220                         case GRAPH_OBJECT_ENUM_ID3:
1221                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1222                                 break;
1223                         }
1224                         switch (bpc) {
1225                         case 0:
1226                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1227                                 break;
1228                         case 6:
1229                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1230                                 break;
1231                         case 8:
1232                         default:
1233                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1234                                 break;
1235                         case 10:
1236                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1237                                 break;
1238                         case 12:
1239                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1240                                 break;
1241                         case 16:
1242                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1243                                 break;
1244                         }
1245                         break;
1246                 default:
1247                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1248                         return;
1249                 }
1250                 break;
1251         default:
1252                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1253                 return;
1254         }
1255         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1256 }
1257
1258 static void
1259 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1260 {
1261         struct drm_device *dev = encoder->dev;
1262         struct radeon_device *rdev = dev->dev_private;
1263         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1264         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1265         ENABLE_YUV_PS_ALLOCATION args;
1266         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1267         uint32_t temp, reg;
1268
1269         memset(&args, 0, sizeof(args));
1270
1271         if (rdev->family >= CHIP_R600)
1272                 reg = R600_BIOS_3_SCRATCH;
1273         else
1274                 reg = RADEON_BIOS_3_SCRATCH;
1275
1276         /* XXX: fix up scratch reg handling */
1277         temp = RREG32(reg);
1278         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1279                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1280                              (radeon_crtc->crtc_id << 18)));
1281         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1282                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1283         else
1284                 WREG32(reg, 0);
1285
1286         if (enable)
1287                 args.ucEnable = ATOM_ENABLE;
1288         args.ucCRTC = radeon_crtc->crtc_id;
1289
1290         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1291
1292         WREG32(reg, temp);
1293 }
1294
1295 static void
1296 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1297 {
1298         struct drm_device *dev = encoder->dev;
1299         struct radeon_device *rdev = dev->dev_private;
1300         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1301         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1302         int index = 0;
1303
1304         memset(&args, 0, sizeof(args));
1305
1306         switch (radeon_encoder->encoder_id) {
1307         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1308         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1309                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1310                 break;
1311         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1312         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1313         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1314                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1315                 break;
1316         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1317                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1318                 break;
1319         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1320                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1321                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1322                 else
1323                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1324                 break;
1325         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1326         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1327                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1328                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1329                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1330                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1331                 else
1332                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1333                 break;
1334         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1335         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1336                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1337                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1338                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1339                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1340                 else
1341                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1342                 break;
1343         default:
1344                 return;
1345         }
1346
1347         switch (mode) {
1348         case DRM_MODE_DPMS_ON:
1349                 args.ucAction = ATOM_ENABLE;
1350                 /* workaround for DVOOutputControl on some RS690 systems */
1351                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1352                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1353                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1354                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1355                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1356                 } else
1357                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1358                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1359                         args.ucAction = ATOM_LCD_BLON;
1360                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1361                 }
1362                 break;
1363         case DRM_MODE_DPMS_STANDBY:
1364         case DRM_MODE_DPMS_SUSPEND:
1365         case DRM_MODE_DPMS_OFF:
1366                 args.ucAction = ATOM_DISABLE;
1367                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1368                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1369                         args.ucAction = ATOM_LCD_BLOFF;
1370                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1371                 }
1372                 break;
1373         }
1374 }
1375
1376 static void
1377 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1378 {
1379         struct drm_device *dev = encoder->dev;
1380         struct radeon_device *rdev = dev->dev_private;
1381         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1382         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1383         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1384         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1385         struct radeon_connector *radeon_connector = NULL;
1386         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1387
1388         if (connector) {
1389                 radeon_connector = to_radeon_connector(connector);
1390                 radeon_dig_connector = radeon_connector->con_priv;
1391         }
1392
1393         switch (mode) {
1394         case DRM_MODE_DPMS_ON:
1395                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1396                         if (!connector)
1397                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1398                         else
1399                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1400
1401                         /* setup and enable the encoder */
1402                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1403                         atombios_dig_encoder_setup(encoder,
1404                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1405                                                    dig->panel_mode);
1406                         if (ext_encoder) {
1407                                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1408                                         atombios_external_encoder_setup(encoder, ext_encoder,
1409                                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1410                         }
1411                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1412                 } else if (ASIC_IS_DCE4(rdev)) {
1413                         /* setup and enable the encoder */
1414                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1415                         /* enable the transmitter */
1416                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1417                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1418                 } else {
1419                         /* setup and enable the encoder and transmitter */
1420                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1421                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1422                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1423                         /* some early dce3.2 boards have a bug in their transmitter control table */
1424                         if ((rdev->family != CHIP_RV710) || (rdev->family != CHIP_RV730))
1425                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1426                 }
1427                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1428                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1429                                 atombios_set_edp_panel_power(connector,
1430                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1431                                 radeon_dig_connector->edp_on = true;
1432                         }
1433                         radeon_dp_link_train(encoder, connector);
1434                         if (ASIC_IS_DCE4(rdev))
1435                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1436                 }
1437                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1438                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1439                 break;
1440         case DRM_MODE_DPMS_STANDBY:
1441         case DRM_MODE_DPMS_SUSPEND:
1442         case DRM_MODE_DPMS_OFF:
1443                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1444                         /* disable the transmitter */
1445                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1446                 } else if (ASIC_IS_DCE4(rdev)) {
1447                         /* disable the transmitter */
1448                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1449                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1450                 } else {
1451                         /* disable the encoder and transmitter */
1452                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1453                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1454                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1455                 }
1456                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1457                         if (ASIC_IS_DCE4(rdev))
1458                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1459                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1460                                 atombios_set_edp_panel_power(connector,
1461                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1462                                 radeon_dig_connector->edp_on = false;
1463                         }
1464                 }
1465                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1466                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1467                 break;
1468         }
1469 }
1470
1471 static void
1472 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1473                              struct drm_encoder *ext_encoder,
1474                              int mode)
1475 {
1476         struct drm_device *dev = encoder->dev;
1477         struct radeon_device *rdev = dev->dev_private;
1478
1479         switch (mode) {
1480         case DRM_MODE_DPMS_ON:
1481         default:
1482                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1483                         atombios_external_encoder_setup(encoder, ext_encoder,
1484                                                         EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1485                         atombios_external_encoder_setup(encoder, ext_encoder,
1486                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1487                 } else
1488                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1489                 break;
1490         case DRM_MODE_DPMS_STANDBY:
1491         case DRM_MODE_DPMS_SUSPEND:
1492         case DRM_MODE_DPMS_OFF:
1493                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1494                         atombios_external_encoder_setup(encoder, ext_encoder,
1495                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1496                         atombios_external_encoder_setup(encoder, ext_encoder,
1497                                                         EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1498                 } else
1499                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1500                 break;
1501         }
1502 }
1503
1504 static void
1505 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1506 {
1507         struct drm_device *dev = encoder->dev;
1508         struct radeon_device *rdev = dev->dev_private;
1509         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1510         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1511
1512         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1513                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1514                   radeon_encoder->active_device);
1515         switch (radeon_encoder->encoder_id) {
1516         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1517         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1518         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1519         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1520         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1521         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1522         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1523         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1524                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1525                 break;
1526         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1527         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1528         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1529         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1530                 radeon_atom_encoder_dpms_dig(encoder, mode);
1531                 break;
1532         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1533                 if (ASIC_IS_DCE5(rdev)) {
1534                         switch (mode) {
1535                         case DRM_MODE_DPMS_ON:
1536                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1537                                 break;
1538                         case DRM_MODE_DPMS_STANDBY:
1539                         case DRM_MODE_DPMS_SUSPEND:
1540                         case DRM_MODE_DPMS_OFF:
1541                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1542                                 break;
1543                         }
1544                 } else if (ASIC_IS_DCE3(rdev))
1545                         radeon_atom_encoder_dpms_dig(encoder, mode);
1546                 else
1547                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1548                 break;
1549         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1550         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1551                 if (ASIC_IS_DCE5(rdev)) {
1552                         switch (mode) {
1553                         case DRM_MODE_DPMS_ON:
1554                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1555                                 break;
1556                         case DRM_MODE_DPMS_STANDBY:
1557                         case DRM_MODE_DPMS_SUSPEND:
1558                         case DRM_MODE_DPMS_OFF:
1559                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1560                                 break;
1561                         }
1562                 } else
1563                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1564                 break;
1565         default:
1566                 return;
1567         }
1568
1569         if (ext_encoder)
1570                 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1571
1572         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1573
1574 }
1575
1576 union crtc_source_param {
1577         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1578         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1579 };
1580
1581 static void
1582 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1583 {
1584         struct drm_device *dev = encoder->dev;
1585         struct radeon_device *rdev = dev->dev_private;
1586         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1587         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1588         union crtc_source_param args;
1589         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1590         uint8_t frev, crev;
1591         struct radeon_encoder_atom_dig *dig;
1592
1593         memset(&args, 0, sizeof(args));
1594
1595         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1596                 return;
1597
1598         switch (frev) {
1599         case 1:
1600                 switch (crev) {
1601                 case 1:
1602                 default:
1603                         if (ASIC_IS_AVIVO(rdev))
1604                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1605                         else {
1606                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1607                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1608                                 } else {
1609                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1610                                 }
1611                         }
1612                         switch (radeon_encoder->encoder_id) {
1613                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1614                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1615                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1616                                 break;
1617                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1618                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1619                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1620                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1621                                 else
1622                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1623                                 break;
1624                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1625                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1626                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1627                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1628                                 break;
1629                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1630                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1631                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1632                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1633                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1634                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1635                                 else
1636                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1637                                 break;
1638                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1639                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1640                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1641                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1642                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1643                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1644                                 else
1645                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1646                                 break;
1647                         }
1648                         break;
1649                 case 2:
1650                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1651                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1652                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1653
1654                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1655                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1656                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1657                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1658                                 else
1659                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1660                         } else
1661                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1662                         switch (radeon_encoder->encoder_id) {
1663                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1664                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1665                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1666                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1667                                 dig = radeon_encoder->enc_priv;
1668                                 switch (dig->dig_encoder) {
1669                                 case 0:
1670                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1671                                         break;
1672                                 case 1:
1673                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1674                                         break;
1675                                 case 2:
1676                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1677                                         break;
1678                                 case 3:
1679                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1680                                         break;
1681                                 case 4:
1682                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1683                                         break;
1684                                 case 5:
1685                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1686                                         break;
1687                                 }
1688                                 break;
1689                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1690                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1691                                 break;
1692                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1693                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1694                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1695                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1696                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1697                                 else
1698                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1699                                 break;
1700                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1701                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1702                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1703                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1704                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1705                                 else
1706                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1707                                 break;
1708                         }
1709                         break;
1710                 }
1711                 break;
1712         default:
1713                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1714                 return;
1715         }
1716
1717         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1718
1719         /* update scratch regs with new routing */
1720         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1721 }
1722
1723 static void
1724 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1725                               struct drm_display_mode *mode)
1726 {
1727         struct drm_device *dev = encoder->dev;
1728         struct radeon_device *rdev = dev->dev_private;
1729         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1730         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1731
1732         /* Funky macbooks */
1733         if ((dev->pdev->device == 0x71C5) &&
1734             (dev->pdev->subsystem_vendor == 0x106b) &&
1735             (dev->pdev->subsystem_device == 0x0080)) {
1736                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1737                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1738
1739                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1740                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1741
1742                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1743                 }
1744         }
1745
1746         /* set scaler clears this on some chips */
1747         if (ASIC_IS_AVIVO(rdev) &&
1748             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1749                 if (ASIC_IS_DCE4(rdev)) {
1750                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1751                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1752                                        EVERGREEN_INTERLEAVE_EN);
1753                         else
1754                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1755                 } else {
1756                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1757                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1758                                        AVIVO_D1MODE_INTERLEAVE_EN);
1759                         else
1760                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1761                 }
1762         }
1763 }
1764
1765 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1766 {
1767         struct drm_device *dev = encoder->dev;
1768         struct radeon_device *rdev = dev->dev_private;
1769         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1770         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1771         struct drm_encoder *test_encoder;
1772         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1773         uint32_t dig_enc_in_use = 0;
1774
1775         if (ASIC_IS_DCE6(rdev)) {
1776                 /* DCE6 */
1777                 switch (radeon_encoder->encoder_id) {
1778                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1779                         if (dig->linkb)
1780                                 return 1;
1781                         else
1782                                 return 0;
1783                         break;
1784                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1785                         if (dig->linkb)
1786                                 return 3;
1787                         else
1788                                 return 2;
1789                         break;
1790                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1791                         if (dig->linkb)
1792                                 return 5;
1793                         else
1794                                 return 4;
1795                         break;
1796                 }
1797         } else if (ASIC_IS_DCE4(rdev)) {
1798                 /* DCE4/5 */
1799                 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
1800                         /* ontario follows DCE4 */
1801                         if (rdev->family == CHIP_PALM) {
1802                                 if (dig->linkb)
1803                                         return 1;
1804                                 else
1805                                         return 0;
1806                         } else
1807                                 /* llano follows DCE3.2 */
1808                                 return radeon_crtc->crtc_id;
1809                 } else {
1810                         switch (radeon_encoder->encoder_id) {
1811                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1812                                 if (dig->linkb)
1813                                         return 1;
1814                                 else
1815                                         return 0;
1816                                 break;
1817                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1818                                 if (dig->linkb)
1819                                         return 3;
1820                                 else
1821                                         return 2;
1822                                 break;
1823                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1824                                 if (dig->linkb)
1825                                         return 5;
1826                                 else
1827                                         return 4;
1828                                 break;
1829                         }
1830                 }
1831         }
1832
1833         /* on DCE32 and encoder can driver any block so just crtc id */
1834         if (ASIC_IS_DCE32(rdev)) {
1835                 return radeon_crtc->crtc_id;
1836         }
1837
1838         /* on DCE3 - LVTMA can only be driven by DIGB */
1839         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1840                 struct radeon_encoder *radeon_test_encoder;
1841
1842                 if (encoder == test_encoder)
1843                         continue;
1844
1845                 if (!radeon_encoder_is_digital(test_encoder))
1846                         continue;
1847
1848                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1849                 dig = radeon_test_encoder->enc_priv;
1850
1851                 if (dig->dig_encoder >= 0)
1852                         dig_enc_in_use |= (1 << dig->dig_encoder);
1853         }
1854
1855         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1856                 if (dig_enc_in_use & 0x2)
1857                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1858                 return 1;
1859         }
1860         if (!(dig_enc_in_use & 1))
1861                 return 0;
1862         return 1;
1863 }
1864
1865 /* This only needs to be called once at startup */
1866 void
1867 radeon_atom_encoder_init(struct radeon_device *rdev)
1868 {
1869         struct drm_device *dev = rdev->ddev;
1870         struct drm_encoder *encoder;
1871
1872         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1873                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1874                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1875
1876                 switch (radeon_encoder->encoder_id) {
1877                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1878                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1879                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1880                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1881                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1882                         break;
1883                 default:
1884                         break;
1885                 }
1886
1887                 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
1888                         atombios_external_encoder_setup(encoder, ext_encoder,
1889                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1890         }
1891 }
1892
1893 static void
1894 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1895                              struct drm_display_mode *mode,
1896                              struct drm_display_mode *adjusted_mode)
1897 {
1898         struct drm_device *dev = encoder->dev;
1899         struct radeon_device *rdev = dev->dev_private;
1900         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1901
1902         radeon_encoder->pixel_clock = adjusted_mode->clock;
1903
1904         /* need to call this here rather than in prepare() since we need some crtc info */
1905         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1906
1907         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1908                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1909                         atombios_yuv_setup(encoder, true);
1910                 else
1911                         atombios_yuv_setup(encoder, false);
1912         }
1913
1914         switch (radeon_encoder->encoder_id) {
1915         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1916         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1917         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1918         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1919                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1920                 break;
1921         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1922         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1923         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1924         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1925                 /* handled in dpms */
1926                 break;
1927         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1928         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1929         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1930                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1931                 break;
1932         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1933         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1934         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1935         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1936                 atombios_dac_setup(encoder, ATOM_ENABLE);
1937                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1938                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1939                                 atombios_tv_setup(encoder, ATOM_ENABLE);
1940                         else
1941                                 atombios_tv_setup(encoder, ATOM_DISABLE);
1942                 }
1943                 break;
1944         }
1945
1946         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1947
1948         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1949                 r600_hdmi_enable(encoder);
1950                 if (ASIC_IS_DCE6(rdev))
1951                         ; /* TODO (use pointers instead of if-s?) */
1952                 else if (ASIC_IS_DCE4(rdev))
1953                         evergreen_hdmi_setmode(encoder, adjusted_mode);
1954                 else
1955                         r600_hdmi_setmode(encoder, adjusted_mode);
1956         }
1957 }
1958
1959 static bool
1960 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1961 {
1962         struct drm_device *dev = encoder->dev;
1963         struct radeon_device *rdev = dev->dev_private;
1964         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1965         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1966
1967         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1968                                        ATOM_DEVICE_CV_SUPPORT |
1969                                        ATOM_DEVICE_CRT_SUPPORT)) {
1970                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1971                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1972                 uint8_t frev, crev;
1973
1974                 memset(&args, 0, sizeof(args));
1975
1976                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1977                         return false;
1978
1979                 args.sDacload.ucMisc = 0;
1980
1981                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1982                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1983                         args.sDacload.ucDacType = ATOM_DAC_A;
1984                 else
1985                         args.sDacload.ucDacType = ATOM_DAC_B;
1986
1987                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1988                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1989                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1990                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1991                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1992                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1993                         if (crev >= 3)
1994                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1995                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1996                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1997                         if (crev >= 3)
1998                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1999                 }
2000
2001                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2002
2003                 return true;
2004         } else
2005                 return false;
2006 }
2007
2008 static enum drm_connector_status
2009 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2010 {
2011         struct drm_device *dev = encoder->dev;
2012         struct radeon_device *rdev = dev->dev_private;
2013         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2014         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2015         uint32_t bios_0_scratch;
2016
2017         if (!atombios_dac_load_detect(encoder, connector)) {
2018                 DRM_DEBUG_KMS("detect returned false \n");
2019                 return connector_status_unknown;
2020         }
2021
2022         if (rdev->family >= CHIP_R600)
2023                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2024         else
2025                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2026
2027         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2028         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2029                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2030                         return connector_status_connected;
2031         }
2032         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2033                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2034                         return connector_status_connected;
2035         }
2036         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2037                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2038                         return connector_status_connected;
2039         }
2040         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2041                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2042                         return connector_status_connected; /* CTV */
2043                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2044                         return connector_status_connected; /* STV */
2045         }
2046         return connector_status_disconnected;
2047 }
2048
2049 static enum drm_connector_status
2050 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2051 {
2052         struct drm_device *dev = encoder->dev;
2053         struct radeon_device *rdev = dev->dev_private;
2054         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2055         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2056         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2057         u32 bios_0_scratch;
2058
2059         if (!ASIC_IS_DCE4(rdev))
2060                 return connector_status_unknown;
2061
2062         if (!ext_encoder)
2063                 return connector_status_unknown;
2064
2065         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2066                 return connector_status_unknown;
2067
2068         /* load detect on the dp bridge */
2069         atombios_external_encoder_setup(encoder, ext_encoder,
2070                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2071
2072         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2073
2074         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2075         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2076                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2077                         return connector_status_connected;
2078         }
2079         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2080                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2081                         return connector_status_connected;
2082         }
2083         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2084                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2085                         return connector_status_connected;
2086         }
2087         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2088                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2089                         return connector_status_connected; /* CTV */
2090                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2091                         return connector_status_connected; /* STV */
2092         }
2093         return connector_status_disconnected;
2094 }
2095
2096 void
2097 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2098 {
2099         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2100
2101         if (ext_encoder)
2102                 /* ddc_setup on the dp bridge */
2103                 atombios_external_encoder_setup(encoder, ext_encoder,
2104                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2105
2106 }
2107
2108 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2109 {
2110         struct radeon_device *rdev = encoder->dev->dev_private;
2111         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2112         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2113
2114         if ((radeon_encoder->active_device &
2115              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2116             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2117              ENCODER_OBJECT_ID_NONE)) {
2118                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2119                 if (dig) {
2120                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2121                         if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2122                                 if (rdev->family >= CHIP_R600)
2123                                         dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2124                                 else
2125                                         /* RS600/690/740 have only 1 afmt block */
2126                                         dig->afmt = rdev->mode_info.afmt[0];
2127                         }
2128                 }
2129         }
2130
2131         radeon_atom_output_lock(encoder, true);
2132
2133         if (connector) {
2134                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2135
2136                 /* select the clock/data port if it uses a router */
2137                 if (radeon_connector->router.cd_valid)
2138                         radeon_router_select_cd_port(radeon_connector);
2139
2140                 /* turn eDP panel on for mode set */
2141                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2142                         atombios_set_edp_panel_power(connector,
2143                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2144         }
2145
2146         /* this is needed for the pll/ss setup to work correctly in some cases */
2147         atombios_set_encoder_crtc_source(encoder);
2148 }
2149
2150 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2151 {
2152         /* need to call this here as we need the crtc set up */
2153         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2154         radeon_atom_output_lock(encoder, false);
2155 }
2156
2157 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2158 {
2159         struct drm_device *dev = encoder->dev;
2160         struct radeon_device *rdev = dev->dev_private;
2161         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2162         struct radeon_encoder_atom_dig *dig;
2163
2164         /* check for pre-DCE3 cards with shared encoders;
2165          * can't really use the links individually, so don't disable
2166          * the encoder if it's in use by another connector
2167          */
2168         if (!ASIC_IS_DCE3(rdev)) {
2169                 struct drm_encoder *other_encoder;
2170                 struct radeon_encoder *other_radeon_encoder;
2171
2172                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2173                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2174                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2175                             drm_helper_encoder_in_use(other_encoder))
2176                                 goto disable_done;
2177                 }
2178         }
2179
2180         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2181
2182         switch (radeon_encoder->encoder_id) {
2183         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2184         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2185         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2186         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2187                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2188                 break;
2189         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2190         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2191         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2192         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2193                 /* handled in dpms */
2194                 break;
2195         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2196         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2197         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2198                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2199                 break;
2200         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2201         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2202         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2203         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2204                 atombios_dac_setup(encoder, ATOM_DISABLE);
2205                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2206                         atombios_tv_setup(encoder, ATOM_DISABLE);
2207                 break;
2208         }
2209
2210 disable_done:
2211         if (radeon_encoder_is_digital(encoder)) {
2212                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2213                         r600_hdmi_disable(encoder);
2214                 dig = radeon_encoder->enc_priv;
2215                 dig->dig_encoder = -1;
2216         }
2217         radeon_encoder->active_device = 0;
2218 }
2219
2220 /* these are handled by the primary encoders */
2221 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2222 {
2223
2224 }
2225
2226 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2227 {
2228
2229 }
2230
2231 static void
2232 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2233                          struct drm_display_mode *mode,
2234                          struct drm_display_mode *adjusted_mode)
2235 {
2236
2237 }
2238
2239 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2240 {
2241
2242 }
2243
2244 static void
2245 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2246 {
2247
2248 }
2249
2250 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2251                                        const struct drm_display_mode *mode,
2252                                        struct drm_display_mode *adjusted_mode)
2253 {
2254         return true;
2255 }
2256
2257 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2258         .dpms = radeon_atom_ext_dpms,
2259         .mode_fixup = radeon_atom_ext_mode_fixup,
2260         .prepare = radeon_atom_ext_prepare,
2261         .mode_set = radeon_atom_ext_mode_set,
2262         .commit = radeon_atom_ext_commit,
2263         .disable = radeon_atom_ext_disable,
2264         /* no detect for TMDS/LVDS yet */
2265 };
2266
2267 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2268         .dpms = radeon_atom_encoder_dpms,
2269         .mode_fixup = radeon_atom_mode_fixup,
2270         .prepare = radeon_atom_encoder_prepare,
2271         .mode_set = radeon_atom_encoder_mode_set,
2272         .commit = radeon_atom_encoder_commit,
2273         .disable = radeon_atom_encoder_disable,
2274         .detect = radeon_atom_dig_detect,
2275 };
2276
2277 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2278         .dpms = radeon_atom_encoder_dpms,
2279         .mode_fixup = radeon_atom_mode_fixup,
2280         .prepare = radeon_atom_encoder_prepare,
2281         .mode_set = radeon_atom_encoder_mode_set,
2282         .commit = radeon_atom_encoder_commit,
2283         .detect = radeon_atom_dac_detect,
2284 };
2285
2286 void radeon_enc_destroy(struct drm_encoder *encoder)
2287 {
2288         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2289         kfree(radeon_encoder->enc_priv);
2290         drm_encoder_cleanup(encoder);
2291         kfree(radeon_encoder);
2292 }
2293
2294 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2295         .destroy = radeon_enc_destroy,
2296 };
2297
2298 struct radeon_encoder_atom_dac *
2299 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2300 {
2301         struct drm_device *dev = radeon_encoder->base.dev;
2302         struct radeon_device *rdev = dev->dev_private;
2303         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2304
2305         if (!dac)
2306                 return NULL;
2307
2308         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2309         return dac;
2310 }
2311
2312 struct radeon_encoder_atom_dig *
2313 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2314 {
2315         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2316         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2317
2318         if (!dig)
2319                 return NULL;
2320
2321         /* coherent mode by default */
2322         dig->coherent_mode = true;
2323         dig->dig_encoder = -1;
2324
2325         if (encoder_enum == 2)
2326                 dig->linkb = true;
2327         else
2328                 dig->linkb = false;
2329
2330         return dig;
2331 }
2332
2333 void
2334 radeon_add_atom_encoder(struct drm_device *dev,
2335                         uint32_t encoder_enum,
2336                         uint32_t supported_device,
2337                         u16 caps)
2338 {
2339         struct radeon_device *rdev = dev->dev_private;
2340         struct drm_encoder *encoder;
2341         struct radeon_encoder *radeon_encoder;
2342
2343         /* see if we already added it */
2344         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2345                 radeon_encoder = to_radeon_encoder(encoder);
2346                 if (radeon_encoder->encoder_enum == encoder_enum) {
2347                         radeon_encoder->devices |= supported_device;
2348                         return;
2349                 }
2350
2351         }
2352
2353         /* add a new one */
2354         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2355         if (!radeon_encoder)
2356                 return;
2357
2358         encoder = &radeon_encoder->base;
2359         switch (rdev->num_crtc) {
2360         case 1:
2361                 encoder->possible_crtcs = 0x1;
2362                 break;
2363         case 2:
2364         default:
2365                 encoder->possible_crtcs = 0x3;
2366                 break;
2367         case 4:
2368                 encoder->possible_crtcs = 0xf;
2369                 break;
2370         case 6:
2371                 encoder->possible_crtcs = 0x3f;
2372                 break;
2373         }
2374
2375         radeon_encoder->enc_priv = NULL;
2376
2377         radeon_encoder->encoder_enum = encoder_enum;
2378         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2379         radeon_encoder->devices = supported_device;
2380         radeon_encoder->rmx_type = RMX_OFF;
2381         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2382         radeon_encoder->is_ext_encoder = false;
2383         radeon_encoder->caps = caps;
2384
2385         switch (radeon_encoder->encoder_id) {
2386         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2387         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2388         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2389         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2390                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2391                         radeon_encoder->rmx_type = RMX_FULL;
2392                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2393                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2394                 } else {
2395                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2396                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2397                 }
2398                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2399                 break;
2400         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2401                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2402                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2403                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2404                 break;
2405         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2406         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2407         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2408                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2409                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2410                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2411                 break;
2412         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2413         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2414         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2415         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2416         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2417         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2418         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2419                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2420                         radeon_encoder->rmx_type = RMX_FULL;
2421                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2422                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2423                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2424                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2425                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2426                 } else {
2427                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2428                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2429                 }
2430                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2431                 break;
2432         case ENCODER_OBJECT_ID_SI170B:
2433         case ENCODER_OBJECT_ID_CH7303:
2434         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2435         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2436         case ENCODER_OBJECT_ID_TITFP513:
2437         case ENCODER_OBJECT_ID_VT1623:
2438         case ENCODER_OBJECT_ID_HDMI_SI1930:
2439         case ENCODER_OBJECT_ID_TRAVIS:
2440         case ENCODER_OBJECT_ID_NUTMEG:
2441                 /* these are handled by the primary encoders */
2442                 radeon_encoder->is_ext_encoder = true;
2443                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2444                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2445                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2446                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2447                 else
2448                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2449                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2450                 break;
2451         }
2452 }