drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "radeon_drm.h"
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "r100d.h"
  37 #include "rs100d.h"
  38 #include "rv200d.h"
  39 #include "rv250d.h"
  40 #include "atom.h"
  41
  42 #include <linux/firmware.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/module.h>
  45
  46 #include "r100_reg_safe.h"
  47 #include "rn50_reg_safe.h"
  48
  49 /* Firmware Names */
  50 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  51 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  52 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  53 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  54 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  55 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  56 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  57
  58 MODULE_FIRMWARE(FIRMWARE_R100);
  59 MODULE_FIRMWARE(FIRMWARE_R200);
  60 MODULE_FIRMWARE(FIRMWARE_R300);
  61 MODULE_FIRMWARE(FIRMWARE_R420);
  62 MODULE_FIRMWARE(FIRMWARE_RS690);
  63 MODULE_FIRMWARE(FIRMWARE_RS600);
  64 MODULE_FIRMWARE(FIRMWARE_R520);
  65
  66 #include "r100_track.h"
  67
  68 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
  69 {
  70         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
  71         int i;
  72
  73         if (radeon_crtc->crtc_id == 0) {
  74                 if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) {
  75                         for (i = 0; i < rdev->usec_timeout; i++) {
  76                                 if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
  77                                         break;
  78                                 udelay(1);
  79                         }
  80                         for (i = 0; i < rdev->usec_timeout; i++) {
  81                                 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
  82                                         break;
  83                                 udelay(1);
  84                         }
  85                 }
  86         } else {
  87                 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) {
  88                         for (i = 0; i < rdev->usec_timeout; i++) {
  89                                 if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR))
  90                                         break;
  91                                 udelay(1);
  92                         }
  93                         for (i = 0; i < rdev->usec_timeout; i++) {
  94                                 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
  95                                         break;
  96                                 udelay(1);
  97                         }
  98                 }
  99         }
 100 }
 101
 102 /* This files gather functions specifics to:
 103  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
 104  */
 105
 106 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
 107 {
 108         /* enable the pflip int */
 109         radeon_irq_kms_pflip_irq_get(rdev, crtc);
 110 }
 111
 112 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
 113 {
 114         /* disable the pflip int */
 115         radeon_irq_kms_pflip_irq_put(rdev, crtc);
 116 }
 117
 118 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 119 {
 120         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 121         u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
 122         int i;
 123
 124         /* Lock the graphics update lock */
 125         /* update the scanout addresses */
 126         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 127
 128         /* Wait for update_pending to go high. */
 129         for (i = 0; i < rdev->usec_timeout; i++) {
 130                 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
 131                         break;
 132                 udelay(1);
 133         }
 134         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 135
 136         /* Unlock the lock, so double-buffering can take place inside vblank */
 137         tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
 138         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 139
 140         /* Return current update_pending status: */
 141         return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
 142 }
 143
 144 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
 145 {
 146         int i;
 147         rdev->pm.dynpm_can_upclock = true;
 148         rdev->pm.dynpm_can_downclock = true;
 149
 150         switch (rdev->pm.dynpm_planned_action) {
 151         case DYNPM_ACTION_MINIMUM:
 152                 rdev->pm.requested_power_state_index = 0;
 153                 rdev->pm.dynpm_can_downclock = false;
 154                 break;
 155         case DYNPM_ACTION_DOWNCLOCK:
 156                 if (rdev->pm.current_power_state_index == 0) {
 157                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 158                         rdev->pm.dynpm_can_downclock = false;
 159                 } else {
 160                         if (rdev->pm.active_crtc_count > 1) {
 161                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
 162                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 163                                                 continue;
 164                                         else if (i >= rdev->pm.current_power_state_index) {
 165                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 166                                                 break;
 167                                         } else {
 168                                                 rdev->pm.requested_power_state_index = i;
 169                                                 break;
 170                                         }
 171                                 }
 172                         } else
 173                                 rdev->pm.requested_power_state_index =
 174                                         rdev->pm.current_power_state_index - 1;
 175                 }
 176                 /* don't use the power state if crtcs are active and no display flag is set */
 177                 if ((rdev->pm.active_crtc_count > 0) &&
 178                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
 179                      RADEON_PM_MODE_NO_DISPLAY)) {
 180                         rdev->pm.requested_power_state_index++;
 181                 }
 182                 break;
 183         case DYNPM_ACTION_UPCLOCK:
 184                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 185                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 186                         rdev->pm.dynpm_can_upclock = false;
 187                 } else {
 188                         if (rdev->pm.active_crtc_count > 1) {
 189                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 190                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 191                                                 continue;
 192                                         else if (i <= rdev->pm.current_power_state_index) {
 193                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 194                                                 break;
 195                                         } else {
 196                                                 rdev->pm.requested_power_state_index = i;
 197                                                 break;
 198                                         }
 199                                 }
 200                         } else
 201                                 rdev->pm.requested_power_state_index =
 202                                         rdev->pm.current_power_state_index + 1;
 203                 }
 204                 break;
 205         case DYNPM_ACTION_DEFAULT:
 206                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 207                 rdev->pm.dynpm_can_upclock = false;
 208                 break;
 209         case DYNPM_ACTION_NONE:
 210         default:
 211                 DRM_ERROR("Requested mode for not defined action\n");
 212                 return;
 213         }
 214         /* only one clock mode per power state */
 215         rdev->pm.requested_clock_mode_index = 0;
 216
 217         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 218                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 219                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 220                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 221                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 222                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 223                   pcie_lanes);
 224 }
 225
 226 void r100_pm_init_profile(struct radeon_device *rdev)
 227 {
 228         /* default */
 229         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 230         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 231         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 232         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 233         /* low sh */
 234         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 235         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 236         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 237         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 238         /* mid sh */
 239         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 240         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 241         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 242         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 243         /* high sh */
 244         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 245         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 246         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 247         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 248         /* low mh */
 249         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 250         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 251         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 252         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 253         /* mid mh */
 254         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 255         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 256         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 257         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 258         /* high mh */
 259         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 260         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 261         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 262         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 263 }
 264
 265 void r100_pm_misc(struct radeon_device *rdev)
 266 {
 267         int requested_index = rdev->pm.requested_power_state_index;
 268         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 269         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 270         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 271
 272         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 273                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 274                         tmp = RREG32(voltage->gpio.reg);
 275                         if (voltage->active_high)
 276                                 tmp |= voltage->gpio.mask;
 277                         else
 278                                 tmp &= ~(voltage->gpio.mask);
 279                         WREG32(voltage->gpio.reg, tmp);
 280                         if (voltage->delay)
 281                                 udelay(voltage->delay);
 282                 } else {
 283                         tmp = RREG32(voltage->gpio.reg);
 284                         if (voltage->active_high)
 285                                 tmp &= ~voltage->gpio.mask;
 286                         else
 287                                 tmp |= voltage->gpio.mask;
 288                         WREG32(voltage->gpio.reg, tmp);
 289                         if (voltage->delay)
 290                                 udelay(voltage->delay);
 291                 }
 292         }
 293
 294         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 295         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 296         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 297         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 298         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 299         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 300                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 301                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 302                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 303                 else
 304                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 305                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 306                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 307                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 308                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 309         } else
 310                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 311
 312         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 313                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 314                 if (voltage->delay) {
 315                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 316                         switch (voltage->delay) {
 317                         case 33:
 318                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 319                                 break;
 320                         case 66:
 321                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 322                                 break;
 323                         case 99:
 324                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 325                                 break;
 326                         case 132:
 327                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 328                                 break;
 329                         }
 330                 } else
 331                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 332         } else
 333                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 334
 335         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 336                 sclk_cntl &= ~FORCE_HDP;
 337         else
 338                 sclk_cntl |= FORCE_HDP;
 339
 340         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 341         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 342         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 343
 344         /* set pcie lanes */
 345         if ((rdev->flags & RADEON_IS_PCIE) &&
 346             !(rdev->flags & RADEON_IS_IGP) &&
 347             rdev->asic->pm.set_pcie_lanes &&
 348             (ps->pcie_lanes !=
 349              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 350                 radeon_set_pcie_lanes(rdev,
 351                                       ps->pcie_lanes);
 352                 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
 353         }
 354 }
 355
 356 void r100_pm_prepare(struct radeon_device *rdev)
 357 {
 358         struct drm_device *ddev = rdev->ddev;
 359         struct drm_crtc *crtc;
 360         struct radeon_crtc *radeon_crtc;
 361         u32 tmp;
 362
 363         /* disable any active CRTCs */
 364         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 365                 radeon_crtc = to_radeon_crtc(crtc);
 366                 if (radeon_crtc->enabled) {
 367                         if (radeon_crtc->crtc_id) {
 368                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 369                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 370                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 371                         } else {
 372                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 373                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 374                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 375                         }
 376                 }
 377         }
 378 }
 379
 380 void r100_pm_finish(struct radeon_device *rdev)
 381 {
 382         struct drm_device *ddev = rdev->ddev;
 383         struct drm_crtc *crtc;
 384         struct radeon_crtc *radeon_crtc;
 385         u32 tmp;
 386
 387         /* enable any active CRTCs */
 388         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 389                 radeon_crtc = to_radeon_crtc(crtc);
 390                 if (radeon_crtc->enabled) {
 391                         if (radeon_crtc->crtc_id) {
 392                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 393                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 394                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 395                         } else {
 396                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 397                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 398                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 399                         }
 400                 }
 401         }
 402 }
 403
 404 bool r100_gui_idle(struct radeon_device *rdev)
 405 {
 406         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 407                 return false;
 408         else
 409                 return true;
 410 }
 411
 412 /* hpd for digital panel detect/disconnect */
 413 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 414 {
 415         bool connected = false;
 416
 417         switch (hpd) {
 418         case RADEON_HPD_1:
 419                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 420                         connected = true;
 421                 break;
 422         case RADEON_HPD_2:
 423                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 424                         connected = true;
 425                 break;
 426         default:
 427                 break;
 428         }
 429         return connected;
 430 }
 431
 432 void r100_hpd_set_polarity(struct radeon_device *rdev,
 433                            enum radeon_hpd_id hpd)
 434 {
 435         u32 tmp;
 436         bool connected = r100_hpd_sense(rdev, hpd);
 437
 438         switch (hpd) {
 439         case RADEON_HPD_1:
 440                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 441                 if (connected)
 442                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 443                 else
 444                         tmp |= RADEON_FP_DETECT_INT_POL;
 445                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 446                 break;
 447         case RADEON_HPD_2:
 448                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 449                 if (connected)
 450                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 451                 else
 452                         tmp |= RADEON_FP2_DETECT_INT_POL;
 453                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 454                 break;
 455         default:
 456                 break;
 457         }
 458 }
 459
 460 void r100_hpd_init(struct radeon_device *rdev)
 461 {
 462         struct drm_device *dev = rdev->ddev;
 463         struct drm_connector *connector;
 464         unsigned enable = 0;
 465
 466         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 467                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 468                 enable |= 1 << radeon_connector->hpd.hpd;
 469                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 470         }
 471         radeon_irq_kms_enable_hpd(rdev, enable);
 472 }
 473
 474 void r100_hpd_fini(struct radeon_device *rdev)
 475 {
 476         struct drm_device *dev = rdev->ddev;
 477         struct drm_connector *connector;
 478         unsigned disable = 0;
 479
 480         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 481                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 482                 disable |= 1 << radeon_connector->hpd.hpd;
 483         }
 484         radeon_irq_kms_disable_hpd(rdev, disable);
 485 }
 486
 487 /*
 488  * PCI GART
 489  */
 490 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 491 {
 492         /* TODO: can we do somethings here ? */
 493         /* It seems hw only cache one entry so we should discard this
 494          * entry otherwise if first GPU GART read hit this entry it
 495          * could end up in wrong address. */
 496 }
 497
 498 int r100_pci_gart_init(struct radeon_device *rdev)
 499 {
 500         int r;
 501
 502         if (rdev->gart.ptr) {
 503                 WARN(1, "R100 PCI GART already initialized\n");
 504                 return 0;
 505         }
 506         /* Initialize common gart structure */
 507         r = radeon_gart_init(rdev);
 508         if (r)
 509                 return r;
 510         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 511         rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 512         rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 513         return radeon_gart_table_ram_alloc(rdev);
 514 }
 515
 516 int r100_pci_gart_enable(struct radeon_device *rdev)
 517 {
 518         uint32_t tmp;
 519
 520         radeon_gart_restore(rdev);
 521         /* discard memory request outside of configured range */
 522         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 523         WREG32(RADEON_AIC_CNTL, tmp);
 524         /* set address range for PCI address translate */
 525         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 526         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 527         /* set PCI GART page-table base address */
 528         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 529         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 530         WREG32(RADEON_AIC_CNTL, tmp);
 531         r100_pci_gart_tlb_flush(rdev);
 532         DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
 533                  (unsigned)(rdev->mc.gtt_size >> 20),
 534                  (unsigned long long)rdev->gart.table_addr);
 535         rdev->gart.ready = true;
 536         return 0;
 537 }
 538
 539 void r100_pci_gart_disable(struct radeon_device *rdev)
 540 {
 541         uint32_t tmp;
 542
 543         /* discard memory request outside of configured range */
 544         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 545         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 546         WREG32(RADEON_AIC_LO_ADDR, 0);
 547         WREG32(RADEON_AIC_HI_ADDR, 0);
 548 }
 549
 550 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 551 {
 552         u32 *gtt = rdev->gart.ptr;
 553
 554         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 555                 return -EINVAL;
 556         }
 557         gtt[i] = cpu_to_le32(lower_32_bits(addr));
 558         return 0;
 559 }
 560
 561 void r100_pci_gart_fini(struct radeon_device *rdev)
 562 {
 563         radeon_gart_fini(rdev);
 564         r100_pci_gart_disable(rdev);
 565         radeon_gart_table_ram_free(rdev);
 566 }
 567
 568 int r100_irq_set(struct radeon_device *rdev)
 569 {
 570         uint32_t tmp = 0;
 571
 572         if (!rdev->irq.installed) {
 573                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 574                 WREG32(R_000040_GEN_INT_CNTL, 0);
 575                 return -EINVAL;
 576         }
 577         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
 578                 tmp |= RADEON_SW_INT_ENABLE;
 579         }
 580         if (rdev->irq.gui_idle) {
 581                 tmp |= RADEON_GUI_IDLE_MASK;
 582         }
 583         if (rdev->irq.crtc_vblank_int[0] ||
 584             atomic_read(&rdev->irq.pflip[0])) {
 585                 tmp |= RADEON_CRTC_VBLANK_MASK;
 586         }
 587         if (rdev->irq.crtc_vblank_int[1] ||
 588             atomic_read(&rdev->irq.pflip[1])) {
 589                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 590         }
 591         if (rdev->irq.hpd[0]) {
 592                 tmp |= RADEON_FP_DETECT_MASK;
 593         }
 594         if (rdev->irq.hpd[1]) {
 595                 tmp |= RADEON_FP2_DETECT_MASK;
 596         }
 597         WREG32(RADEON_GEN_INT_CNTL, tmp);
 598         return 0;
 599 }
 600
 601 void r100_irq_disable(struct radeon_device *rdev)
 602 {
 603         u32 tmp;
 604
 605         WREG32(R_000040_GEN_INT_CNTL, 0);
 606         /* Wait and acknowledge irq */
 607         mdelay(1);
 608         tmp = RREG32(R_000044_GEN_INT_STATUS);
 609         WREG32(R_000044_GEN_INT_STATUS, tmp);
 610 }
 611
 612 static uint32_t r100_irq_ack(struct radeon_device *rdev)
 613 {
 614         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 615         uint32_t irq_mask = RADEON_SW_INT_TEST |
 616                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 617                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 618
 619         /* the interrupt works, but the status bit is permanently asserted */
 620         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
 621                 if (!rdev->irq.gui_idle_acked)
 622                         irq_mask |= RADEON_GUI_IDLE_STAT;
 623         }
 624
 625         if (irqs) {
 626                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 627         }
 628         return irqs & irq_mask;
 629 }
 630
 631 int r100_irq_process(struct radeon_device *rdev)
 632 {
 633         uint32_t status, msi_rearm;
 634         bool queue_hotplug = false;
 635
 636         /* reset gui idle ack.  the status bit is broken */
 637         rdev->irq.gui_idle_acked = false;
 638
 639         status = r100_irq_ack(rdev);
 640         if (!status) {
 641                 return IRQ_NONE;
 642         }
 643         if (rdev->shutdown) {
 644                 return IRQ_NONE;
 645         }
 646         while (status) {
 647                 /* SW interrupt */
 648                 if (status & RADEON_SW_INT_TEST) {
 649                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
 650                 }
 651                 /* gui idle interrupt */
 652                 if (status & RADEON_GUI_IDLE_STAT) {
 653                         rdev->irq.gui_idle_acked = true;
 654                         wake_up(&rdev->irq.idle_queue);
 655                 }
 656                 /* Vertical blank interrupts */
 657                 if (status & RADEON_CRTC_VBLANK_STAT) {
 658                         if (rdev->irq.crtc_vblank_int[0]) {
 659                                 drm_handle_vblank(rdev->ddev, 0);
 660                                 rdev->pm.vblank_sync = true;
 661                                 wake_up(&rdev->irq.vblank_queue);
 662                         }
 663                         if (atomic_read(&rdev->irq.pflip[0]))
 664                                 radeon_crtc_handle_flip(rdev, 0);
 665                 }
 666                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 667                         if (rdev->irq.crtc_vblank_int[1]) {
 668                                 drm_handle_vblank(rdev->ddev, 1);
 669                                 rdev->pm.vblank_sync = true;
 670                                 wake_up(&rdev->irq.vblank_queue);
 671                         }
 672                         if (atomic_read(&rdev->irq.pflip[1]))
 673                                 radeon_crtc_handle_flip(rdev, 1);
 674                 }
 675                 if (status & RADEON_FP_DETECT_STAT) {
 676                         queue_hotplug = true;
 677                         DRM_DEBUG("HPD1\n");
 678                 }
 679                 if (status & RADEON_FP2_DETECT_STAT) {
 680                         queue_hotplug = true;
 681                         DRM_DEBUG("HPD2\n");
 682                 }
 683                 status = r100_irq_ack(rdev);
 684         }
 685         /* reset gui idle ack.  the status bit is broken */
 686         rdev->irq.gui_idle_acked = false;
 687         if (queue_hotplug)
 688                 schedule_work(&rdev->hotplug_work);
 689         if (rdev->msi_enabled) {
 690                 switch (rdev->family) {
 691                 case CHIP_RS400:
 692                 case CHIP_RS480:
 693                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 694                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 695                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 696                         break;
 697                 default:
 698                         WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
 699                         break;
 700                 }
 701         }
 702         return IRQ_HANDLED;
 703 }
 704
 705 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 706 {
 707         if (crtc == 0)
 708                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 709         else
 710                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 711 }
 712
 713 /* Who ever call radeon_fence_emit should call ring_lock and ask
 714  * for enough space (today caller are ib schedule and buffer move) */
 715 void r100_fence_ring_emit(struct radeon_device *rdev,
 716                           struct radeon_fence *fence)
 717 {
 718         struct radeon_ring *ring = &rdev->ring[fence->ring];
 719
 720         /* We have to make sure that caches are flushed before
 721          * CPU might read something from VRAM. */
 722         radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 723         radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
 724         radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 725         radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
 726         /* Wait until IDLE & CLEAN */
 727         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 728         radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 729         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 730         radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
 731                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 732         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 733         radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
 734         /* Emit fence sequence & fire IRQ */
 735         radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
 736         radeon_ring_write(ring, fence->seq);
 737         radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
 738         radeon_ring_write(ring, RADEON_SW_INT_FIRE);
 739 }
 740
 741 void r100_semaphore_ring_emit(struct radeon_device *rdev,
 742                               struct radeon_ring *ring,
 743                               struct radeon_semaphore *semaphore,
 744                               bool emit_wait)
 745 {
 746         /* Unused on older asics, since we don't have semaphores or multiple rings */
 747         BUG();
 748 }
 749
 750 int r100_copy_blit(struct radeon_device *rdev,
 751                    uint64_t src_offset,
 752                    uint64_t dst_offset,
 753                    unsigned num_gpu_pages,
 754                    struct radeon_fence **fence)
 755 {
 756         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 757         uint32_t cur_pages;
 758         uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
 759         uint32_t pitch;
 760         uint32_t stride_pixels;
 761         unsigned ndw;
 762         int num_loops;
 763         int r = 0;
 764
 765         /* radeon limited to 16k stride */
 766         stride_bytes &= 0x3fff;
 767         /* radeon pitch is /64 */
 768         pitch = stride_bytes / 64;
 769         stride_pixels = stride_bytes / 4;
 770         num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
 771
 772         /* Ask for enough room for blit + flush + fence */
 773         ndw = 64 + (10 * num_loops);
 774         r = radeon_ring_lock(rdev, ring, ndw);
 775         if (r) {
 776                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 777                 return -EINVAL;
 778         }
 779         while (num_gpu_pages > 0) {
 780                 cur_pages = num_gpu_pages;
 781                 if (cur_pages > 8191) {
 782                         cur_pages = 8191;
 783                 }
 784                 num_gpu_pages -= cur_pages;
 785
 786                 /* pages are in Y direction - height
 787                    page width in X direction - width */
 788                 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
 789                 radeon_ring_write(ring,
 790                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 791                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 792                                   RADEON_GMC_SRC_CLIPPING |
 793                                   RADEON_GMC_DST_CLIPPING |
 794                                   RADEON_GMC_BRUSH_NONE |
 795                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 796                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 797                                   RADEON_ROP3_S |
 798                                   RADEON_DP_SRC_SOURCE_MEMORY |
 799                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 800                                   RADEON_GMC_WR_MSK_DIS);
 801                 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
 802                 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
 803                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
 804                 radeon_ring_write(ring, 0);
 805                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
 806                 radeon_ring_write(ring, num_gpu_pages);
 807                 radeon_ring_write(ring, num_gpu_pages);
 808                 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
 809         }
 810         radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 811         radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
 812         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 813         radeon_ring_write(ring,
 814                           RADEON_WAIT_2D_IDLECLEAN |
 815                           RADEON_WAIT_HOST_IDLECLEAN |
 816                           RADEON_WAIT_DMA_GUI_IDLE);
 817         if (fence) {
 818                 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
 819         }
 820         radeon_ring_unlock_commit(rdev, ring);
 821         return r;
 822 }
 823
 824 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 825 {
 826         unsigned i;
 827         u32 tmp;
 828
 829         for (i = 0; i < rdev->usec_timeout; i++) {
 830                 tmp = RREG32(R_000E40_RBBM_STATUS);
 831                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 832                         return 0;
 833                 }
 834                 udelay(1);
 835         }
 836         return -1;
 837 }
 838
 839 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
 840 {
 841         int r;
 842
 843         r = radeon_ring_lock(rdev, ring, 2);
 844         if (r) {
 845                 return;
 846         }
 847         radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
 848         radeon_ring_write(ring,
 849                           RADEON_ISYNC_ANY2D_IDLE3D |
 850                           RADEON_ISYNC_ANY3D_IDLE2D |
 851                           RADEON_ISYNC_WAIT_IDLEGUI |
 852                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 853         radeon_ring_unlock_commit(rdev, ring);
 854 }
 855
 856
 857 /* Load the microcode for the CP */
 858 static int r100_cp_init_microcode(struct radeon_device *rdev)
 859 {
 860         struct platform_device *pdev;
 861         const char *fw_name = NULL;
 862         int err;
 863
 864         DRM_DEBUG_KMS("\n");
 865
 866         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 867         err = IS_ERR(pdev);
 868         if (err) {
 869                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 870                 return -EINVAL;
 871         }
 872         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 873             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 874             (rdev->family == CHIP_RS200)) {
 875                 DRM_INFO("Loading R100 Microcode\n");
 876                 fw_name = FIRMWARE_R100;
 877         } else if ((rdev->family == CHIP_R200) ||
 878                    (rdev->family == CHIP_RV250) ||
 879                    (rdev->family == CHIP_RV280) ||
 880                    (rdev->family == CHIP_RS300)) {
 881                 DRM_INFO("Loading R200 Microcode\n");
 882                 fw_name = FIRMWARE_R200;
 883         } else if ((rdev->family == CHIP_R300) ||
 884                    (rdev->family == CHIP_R350) ||
 885                    (rdev->family == CHIP_RV350) ||
 886                    (rdev->family == CHIP_RV380) ||
 887                    (rdev->family == CHIP_RS400) ||
 888                    (rdev->family == CHIP_RS480)) {
 889                 DRM_INFO("Loading R300 Microcode\n");
 890                 fw_name = FIRMWARE_R300;
 891         } else if ((rdev->family == CHIP_R420) ||
 892                    (rdev->family == CHIP_R423) ||
 893                    (rdev->family == CHIP_RV410)) {
 894                 DRM_INFO("Loading R400 Microcode\n");
 895                 fw_name = FIRMWARE_R420;
 896         } else if ((rdev->family == CHIP_RS690) ||
 897                    (rdev->family == CHIP_RS740)) {
 898                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 899                 fw_name = FIRMWARE_RS690;
 900         } else if (rdev->family == CHIP_RS600) {
 901                 DRM_INFO("Loading RS600 Microcode\n");
 902                 fw_name = FIRMWARE_RS600;
 903         } else if ((rdev->family == CHIP_RV515) ||
 904                    (rdev->family == CHIP_R520) ||
 905                    (rdev->family == CHIP_RV530) ||
 906                    (rdev->family == CHIP_R580) ||
 907                    (rdev->family == CHIP_RV560) ||
 908                    (rdev->family == CHIP_RV570)) {
 909                 DRM_INFO("Loading R500 Microcode\n");
 910                 fw_name = FIRMWARE_R520;
 911         }
 912
 913         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 914         platform_device_unregister(pdev);
 915         if (err) {
 916                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 917                        fw_name);
 918         } else if (rdev->me_fw->size % 8) {
 919                 printk(KERN_ERR
 920                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 921                        rdev->me_fw->size, fw_name);
 922                 err = -EINVAL;
 923                 release_firmware(rdev->me_fw);
 924                 rdev->me_fw = NULL;
 925         }
 926         return err;
 927 }
 928
 929 static void r100_cp_load_microcode(struct radeon_device *rdev)
 930 {
 931         const __be32 *fw_data;
 932         int i, size;
 933
 934         if (r100_gui_wait_for_idle(rdev)) {
 935                 printk(KERN_WARNING "Failed to wait GUI idle while "
 936                        "programming pipes. Bad things might happen.\n");
 937         }
 938
 939         if (rdev->me_fw) {
 940                 size = rdev->me_fw->size / 4;
 941                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
 942                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 943                 for (i = 0; i < size; i += 2) {
 944                         WREG32(RADEON_CP_ME_RAM_DATAH,
 945                                be32_to_cpup(&fw_data[i]));
 946                         WREG32(RADEON_CP_ME_RAM_DATAL,
 947                                be32_to_cpup(&fw_data[i + 1]));
 948                 }
 949         }
 950 }
 951
 952 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 953 {
 954         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 955         unsigned rb_bufsz;
 956         unsigned rb_blksz;
 957         unsigned max_fetch;
 958         unsigned pre_write_timer;
 959         unsigned pre_write_limit;
 960         unsigned indirect2_start;
 961         unsigned indirect1_start;
 962         uint32_t tmp;
 963         int r;
 964
 965         if (r100_debugfs_cp_init(rdev)) {
 966                 DRM_ERROR("Failed to register debugfs file for CP !\n");
 967         }
 968         if (!rdev->me_fw) {
 969                 r = r100_cp_init_microcode(rdev);
 970                 if (r) {
 971                         DRM_ERROR("Failed to load firmware!\n");
 972                         return r;
 973                 }
 974         }
 975
 976         /* Align ring size */
 977         rb_bufsz = drm_order(ring_size / 8);
 978         ring_size = (1 << (rb_bufsz + 1)) * 4;
 979         r100_cp_load_microcode(rdev);
 980         r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
 981                              RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
 982                              0, 0x7fffff, RADEON_CP_PACKET2);
 983         if (r) {
 984                 return r;
 985         }
 986         /* Each time the cp read 1024 bytes (16 dword/quadword) update
 987          * the rptr copy in system ram */
 988         rb_blksz = 9;
 989         /* cp will read 128bytes at a time (4 dwords) */
 990         max_fetch = 1;
 991         ring->align_mask = 16 - 1;
 992         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
 993         pre_write_timer = 64;
 994         /* Force CP_RB_WPTR write if written more than one time before the
 995          * delay expire
 996          */
 997         pre_write_limit = 0;
 998         /* Setup the cp cache like this (cache size is 96 dwords) :
 999          *      RING            0  to 15
1000          *      INDIRECT1       16 to 79
1001          *      INDIRECT2       80 to 95
1002          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1003          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1004          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1005          * Idea being that most of the gpu cmd will be through indirect1 buffer
1006          * so it gets the bigger cache.
1007          */
1008         indirect2_start = 80;
1009         indirect1_start = 16;
1010         /* cp setup */
1011         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1012         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1013                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1014                REG_SET(RADEON_MAX_FETCH, max_fetch));
1015 #ifdef __BIG_ENDIAN
1016         tmp |= RADEON_BUF_SWAP_32BIT;
1017 #endif
1018         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1019
1020         /* Set ring address */
1021         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1022         WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1023         /* Force read & write ptr to 0 */
1024         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1025         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1026         ring->wptr = 0;
1027         WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1028
1029         /* set the wb address whether it's enabled or not */
1030         WREG32(R_00070C_CP_RB_RPTR_ADDR,
1031                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1032         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1033
1034         if (rdev->wb.enabled)
1035                 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1036         else {
1037                 tmp |= RADEON_RB_NO_UPDATE;
1038                 WREG32(R_000770_SCRATCH_UMSK, 0);
1039         }
1040
1041         WREG32(RADEON_CP_RB_CNTL, tmp);
1042         udelay(10);
1043         ring->rptr = RREG32(RADEON_CP_RB_RPTR);
1044         /* Set cp mode to bus mastering & enable cp*/
1045         WREG32(RADEON_CP_CSQ_MODE,
1046                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1047                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1048         WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1049         WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1050         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1051
1052         /* at this point everything should be setup correctly to enable master */
1053         pci_set_master(rdev->pdev);
1054
1055         radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1056         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1057         if (r) {
1058                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1059                 return r;
1060         }
1061         ring->ready = true;
1062         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1063         return 0;
1064 }
1065
1066 void r100_cp_fini(struct radeon_device *rdev)
1067 {
1068         if (r100_cp_wait_for_idle(rdev)) {
1069                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1070         }
1071         /* Disable ring */
1072         r100_cp_disable(rdev);
1073         radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1074         DRM_INFO("radeon: cp finalized\n");
1075 }
1076
1077 void r100_cp_disable(struct radeon_device *rdev)
1078 {
1079         /* Disable ring */
1080         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1081         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1082         WREG32(RADEON_CP_CSQ_MODE, 0);
1083         WREG32(RADEON_CP_CSQ_CNTL, 0);
1084         WREG32(R_000770_SCRATCH_UMSK, 0);
1085         if (r100_gui_wait_for_idle(rdev)) {
1086                 printk(KERN_WARNING "Failed to wait GUI idle while "
1087                        "programming pipes. Bad things might happen.\n");
1088         }
1089 }
1090
1091 /*
1092  * CS functions
1093  */
1094 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1095                             struct radeon_cs_packet *pkt,
1096                             unsigned idx,
1097                             unsigned reg)
1098 {
1099         int r;
1100         u32 tile_flags = 0;
1101         u32 tmp;
1102         struct radeon_cs_reloc *reloc;
1103         u32 value;
1104
1105         r = r100_cs_packet_next_reloc(p, &reloc);
1106         if (r) {
1107                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1108                           idx, reg);
1109                 r100_cs_dump_packet(p, pkt);
1110                 return r;
1111         }
1112
1113         value = radeon_get_ib_value(p, idx);
1114         tmp = value & 0x003fffff;
1115         tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
1116
1117         if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1118                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1119                         tile_flags |= RADEON_DST_TILE_MACRO;
1120                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1121                         if (reg == RADEON_SRC_PITCH_OFFSET) {
1122                                 DRM_ERROR("Cannot src blit from microtiled surface\n");
1123                                 r100_cs_dump_packet(p, pkt);
1124                                 return -EINVAL;
1125                         }
1126                         tile_flags |= RADEON_DST_TILE_MICRO;
1127                 }
1128
1129                 tmp |= tile_flags;
1130                 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1131         } else
1132                 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1133         return 0;
1134 }
1135
1136 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1137                              struct radeon_cs_packet *pkt,
1138                              int idx)
1139 {
1140         unsigned c, i;
1141         struct radeon_cs_reloc *reloc;
1142         struct r100_cs_track *track;
1143         int r = 0;
1144         volatile uint32_t *ib;
1145         u32 idx_value;
1146
1147         ib = p->ib.ptr;
1148         track = (struct r100_cs_track *)p->track;
1149         c = radeon_get_ib_value(p, idx++) & 0x1F;
1150         if (c > 16) {
1151             DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1152                       pkt->opcode);
1153             r100_cs_dump_packet(p, pkt);
1154             return -EINVAL;
1155         }
1156         track->num_arrays = c;
1157         for (i = 0; i < (c - 1); i+=2, idx+=3) {
1158                 r = r100_cs_packet_next_reloc(p, &reloc);
1159                 if (r) {
1160                         DRM_ERROR("No reloc for packet3 %d\n",
1161                                   pkt->opcode);
1162                         r100_cs_dump_packet(p, pkt);
1163                         return r;
1164                 }
1165                 idx_value = radeon_get_ib_value(p, idx);
1166                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1167
1168                 track->arrays[i + 0].esize = idx_value >> 8;
1169                 track->arrays[i + 0].robj = reloc->robj;
1170                 track->arrays[i + 0].esize &= 0x7F;
1171                 r = r100_cs_packet_next_reloc(p, &reloc);
1172                 if (r) {
1173                         DRM_ERROR("No reloc for packet3 %d\n",
1174                                   pkt->opcode);
1175                         r100_cs_dump_packet(p, pkt);
1176                         return r;
1177                 }
1178                 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
1179                 track->arrays[i + 1].robj = reloc->robj;
1180                 track->arrays[i + 1].esize = idx_value >> 24;
1181                 track->arrays[i + 1].esize &= 0x7F;
1182         }
1183         if (c & 1) {
1184                 r = r100_cs_packet_next_reloc(p, &reloc);
1185                 if (r) {
1186                         DRM_ERROR("No reloc for packet3 %d\n",
1187                                           pkt->opcode);
1188                         r100_cs_dump_packet(p, pkt);
1189                         return r;
1190                 }
1191                 idx_value = radeon_get_ib_value(p, idx);
1192                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1193                 track->arrays[i + 0].robj = reloc->robj;
1194                 track->arrays[i + 0].esize = idx_value >> 8;
1195                 track->arrays[i + 0].esize &= 0x7F;
1196         }
1197         return r;
1198 }
1199
1200 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1201                           struct radeon_cs_packet *pkt,
1202                           const unsigned *auth, unsigned n,
1203                           radeon_packet0_check_t check)
1204 {
1205         unsigned reg;
1206         unsigned i, j, m;
1207         unsigned idx;
1208         int r;
1209
1210         idx = pkt->idx + 1;
1211         reg = pkt->reg;
1212         /* Check that register fall into register range
1213          * determined by the number of entry (n) in the
1214          * safe register bitmap.
1215          */
1216         if (pkt->one_reg_wr) {
1217                 if ((reg >> 7) > n) {
1218                         return -EINVAL;
1219                 }
1220         } else {
1221                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1222                         return -EINVAL;
1223                 }
1224         }
1225         for (i = 0; i <= pkt->count; i++, idx++) {
1226                 j = (reg >> 7);
1227                 m = 1 << ((reg >> 2) & 31);
1228                 if (auth[j] & m) {
1229                         r = check(p, pkt, idx, reg);
1230                         if (r) {
1231                                 return r;
1232                         }
1233                 }
1234                 if (pkt->one_reg_wr) {
1235                         if (!(auth[j] & m)) {
1236                                 break;
1237                         }
1238                 } else {
1239                         reg += 4;
1240                 }
1241         }
1242         return 0;
1243 }
1244
1245 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1246                          struct radeon_cs_packet *pkt)
1247 {
1248         volatile uint32_t *ib;
1249         unsigned i;
1250         unsigned idx;
1251
1252         ib = p->ib.ptr;
1253         idx = pkt->idx;
1254         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1255                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1256         }
1257 }
1258
1259 /**
1260  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1261  * @parser:     parser structure holding parsing context.
1262  * @pkt:        where to store packet informations
1263  *
1264  * Assume that chunk_ib_index is properly set. Will return -EINVAL
1265  * if packet is bigger than remaining ib size. or if packets is unknown.
1266  **/
1267 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1268                          struct radeon_cs_packet *pkt,
1269                          unsigned idx)
1270 {
1271         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1272         uint32_t header;
1273
1274         if (idx >= ib_chunk->length_dw) {
1275                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1276                           idx, ib_chunk->length_dw);
1277                 return -EINVAL;
1278         }
1279         header = radeon_get_ib_value(p, idx);
1280         pkt->idx = idx;
1281         pkt->type = CP_PACKET_GET_TYPE(header);
1282         pkt->count = CP_PACKET_GET_COUNT(header);
1283         switch (pkt->type) {
1284         case PACKET_TYPE0:
1285                 pkt->reg = CP_PACKET0_GET_REG(header);
1286                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1287                 break;
1288         case PACKET_TYPE3:
1289                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1290                 break;
1291         case PACKET_TYPE2:
1292                 pkt->count = -1;
1293                 break;
1294         default:
1295                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1296                 return -EINVAL;
1297         }
1298         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1299                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1300                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1301                 return -EINVAL;
1302         }
1303         return 0;
1304 }
1305
1306 /**
1307  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1308  * @parser:             parser structure holding parsing context.
1309  *
1310  * Userspace sends a special sequence for VLINE waits.
1311  * PACKET0 - VLINE_START_END + value
1312  * PACKET0 - WAIT_UNTIL +_value
1313  * RELOC (P3) - crtc_id in reloc.
1314  *
1315  * This function parses this and relocates the VLINE START END
1316  * and WAIT UNTIL packets to the correct crtc.
1317  * It also detects a switched off crtc and nulls out the
1318  * wait in that case.
1319  */
1320 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1321 {
1322         struct drm_mode_object *obj;
1323         struct drm_crtc *crtc;
1324         struct radeon_crtc *radeon_crtc;
1325         struct radeon_cs_packet p3reloc, waitreloc;
1326         int crtc_id;
1327         int r;
1328         uint32_t header, h_idx, reg;
1329         volatile uint32_t *ib;
1330
1331         ib = p->ib.ptr;
1332
1333         /* parse the wait until */
1334         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1335         if (r)
1336                 return r;
1337
1338         /* check its a wait until and only 1 count */
1339         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1340             waitreloc.count != 0) {
1341                 DRM_ERROR("vline wait had illegal wait until segment\n");
1342                 return -EINVAL;
1343         }
1344
1345         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1346                 DRM_ERROR("vline wait had illegal wait until\n");
1347                 return -EINVAL;
1348         }
1349
1350         /* jump over the NOP */
1351         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1352         if (r)
1353                 return r;
1354
1355         h_idx = p->idx - 2;
1356         p->idx += waitreloc.count + 2;
1357         p->idx += p3reloc.count + 2;
1358
1359         header = radeon_get_ib_value(p, h_idx);
1360         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1361         reg = CP_PACKET0_GET_REG(header);
1362         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1363         if (!obj) {
1364                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1365                 return -EINVAL;
1366         }
1367         crtc = obj_to_crtc(obj);
1368         radeon_crtc = to_radeon_crtc(crtc);
1369         crtc_id = radeon_crtc->crtc_id;
1370
1371         if (!crtc->enabled) {
1372                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1373                 ib[h_idx + 2] = PACKET2(0);
1374                 ib[h_idx + 3] = PACKET2(0);
1375         } else if (crtc_id == 1) {
1376                 switch (reg) {
1377                 case AVIVO_D1MODE_VLINE_START_END:
1378                         header &= ~R300_CP_PACKET0_REG_MASK;
1379                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1380                         break;
1381                 case RADEON_CRTC_GUI_TRIG_VLINE:
1382                         header &= ~R300_CP_PACKET0_REG_MASK;
1383                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1384                         break;
1385                 default:
1386                         DRM_ERROR("unknown crtc reloc\n");
1387                         return -EINVAL;
1388                 }
1389                 ib[h_idx] = header;
1390                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1391         }
1392
1393         return 0;
1394 }
1395
1396 /**
1397  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1398  * @parser:             parser structure holding parsing context.
1399  * @data:               pointer to relocation data
1400  * @offset_start:       starting offset
1401  * @offset_mask:        offset mask (to align start offset on)
1402  * @reloc:              reloc informations
1403  *
1404  * Check next packet is relocation packet3, do bo validation and compute
1405  * GPU offset using the provided start.
1406  **/
1407 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1408                               struct radeon_cs_reloc **cs_reloc)
1409 {
1410         struct radeon_cs_chunk *relocs_chunk;
1411         struct radeon_cs_packet p3reloc;
1412         unsigned idx;
1413         int r;
1414
1415         if (p->chunk_relocs_idx == -1) {
1416                 DRM_ERROR("No relocation chunk !\n");
1417                 return -EINVAL;
1418         }
1419         *cs_reloc = NULL;
1420         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1421         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1422         if (r) {
1423                 return r;
1424         }
1425         p->idx += p3reloc.count + 2;
1426         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1427                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1428                           p3reloc.idx);
1429                 r100_cs_dump_packet(p, &p3reloc);
1430                 return -EINVAL;
1431         }
1432         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1433         if (idx >= relocs_chunk->length_dw) {
1434                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1435                           idx, relocs_chunk->length_dw);
1436                 r100_cs_dump_packet(p, &p3reloc);
1437                 return -EINVAL;
1438         }
1439         /* FIXME: we assume reloc size is 4 dwords */
1440         *cs_reloc = p->relocs_ptr[(idx / 4)];
1441         return 0;
1442 }
1443
1444 static int r100_get_vtx_size(uint32_t vtx_fmt)
1445 {
1446         int vtx_size;
1447         vtx_size = 2;
1448         /* ordered according to bits in spec */
1449         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1450                 vtx_size++;
1451         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1452                 vtx_size += 3;
1453         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1454                 vtx_size++;
1455         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1456                 vtx_size++;
1457         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1458                 vtx_size += 3;
1459         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1460                 vtx_size++;
1461         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1462                 vtx_size++;
1463         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1464                 vtx_size += 2;
1465         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1466                 vtx_size += 2;
1467         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1468                 vtx_size++;
1469         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1470                 vtx_size += 2;
1471         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1472                 vtx_size++;
1473         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1474                 vtx_size += 2;
1475         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1476                 vtx_size++;
1477         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1478                 vtx_size++;
1479         /* blend weight */
1480         if (vtx_fmt & (0x7 << 15))
1481                 vtx_size += (vtx_fmt >> 15) & 0x7;
1482         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1483                 vtx_size += 3;
1484         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1485                 vtx_size += 2;
1486         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1487                 vtx_size++;
1488         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1489                 vtx_size++;
1490         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1491                 vtx_size++;
1492         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1493                 vtx_size++;
1494         return vtx_size;
1495 }
1496
1497 static int r100_packet0_check(struct radeon_cs_parser *p,
1498                               struct radeon_cs_packet *pkt,
1499                               unsigned idx, unsigned reg)
1500 {
1501         struct radeon_cs_reloc *reloc;
1502         struct r100_cs_track *track;
1503         volatile uint32_t *ib;
1504         uint32_t tmp;
1505         int r;
1506         int i, face;
1507         u32 tile_flags = 0;
1508         u32 idx_value;
1509
1510         ib = p->ib.ptr;
1511         track = (struct r100_cs_track *)p->track;
1512
1513         idx_value = radeon_get_ib_value(p, idx);
1514
1515         switch (reg) {
1516         case RADEON_CRTC_GUI_TRIG_VLINE:
1517                 r = r100_cs_packet_parse_vline(p);
1518                 if (r) {
1519                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1520                                   idx, reg);
1521                         r100_cs_dump_packet(p, pkt);
1522                         return r;
1523                 }
1524                 break;
1525                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1526                  * range access */
1527         case RADEON_DST_PITCH_OFFSET:
1528         case RADEON_SRC_PITCH_OFFSET:
1529                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1530                 if (r)
1531                         return r;
1532                 break;
1533         case RADEON_RB3D_DEPTHOFFSET:
1534                 r = r100_cs_packet_next_reloc(p, &reloc);
1535                 if (r) {
1536                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1537                                   idx, reg);
1538                         r100_cs_dump_packet(p, pkt);
1539                         return r;
1540                 }
1541                 track->zb.robj = reloc->robj;
1542                 track->zb.offset = idx_value;
1543                 track->zb_dirty = true;
1544                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1545                 break;
1546         case RADEON_RB3D_COLOROFFSET:
1547                 r = r100_cs_packet_next_reloc(p, &reloc);
1548                 if (r) {
1549                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1550                                   idx, reg);
1551                         r100_cs_dump_packet(p, pkt);
1552                         return r;
1553                 }
1554                 track->cb[0].robj = reloc->robj;
1555                 track->cb[0].offset = idx_value;
1556                 track->cb_dirty = true;
1557                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1558                 break;
1559         case RADEON_PP_TXOFFSET_0:
1560         case RADEON_PP_TXOFFSET_1:
1561         case RADEON_PP_TXOFFSET_2:
1562                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1563                 r = r100_cs_packet_next_reloc(p, &reloc);
1564                 if (r) {
1565                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1566                                   idx, reg);
1567                         r100_cs_dump_packet(p, pkt);
1568                         return r;
1569                 }
1570                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1571                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1572                                 tile_flags |= RADEON_TXO_MACRO_TILE;
1573                         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1574                                 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1575
1576                         tmp = idx_value & ~(0x7 << 2);
1577                         tmp |= tile_flags;
1578                         ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1579                 } else
1580                         ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1581                 track->textures[i].robj = reloc->robj;
1582                 track->tex_dirty = true;
1583                 break;
1584         case RADEON_PP_CUBIC_OFFSET_T0_0:
1585         case RADEON_PP_CUBIC_OFFSET_T0_1:
1586         case RADEON_PP_CUBIC_OFFSET_T0_2:
1587         case RADEON_PP_CUBIC_OFFSET_T0_3:
1588         case RADEON_PP_CUBIC_OFFSET_T0_4:
1589                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1590                 r = r100_cs_packet_next_reloc(p, &reloc);
1591                 if (r) {
1592                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1593                                   idx, reg);
1594                         r100_cs_dump_packet(p, pkt);
1595                         return r;
1596                 }
1597                 track->textures[0].cube_info[i].offset = idx_value;
1598                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1599                 track->textures[0].cube_info[i].robj = reloc->robj;
1600                 track->tex_dirty = true;
1601                 break;
1602         case RADEON_PP_CUBIC_OFFSET_T1_0:
1603         case RADEON_PP_CUBIC_OFFSET_T1_1:
1604         case RADEON_PP_CUBIC_OFFSET_T1_2:
1605         case RADEON_PP_CUBIC_OFFSET_T1_3:
1606         case RADEON_PP_CUBIC_OFFSET_T1_4:
1607                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1608                 r = r100_cs_packet_next_reloc(p, &reloc);
1609                 if (r) {
1610                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1611                                   idx, reg);
1612                         r100_cs_dump_packet(p, pkt);
1613                         return r;
1614                 }
1615                 track->textures[1].cube_info[i].offset = idx_value;
1616                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1617                 track->textures[1].cube_info[i].robj = reloc->robj;
1618                 track->tex_dirty = true;
1619                 break;
1620         case RADEON_PP_CUBIC_OFFSET_T2_0:
1621         case RADEON_PP_CUBIC_OFFSET_T2_1:
1622         case RADEON_PP_CUBIC_OFFSET_T2_2:
1623         case RADEON_PP_CUBIC_OFFSET_T2_3:
1624         case RADEON_PP_CUBIC_OFFSET_T2_4:
1625                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1626                 r = r100_cs_packet_next_reloc(p, &reloc);
1627                 if (r) {
1628                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1629                                   idx, reg);
1630                         r100_cs_dump_packet(p, pkt);
1631                         return r;
1632                 }
1633                 track->textures[2].cube_info[i].offset = idx_value;
1634                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1635                 track->textures[2].cube_info[i].robj = reloc->robj;
1636                 track->tex_dirty = true;
1637                 break;
1638         case RADEON_RE_WIDTH_HEIGHT:
1639                 track->maxy = ((idx_value >> 16) & 0x7FF);
1640                 track->cb_dirty = true;
1641                 track->zb_dirty = true;
1642                 break;
1643         case RADEON_RB3D_COLORPITCH:
1644                 r = r100_cs_packet_next_reloc(p, &reloc);
1645                 if (r) {
1646                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1647                                   idx, reg);
1648                         r100_cs_dump_packet(p, pkt);
1649                         return r;
1650                 }
1651                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1652                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1653                                 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1654                         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1655                                 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1656
1657                         tmp = idx_value & ~(0x7 << 16);
1658                         tmp |= tile_flags;
1659                         ib[idx] = tmp;
1660                 } else
1661                         ib[idx] = idx_value;
1662
1663                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1664                 track->cb_dirty = true;
1665                 break;
1666         case RADEON_RB3D_DEPTHPITCH:
1667                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1668                 track->zb_dirty = true;
1669                 break;
1670         case RADEON_RB3D_CNTL:
1671                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1672                 case 7:
1673                 case 8:
1674                 case 9:
1675                 case 11:
1676                 case 12:
1677                         track->cb[0].cpp = 1;
1678                         break;
1679                 case 3:
1680                 case 4:
1681                 case 15:
1682                         track->cb[0].cpp = 2;
1683                         break;
1684                 case 6:
1685                         track->cb[0].cpp = 4;
1686                         break;
1687                 default:
1688                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1689                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1690                         return -EINVAL;
1691                 }
1692                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1693                 track->cb_dirty = true;
1694                 track->zb_dirty = true;
1695                 break;
1696         case RADEON_RB3D_ZSTENCILCNTL:
1697                 switch (idx_value & 0xf) {
1698                 case 0:
1699                         track->zb.cpp = 2;
1700                         break;
1701                 case 2:
1702                 case 3:
1703                 case 4:
1704                 case 5:
1705                 case 9:
1706                 case 11:
1707                         track->zb.cpp = 4;
1708                         break;
1709                 default:
1710                         break;
1711                 }
1712                 track->zb_dirty = true;
1713                 break;
1714         case RADEON_RB3D_ZPASS_ADDR:
1715                 r = r100_cs_packet_next_reloc(p, &reloc);
1716                 if (r) {
1717                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1718                                   idx, reg);
1719                         r100_cs_dump_packet(p, pkt);
1720                         return r;
1721                 }
1722                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1723                 break;
1724         case RADEON_PP_CNTL:
1725                 {
1726                         uint32_t temp = idx_value >> 4;
1727                         for (i = 0; i < track->num_texture; i++)
1728                                 track->textures[i].enabled = !!(temp & (1 << i));
1729                         track->tex_dirty = true;
1730                 }
1731                 break;
1732         case RADEON_SE_VF_CNTL:
1733                 track->vap_vf_cntl = idx_value;
1734                 break;
1735         case RADEON_SE_VTX_FMT:
1736                 track->vtx_size = r100_get_vtx_size(idx_value);
1737                 break;
1738         case RADEON_PP_TEX_SIZE_0:
1739         case RADEON_PP_TEX_SIZE_1:
1740         case RADEON_PP_TEX_SIZE_2:
1741                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1742                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1743                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1744                 track->tex_dirty = true;
1745                 break;
1746         case RADEON_PP_TEX_PITCH_0:
1747         case RADEON_PP_TEX_PITCH_1:
1748         case RADEON_PP_TEX_PITCH_2:
1749                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1750                 track->textures[i].pitch = idx_value + 32;
1751                 track->tex_dirty = true;
1752                 break;
1753         case RADEON_PP_TXFILTER_0:
1754         case RADEON_PP_TXFILTER_1:
1755         case RADEON_PP_TXFILTER_2:
1756                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1757                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1758                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1759                 tmp = (idx_value >> 23) & 0x7;
1760                 if (tmp == 2 || tmp == 6)
1761                         track->textures[i].roundup_w = false;
1762                 tmp = (idx_value >> 27) & 0x7;
1763                 if (tmp == 2 || tmp == 6)
1764                         track->textures[i].roundup_h = false;
1765                 track->tex_dirty = true;
1766                 break;
1767         case RADEON_PP_TXFORMAT_0:
1768         case RADEON_PP_TXFORMAT_1:
1769         case RADEON_PP_TXFORMAT_2:
1770                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1771                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1772                         track->textures[i].use_pitch = 1;
1773                 } else {
1774                         track->textures[i].use_pitch = 0;
1775                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1776                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1777                 }
1778                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1779                         track->textures[i].tex_coord_type = 2;
1780                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1781                 case RADEON_TXFORMAT_I8:
1782                 case RADEON_TXFORMAT_RGB332:
1783                 case RADEON_TXFORMAT_Y8:
1784                         track->textures[i].cpp = 1;
1785                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1786                         break;
1787                 case RADEON_TXFORMAT_AI88:
1788                 case RADEON_TXFORMAT_ARGB1555:
1789                 case RADEON_TXFORMAT_RGB565:
1790                 case RADEON_TXFORMAT_ARGB4444:
1791                 case RADEON_TXFORMAT_VYUY422:
1792                 case RADEON_TXFORMAT_YVYU422:
1793                 case RADEON_TXFORMAT_SHADOW16:
1794                 case RADEON_TXFORMAT_LDUDV655:
1795                 case RADEON_TXFORMAT_DUDV88:
1796                         track->textures[i].cpp = 2;
1797                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1798                         break;
1799                 case RADEON_TXFORMAT_ARGB8888:
1800                 case RADEON_TXFORMAT_RGBA8888:
1801                 case RADEON_TXFORMAT_SHADOW32:
1802                 case RADEON_TXFORMAT_LDUDUV8888:
1803                         track->textures[i].cpp = 4;
1804                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1805                         break;
1806                 case RADEON_TXFORMAT_DXT1:
1807                         track->textures[i].cpp = 1;
1808                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1809                         break;
1810                 case RADEON_TXFORMAT_DXT23:
1811                 case RADEON_TXFORMAT_DXT45:
1812                         track->textures[i].cpp = 1;
1813                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1814                         break;
1815                 }
1816                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1817                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1818                 track->tex_dirty = true;
1819                 break;
1820         case RADEON_PP_CUBIC_FACES_0:
1821         case RADEON_PP_CUBIC_FACES_1:
1822         case RADEON_PP_CUBIC_FACES_2:
1823                 tmp = idx_value;
1824                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1825                 for (face = 0; face < 4; face++) {
1826                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1827                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1828                 }
1829                 track->tex_dirty = true;
1830                 break;
1831         default:
1832                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1833                        reg, idx);
1834                 return -EINVAL;
1835         }
1836         return 0;
1837 }
1838
1839 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1840                                          struct radeon_cs_packet *pkt,
1841                                          struct radeon_bo *robj)
1842 {
1843         unsigned idx;
1844         u32 value;
1845         idx = pkt->idx + 1;
1846         value = radeon_get_ib_value(p, idx + 2);
1847         if ((value + 1) > radeon_bo_size(robj)) {
1848                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1849                           "(need %u have %lu) !\n",
1850                           value + 1,
1851                           radeon_bo_size(robj));
1852                 return -EINVAL;
1853         }
1854         return 0;
1855 }
1856
1857 static int r100_packet3_check(struct radeon_cs_parser *p,
1858                               struct radeon_cs_packet *pkt)
1859 {
1860         struct radeon_cs_reloc *reloc;
1861         struct r100_cs_track *track;
1862         unsigned idx;
1863         volatile uint32_t *ib;
1864         int r;
1865
1866         ib = p->ib.ptr;
1867         idx = pkt->idx + 1;
1868         track = (struct r100_cs_track *)p->track;
1869         switch (pkt->opcode) {
1870         case PACKET3_3D_LOAD_VBPNTR:
1871                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1872                 if (r)
1873                         return r;
1874                 break;
1875         case PACKET3_INDX_BUFFER:
1876                 r = r100_cs_packet_next_reloc(p, &reloc);
1877                 if (r) {
1878                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1879                         r100_cs_dump_packet(p, pkt);
1880                         return r;
1881                 }
1882                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1883                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1884                 if (r) {
1885                         return r;
1886                 }
1887                 break;
1888         case 0x23:
1889                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1890                 r = r100_cs_packet_next_reloc(p, &reloc);
1891                 if (r) {
1892                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1893                         r100_cs_dump_packet(p, pkt);
1894                         return r;
1895                 }
1896                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1897                 track->num_arrays = 1;
1898                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1899
1900                 track->arrays[0].robj = reloc->robj;
1901                 track->arrays[0].esize = track->vtx_size;
1902
1903                 track->max_indx = radeon_get_ib_value(p, idx+1);
1904
1905                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1906                 track->immd_dwords = pkt->count - 1;
1907                 r = r100_cs_track_check(p->rdev, track);
1908                 if (r)
1909                         return r;
1910                 break;
1911         case PACKET3_3D_DRAW_IMMD:
1912                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1913                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1914                         return -EINVAL;
1915                 }
1916                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1917                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1918                 track->immd_dwords = pkt->count - 1;
1919                 r = r100_cs_track_check(p->rdev, track);
1920                 if (r)
1921                         return r;
1922                 break;
1923                 /* triggers drawing using in-packet vertex data */
1924         case PACKET3_3D_DRAW_IMMD_2:
1925                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1926                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1927                         return -EINVAL;
1928                 }
1929                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1930                 track->immd_dwords = pkt->count;
1931                 r = r100_cs_track_check(p->rdev, track);
1932                 if (r)
1933                         return r;
1934                 break;
1935                 /* triggers drawing using in-packet vertex data */
1936         case PACKET3_3D_DRAW_VBUF_2:
1937                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1938                 r = r100_cs_track_check(p->rdev, track);
1939                 if (r)
1940                         return r;
1941                 break;
1942                 /* triggers drawing of vertex buffers setup elsewhere */
1943         case PACKET3_3D_DRAW_INDX_2:
1944                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1945                 r = r100_cs_track_check(p->rdev, track);
1946                 if (r)
1947                         return r;
1948                 break;
1949                 /* triggers drawing using indices to vertex buffer */
1950         case PACKET3_3D_DRAW_VBUF:
1951                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1952                 r = r100_cs_track_check(p->rdev, track);
1953                 if (r)
1954                         return r;
1955                 break;
1956                 /* triggers drawing of vertex buffers setup elsewhere */
1957         case PACKET3_3D_DRAW_INDX:
1958                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1959                 r = r100_cs_track_check(p->rdev, track);
1960                 if (r)
1961                         return r;
1962                 break;
1963                 /* triggers drawing using indices to vertex buffer */
1964         case PACKET3_3D_CLEAR_HIZ:
1965         case PACKET3_3D_CLEAR_ZMASK:
1966                 if (p->rdev->hyperz_filp != p->filp)
1967                         return -EINVAL;
1968                 break;
1969         case PACKET3_NOP:
1970                 break;
1971         default:
1972                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1973                 return -EINVAL;
1974         }
1975         return 0;
1976 }
1977
1978 int r100_cs_parse(struct radeon_cs_parser *p)
1979 {
1980         struct radeon_cs_packet pkt;
1981         struct r100_cs_track *track;
1982         int r;
1983
1984         track = kzalloc(sizeof(*track), GFP_KERNEL);
1985         if (!track)
1986                 return -ENOMEM;
1987         r100_cs_track_clear(p->rdev, track);
1988         p->track = track;
1989         do {
1990                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1991                 if (r) {
1992                         return r;
1993                 }
1994                 p->idx += pkt.count + 2;
1995                 switch (pkt.type) {
1996                         case PACKET_TYPE0:
1997                                 if (p->rdev->family >= CHIP_R200)
1998                                         r = r100_cs_parse_packet0(p, &pkt,
1999                                                                   p->rdev->config.r100.reg_safe_bm,
2000                                                                   p->rdev->config.r100.reg_safe_bm_size,
2001                                                                   &r200_packet0_check);
2002                                 else
2003                                         r = r100_cs_parse_packet0(p, &pkt,
2004                                                                   p->rdev->config.r100.reg_safe_bm,
2005                                                                   p->rdev->config.r100.reg_safe_bm_size,
2006                                                                   &r100_packet0_check);
2007                                 break;
2008                         case PACKET_TYPE2:
2009                                 break;
2010                         case PACKET_TYPE3:
2011                                 r = r100_packet3_check(p, &pkt);
2012                                 break;
2013                         default:
2014                                 DRM_ERROR("Unknown packet type %d !\n",
2015                                           pkt.type);
2016                                 return -EINVAL;
2017                 }
2018                 if (r) {
2019                         return r;
2020                 }
2021         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2022         return 0;
2023 }
2024
2025 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2026 {
2027         DRM_ERROR("pitch                      %d\n", t->pitch);
2028         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
2029         DRM_ERROR("width                      %d\n", t->width);
2030         DRM_ERROR("width_11                   %d\n", t->width_11);
2031         DRM_ERROR("height                     %d\n", t->height);
2032         DRM_ERROR("height_11                  %d\n", t->height_11);
2033         DRM_ERROR("num levels                 %d\n", t->num_levels);
2034         DRM_ERROR("depth                      %d\n", t->txdepth);
2035         DRM_ERROR("bpp                        %d\n", t->cpp);
2036         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
2037         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
2038         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2039         DRM_ERROR("compress format            %d\n", t->compress_format);
2040 }
2041
2042 static int r100_track_compress_size(int compress_format, int w, int h)
2043 {
2044         int block_width, block_height, block_bytes;
2045         int wblocks, hblocks;
2046         int min_wblocks;
2047         int sz;
2048
2049         block_width = 4;
2050         block_height = 4;
2051
2052         switch (compress_format) {
2053         case R100_TRACK_COMP_DXT1:
2054                 block_bytes = 8;
2055                 min_wblocks = 4;
2056                 break;
2057         default:
2058         case R100_TRACK_COMP_DXT35:
2059                 block_bytes = 16;
2060                 min_wblocks = 2;
2061                 break;
2062         }
2063
2064         hblocks = (h + block_height - 1) / block_height;
2065         wblocks = (w + block_width - 1) / block_width;
2066         if (wblocks < min_wblocks)
2067                 wblocks = min_wblocks;
2068         sz = wblocks * hblocks * block_bytes;
2069         return sz;
2070 }
2071
2072 static int r100_cs_track_cube(struct radeon_device *rdev,
2073                               struct r100_cs_track *track, unsigned idx)
2074 {
2075         unsigned face, w, h;
2076         struct radeon_bo *cube_robj;
2077         unsigned long size;
2078         unsigned compress_format = track->textures[idx].compress_format;
2079
2080         for (face = 0; face < 5; face++) {
2081                 cube_robj = track->textures[idx].cube_info[face].robj;
2082                 w = track->textures[idx].cube_info[face].width;
2083                 h = track->textures[idx].cube_info[face].height;
2084
2085                 if (compress_format) {
2086                         size = r100_track_compress_size(compress_format, w, h);
2087                 } else
2088                         size = w * h;
2089                 size *= track->textures[idx].cpp;
2090
2091                 size += track->textures[idx].cube_info[face].offset;
2092
2093                 if (size > radeon_bo_size(cube_robj)) {
2094                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2095                                   size, radeon_bo_size(cube_robj));
2096                         r100_cs_track_texture_print(&track->textures[idx]);
2097                         return -1;
2098                 }
2099         }
2100         return 0;
2101 }
2102
2103 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2104                                        struct r100_cs_track *track)
2105 {
2106         struct radeon_bo *robj;
2107         unsigned long size;
2108         unsigned u, i, w, h, d;
2109         int ret;
2110
2111         for (u = 0; u < track->num_texture; u++) {
2112                 if (!track->textures[u].enabled)
2113                         continue;
2114                 if (track->textures[u].lookup_disable)
2115                         continue;
2116                 robj = track->textures[u].robj;
2117                 if (robj == NULL) {
2118                         DRM_ERROR("No texture bound to unit %u\n", u);
2119                         return -EINVAL;
2120                 }
2121                 size = 0;
2122                 for (i = 0; i <= track->textures[u].num_levels; i++) {
2123                         if (track->textures[u].use_pitch) {
2124                                 if (rdev->family < CHIP_R300)
2125                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2126                                 else
2127                                         w = track->textures[u].pitch / (1 << i);
2128                         } else {
2129                                 w = track->textures[u].width;
2130                                 if (rdev->family >= CHIP_RV515)
2131                                         w |= track->textures[u].width_11;
2132                                 w = w / (1 << i);
2133                                 if (track->textures[u].roundup_w)
2134                                         w = roundup_pow_of_two(w);
2135                         }
2136                         h = track->textures[u].height;
2137                         if (rdev->family >= CHIP_RV515)
2138                                 h |= track->textures[u].height_11;
2139                         h = h / (1 << i);
2140                         if (track->textures[u].roundup_h)
2141                                 h = roundup_pow_of_two(h);
2142                         if (track->textures[u].tex_coord_type == 1) {
2143                                 d = (1 << track->textures[u].txdepth) / (1 << i);
2144                                 if (!d)
2145                                         d = 1;
2146                         } else {
2147                                 d = 1;
2148                         }
2149                         if (track->textures[u].compress_format) {
2150
2151                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2152                                 /* compressed textures are block based */
2153                         } else
2154                                 size += w * h * d;
2155                 }
2156                 size *= track->textures[u].cpp;
2157
2158                 switch (track->textures[u].tex_coord_type) {
2159                 case 0:
2160                 case 1:
2161                         break;
2162                 case 2:
2163                         if (track->separate_cube) {
2164                                 ret = r100_cs_track_cube(rdev, track, u);
2165                                 if (ret)
2166                                         return ret;
2167                         } else
2168                                 size *= 6;
2169                         break;
2170                 default:
2171                         DRM_ERROR("Invalid texture coordinate type %u for unit "
2172                                   "%u\n", track->textures[u].tex_coord_type, u);
2173                         return -EINVAL;
2174                 }
2175                 if (size > radeon_bo_size(robj)) {
2176                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2177                                   "%lu\n", u, size, radeon_bo_size(robj));
2178                         r100_cs_track_texture_print(&track->textures[u]);
2179                         return -EINVAL;
2180                 }
2181         }
2182         return 0;
2183 }
2184
2185 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2186 {
2187         unsigned i;
2188         unsigned long size;
2189         unsigned prim_walk;
2190         unsigned nverts;
2191         unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2192
2193         if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2194             !track->blend_read_enable)
2195                 num_cb = 0;
2196
2197         for (i = 0; i < num_cb; i++) {
2198                 if (track->cb[i].robj == NULL) {
2199                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2200                         return -EINVAL;
2201                 }
2202                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2203                 size += track->cb[i].offset;
2204                 if (size > radeon_bo_size(track->cb[i].robj)) {
2205                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
2206                                   "(need %lu have %lu) !\n", i, size,
2207                                   radeon_bo_size(track->cb[i].robj));
2208                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2209                                   i, track->cb[i].pitch, track->cb[i].cpp,
2210                                   track->cb[i].offset, track->maxy);
2211                         return -EINVAL;
2212                 }
2213         }
2214         track->cb_dirty = false;
2215
2216         if (track->zb_dirty && track->z_enabled) {
2217                 if (track->zb.robj == NULL) {
2218                         DRM_ERROR("[drm] No buffer for z buffer !\n");
2219                         return -EINVAL;
2220                 }
2221                 size = track->zb.pitch * track->zb.cpp * track->maxy;
2222                 size += track->zb.offset;
2223                 if (size > radeon_bo_size(track->zb.robj)) {
2224                         DRM_ERROR("[drm] Buffer too small for z buffer "
2225                                   "(need %lu have %lu) !\n", size,
2226                                   radeon_bo_size(track->zb.robj));
2227                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2228                                   track->zb.pitch, track->zb.cpp,
2229                                   track->zb.offset, track->maxy);
2230                         return -EINVAL;
2231                 }
2232         }
2233         track->zb_dirty = false;
2234
2235         if (track->aa_dirty && track->aaresolve) {
2236                 if (track->aa.robj == NULL) {
2237                         DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2238                         return -EINVAL;
2239                 }
2240                 /* I believe the format comes from colorbuffer0. */
2241                 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2242                 size += track->aa.offset;
2243                 if (size > radeon_bo_size(track->aa.robj)) {
2244                         DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2245                                   "(need %lu have %lu) !\n", i, size,
2246                                   radeon_bo_size(track->aa.robj));
2247                         DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2248                                   i, track->aa.pitch, track->cb[0].cpp,
2249                                   track->aa.offset, track->maxy);
2250                         return -EINVAL;
2251                 }
2252         }
2253         track->aa_dirty = false;
2254
2255         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2256         if (track->vap_vf_cntl & (1 << 14)) {
2257                 nverts = track->vap_alt_nverts;
2258         } else {
2259                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2260         }
2261         switch (prim_walk) {
2262         case 1:
2263                 for (i = 0; i < track->num_arrays; i++) {
2264                         size = track->arrays[i].esize * track->max_indx * 4;
2265                         if (track->arrays[i].robj == NULL) {
2266                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2267                                           "bound\n", prim_walk, i);
2268                                 return -EINVAL;
2269                         }
2270                         if (size > radeon_bo_size(track->arrays[i].robj)) {
2271                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2272                                         "need %lu dwords have %lu dwords\n",
2273                                         prim_walk, i, size >> 2,
2274                                         radeon_bo_size(track->arrays[i].robj)
2275                                         >> 2);
2276                                 DRM_ERROR("Max indices %u\n", track->max_indx);
2277                                 return -EINVAL;
2278                         }
2279                 }
2280                 break;
2281         case 2:
2282                 for (i = 0; i < track->num_arrays; i++) {
2283                         size = track->arrays[i].esize * (nverts - 1) * 4;
2284                         if (track->arrays[i].robj == NULL) {
2285                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2286                                           "bound\n", prim_walk, i);
2287                                 return -EINVAL;
2288                         }
2289                         if (size > radeon_bo_size(track->arrays[i].robj)) {
2290                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2291                                         "need %lu dwords have %lu dwords\n",
2292                                         prim_walk, i, size >> 2,
2293                                         radeon_bo_size(track->arrays[i].robj)
2294                                         >> 2);
2295                                 return -EINVAL;
2296                         }
2297                 }
2298                 break;
2299         case 3:
2300                 size = track->vtx_size * nverts;
2301                 if (size != track->immd_dwords) {
2302                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2303                                   track->immd_dwords, size);
2304                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2305                                   nverts, track->vtx_size);
2306                         return -EINVAL;
2307                 }
2308                 break;
2309         default:
2310                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2311                           prim_walk);
2312                 return -EINVAL;
2313         }
2314
2315         if (track->tex_dirty) {
2316                 track->tex_dirty = false;
2317                 return r100_cs_track_texture_check(rdev, track);
2318         }
2319         return 0;
2320 }
2321
2322 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2323 {
2324         unsigned i, face;
2325
2326         track->cb_dirty = true;
2327         track->zb_dirty = true;
2328         track->tex_dirty = true;
2329         track->aa_dirty = true;
2330
2331         if (rdev->family < CHIP_R300) {
2332                 track->num_cb = 1;
2333                 if (rdev->family <= CHIP_RS200)
2334                         track->num_texture = 3;
2335                 else
2336                         track->num_texture = 6;
2337                 track->maxy = 2048;
2338                 track->separate_cube = 1;
2339         } else {
2340                 track->num_cb = 4;
2341                 track->num_texture = 16;
2342                 track->maxy = 4096;
2343                 track->separate_cube = 0;
2344                 track->aaresolve = false;
2345                 track->aa.robj = NULL;
2346         }
2347
2348         for (i = 0; i < track->num_cb; i++) {
2349                 track->cb[i].robj = NULL;
2350                 track->cb[i].pitch = 8192;
2351                 track->cb[i].cpp = 16;
2352                 track->cb[i].offset = 0;
2353         }
2354         track->z_enabled = true;
2355         track->zb.robj = NULL;
2356         track->zb.pitch = 8192;
2357         track->zb.cpp = 4;
2358         track->zb.offset = 0;
2359         track->vtx_size = 0x7F;
2360         track->immd_dwords = 0xFFFFFFFFUL;
2361         track->num_arrays = 11;
2362         track->max_indx = 0x00FFFFFFUL;
2363         for (i = 0; i < track->num_arrays; i++) {
2364                 track->arrays[i].robj = NULL;
2365                 track->arrays[i].esize = 0x7F;
2366         }
2367         for (i = 0; i < track->num_texture; i++) {
2368                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2369                 track->textures[i].pitch = 16536;
2370                 track->textures[i].width = 16536;
2371                 track->textures[i].height = 16536;
2372                 track->textures[i].width_11 = 1 << 11;
2373                 track->textures[i].height_11 = 1 << 11;
2374                 track->textures[i].num_levels = 12;
2375                 if (rdev->family <= CHIP_RS200) {
2376                         track->textures[i].tex_coord_type = 0;
2377                         track->textures[i].txdepth = 0;
2378                 } else {
2379                         track->textures[i].txdepth = 16;
2380                         track->textures[i].tex_coord_type = 1;
2381                 }
2382                 track->textures[i].cpp = 64;
2383                 track->textures[i].robj = NULL;
2384                 /* CS IB emission code makes sure texture unit are disabled */
2385                 track->textures[i].enabled = false;
2386                 track->textures[i].lookup_disable = false;
2387                 track->textures[i].roundup_w = true;
2388                 track->textures[i].roundup_h = true;
2389                 if (track->separate_cube)
2390                         for (face = 0; face < 5; face++) {
2391                                 track->textures[i].cube_info[face].robj = NULL;
2392                                 track->textures[i].cube_info[face].width = 16536;
2393                                 track->textures[i].cube_info[face].height = 16536;
2394                                 track->textures[i].cube_info[face].offset = 0;
2395                         }
2396         }
2397 }
2398
2399 /*
2400  * Global GPU functions
2401  */
2402 void r100_errata(struct radeon_device *rdev)
2403 {
2404         rdev->pll_errata = 0;
2405
2406         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2407                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2408         }
2409
2410         if (rdev->family == CHIP_RV100 ||
2411             rdev->family == CHIP_RS100 ||
2412             rdev->family == CHIP_RS200) {
2413                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2414         }
2415 }
2416
2417 /* Wait for vertical sync on primary CRTC */
2418 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
2419 {
2420         uint32_t crtc_gen_cntl, tmp;
2421         int i;
2422
2423         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2424         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2425             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2426                 return;
2427         }
2428         /* Clear the CRTC_VBLANK_SAVE bit */
2429         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2430         for (i = 0; i < rdev->usec_timeout; i++) {
2431                 tmp = RREG32(RADEON_CRTC_STATUS);
2432                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2433                         return;
2434                 }
2435                 DRM_UDELAY(1);
2436         }
2437 }
2438
2439 /* Wait for vertical sync on secondary CRTC */
2440 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
2441 {
2442         uint32_t crtc2_gen_cntl, tmp;
2443         int i;
2444
2445         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2446         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2447             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2448                 return;
2449
2450         /* Clear the CRTC_VBLANK_SAVE bit */
2451         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2452         for (i = 0; i < rdev->usec_timeout; i++) {
2453                 tmp = RREG32(RADEON_CRTC2_STATUS);
2454                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2455                         return;
2456                 }
2457                 DRM_UDELAY(1);
2458         }
2459 }
2460
2461 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2462 {
2463         unsigned i;
2464         uint32_t tmp;
2465
2466         for (i = 0; i < rdev->usec_timeout; i++) {
2467                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2468                 if (tmp >= n) {
2469                         return 0;
2470                 }
2471                 DRM_UDELAY(1);
2472         }
2473         return -1;
2474 }
2475
2476 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2477 {
2478         unsigned i;
2479         uint32_t tmp;
2480
2481         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2482                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2483                        " Bad things might happen.\n");
2484         }
2485         for (i = 0; i < rdev->usec_timeout; i++) {
2486                 tmp = RREG32(RADEON_RBBM_STATUS);
2487                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2488                         return 0;
2489                 }
2490                 DRM_UDELAY(1);
2491         }
2492         return -1;
2493 }
2494
2495 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2496 {
2497         unsigned i;
2498         uint32_t tmp;
2499
2500         for (i = 0; i < rdev->usec_timeout; i++) {
2501                 /* read MC_STATUS */
2502                 tmp = RREG32(RADEON_MC_STATUS);
2503                 if (tmp & RADEON_MC_IDLE) {
2504                         return 0;
2505                 }
2506                 DRM_UDELAY(1);
2507         }
2508         return -1;
2509 }
2510
2511 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2512 {
2513         u32 rbbm_status;
2514
2515         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2516         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2517                 radeon_ring_lockup_update(ring);
2518                 return false;
2519         }
2520         /* force CP activities */
2521         radeon_ring_force_activity(rdev, ring);
2522         return radeon_ring_test_lockup(rdev, ring);
2523 }
2524
2525 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2526 void r100_enable_bm(struct radeon_device *rdev)
2527 {
2528         uint32_t tmp;
2529         /* Enable bus mastering */
2530         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2531         WREG32(RADEON_BUS_CNTL, tmp);
2532 }
2533
2534 void r100_bm_disable(struct radeon_device *rdev)
2535 {
2536         u32 tmp;
2537
2538         /* disable bus mastering */
2539         tmp = RREG32(R_000030_BUS_CNTL);
2540         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2541         mdelay(1);
2542         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2543         mdelay(1);
2544         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2545         tmp = RREG32(RADEON_BUS_CNTL);
2546         mdelay(1);
2547         pci_clear_master(rdev->pdev);
2548         mdelay(1);
2549 }
2550
2551 int r100_asic_reset(struct radeon_device *rdev)
2552 {
2553         struct r100_mc_save save;
2554         u32 status, tmp;
2555         int ret = 0;
2556
2557         status = RREG32(R_000E40_RBBM_STATUS);
2558         if (!G_000E40_GUI_ACTIVE(status)) {
2559                 return 0;
2560         }
2561         r100_mc_stop(rdev, &save);
2562         status = RREG32(R_000E40_RBBM_STATUS);
2563         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2564         /* stop CP */
2565         WREG32(RADEON_CP_CSQ_CNTL, 0);
2566         tmp = RREG32(RADEON_CP_RB_CNTL);
2567         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2568         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2569         WREG32(RADEON_CP_RB_WPTR, 0);
2570         WREG32(RADEON_CP_RB_CNTL, tmp);
2571         /* save PCI state */
2572         pci_save_state(rdev->pdev);
2573         /* disable bus mastering */
2574         r100_bm_disable(rdev);
2575         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2576                                         S_0000F0_SOFT_RESET_RE(1) |
2577                                         S_0000F0_SOFT_RESET_PP(1) |
2578                                         S_0000F0_SOFT_RESET_RB(1));
2579         RREG32(R_0000F0_RBBM_SOFT_RESET);
2580         mdelay(500);
2581         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2582         mdelay(1);
2583         status = RREG32(R_000E40_RBBM_STATUS);
2584         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2585         /* reset CP */
2586         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2587         RREG32(R_0000F0_RBBM_SOFT_RESET);
2588         mdelay(500);
2589         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2590         mdelay(1);
2591         status = RREG32(R_000E40_RBBM_STATUS);
2592         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2593         /* restore PCI & busmastering */
2594         pci_restore_state(rdev->pdev);
2595         r100_enable_bm(rdev);
2596         /* Check if GPU is idle */
2597         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2598                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2599                 dev_err(rdev->dev, "failed to reset GPU\n");
2600                 ret = -1;
2601         } else
2602                 dev_info(rdev->dev, "GPU reset succeed\n");
2603         r100_mc_resume(rdev, &save);
2604         return ret;
2605 }
2606
2607 void r100_set_common_regs(struct radeon_device *rdev)
2608 {
2609         struct drm_device *dev = rdev->ddev;
2610         bool force_dac2 = false;
2611         u32 tmp;
2612
2613         /* set these so they don't interfere with anything */
2614         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2615         WREG32(RADEON_SUBPIC_CNTL, 0);
2616         WREG32(RADEON_VIPH_CONTROL, 0);
2617         WREG32(RADEON_I2C_CNTL_1, 0);
2618         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2619         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2620         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2621
2622         /* always set up dac2 on rn50 and some rv100 as lots
2623          * of servers seem to wire it up to a VGA port but
2624          * don't report it in the bios connector
2625          * table.
2626          */
2627         switch (dev->pdev->device) {
2628                 /* RN50 */
2629         case 0x515e:
2630         case 0x5969:
2631                 force_dac2 = true;
2632                 break;
2633                 /* RV100*/
2634         case 0x5159:
2635         case 0x515a:
2636                 /* DELL triple head servers */
2637                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2638                     ((dev->pdev->subsystem_device == 0x016c) ||
2639                      (dev->pdev->subsystem_device == 0x016d) ||
2640                      (dev->pdev->subsystem_device == 0x016e) ||
2641                      (dev->pdev->subsystem_device == 0x016f) ||
2642                      (dev->pdev->subsystem_device == 0x0170) ||
2643                      (dev->pdev->subsystem_device == 0x017d) ||
2644                      (dev->pdev->subsystem_device == 0x017e) ||
2645                      (dev->pdev->subsystem_device == 0x0183) ||
2646                      (dev->pdev->subsystem_device == 0x018a) ||
2647                      (dev->pdev->subsystem_device == 0x019a)))
2648                         force_dac2 = true;
2649                 break;
2650         }
2651
2652         if (force_dac2) {
2653                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2654                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2655                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2656
2657                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2658                    enable it, even it's detected.
2659                 */
2660
2661                 /* force it to crtc0 */
2662                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2663                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2664                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2665
2666                 /* set up the TV DAC */
2667                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2668                                  RADEON_TV_DAC_STD_MASK |
2669                                  RADEON_TV_DAC_RDACPD |
2670                                  RADEON_TV_DAC_GDACPD |
2671                                  RADEON_TV_DAC_BDACPD |
2672                                  RADEON_TV_DAC_BGADJ_MASK |
2673                                  RADEON_TV_DAC_DACADJ_MASK);
2674                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2675                                 RADEON_TV_DAC_NHOLD |
2676                                 RADEON_TV_DAC_STD_PS2 |
2677                                 (0x58 << 16));
2678
2679                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2680                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2681                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2682         }
2683
2684         /* switch PM block to ACPI mode */
2685         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2686         tmp &= ~RADEON_PM_MODE_SEL;
2687         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2688
2689 }
2690
2691 /*
2692  * VRAM info
2693  */
2694 static void r100_vram_get_type(struct radeon_device *rdev)
2695 {
2696         uint32_t tmp;
2697
2698         rdev->mc.vram_is_ddr = false;
2699         if (rdev->flags & RADEON_IS_IGP)
2700                 rdev->mc.vram_is_ddr = true;
2701         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2702                 rdev->mc.vram_is_ddr = true;
2703         if ((rdev->family == CHIP_RV100) ||
2704             (rdev->family == CHIP_RS100) ||
2705             (rdev->family == CHIP_RS200)) {
2706                 tmp = RREG32(RADEON_MEM_CNTL);
2707                 if (tmp & RV100_HALF_MODE) {
2708                         rdev->mc.vram_width = 32;
2709                 } else {
2710                         rdev->mc.vram_width = 64;
2711                 }
2712                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2713                         rdev->mc.vram_width /= 4;
2714                         rdev->mc.vram_is_ddr = true;
2715                 }
2716         } else if (rdev->family <= CHIP_RV280) {
2717                 tmp = RREG32(RADEON_MEM_CNTL);
2718                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2719                         rdev->mc.vram_width = 128;
2720                 } else {
2721                         rdev->mc.vram_width = 64;
2722                 }
2723         } else {
2724                 /* newer IGPs */
2725                 rdev->mc.vram_width = 128;
2726         }
2727 }
2728
2729 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2730 {
2731         u32 aper_size;
2732         u8 byte;
2733
2734         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2735
2736         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2737          * that is has the 2nd generation multifunction PCI interface
2738          */
2739         if (rdev->family == CHIP_RV280 ||
2740             rdev->family >= CHIP_RV350) {
2741                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2742                        ~RADEON_HDP_APER_CNTL);
2743                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2744                 return aper_size * 2;
2745         }
2746
2747         /* Older cards have all sorts of funny issues to deal with. First
2748          * check if it's a multifunction card by reading the PCI config
2749          * header type... Limit those to one aperture size
2750          */
2751         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2752         if (byte & 0x80) {
2753                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2754                 DRM_INFO("Limiting VRAM to one aperture\n");
2755                 return aper_size;
2756         }
2757
2758         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2759          * have set it up. We don't write this as it's broken on some ASICs but
2760          * we expect the BIOS to have done the right thing (might be too optimistic...)
2761          */
2762         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2763                 return aper_size * 2;
2764         return aper_size;
2765 }
2766
2767 void r100_vram_init_sizes(struct radeon_device *rdev)
2768 {
2769         u64 config_aper_size;
2770
2771         /* work out accessible VRAM */
2772         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2773         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2774         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2775         /* FIXME we don't use the second aperture yet when we could use it */
2776         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2777                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2778         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2779         if (rdev->flags & RADEON_IS_IGP) {
2780                 uint32_t tom;
2781                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2782                 tom = RREG32(RADEON_NB_TOM);
2783                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2784                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2785                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2786         } else {
2787                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2788                 /* Some production boards of m6 will report 0
2789                  * if it's 8 MB
2790                  */
2791                 if (rdev->mc.real_vram_size == 0) {
2792                         rdev->mc.real_vram_size = 8192 * 1024;
2793                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2794                 }
2795                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2796                  * Novell bug 204882 + along with lots of ubuntu ones
2797                  */
2798                 if (rdev->mc.aper_size > config_aper_size)
2799                         config_aper_size = rdev->mc.aper_size;
2800
2801                 if (config_aper_size > rdev->mc.real_vram_size)
2802                         rdev->mc.mc_vram_size = config_aper_size;
2803                 else
2804                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2805         }
2806 }
2807
2808 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2809 {
2810         uint32_t temp;
2811
2812         temp = RREG32(RADEON_CONFIG_CNTL);
2813         if (state == false) {
2814                 temp &= ~RADEON_CFG_VGA_RAM_EN;
2815                 temp |= RADEON_CFG_VGA_IO_DIS;
2816         } else {
2817                 temp &= ~RADEON_CFG_VGA_IO_DIS;
2818         }
2819         WREG32(RADEON_CONFIG_CNTL, temp);
2820 }
2821
2822 void r100_mc_init(struct radeon_device *rdev)
2823 {
2824         u64 base;
2825
2826         r100_vram_get_type(rdev);
2827         r100_vram_init_sizes(rdev);
2828         base = rdev->mc.aper_base;
2829         if (rdev->flags & RADEON_IS_IGP)
2830                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2831         radeon_vram_location(rdev, &rdev->mc, base);
2832         rdev->mc.gtt_base_align = 0;
2833         if (!(rdev->flags & RADEON_IS_AGP))
2834                 radeon_gtt_location(rdev, &rdev->mc);
2835         radeon_update_bandwidth_info(rdev);
2836 }
2837
2838
2839 /*
2840  * Indirect registers accessor
2841  */
2842 void r100_pll_errata_after_index(struct radeon_device *rdev)
2843 {
2844         if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2845                 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2846                 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2847         }
2848 }
2849
2850 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2851 {
2852         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2853          * or the chip could hang on a subsequent access
2854          */
2855         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2856                 mdelay(5);
2857         }
2858
2859         /* This function is required to workaround a hardware bug in some (all?)
2860          * revisions of the R300.  This workaround should be called after every
2861          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2862          * may not be correct.
2863          */
2864         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2865                 uint32_t save, tmp;
2866
2867                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2868                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2869                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2870                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2871                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2872         }
2873 }
2874
2875 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2876 {
2877         uint32_t data;
2878
2879         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2880         r100_pll_errata_after_index(rdev);
2881         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2882         r100_pll_errata_after_data(rdev);
2883         return data;
2884 }
2885
2886 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2887 {
2888         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2889         r100_pll_errata_after_index(rdev);
2890         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2891         r100_pll_errata_after_data(rdev);
2892 }
2893
2894 void r100_set_safe_registers(struct radeon_device *rdev)
2895 {
2896         if (ASIC_IS_RN50(rdev)) {
2897                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2898                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2899         } else if (rdev->family < CHIP_R200) {
2900                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2901                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2902         } else {
2903                 r200_set_safe_registers(rdev);
2904         }
2905 }
2906
2907 /*
2908  * Debugfs info
2909  */
2910 #if defined(CONFIG_DEBUG_FS)
2911 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2912 {
2913         struct drm_info_node *node = (struct drm_info_node *) m->private;
2914         struct drm_device *dev = node->minor->dev;
2915         struct radeon_device *rdev = dev->dev_private;
2916         uint32_t reg, value;
2917         unsigned i;
2918
2919         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2920         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2921         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2922         for (i = 0; i < 64; i++) {
2923                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2924                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2925                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2926                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2927                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2928         }
2929         return 0;
2930 }
2931
2932 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2933 {
2934         struct drm_info_node *node = (struct drm_info_node *) m->private;
2935         struct drm_device *dev = node->minor->dev;
2936         struct radeon_device *rdev = dev->dev_private;
2937         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2938         uint32_t rdp, wdp;
2939         unsigned count, i, j;
2940
2941         radeon_ring_free_size(rdev, ring);
2942         rdp = RREG32(RADEON_CP_RB_RPTR);
2943         wdp = RREG32(RADEON_CP_RB_WPTR);
2944         count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2945         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2946         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2947         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2948         seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2949         seq_printf(m, "%u dwords in ring\n", count);
2950         for (j = 0; j <= count; j++) {
2951                 i = (rdp + j) & ring->ptr_mask;
2952                 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2953         }
2954         return 0;
2955 }
2956
2957
2958 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2959 {
2960         struct drm_info_node *node = (struct drm_info_node *) m->private;
2961         struct drm_device *dev = node->minor->dev;
2962         struct radeon_device *rdev = dev->dev_private;
2963         uint32_t csq_stat, csq2_stat, tmp;
2964         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2965         unsigned i;
2966
2967         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2968         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2969         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2970         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2971         r_rptr = (csq_stat >> 0) & 0x3ff;
2972         r_wptr = (csq_stat >> 10) & 0x3ff;
2973         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2974         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2975         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2976         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2977         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2978         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2979         seq_printf(m, "Ring rptr %u\n", r_rptr);
2980         seq_printf(m, "Ring wptr %u\n", r_wptr);
2981         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2982         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2983         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2984         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2985         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2986          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2987         seq_printf(m, "Ring fifo:\n");
2988         for (i = 0; i < 256; i++) {
2989                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2990                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2991                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2992         }
2993         seq_printf(m, "Indirect1 fifo:\n");
2994         for (i = 256; i <= 512; i++) {
2995                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2996                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2997                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2998         }
2999         seq_printf(m, "Indirect2 fifo:\n");
3000         for (i = 640; i < ib1_wptr; i++) {
3001                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3002                 tmp = RREG32(RADEON_CP_CSQ_DATA);
3003                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3004         }
3005         return 0;
3006 }
3007
3008 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3009 {
3010         struct drm_info_node *node = (struct drm_info_node *) m->private;
3011         struct drm_device *dev = node->minor->dev;
3012         struct radeon_device *rdev = dev->dev_private;
3013         uint32_t tmp;
3014
3015         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3016         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3017         tmp = RREG32(RADEON_MC_FB_LOCATION);
3018         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3019         tmp = RREG32(RADEON_BUS_CNTL);
3020         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3021         tmp = RREG32(RADEON_MC_AGP_LOCATION);
3022         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3023         tmp = RREG32(RADEON_AGP_BASE);
3024         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3025         tmp = RREG32(RADEON_HOST_PATH_CNTL);
3026         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3027         tmp = RREG32(0x01D0);
3028         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3029         tmp = RREG32(RADEON_AIC_LO_ADDR);
3030         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3031         tmp = RREG32(RADEON_AIC_HI_ADDR);
3032         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3033         tmp = RREG32(0x01E4);
3034         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3035         return 0;
3036 }
3037
3038 static struct drm_info_list r100_debugfs_rbbm_list[] = {
3039         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3040 };
3041
3042 static struct drm_info_list r100_debugfs_cp_list[] = {
3043         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3044         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3045 };
3046
3047 static struct drm_info_list r100_debugfs_mc_info_list[] = {
3048         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3049 };
3050 #endif
3051
3052 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3053 {
3054 #if defined(CONFIG_DEBUG_FS)
3055         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3056 #else
3057         return 0;
3058 #endif
3059 }
3060
3061 int r100_debugfs_cp_init(struct radeon_device *rdev)
3062 {
3063 #if defined(CONFIG_DEBUG_FS)
3064         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3065 #else
3066         return 0;
3067 #endif
3068 }
3069
3070 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3071 {
3072 #if defined(CONFIG_DEBUG_FS)
3073         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3074 #else
3075         return 0;
3076 #endif
3077 }
3078
3079 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3080                          uint32_t tiling_flags, uint32_t pitch,
3081                          uint32_t offset, uint32_t obj_size)
3082 {
3083         int surf_index = reg * 16;
3084         int flags = 0;
3085
3086         if (rdev->family <= CHIP_RS200) {
3087                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3088                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3089                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
3090                 if (tiling_flags & RADEON_TILING_MACRO)
3091                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
3092         } else if (rdev->family <= CHIP_RV280) {
3093                 if (tiling_flags & (RADEON_TILING_MACRO))
3094                         flags |= R200_SURF_TILE_COLOR_MACRO;
3095                 if (tiling_flags & RADEON_TILING_MICRO)
3096                         flags |= R200_SURF_TILE_COLOR_MICRO;
3097         } else {
3098                 if (tiling_flags & RADEON_TILING_MACRO)
3099                         flags |= R300_SURF_TILE_MACRO;
3100                 if (tiling_flags & RADEON_TILING_MICRO)
3101                         flags |= R300_SURF_TILE_MICRO;
3102         }
3103
3104         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3105                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3106         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3107                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3108
3109         /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
3110         if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
3111                 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
3112                         if (ASIC_IS_RN50(rdev))
3113                                 pitch /= 16;
3114         }
3115
3116         /* r100/r200 divide by 16 */
3117         if (rdev->family < CHIP_R300)
3118                 flags |= pitch / 16;
3119         else
3120                 flags |= pitch / 8;
3121
3122
3123         DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3124         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3125         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3126         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3127         return 0;
3128 }
3129
3130 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3131 {
3132         int surf_index = reg * 16;
3133         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3134 }
3135
3136 void r100_bandwidth_update(struct radeon_device *rdev)
3137 {
3138         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3139         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3140         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3141         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3142         fixed20_12 memtcas_ff[8] = {
3143                 dfixed_init(1),
3144                 dfixed_init(2),
3145                 dfixed_init(3),
3146                 dfixed_init(0),
3147                 dfixed_init_half(1),
3148                 dfixed_init_half(2),
3149                 dfixed_init(0),
3150         };
3151         fixed20_12 memtcas_rs480_ff[8] = {
3152                 dfixed_init(0),
3153                 dfixed_init(1),
3154                 dfixed_init(2),
3155                 dfixed_init(3),
3156                 dfixed_init(0),
3157                 dfixed_init_half(1),
3158                 dfixed_init_half(2),
3159                 dfixed_init_half(3),
3160         };
3161         fixed20_12 memtcas2_ff[8] = {
3162                 dfixed_init(0),
3163                 dfixed_init(1),
3164                 dfixed_init(2),
3165                 dfixed_init(3),
3166                 dfixed_init(4),
3167                 dfixed_init(5),
3168                 dfixed_init(6),
3169                 dfixed_init(7),
3170         };
3171         fixed20_12 memtrbs[8] = {
3172                 dfixed_init(1),
3173                 dfixed_init_half(1),
3174                 dfixed_init(2),
3175                 dfixed_init_half(2),
3176                 dfixed_init(3),
3177                 dfixed_init_half(3),
3178                 dfixed_init(4),
3179                 dfixed_init_half(4)
3180         };
3181         fixed20_12 memtrbs_r4xx[8] = {
3182                 dfixed_init(4),
3183                 dfixed_init(5),
3184                 dfixed_init(6),
3185                 dfixed_init(7),
3186                 dfixed_init(8),
3187                 dfixed_init(9),
3188                 dfixed_init(10),
3189                 dfixed_init(11)
3190         };
3191         fixed20_12 min_mem_eff;
3192         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3193         fixed20_12 cur_latency_mclk, cur_latency_sclk;
3194         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3195                 disp_drain_rate2, read_return_rate;
3196         fixed20_12 time_disp1_drop_priority;
3197         int c;
3198         int cur_size = 16;       /* in octawords */
3199         int critical_point = 0, critical_point2;
3200 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
3201         int stop_req, max_stop_req;
3202         struct drm_display_mode *mode1 = NULL;
3203         struct drm_display_mode *mode2 = NULL;
3204         uint32_t pixel_bytes1 = 0;
3205         uint32_t pixel_bytes2 = 0;
3206
3207         radeon_update_display_priority(rdev);
3208
3209         if (rdev->mode_info.crtcs[0]->base.enabled) {
3210                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3211                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
3212         }
3213         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3214                 if (rdev->mode_info.crtcs[1]->base.enabled) {
3215                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3216                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
3217                 }
3218         }
3219
3220         min_mem_eff.full = dfixed_const_8(0);
3221         /* get modes */
3222         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3223                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3224                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3225                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3226                 /* check crtc enables */
3227                 if (mode2)
3228                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3229                 if (mode1)
3230                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3231                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3232         }
3233
3234         /*
3235          * determine is there is enough bw for current mode
3236          */
3237         sclk_ff = rdev->pm.sclk;
3238         mclk_ff = rdev->pm.mclk;
3239
3240         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3241         temp_ff.full = dfixed_const(temp);
3242         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3243
3244         pix_clk.full = 0;
3245         pix_clk2.full = 0;
3246         peak_disp_bw.full = 0;
3247         if (mode1) {
3248                 temp_ff.full = dfixed_const(1000);
3249                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3250                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3251                 temp_ff.full = dfixed_const(pixel_bytes1);
3252                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3253         }
3254         if (mode2) {
3255                 temp_ff.full = dfixed_const(1000);
3256                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3257                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3258                 temp_ff.full = dfixed_const(pixel_bytes2);
3259                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3260         }
3261
3262         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3263         if (peak_disp_bw.full >= mem_bw.full) {
3264                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3265                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3266         }
3267
3268         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
3269         temp = RREG32(RADEON_MEM_TIMING_CNTL);
3270         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3271                 mem_trcd = ((temp >> 2) & 0x3) + 1;
3272                 mem_trp  = ((temp & 0x3)) + 1;
3273                 mem_tras = ((temp & 0x70) >> 4) + 1;
3274         } else if (rdev->family == CHIP_R300 ||
3275                    rdev->family == CHIP_R350) { /* r300, r350 */
3276                 mem_trcd = (temp & 0x7) + 1;
3277                 mem_trp = ((temp >> 8) & 0x7) + 1;
3278                 mem_tras = ((temp >> 11) & 0xf) + 4;
3279         } else if (rdev->family == CHIP_RV350 ||
3280                    rdev->family <= CHIP_RV380) {
3281                 /* rv3x0 */
3282                 mem_trcd = (temp & 0x7) + 3;
3283                 mem_trp = ((temp >> 8) & 0x7) + 3;
3284                 mem_tras = ((temp >> 11) & 0xf) + 6;
3285         } else if (rdev->family == CHIP_R420 ||
3286                    rdev->family == CHIP_R423 ||
3287                    rdev->family == CHIP_RV410) {
3288                 /* r4xx */
3289                 mem_trcd = (temp & 0xf) + 3;
3290                 if (mem_trcd > 15)
3291                         mem_trcd = 15;
3292                 mem_trp = ((temp >> 8) & 0xf) + 3;
3293                 if (mem_trp > 15)
3294                         mem_trp = 15;
3295                 mem_tras = ((temp >> 12) & 0x1f) + 6;
3296                 if (mem_tras > 31)
3297                         mem_tras = 31;
3298         } else { /* RV200, R200 */
3299                 mem_trcd = (temp & 0x7) + 1;
3300                 mem_trp = ((temp >> 8) & 0x7) + 1;
3301                 mem_tras = ((temp >> 12) & 0xf) + 4;
3302         }
3303         /* convert to FF */
3304         trcd_ff.full = dfixed_const(mem_trcd);
3305         trp_ff.full = dfixed_const(mem_trp);
3306         tras_ff.full = dfixed_const(mem_tras);
3307
3308         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3309         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3310         data = (temp & (7 << 20)) >> 20;
3311         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3312                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3313                         tcas_ff = memtcas_rs480_ff[data];
3314                 else
3315                         tcas_ff = memtcas_ff[data];
3316         } else
3317                 tcas_ff = memtcas2_ff[data];
3318
3319         if (rdev->family == CHIP_RS400 ||
3320             rdev->family == CHIP_RS480) {
3321                 /* extra cas latency stored in bits 23-25 0-4 clocks */
3322                 data = (temp >> 23) & 0x7;
3323                 if (data < 5)
3324                         tcas_ff.full += dfixed_const(data);
3325         }
3326
3327         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3328                 /* on the R300, Tcas is included in Trbs.
3329                  */
3330                 temp = RREG32(RADEON_MEM_CNTL);
3331                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3332                 if (data == 1) {
3333                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
3334                                 temp = RREG32(R300_MC_IND_INDEX);
3335                                 temp &= ~R300_MC_IND_ADDR_MASK;
3336                                 temp |= R300_MC_READ_CNTL_CD_mcind;
3337                                 WREG32(R300_MC_IND_INDEX, temp);
3338                                 temp = RREG32(R300_MC_IND_DATA);
3339                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3340                         } else {
3341                                 temp = RREG32(R300_MC_READ_CNTL_AB);
3342                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3343                         }
3344                 } else {
3345                         temp = RREG32(R300_MC_READ_CNTL_AB);
3346                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3347                 }
3348                 if (rdev->family == CHIP_RV410 ||
3349                     rdev->family == CHIP_R420 ||
3350                     rdev->family == CHIP_R423)
3351                         trbs_ff = memtrbs_r4xx[data];
3352                 else
3353                         trbs_ff = memtrbs[data];
3354                 tcas_ff.full += trbs_ff.full;
3355         }
3356
3357         sclk_eff_ff.full = sclk_ff.full;
3358
3359         if (rdev->flags & RADEON_IS_AGP) {
3360                 fixed20_12 agpmode_ff;
3361                 agpmode_ff.full = dfixed_const(radeon_agpmode);
3362                 temp_ff.full = dfixed_const_666(16);
3363                 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3364         }
3365         /* TODO PCIE lanes may affect this - agpmode == 16?? */
3366
3367         if (ASIC_IS_R300(rdev)) {
3368                 sclk_delay_ff.full = dfixed_const(250);
3369         } else {
3370                 if ((rdev->family == CHIP_RV100) ||
3371                     rdev->flags & RADEON_IS_IGP) {
3372                         if (rdev->mc.vram_is_ddr)
3373                                 sclk_delay_ff.full = dfixed_const(41);
3374                         else
3375                                 sclk_delay_ff.full = dfixed_const(33);
3376                 } else {
3377                         if (rdev->mc.vram_width == 128)
3378                                 sclk_delay_ff.full = dfixed_const(57);
3379                         else
3380                                 sclk_delay_ff.full = dfixed_const(41);
3381                 }
3382         }
3383
3384         mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3385
3386         if (rdev->mc.vram_is_ddr) {
3387                 if (rdev->mc.vram_width == 32) {
3388                         k1.full = dfixed_const(40);
3389                         c  = 3;
3390                 } else {
3391                         k1.full = dfixed_const(20);
3392                         c  = 1;
3393                 }
3394         } else {
3395                 k1.full = dfixed_const(40);
3396                 c  = 3;
3397         }
3398
3399         temp_ff.full = dfixed_const(2);
3400         mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3401         temp_ff.full = dfixed_const(c);
3402         mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3403         temp_ff.full = dfixed_const(4);
3404         mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3405         mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3406         mc_latency_mclk.full += k1.full;
3407
3408         mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3409         mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3410
3411         /*
3412           HW cursor time assuming worst case of full size colour cursor.
3413         */
3414         temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3415         temp_ff.full += trcd_ff.full;
3416         if (temp_ff.full < tras_ff.full)
3417                 temp_ff.full = tras_ff.full;
3418         cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3419
3420         temp_ff.full = dfixed_const(cur_size);
3421         cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3422         /*
3423           Find the total latency for the display data.
3424         */
3425         disp_latency_overhead.full = dfixed_const(8);
3426         disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3427         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3428         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3429
3430         if (mc_latency_mclk.full > mc_latency_sclk.full)
3431                 disp_latency.full = mc_latency_mclk.full;
3432         else
3433                 disp_latency.full = mc_latency_sclk.full;
3434
3435         /* setup Max GRPH_STOP_REQ default value */
3436         if (ASIC_IS_RV100(rdev))
3437                 max_stop_req = 0x5c;
3438         else
3439                 max_stop_req = 0x7c;
3440
3441         if (mode1) {
3442                 /*  CRTC1
3443                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3444                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3445                 */
3446                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3447
3448                 if (stop_req > max_stop_req)
3449                         stop_req = max_stop_req;
3450
3451                 /*
3452                   Find the drain rate of the display buffer.
3453                 */
3454                 temp_ff.full = dfixed_const((16/pixel_bytes1));
3455                 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3456
3457                 /*
3458                   Find the critical point of the display buffer.
3459                 */
3460                 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3461                 crit_point_ff.full += dfixed_const_half(0);
3462
3463                 critical_point = dfixed_trunc(crit_point_ff);
3464
3465                 if (rdev->disp_priority == 2) {
3466                         critical_point = 0;
3467                 }
3468
3469                 /*
3470                   The critical point should never be above max_stop_req-4.  Setting
3471                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3472                 */
3473                 if (max_stop_req - critical_point < 4)
3474                         critical_point = 0;
3475
3476                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3477                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3478                         critical_point = 0x10;
3479                 }
3480
3481                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3482                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3483                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3484                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3485                 if ((rdev->family == CHIP_R350) &&
3486                     (stop_req > 0x15)) {
3487                         stop_req -= 0x10;
3488                 }
3489                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3490                 temp |= RADEON_GRPH_BUFFER_SIZE;
3491                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3492                           RADEON_GRPH_CRITICAL_AT_SOF |
3493                           RADEON_GRPH_STOP_CNTL);
3494                 /*
3495                   Write the result into the register.
3496                 */
3497                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3498                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3499
3500 #if 0
3501                 if ((rdev->family == CHIP_RS400) ||
3502                     (rdev->family == CHIP_RS480)) {
3503                         /* attempt to program RS400 disp regs correctly ??? */
3504                         temp = RREG32(RS400_DISP1_REG_CNTL);
3505                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3506                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3507                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3508                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3509                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3510                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3511                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3512                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3513                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3514                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3515                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3516                 }
3517 #endif
3518
3519                 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3520                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3521                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3522         }
3523
3524         if (mode2) {
3525                 u32 grph2_cntl;
3526                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3527
3528                 if (stop_req > max_stop_req)
3529                         stop_req = max_stop_req;
3530
3531                 /*
3532                   Find the drain rate of the display buffer.
3533                 */
3534                 temp_ff.full = dfixed_const((16/pixel_bytes2));
3535                 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3536
3537                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3538                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3539                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3540                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3541                 if ((rdev->family == CHIP_R350) &&
3542                     (stop_req > 0x15)) {
3543                         stop_req -= 0x10;
3544                 }
3545                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3546                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3547                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3548                           RADEON_GRPH_CRITICAL_AT_SOF |
3549                           RADEON_GRPH_STOP_CNTL);
3550
3551                 if ((rdev->family == CHIP_RS100) ||
3552                     (rdev->family == CHIP_RS200))
3553                         critical_point2 = 0;
3554                 else {
3555                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3556                         temp_ff.full = dfixed_const(temp);
3557                         temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3558                         if (sclk_ff.full < temp_ff.full)
3559                                 temp_ff.full = sclk_ff.full;
3560
3561                         read_return_rate.full = temp_ff.full;
3562
3563                         if (mode1) {
3564                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3565                                 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3566                         } else {
3567                                 time_disp1_drop_priority.full = 0;
3568                         }
3569                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3570                         crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3571                         crit_point_ff.full += dfixed_const_half(0);
3572
3573                         critical_point2 = dfixed_trunc(crit_point_ff);
3574
3575                         if (rdev->disp_priority == 2) {
3576                                 critical_point2 = 0;
3577                         }
3578
3579                         if (max_stop_req - critical_point2 < 4)
3580                                 critical_point2 = 0;
3581
3582                 }
3583
3584                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3585                         /* some R300 cards have problem with this set to 0 */
3586                         critical_point2 = 0x10;
3587                 }
3588
3589                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3590                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3591
3592                 if ((rdev->family == CHIP_RS400) ||
3593                     (rdev->family == CHIP_RS480)) {
3594 #if 0
3595                         /* attempt to program RS400 disp2 regs correctly ??? */
3596                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3597                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3598                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3599                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3600                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3601                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3602                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3603                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3604                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3605                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3606                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3607                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3608 #endif
3609                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3610                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3611                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3612                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3613                 }
3614
3615                 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3616                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3617         }
3618 }
3619
3620 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3621 {
3622         uint32_t scratch;
3623         uint32_t tmp = 0;
3624         unsigned i;
3625         int r;
3626
3627         r = radeon_scratch_get(rdev, &scratch);
3628         if (r) {
3629                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3630                 return r;
3631         }
3632         WREG32(scratch, 0xCAFEDEAD);
3633         r = radeon_ring_lock(rdev, ring, 2);
3634         if (r) {
3635                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3636                 radeon_scratch_free(rdev, scratch);
3637                 return r;
3638         }
3639         radeon_ring_write(ring, PACKET0(scratch, 0));
3640         radeon_ring_write(ring, 0xDEADBEEF);
3641         radeon_ring_unlock_commit(rdev, ring);
3642         for (i = 0; i < rdev->usec_timeout; i++) {
3643                 tmp = RREG32(scratch);
3644                 if (tmp == 0xDEADBEEF) {
3645                         break;
3646                 }
3647                 DRM_UDELAY(1);
3648         }
3649         if (i < rdev->usec_timeout) {
3650                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3651         } else {
3652                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3653                           scratch, tmp);
3654                 r = -EINVAL;
3655         }
3656         radeon_scratch_free(rdev, scratch);
3657         return r;
3658 }
3659
3660 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3661 {
3662         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3663
3664         radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3665         radeon_ring_write(ring, ib->gpu_addr);
3666         radeon_ring_write(ring, ib->length_dw);
3667 }
3668
3669 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3670 {
3671         struct radeon_ib ib;
3672         uint32_t scratch;
3673         uint32_t tmp = 0;
3674         unsigned i;
3675         int r;
3676
3677         r = radeon_scratch_get(rdev, &scratch);
3678         if (r) {
3679                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3680                 return r;
3681         }
3682         WREG32(scratch, 0xCAFEDEAD);
3683         r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, 256);
3684         if (r) {
3685                 return r;
3686         }
3687         ib.ptr[0] = PACKET0(scratch, 0);
3688         ib.ptr[1] = 0xDEADBEEF;
3689         ib.ptr[2] = PACKET2(0);
3690         ib.ptr[3] = PACKET2(0);
3691         ib.ptr[4] = PACKET2(0);
3692         ib.ptr[5] = PACKET2(0);
3693         ib.ptr[6] = PACKET2(0);
3694         ib.ptr[7] = PACKET2(0);
3695         ib.length_dw = 8;
3696         r = radeon_ib_schedule(rdev, &ib);
3697         if (r) {
3698                 radeon_scratch_free(rdev, scratch);
3699                 radeon_ib_free(rdev, &ib);
3700                 return r;
3701         }
3702         r = radeon_fence_wait(ib.fence, false);
3703         if (r) {
3704                 return r;
3705         }
3706         for (i = 0; i < rdev->usec_timeout; i++) {
3707                 tmp = RREG32(scratch);
3708                 if (tmp == 0xDEADBEEF) {
3709                         break;
3710                 }
3711                 DRM_UDELAY(1);
3712         }
3713         if (i < rdev->usec_timeout) {
3714                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3715         } else {
3716                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3717                           scratch, tmp);
3718                 r = -EINVAL;
3719         }
3720         radeon_scratch_free(rdev, scratch);
3721         radeon_ib_free(rdev, &ib);
3722         return r;
3723 }
3724
3725 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3726 {
3727         /* Shutdown CP we shouldn't need to do that but better be safe than
3728          * sorry
3729          */
3730         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3731         WREG32(R_000740_CP_CSQ_CNTL, 0);
3732
3733         /* Save few CRTC registers */
3734         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3735         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3736         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3737         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3738         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3739                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3740                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3741         }
3742
3743         /* Disable VGA aperture access */
3744         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3745         /* Disable cursor, overlay, crtc */
3746         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3747         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3748                                         S_000054_CRTC_DISPLAY_DIS(1));
3749         WREG32(R_000050_CRTC_GEN_CNTL,
3750                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3751                         S_000050_CRTC_DISP_REQ_EN_B(1));
3752         WREG32(R_000420_OV0_SCALE_CNTL,
3753                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3754         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3755         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3756                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3757                                                 S_000360_CUR2_LOCK(1));
3758                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3759                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3760                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3761                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3762                 WREG32(R_000360_CUR2_OFFSET,
3763                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3764         }
3765 }
3766
3767 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3768 {
3769         /* Update base address for crtc */
3770         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3771         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3772                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3773         }
3774         /* Restore CRTC registers */
3775         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3776         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3777         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3778         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3779                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3780         }
3781 }
3782
3783 void r100_vga_render_disable(struct radeon_device *rdev)
3784 {
3785         u32 tmp;
3786
3787         tmp = RREG8(R_0003C2_GENMO_WT);
3788         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3789 }
3790
3791 static void r100_debugfs(struct radeon_device *rdev)
3792 {
3793         int r;
3794
3795         r = r100_debugfs_mc_info_init(rdev);
3796         if (r)
3797                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3798 }
3799
3800 static void r100_mc_program(struct radeon_device *rdev)
3801 {
3802         struct r100_mc_save save;
3803
3804         /* Stops all mc clients */
3805         r100_mc_stop(rdev, &save);
3806         if (rdev->flags & RADEON_IS_AGP) {
3807                 WREG32(R_00014C_MC_AGP_LOCATION,
3808                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3809                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3810                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3811                 if (rdev->family > CHIP_RV200)
3812                         WREG32(R_00015C_AGP_BASE_2,
3813                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3814         } else {
3815                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3816                 WREG32(R_000170_AGP_BASE, 0);
3817                 if (rdev->family > CHIP_RV200)
3818                         WREG32(R_00015C_AGP_BASE_2, 0);
3819         }
3820         /* Wait for mc idle */
3821         if (r100_mc_wait_for_idle(rdev))
3822                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3823         /* Program MC, should be a 32bits limited address space */
3824         WREG32(R_000148_MC_FB_LOCATION,
3825                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3826                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3827         r100_mc_resume(rdev, &save);
3828 }
3829
3830 void r100_clock_startup(struct radeon_device *rdev)
3831 {
3832         u32 tmp;
3833
3834         if (radeon_dynclks != -1 && radeon_dynclks)
3835                 radeon_legacy_set_clock_gating(rdev, 1);
3836         /* We need to force on some of the block */
3837         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3838         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3839         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3840                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3841         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3842 }
3843
3844 static int r100_startup(struct radeon_device *rdev)
3845 {
3846         int r;
3847
3848         /* set common regs */
3849         r100_set_common_regs(rdev);
3850         /* program mc */
3851         r100_mc_program(rdev);
3852         /* Resume clock */
3853         r100_clock_startup(rdev);
3854         /* Initialize GART (initialize after TTM so we can allocate
3855          * memory through TTM but finalize after TTM) */
3856         r100_enable_bm(rdev);
3857         if (rdev->flags & RADEON_IS_PCI) {
3858                 r = r100_pci_gart_enable(rdev);
3859                 if (r)
3860                         return r;
3861         }
3862
3863         /* allocate wb buffer */
3864         r = radeon_wb_init(rdev);
3865         if (r)
3866                 return r;
3867
3868         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3869         if (r) {
3870                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3871                 return r;
3872         }
3873
3874         /* Enable IRQ */
3875         r100_irq_set(rdev);
3876         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3877         /* 1M ring buffer */
3878         r = r100_cp_init(rdev, 1024 * 1024);
3879         if (r) {
3880                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3881                 return r;
3882         }
3883
3884         r = radeon_ib_pool_init(rdev);
3885         if (r) {
3886                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3887                 return r;
3888         }
3889
3890         return 0;
3891 }
3892
3893 int r100_resume(struct radeon_device *rdev)
3894 {
3895         int r;
3896
3897         /* Make sur GART are not working */
3898         if (rdev->flags & RADEON_IS_PCI)
3899                 r100_pci_gart_disable(rdev);
3900         /* Resume clock before doing reset */
3901         r100_clock_startup(rdev);
3902         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3903         if (radeon_asic_reset(rdev)) {
3904                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3905                         RREG32(R_000E40_RBBM_STATUS),
3906                         RREG32(R_0007C0_CP_STAT));
3907         }
3908         /* post */
3909         radeon_combios_asic_init(rdev->ddev);
3910         /* Resume clock after posting */
3911         r100_clock_startup(rdev);
3912         /* Initialize surface registers */
3913         radeon_surface_init(rdev);
3914
3915         rdev->accel_working = true;
3916         r = r100_startup(rdev);
3917         if (r) {
3918                 rdev->accel_working = false;
3919         }
3920         return r;
3921 }
3922
3923 int r100_suspend(struct radeon_device *rdev)
3924 {
3925         r100_cp_disable(rdev);
3926         radeon_wb_disable(rdev);
3927         r100_irq_disable(rdev);
3928         if (rdev->flags & RADEON_IS_PCI)
3929                 r100_pci_gart_disable(rdev);
3930         return 0;
3931 }
3932
3933 void r100_fini(struct radeon_device *rdev)
3934 {
3935         r100_cp_fini(rdev);
3936         radeon_wb_fini(rdev);
3937         radeon_ib_pool_fini(rdev);
3938         radeon_gem_fini(rdev);
3939         if (rdev->flags & RADEON_IS_PCI)
3940                 r100_pci_gart_fini(rdev);
3941         radeon_agp_fini(rdev);
3942         radeon_irq_kms_fini(rdev);
3943         radeon_fence_driver_fini(rdev);
3944         radeon_bo_fini(rdev);
3945         radeon_atombios_fini(rdev);
3946         kfree(rdev->bios);
3947         rdev->bios = NULL;
3948 }
3949
3950 /*
3951  * Due to how kexec works, it can leave the hw fully initialised when it
3952  * boots the new kernel. However doing our init sequence with the CP and
3953  * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3954  * do some quick sanity checks and restore sane values to avoid this
3955  * problem.
3956  */
3957 void r100_restore_sanity(struct radeon_device *rdev)
3958 {
3959         u32 tmp;
3960
3961         tmp = RREG32(RADEON_CP_CSQ_CNTL);
3962         if (tmp) {
3963                 WREG32(RADEON_CP_CSQ_CNTL, 0);
3964         }
3965         tmp = RREG32(RADEON_CP_RB_CNTL);
3966         if (tmp) {
3967                 WREG32(RADEON_CP_RB_CNTL, 0);
3968         }
3969         tmp = RREG32(RADEON_SCRATCH_UMSK);
3970         if (tmp) {
3971                 WREG32(RADEON_SCRATCH_UMSK, 0);
3972         }
3973 }
3974
3975 int r100_init(struct radeon_device *rdev)
3976 {
3977         int r;
3978
3979         /* Register debugfs file specific to this group of asics */
3980         r100_debugfs(rdev);
3981         /* Disable VGA */
3982         r100_vga_render_disable(rdev);
3983         /* Initialize scratch registers */
3984         radeon_scratch_init(rdev);
3985         /* Initialize surface registers */
3986         radeon_surface_init(rdev);
3987         /* sanity check some register to avoid hangs like after kexec */
3988         r100_restore_sanity(rdev);
3989         /* TODO: disable VGA need to use VGA request */
3990         /* BIOS*/
3991         if (!radeon_get_bios(rdev)) {
3992                 if (ASIC_IS_AVIVO(rdev))
3993                         return -EINVAL;
3994         }
3995         if (rdev->is_atom_bios) {
3996                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3997                 return -EINVAL;
3998         } else {
3999                 r = radeon_combios_init(rdev);
4000                 if (r)
4001                         return r;
4002         }
4003         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4004         if (radeon_asic_reset(rdev)) {
4005                 dev_warn(rdev->dev,
4006                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4007                         RREG32(R_000E40_RBBM_STATUS),
4008                         RREG32(R_0007C0_CP_STAT));
4009         }
4010         /* check if cards are posted or not */
4011         if (radeon_boot_test_post_card(rdev) == false)
4012                 return -EINVAL;
4013         /* Set asic errata */
4014         r100_errata(rdev);
4015         /* Initialize clocks */
4016         radeon_get_clock_info(rdev->ddev);
4017         /* initialize AGP */
4018         if (rdev->flags & RADEON_IS_AGP) {
4019                 r = radeon_agp_init(rdev);
4020                 if (r) {
4021                         radeon_agp_disable(rdev);
4022                 }
4023         }
4024         /* initialize VRAM */
4025         r100_mc_init(rdev);
4026         /* Fence driver */
4027         r = radeon_fence_driver_init(rdev);
4028         if (r)
4029                 return r;
4030         r = radeon_irq_kms_init(rdev);
4031         if (r)
4032                 return r;
4033         /* Memory manager */
4034         r = radeon_bo_init(rdev);
4035         if (r)
4036                 return r;
4037         if (rdev->flags & RADEON_IS_PCI) {
4038                 r = r100_pci_gart_init(rdev);
4039                 if (r)
4040                         return r;
4041         }
4042         r100_set_safe_registers(rdev);
4043
4044         rdev->accel_working = true;
4045         r = r100_startup(rdev);
4046         if (r) {
4047                 /* Somethings want wront with the accel init stop accel */
4048                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4049                 r100_cp_fini(rdev);
4050                 radeon_wb_fini(rdev);
4051                 radeon_ib_pool_fini(rdev);
4052                 radeon_irq_kms_fini(rdev);
4053                 if (rdev->flags & RADEON_IS_PCI)
4054                         r100_pci_gart_fini(rdev);
4055                 rdev->accel_working = false;
4056         }
4057         return 0;
4058 }
4059
4060 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
4061 {
4062         if (reg < rdev->rmmio_size)
4063                 return readl(((void __iomem *)rdev->rmmio) + reg);
4064         else {
4065                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4066                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4067         }
4068 }
4069
4070 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4071 {
4072         if (reg < rdev->rmmio_size)
4073                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4074         else {
4075                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4076                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4077         }
4078 }
4079
4080 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4081 {
4082         if (reg < rdev->rio_mem_size)
4083                 return ioread32(rdev->rio_mem + reg);
4084         else {
4085                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4086                 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4087         }
4088 }
4089
4090 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4091 {
4092         if (reg < rdev->rio_mem_size)
4093                 iowrite32(v, rdev->rio_mem + reg);
4094         else {
4095                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4096                 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4097         }
4098 }