drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/radeon_drm.h>
  32 #include "radeon_reg.h"
  33 #include "radeon.h"
  34 #include "radeon_asic.h"
  35 #include "r100d.h"
  36 #include "rs100d.h"
  37 #include "rv200d.h"
  38 #include "rv250d.h"
  39 #include "atom.h"
  40
  41 #include <linux/firmware.h>
  42 #include <linux/module.h>
  43
  44 #include "r100_reg_safe.h"
  45 #include "rn50_reg_safe.h"
  46
  47 /* Firmware Names */
  48 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  49 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  50 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  51 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  52 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  53 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  54 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  55
  56 MODULE_FIRMWARE(FIRMWARE_R100);
  57 MODULE_FIRMWARE(FIRMWARE_R200);
  58 MODULE_FIRMWARE(FIRMWARE_R300);
  59 MODULE_FIRMWARE(FIRMWARE_R420);
  60 MODULE_FIRMWARE(FIRMWARE_RS690);
  61 MODULE_FIRMWARE(FIRMWARE_RS600);
  62 MODULE_FIRMWARE(FIRMWARE_R520);
  63
  64 #include "r100_track.h"
  65
  66 /* This files gather functions specifics to:
  67  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  68  * and others in some cases.
  69  */
  70
  71 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
  72 {
  73         if (crtc == 0) {
  74                 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
  75                         return true;
  76                 else
  77                         return false;
  78         } else {
  79                 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
  80                         return true;
  81                 else
  82                         return false;
  83         }
  84 }
  85
  86 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
  87 {
  88         u32 vline1, vline2;
  89
  90         if (crtc == 0) {
  91                 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  92                 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  93         } else {
  94                 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  95                 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  96         }
  97         if (vline1 != vline2)
  98                 return true;
  99         else
 100                 return false;
 101 }
 102
 103 /**
 104  * r100_wait_for_vblank - vblank wait asic callback.
 105  *
 106  * @rdev: radeon_device pointer
 107  * @crtc: crtc to wait for vblank on
 108  *
 109  * Wait for vblank on the requested crtc (r1xx-r4xx).
 110  */
 111 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
 112 {
 113         unsigned i = 0;
 114
 115         if (crtc >= rdev->num_crtc)
 116                 return;
 117
 118         if (crtc == 0) {
 119                 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
 120                         return;
 121         } else {
 122                 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
 123                         return;
 124         }
 125
 126         /* depending on when we hit vblank, we may be close to active; if so,
 127          * wait for another frame.
 128          */
 129         while (r100_is_in_vblank(rdev, crtc)) {
 130                 if (i++ % 100 == 0) {
 131                         if (!r100_is_counter_moving(rdev, crtc))
 132                                 break;
 133                 }
 134         }
 135
 136         while (!r100_is_in_vblank(rdev, crtc)) {
 137                 if (i++ % 100 == 0) {
 138                         if (!r100_is_counter_moving(rdev, crtc))
 139                                 break;
 140                 }
 141         }
 142 }
 143
 144 /**
 145  * r100_page_flip - pageflip callback.
 146  *
 147  * @rdev: radeon_device pointer
 148  * @crtc_id: crtc to cleanup pageflip on
 149  * @crtc_base: new address of the crtc (GPU MC address)
 150  *
 151  * Does the actual pageflip (r1xx-r4xx).
 152  * During vblank we take the crtc lock and wait for the update_pending
 153  * bit to go high, when it does, we release the lock, and allow the
 154  * double buffered update to take place.
 155  */
 156 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
 157 {
 158         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 159         u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
 160         int i;
 161
 162         /* Lock the graphics update lock */
 163         /* update the scanout addresses */
 164         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 165
 166         /* Wait for update_pending to go high. */
 167         for (i = 0; i < rdev->usec_timeout; i++) {
 168                 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
 169                         break;
 170                 udelay(1);
 171         }
 172         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 173
 174         /* Unlock the lock, so double-buffering can take place inside vblank */
 175         tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
 176         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 177
 178 }
 179
 180 /**
 181  * r100_page_flip_pending - check if page flip is still pending
 182  *
 183  * @rdev: radeon_device pointer
 184  * @crtc_id: crtc to check
 185  *
 186  * Check if the last pagefilp is still pending (r1xx-r4xx).
 187  * Returns the current update pending status.
 188  */
 189 bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
 190 {
 191         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 192
 193         /* Return current update_pending status: */
 194         return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
 195                 RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET);
 196 }
 197
 198 /**
 199  * r100_pm_get_dynpm_state - look up dynpm power state callback.
 200  *
 201  * @rdev: radeon_device pointer
 202  *
 203  * Look up the optimal power state based on the
 204  * current state of the GPU (r1xx-r5xx).
 205  * Used for dynpm only.
 206  */
 207 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
 208 {
 209         int i;
 210         rdev->pm.dynpm_can_upclock = true;
 211         rdev->pm.dynpm_can_downclock = true;
 212
 213         switch (rdev->pm.dynpm_planned_action) {
 214         case DYNPM_ACTION_MINIMUM:
 215                 rdev->pm.requested_power_state_index = 0;
 216                 rdev->pm.dynpm_can_downclock = false;
 217                 break;
 218         case DYNPM_ACTION_DOWNCLOCK:
 219                 if (rdev->pm.current_power_state_index == 0) {
 220                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 221                         rdev->pm.dynpm_can_downclock = false;
 222                 } else {
 223                         if (rdev->pm.active_crtc_count > 1) {
 224                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
 225                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 226                                                 continue;
 227                                         else if (i >= rdev->pm.current_power_state_index) {
 228                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 229                                                 break;
 230                                         } else {
 231                                                 rdev->pm.requested_power_state_index = i;
 232                                                 break;
 233                                         }
 234                                 }
 235                         } else
 236                                 rdev->pm.requested_power_state_index =
 237                                         rdev->pm.current_power_state_index - 1;
 238                 }
 239                 /* don't use the power state if crtcs are active and no display flag is set */
 240                 if ((rdev->pm.active_crtc_count > 0) &&
 241                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
 242                      RADEON_PM_MODE_NO_DISPLAY)) {
 243                         rdev->pm.requested_power_state_index++;
 244                 }
 245                 break;
 246         case DYNPM_ACTION_UPCLOCK:
 247                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 248                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 249                         rdev->pm.dynpm_can_upclock = false;
 250                 } else {
 251                         if (rdev->pm.active_crtc_count > 1) {
 252                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 253                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 254                                                 continue;
 255                                         else if (i <= rdev->pm.current_power_state_index) {
 256                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 257                                                 break;
 258                                         } else {
 259                                                 rdev->pm.requested_power_state_index = i;
 260                                                 break;
 261                                         }
 262                                 }
 263                         } else
 264                                 rdev->pm.requested_power_state_index =
 265                                         rdev->pm.current_power_state_index + 1;
 266                 }
 267                 break;
 268         case DYNPM_ACTION_DEFAULT:
 269                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 270                 rdev->pm.dynpm_can_upclock = false;
 271                 break;
 272         case DYNPM_ACTION_NONE:
 273         default:
 274                 DRM_ERROR("Requested mode for not defined action\n");
 275                 return;
 276         }
 277         /* only one clock mode per power state */
 278         rdev->pm.requested_clock_mode_index = 0;
 279
 280         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 281                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 282                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 283                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 284                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 285                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 286                   pcie_lanes);
 287 }
 288
 289 /**
 290  * r100_pm_init_profile - Initialize power profiles callback.
 291  *
 292  * @rdev: radeon_device pointer
 293  *
 294  * Initialize the power states used in profile mode
 295  * (r1xx-r3xx).
 296  * Used for profile mode only.
 297  */
 298 void r100_pm_init_profile(struct radeon_device *rdev)
 299 {
 300         /* default */
 301         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 302         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 303         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 304         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 305         /* low sh */
 306         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 307         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 308         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 309         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 310         /* mid sh */
 311         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 312         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 313         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 314         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 315         /* high sh */
 316         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 317         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 318         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 319         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 320         /* low mh */
 321         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 322         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 323         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 324         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 325         /* mid mh */
 326         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 327         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 328         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 329         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 330         /* high mh */
 331         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 332         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 333         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 334         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 335 }
 336
 337 /**
 338  * r100_pm_misc - set additional pm hw parameters callback.
 339  *
 340  * @rdev: radeon_device pointer
 341  *
 342  * Set non-clock parameters associated with a power state
 343  * (voltage, pcie lanes, etc.) (r1xx-r4xx).
 344  */
 345 void r100_pm_misc(struct radeon_device *rdev)
 346 {
 347         int requested_index = rdev->pm.requested_power_state_index;
 348         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 349         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 350         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 351
 352         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 353                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 354                         tmp = RREG32(voltage->gpio.reg);
 355                         if (voltage->active_high)
 356                                 tmp |= voltage->gpio.mask;
 357                         else
 358                                 tmp &= ~(voltage->gpio.mask);
 359                         WREG32(voltage->gpio.reg, tmp);
 360                         if (voltage->delay)
 361                                 udelay(voltage->delay);
 362                 } else {
 363                         tmp = RREG32(voltage->gpio.reg);
 364                         if (voltage->active_high)
 365                                 tmp &= ~voltage->gpio.mask;
 366                         else
 367                                 tmp |= voltage->gpio.mask;
 368                         WREG32(voltage->gpio.reg, tmp);
 369                         if (voltage->delay)
 370                                 udelay(voltage->delay);
 371                 }
 372         }
 373
 374         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 375         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 376         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 377         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 378         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 379         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 380                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 381                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 382                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 383                 else
 384                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 385                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 386                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 387                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 388                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 389         } else
 390                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 391
 392         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 393                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 394                 if (voltage->delay) {
 395                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 396                         switch (voltage->delay) {
 397                         case 33:
 398                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 399                                 break;
 400                         case 66:
 401                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 402                                 break;
 403                         case 99:
 404                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 405                                 break;
 406                         case 132:
 407                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 408                                 break;
 409                         }
 410                 } else
 411                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 412         } else
 413                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 414
 415         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 416                 sclk_cntl &= ~FORCE_HDP;
 417         else
 418                 sclk_cntl |= FORCE_HDP;
 419
 420         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 421         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 422         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 423
 424         /* set pcie lanes */
 425         if ((rdev->flags & RADEON_IS_PCIE) &&
 426             !(rdev->flags & RADEON_IS_IGP) &&
 427             rdev->asic->pm.set_pcie_lanes &&
 428             (ps->pcie_lanes !=
 429              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 430                 radeon_set_pcie_lanes(rdev,
 431                                       ps->pcie_lanes);
 432                 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
 433         }
 434 }
 435
 436 /**
 437  * r100_pm_prepare - pre-power state change callback.
 438  *
 439  * @rdev: radeon_device pointer
 440  *
 441  * Prepare for a power state change (r1xx-r4xx).
 442  */
 443 void r100_pm_prepare(struct radeon_device *rdev)
 444 {
 445         struct drm_device *ddev = rdev->ddev;
 446         struct drm_crtc *crtc;
 447         struct radeon_crtc *radeon_crtc;
 448         u32 tmp;
 449
 450         /* disable any active CRTCs */
 451         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 452                 radeon_crtc = to_radeon_crtc(crtc);
 453                 if (radeon_crtc->enabled) {
 454                         if (radeon_crtc->crtc_id) {
 455                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 456                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 457                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 458                         } else {
 459                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 460                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 461                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 462                         }
 463                 }
 464         }
 465 }
 466
 467 /**
 468  * r100_pm_finish - post-power state change callback.
 469  *
 470  * @rdev: radeon_device pointer
 471  *
 472  * Clean up after a power state change (r1xx-r4xx).
 473  */
 474 void r100_pm_finish(struct radeon_device *rdev)
 475 {
 476         struct drm_device *ddev = rdev->ddev;
 477         struct drm_crtc *crtc;
 478         struct radeon_crtc *radeon_crtc;
 479         u32 tmp;
 480
 481         /* enable any active CRTCs */
 482         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 483                 radeon_crtc = to_radeon_crtc(crtc);
 484                 if (radeon_crtc->enabled) {
 485                         if (radeon_crtc->crtc_id) {
 486                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 487                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 488                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 489                         } else {
 490                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 491                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 492                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 493                         }
 494                 }
 495         }
 496 }
 497
 498 /**
 499  * r100_gui_idle - gui idle callback.
 500  *
 501  * @rdev: radeon_device pointer
 502  *
 503  * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
 504  * Returns true if idle, false if not.
 505  */
 506 bool r100_gui_idle(struct radeon_device *rdev)
 507 {
 508         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 509                 return false;
 510         else
 511                 return true;
 512 }
 513
 514 /* hpd for digital panel detect/disconnect */
 515 /**
 516  * r100_hpd_sense - hpd sense callback.
 517  *
 518  * @rdev: radeon_device pointer
 519  * @hpd: hpd (hotplug detect) pin
 520  *
 521  * Checks if a digital monitor is connected (r1xx-r4xx).
 522  * Returns true if connected, false if not connected.
 523  */
 524 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 525 {
 526         bool connected = false;
 527
 528         switch (hpd) {
 529         case RADEON_HPD_1:
 530                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 531                         connected = true;
 532                 break;
 533         case RADEON_HPD_2:
 534                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 535                         connected = true;
 536                 break;
 537         default:
 538                 break;
 539         }
 540         return connected;
 541 }
 542
 543 /**
 544  * r100_hpd_set_polarity - hpd set polarity callback.
 545  *
 546  * @rdev: radeon_device pointer
 547  * @hpd: hpd (hotplug detect) pin
 548  *
 549  * Set the polarity of the hpd pin (r1xx-r4xx).
 550  */
 551 void r100_hpd_set_polarity(struct radeon_device *rdev,
 552                            enum radeon_hpd_id hpd)
 553 {
 554         u32 tmp;
 555         bool connected = r100_hpd_sense(rdev, hpd);
 556
 557         switch (hpd) {
 558         case RADEON_HPD_1:
 559                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 560                 if (connected)
 561                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 562                 else
 563                         tmp |= RADEON_FP_DETECT_INT_POL;
 564                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 565                 break;
 566         case RADEON_HPD_2:
 567                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 568                 if (connected)
 569                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 570                 else
 571                         tmp |= RADEON_FP2_DETECT_INT_POL;
 572                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 573                 break;
 574         default:
 575                 break;
 576         }
 577 }
 578
 579 /**
 580  * r100_hpd_init - hpd setup callback.
 581  *
 582  * @rdev: radeon_device pointer
 583  *
 584  * Setup the hpd pins used by the card (r1xx-r4xx).
 585  * Set the polarity, and enable the hpd interrupts.
 586  */
 587 void r100_hpd_init(struct radeon_device *rdev)
 588 {
 589         struct drm_device *dev = rdev->ddev;
 590         struct drm_connector *connector;
 591         unsigned enable = 0;
 592
 593         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 594                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 595                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 596                         enable |= 1 << radeon_connector->hpd.hpd;
 597                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 598         }
 599         radeon_irq_kms_enable_hpd(rdev, enable);
 600 }
 601
 602 /**
 603  * r100_hpd_fini - hpd tear down callback.
 604  *
 605  * @rdev: radeon_device pointer
 606  *
 607  * Tear down the hpd pins used by the card (r1xx-r4xx).
 608  * Disable the hpd interrupts.
 609  */
 610 void r100_hpd_fini(struct radeon_device *rdev)
 611 {
 612         struct drm_device *dev = rdev->ddev;
 613         struct drm_connector *connector;
 614         unsigned disable = 0;
 615
 616         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 617                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 618                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 619                         disable |= 1 << radeon_connector->hpd.hpd;
 620         }
 621         radeon_irq_kms_disable_hpd(rdev, disable);
 622 }
 623
 624 /*
 625  * PCI GART
 626  */
 627 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 628 {
 629         /* TODO: can we do somethings here ? */
 630         /* It seems hw only cache one entry so we should discard this
 631          * entry otherwise if first GPU GART read hit this entry it
 632          * could end up in wrong address. */
 633 }
 634
 635 int r100_pci_gart_init(struct radeon_device *rdev)
 636 {
 637         int r;
 638
 639         if (rdev->gart.ptr) {
 640                 WARN(1, "R100 PCI GART already initialized\n");
 641                 return 0;
 642         }
 643         /* Initialize common gart structure */
 644         r = radeon_gart_init(rdev);
 645         if (r)
 646                 return r;
 647         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 648         rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 649         rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
 650         rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 651         return radeon_gart_table_ram_alloc(rdev);
 652 }
 653
 654 int r100_pci_gart_enable(struct radeon_device *rdev)
 655 {
 656         uint32_t tmp;
 657
 658         /* discard memory request outside of configured range */
 659         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 660         WREG32(RADEON_AIC_CNTL, tmp);
 661         /* set address range for PCI address translate */
 662         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 663         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 664         /* set PCI GART page-table base address */
 665         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 666         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 667         WREG32(RADEON_AIC_CNTL, tmp);
 668         r100_pci_gart_tlb_flush(rdev);
 669         DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
 670                  (unsigned)(rdev->mc.gtt_size >> 20),
 671                  (unsigned long long)rdev->gart.table_addr);
 672         rdev->gart.ready = true;
 673         return 0;
 674 }
 675
 676 void r100_pci_gart_disable(struct radeon_device *rdev)
 677 {
 678         uint32_t tmp;
 679
 680         /* discard memory request outside of configured range */
 681         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 682         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 683         WREG32(RADEON_AIC_LO_ADDR, 0);
 684         WREG32(RADEON_AIC_HI_ADDR, 0);
 685 }
 686
 687 uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags)
 688 {
 689         return addr;
 690 }
 691
 692 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
 693                             uint64_t entry)
 694 {
 695         u32 *gtt = rdev->gart.ptr;
 696         gtt[i] = cpu_to_le32(lower_32_bits(entry));
 697 }
 698
 699 void r100_pci_gart_fini(struct radeon_device *rdev)
 700 {
 701         radeon_gart_fini(rdev);
 702         r100_pci_gart_disable(rdev);
 703         radeon_gart_table_ram_free(rdev);
 704 }
 705
 706 int r100_irq_set(struct radeon_device *rdev)
 707 {
 708         uint32_t tmp = 0;
 709
 710         if (!rdev->irq.installed) {
 711                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 712                 WREG32(R_000040_GEN_INT_CNTL, 0);
 713                 return -EINVAL;
 714         }
 715         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
 716                 tmp |= RADEON_SW_INT_ENABLE;
 717         }
 718         if (rdev->irq.crtc_vblank_int[0] ||
 719             atomic_read(&rdev->irq.pflip[0])) {
 720                 tmp |= RADEON_CRTC_VBLANK_MASK;
 721         }
 722         if (rdev->irq.crtc_vblank_int[1] ||
 723             atomic_read(&rdev->irq.pflip[1])) {
 724                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 725         }
 726         if (rdev->irq.hpd[0]) {
 727                 tmp |= RADEON_FP_DETECT_MASK;
 728         }
 729         if (rdev->irq.hpd[1]) {
 730                 tmp |= RADEON_FP2_DETECT_MASK;
 731         }
 732         WREG32(RADEON_GEN_INT_CNTL, tmp);
 733
 734         /* read back to post the write */
 735         RREG32(RADEON_GEN_INT_CNTL);
 736
 737         return 0;
 738 }
 739
 740 void r100_irq_disable(struct radeon_device *rdev)
 741 {
 742         u32 tmp;
 743
 744         WREG32(R_000040_GEN_INT_CNTL, 0);
 745         /* Wait and acknowledge irq */
 746         mdelay(1);
 747         tmp = RREG32(R_000044_GEN_INT_STATUS);
 748         WREG32(R_000044_GEN_INT_STATUS, tmp);
 749 }
 750
 751 static uint32_t r100_irq_ack(struct radeon_device *rdev)
 752 {
 753         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 754         uint32_t irq_mask = RADEON_SW_INT_TEST |
 755                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 756                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 757
 758         if (irqs) {
 759                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 760         }
 761         return irqs & irq_mask;
 762 }
 763
 764 int r100_irq_process(struct radeon_device *rdev)
 765 {
 766         uint32_t status, msi_rearm;
 767         bool queue_hotplug = false;
 768
 769         status = r100_irq_ack(rdev);
 770         if (!status) {
 771                 return IRQ_NONE;
 772         }
 773         if (rdev->shutdown) {
 774                 return IRQ_NONE;
 775         }
 776         while (status) {
 777                 /* SW interrupt */
 778                 if (status & RADEON_SW_INT_TEST) {
 779                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
 780                 }
 781                 /* Vertical blank interrupts */
 782                 if (status & RADEON_CRTC_VBLANK_STAT) {
 783                         if (rdev->irq.crtc_vblank_int[0]) {
 784                                 drm_handle_vblank(rdev->ddev, 0);
 785                                 rdev->pm.vblank_sync = true;
 786                                 wake_up(&rdev->irq.vblank_queue);
 787                         }
 788                         if (atomic_read(&rdev->irq.pflip[0]))
 789                                 radeon_crtc_handle_vblank(rdev, 0);
 790                 }
 791                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 792                         if (rdev->irq.crtc_vblank_int[1]) {
 793                                 drm_handle_vblank(rdev->ddev, 1);
 794                                 rdev->pm.vblank_sync = true;
 795                                 wake_up(&rdev->irq.vblank_queue);
 796                         }
 797                         if (atomic_read(&rdev->irq.pflip[1]))
 798                                 radeon_crtc_handle_vblank(rdev, 1);
 799                 }
 800                 if (status & RADEON_FP_DETECT_STAT) {
 801                         queue_hotplug = true;
 802                         DRM_DEBUG("HPD1\n");
 803                 }
 804                 if (status & RADEON_FP2_DETECT_STAT) {
 805                         queue_hotplug = true;
 806                         DRM_DEBUG("HPD2\n");
 807                 }
 808                 status = r100_irq_ack(rdev);
 809         }
 810         if (queue_hotplug)
 811                 schedule_delayed_work(&rdev->hotplug_work, 0);
 812         if (rdev->msi_enabled) {
 813                 switch (rdev->family) {
 814                 case CHIP_RS400:
 815                 case CHIP_RS480:
 816                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 817                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 818                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 819                         break;
 820                 default:
 821                         WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
 822                         break;
 823                 }
 824         }
 825         return IRQ_HANDLED;
 826 }
 827
 828 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 829 {
 830         if (crtc == 0)
 831                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 832         else
 833                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 834 }
 835
 836 /**
 837  * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
 838  * rdev: radeon device structure
 839  * ring: ring buffer struct for emitting packets
 840  */
 841 static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
 842 {
 843         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 844         radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
 845                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 846         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 847         radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
 848 }
 849
 850 /* Who ever call radeon_fence_emit should call ring_lock and ask
 851  * for enough space (today caller are ib schedule and buffer move) */
 852 void r100_fence_ring_emit(struct radeon_device *rdev,
 853                           struct radeon_fence *fence)
 854 {
 855         struct radeon_ring *ring = &rdev->ring[fence->ring];
 856
 857         /* We have to make sure that caches are flushed before
 858          * CPU might read something from VRAM. */
 859         radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 860         radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
 861         radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 862         radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
 863         /* Wait until IDLE & CLEAN */
 864         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 865         radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 866         r100_ring_hdp_flush(rdev, ring);
 867         /* Emit fence sequence & fire IRQ */
 868         radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
 869         radeon_ring_write(ring, fence->seq);
 870         radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
 871         radeon_ring_write(ring, RADEON_SW_INT_FIRE);
 872 }
 873
 874 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
 875                               struct radeon_ring *ring,
 876                               struct radeon_semaphore *semaphore,
 877                               bool emit_wait)
 878 {
 879         /* Unused on older asics, since we don't have semaphores or multiple rings */
 880         BUG();
 881         return false;
 882 }
 883
 884 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
 885                                     uint64_t src_offset,
 886                                     uint64_t dst_offset,
 887                                     unsigned num_gpu_pages,
 888                                     struct reservation_object *resv)
 889 {
 890         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 891         struct radeon_fence *fence;
 892         uint32_t cur_pages;
 893         uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
 894         uint32_t pitch;
 895         uint32_t stride_pixels;
 896         unsigned ndw;
 897         int num_loops;
 898         int r = 0;
 899
 900         /* radeon limited to 16k stride */
 901         stride_bytes &= 0x3fff;
 902         /* radeon pitch is /64 */
 903         pitch = stride_bytes / 64;
 904         stride_pixels = stride_bytes / 4;
 905         num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
 906
 907         /* Ask for enough room for blit + flush + fence */
 908         ndw = 64 + (10 * num_loops);
 909         r = radeon_ring_lock(rdev, ring, ndw);
 910         if (r) {
 911                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 912                 return ERR_PTR(-EINVAL);
 913         }
 914         while (num_gpu_pages > 0) {
 915                 cur_pages = num_gpu_pages;
 916                 if (cur_pages > 8191) {
 917                         cur_pages = 8191;
 918                 }
 919                 num_gpu_pages -= cur_pages;
 920
 921                 /* pages are in Y direction - height
 922                    page width in X direction - width */
 923                 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
 924                 radeon_ring_write(ring,
 925                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 926                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 927                                   RADEON_GMC_SRC_CLIPPING |
 928                                   RADEON_GMC_DST_CLIPPING |
 929                                   RADEON_GMC_BRUSH_NONE |
 930                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 931                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 932                                   RADEON_ROP3_S |
 933                                   RADEON_DP_SRC_SOURCE_MEMORY |
 934                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 935                                   RADEON_GMC_WR_MSK_DIS);
 936                 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
 937                 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
 938                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
 939                 radeon_ring_write(ring, 0);
 940                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
 941                 radeon_ring_write(ring, num_gpu_pages);
 942                 radeon_ring_write(ring, num_gpu_pages);
 943                 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
 944         }
 945         radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 946         radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
 947         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 948         radeon_ring_write(ring,
 949                           RADEON_WAIT_2D_IDLECLEAN |
 950                           RADEON_WAIT_HOST_IDLECLEAN |
 951                           RADEON_WAIT_DMA_GUI_IDLE);
 952         r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
 953         if (r) {
 954                 radeon_ring_unlock_undo(rdev, ring);
 955                 return ERR_PTR(r);
 956         }
 957         radeon_ring_unlock_commit(rdev, ring, false);
 958         return fence;
 959 }
 960
 961 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 962 {
 963         unsigned i;
 964         u32 tmp;
 965
 966         for (i = 0; i < rdev->usec_timeout; i++) {
 967                 tmp = RREG32(R_000E40_RBBM_STATUS);
 968                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 969                         return 0;
 970                 }
 971                 udelay(1);
 972         }
 973         return -1;
 974 }
 975
 976 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
 977 {
 978         int r;
 979
 980         r = radeon_ring_lock(rdev, ring, 2);
 981         if (r) {
 982                 return;
 983         }
 984         radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
 985         radeon_ring_write(ring,
 986                           RADEON_ISYNC_ANY2D_IDLE3D |
 987                           RADEON_ISYNC_ANY3D_IDLE2D |
 988                           RADEON_ISYNC_WAIT_IDLEGUI |
 989                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 990         radeon_ring_unlock_commit(rdev, ring, false);
 991 }
 992
 993
 994 /* Load the microcode for the CP */
 995 static int r100_cp_init_microcode(struct radeon_device *rdev)
 996 {
 997         const char *fw_name = NULL;
 998         int err;
 999
1000         DRM_DEBUG_KMS("\n");
1001
1002         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
1003             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
1004             (rdev->family == CHIP_RS200)) {
1005                 DRM_INFO("Loading R100 Microcode\n");
1006                 fw_name = FIRMWARE_R100;
1007         } else if ((rdev->family == CHIP_R200) ||
1008                    (rdev->family == CHIP_RV250) ||
1009                    (rdev->family == CHIP_RV280) ||
1010                    (rdev->family == CHIP_RS300)) {
1011                 DRM_INFO("Loading R200 Microcode\n");
1012                 fw_name = FIRMWARE_R200;
1013         } else if ((rdev->family == CHIP_R300) ||
1014                    (rdev->family == CHIP_R350) ||
1015                    (rdev->family == CHIP_RV350) ||
1016                    (rdev->family == CHIP_RV380) ||
1017                    (rdev->family == CHIP_RS400) ||
1018                    (rdev->family == CHIP_RS480)) {
1019                 DRM_INFO("Loading R300 Microcode\n");
1020                 fw_name = FIRMWARE_R300;
1021         } else if ((rdev->family == CHIP_R420) ||
1022                    (rdev->family == CHIP_R423) ||
1023                    (rdev->family == CHIP_RV410)) {
1024                 DRM_INFO("Loading R400 Microcode\n");
1025                 fw_name = FIRMWARE_R420;
1026         } else if ((rdev->family == CHIP_RS690) ||
1027                    (rdev->family == CHIP_RS740)) {
1028                 DRM_INFO("Loading RS690/RS740 Microcode\n");
1029                 fw_name = FIRMWARE_RS690;
1030         } else if (rdev->family == CHIP_RS600) {
1031                 DRM_INFO("Loading RS600 Microcode\n");
1032                 fw_name = FIRMWARE_RS600;
1033         } else if ((rdev->family == CHIP_RV515) ||
1034                    (rdev->family == CHIP_R520) ||
1035                    (rdev->family == CHIP_RV530) ||
1036                    (rdev->family == CHIP_R580) ||
1037                    (rdev->family == CHIP_RV560) ||
1038                    (rdev->family == CHIP_RV570)) {
1039                 DRM_INFO("Loading R500 Microcode\n");
1040                 fw_name = FIRMWARE_R520;
1041         }
1042
1043         err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1044         if (err) {
1045                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1046                        fw_name);
1047         } else if (rdev->me_fw->size % 8) {
1048                 printk(KERN_ERR
1049                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1050                        rdev->me_fw->size, fw_name);
1051                 err = -EINVAL;
1052                 release_firmware(rdev->me_fw);
1053                 rdev->me_fw = NULL;
1054         }
1055         return err;
1056 }
1057
1058 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1059                       struct radeon_ring *ring)
1060 {
1061         u32 rptr;
1062
1063         if (rdev->wb.enabled)
1064                 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1065         else
1066                 rptr = RREG32(RADEON_CP_RB_RPTR);
1067
1068         return rptr;
1069 }
1070
1071 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1072                       struct radeon_ring *ring)
1073 {
1074         u32 wptr;
1075
1076         wptr = RREG32(RADEON_CP_RB_WPTR);
1077
1078         return wptr;
1079 }
1080
1081 void r100_gfx_set_wptr(struct radeon_device *rdev,
1082                        struct radeon_ring *ring)
1083 {
1084         WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1085         (void)RREG32(RADEON_CP_RB_WPTR);
1086 }
1087
1088 static void r100_cp_load_microcode(struct radeon_device *rdev)
1089 {
1090         const __be32 *fw_data;
1091         int i, size;
1092
1093         if (r100_gui_wait_for_idle(rdev)) {
1094                 printk(KERN_WARNING "Failed to wait GUI idle while "
1095                        "programming pipes. Bad things might happen.\n");
1096         }
1097
1098         if (rdev->me_fw) {
1099                 size = rdev->me_fw->size / 4;
1100                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1101                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1102                 for (i = 0; i < size; i += 2) {
1103                         WREG32(RADEON_CP_ME_RAM_DATAH,
1104                                be32_to_cpup(&fw_data[i]));
1105                         WREG32(RADEON_CP_ME_RAM_DATAL,
1106                                be32_to_cpup(&fw_data[i + 1]));
1107                 }
1108         }
1109 }
1110
1111 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1112 {
1113         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1114         unsigned rb_bufsz;
1115         unsigned rb_blksz;
1116         unsigned max_fetch;
1117         unsigned pre_write_timer;
1118         unsigned pre_write_limit;
1119         unsigned indirect2_start;
1120         unsigned indirect1_start;
1121         uint32_t tmp;
1122         int r;
1123
1124         if (r100_debugfs_cp_init(rdev)) {
1125                 DRM_ERROR("Failed to register debugfs file for CP !\n");
1126         }
1127         if (!rdev->me_fw) {
1128                 r = r100_cp_init_microcode(rdev);
1129                 if (r) {
1130                         DRM_ERROR("Failed to load firmware!\n");
1131                         return r;
1132                 }
1133         }
1134
1135         /* Align ring size */
1136         rb_bufsz = order_base_2(ring_size / 8);
1137         ring_size = (1 << (rb_bufsz + 1)) * 4;
1138         r100_cp_load_microcode(rdev);
1139         r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1140                              RADEON_CP_PACKET2);
1141         if (r) {
1142                 return r;
1143         }
1144         /* Each time the cp read 1024 bytes (16 dword/quadword) update
1145          * the rptr copy in system ram */
1146         rb_blksz = 9;
1147         /* cp will read 128bytes at a time (4 dwords) */
1148         max_fetch = 1;
1149         ring->align_mask = 16 - 1;
1150         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1151         pre_write_timer = 64;
1152         /* Force CP_RB_WPTR write if written more than one time before the
1153          * delay expire
1154          */
1155         pre_write_limit = 0;
1156         /* Setup the cp cache like this (cache size is 96 dwords) :
1157          *      RING            0  to 15
1158          *      INDIRECT1       16 to 79
1159          *      INDIRECT2       80 to 95
1160          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1161          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1162          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1163          * Idea being that most of the gpu cmd will be through indirect1 buffer
1164          * so it gets the bigger cache.
1165          */
1166         indirect2_start = 80;
1167         indirect1_start = 16;
1168         /* cp setup */
1169         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1170         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1171                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1172                REG_SET(RADEON_MAX_FETCH, max_fetch));
1173 #ifdef __BIG_ENDIAN
1174         tmp |= RADEON_BUF_SWAP_32BIT;
1175 #endif
1176         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1177
1178         /* Set ring address */
1179         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1180         WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1181         /* Force read & write ptr to 0 */
1182         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1183         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1184         ring->wptr = 0;
1185         WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1186
1187         /* set the wb address whether it's enabled or not */
1188         WREG32(R_00070C_CP_RB_RPTR_ADDR,
1189                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1190         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1191
1192         if (rdev->wb.enabled)
1193                 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1194         else {
1195                 tmp |= RADEON_RB_NO_UPDATE;
1196                 WREG32(R_000770_SCRATCH_UMSK, 0);
1197         }
1198
1199         WREG32(RADEON_CP_RB_CNTL, tmp);
1200         udelay(10);
1201         /* Set cp mode to bus mastering & enable cp*/
1202         WREG32(RADEON_CP_CSQ_MODE,
1203                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1204                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1205         WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1206         WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1207         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1208
1209         /* at this point everything should be setup correctly to enable master */
1210         pci_set_master(rdev->pdev);
1211
1212         radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1213         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1214         if (r) {
1215                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1216                 return r;
1217         }
1218         ring->ready = true;
1219         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1220
1221         if (!ring->rptr_save_reg /* not resuming from suspend */
1222             && radeon_ring_supports_scratch_reg(rdev, ring)) {
1223                 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1224                 if (r) {
1225                         DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1226                         ring->rptr_save_reg = 0;
1227                 }
1228         }
1229         return 0;
1230 }
1231
1232 void r100_cp_fini(struct radeon_device *rdev)
1233 {
1234         if (r100_cp_wait_for_idle(rdev)) {
1235                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1236         }
1237         /* Disable ring */
1238         r100_cp_disable(rdev);
1239         radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1240         radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1241         DRM_INFO("radeon: cp finalized\n");
1242 }
1243
1244 void r100_cp_disable(struct radeon_device *rdev)
1245 {
1246         /* Disable ring */
1247         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1248         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1249         WREG32(RADEON_CP_CSQ_MODE, 0);
1250         WREG32(RADEON_CP_CSQ_CNTL, 0);
1251         WREG32(R_000770_SCRATCH_UMSK, 0);
1252         if (r100_gui_wait_for_idle(rdev)) {
1253                 printk(KERN_WARNING "Failed to wait GUI idle while "
1254                        "programming pipes. Bad things might happen.\n");
1255         }
1256 }
1257
1258 /*
1259  * CS functions
1260  */
1261 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1262                             struct radeon_cs_packet *pkt,
1263                             unsigned idx,
1264                             unsigned reg)
1265 {
1266         int r;
1267         u32 tile_flags = 0;
1268         u32 tmp;
1269         struct radeon_bo_list *reloc;
1270         u32 value;
1271
1272         r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1273         if (r) {
1274                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1275                           idx, reg);
1276                 radeon_cs_dump_packet(p, pkt);
1277                 return r;
1278         }
1279
1280         value = radeon_get_ib_value(p, idx);
1281         tmp = value & 0x003fffff;
1282         tmp += (((u32)reloc->gpu_offset) >> 10);
1283
1284         if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1285                 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1286                         tile_flags |= RADEON_DST_TILE_MACRO;
1287                 if (reloc->tiling_flags & RADEON_TILING_MICRO) {
1288                         if (reg == RADEON_SRC_PITCH_OFFSET) {
1289                                 DRM_ERROR("Cannot src blit from microtiled surface\n");
1290                                 radeon_cs_dump_packet(p, pkt);
1291                                 return -EINVAL;
1292                         }
1293                         tile_flags |= RADEON_DST_TILE_MICRO;
1294                 }
1295
1296                 tmp |= tile_flags;
1297                 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1298         } else
1299                 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1300         return 0;
1301 }
1302
1303 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1304                              struct radeon_cs_packet *pkt,
1305                              int idx)
1306 {
1307         unsigned c, i;
1308         struct radeon_bo_list *reloc;
1309         struct r100_cs_track *track;
1310         int r = 0;
1311         volatile uint32_t *ib;
1312         u32 idx_value;
1313
1314         ib = p->ib.ptr;
1315         track = (struct r100_cs_track *)p->track;
1316         c = radeon_get_ib_value(p, idx++) & 0x1F;
1317         if (c > 16) {
1318             DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1319                       pkt->opcode);
1320             radeon_cs_dump_packet(p, pkt);
1321             return -EINVAL;
1322         }
1323         track->num_arrays = c;
1324         for (i = 0; i < (c - 1); i+=2, idx+=3) {
1325                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1326                 if (r) {
1327                         DRM_ERROR("No reloc for packet3 %d\n",
1328                                   pkt->opcode);
1329                         radeon_cs_dump_packet(p, pkt);
1330                         return r;
1331                 }
1332                 idx_value = radeon_get_ib_value(p, idx);
1333                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1334
1335                 track->arrays[i + 0].esize = idx_value >> 8;
1336                 track->arrays[i + 0].robj = reloc->robj;
1337                 track->arrays[i + 0].esize &= 0x7F;
1338                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1339                 if (r) {
1340                         DRM_ERROR("No reloc for packet3 %d\n",
1341                                   pkt->opcode);
1342                         radeon_cs_dump_packet(p, pkt);
1343                         return r;
1344                 }
1345                 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
1346                 track->arrays[i + 1].robj = reloc->robj;
1347                 track->arrays[i + 1].esize = idx_value >> 24;
1348                 track->arrays[i + 1].esize &= 0x7F;
1349         }
1350         if (c & 1) {
1351                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1352                 if (r) {
1353                         DRM_ERROR("No reloc for packet3 %d\n",
1354                                           pkt->opcode);
1355                         radeon_cs_dump_packet(p, pkt);
1356                         return r;
1357                 }
1358                 idx_value = radeon_get_ib_value(p, idx);
1359                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1360                 track->arrays[i + 0].robj = reloc->robj;
1361                 track->arrays[i + 0].esize = idx_value >> 8;
1362                 track->arrays[i + 0].esize &= 0x7F;
1363         }
1364         return r;
1365 }
1366
1367 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1368                           struct radeon_cs_packet *pkt,
1369                           const unsigned *auth, unsigned n,
1370                           radeon_packet0_check_t check)
1371 {
1372         unsigned reg;
1373         unsigned i, j, m;
1374         unsigned idx;
1375         int r;
1376
1377         idx = pkt->idx + 1;
1378         reg = pkt->reg;
1379         /* Check that register fall into register range
1380          * determined by the number of entry (n) in the
1381          * safe register bitmap.
1382          */
1383         if (pkt->one_reg_wr) {
1384                 if ((reg >> 7) > n) {
1385                         return -EINVAL;
1386                 }
1387         } else {
1388                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1389                         return -EINVAL;
1390                 }
1391         }
1392         for (i = 0; i <= pkt->count; i++, idx++) {
1393                 j = (reg >> 7);
1394                 m = 1 << ((reg >> 2) & 31);
1395                 if (auth[j] & m) {
1396                         r = check(p, pkt, idx, reg);
1397                         if (r) {
1398                                 return r;
1399                         }
1400                 }
1401                 if (pkt->one_reg_wr) {
1402                         if (!(auth[j] & m)) {
1403                                 break;
1404                         }
1405                 } else {
1406                         reg += 4;
1407                 }
1408         }
1409         return 0;
1410 }
1411
1412 /**
1413  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1414  * @parser:             parser structure holding parsing context.
1415  *
1416  * Userspace sends a special sequence for VLINE waits.
1417  * PACKET0 - VLINE_START_END + value
1418  * PACKET0 - WAIT_UNTIL +_value
1419  * RELOC (P3) - crtc_id in reloc.
1420  *
1421  * This function parses this and relocates the VLINE START END
1422  * and WAIT UNTIL packets to the correct crtc.
1423  * It also detects a switched off crtc and nulls out the
1424  * wait in that case.
1425  */
1426 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1427 {
1428         struct drm_crtc *crtc;
1429         struct radeon_crtc *radeon_crtc;
1430         struct radeon_cs_packet p3reloc, waitreloc;
1431         int crtc_id;
1432         int r;
1433         uint32_t header, h_idx, reg;
1434         volatile uint32_t *ib;
1435
1436         ib = p->ib.ptr;
1437
1438         /* parse the wait until */
1439         r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1440         if (r)
1441                 return r;
1442
1443         /* check its a wait until and only 1 count */
1444         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1445             waitreloc.count != 0) {
1446                 DRM_ERROR("vline wait had illegal wait until segment\n");
1447                 return -EINVAL;
1448         }
1449
1450         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1451                 DRM_ERROR("vline wait had illegal wait until\n");
1452                 return -EINVAL;
1453         }
1454
1455         /* jump over the NOP */
1456         r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1457         if (r)
1458                 return r;
1459
1460         h_idx = p->idx - 2;
1461         p->idx += waitreloc.count + 2;
1462         p->idx += p3reloc.count + 2;
1463
1464         header = radeon_get_ib_value(p, h_idx);
1465         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1466         reg = R100_CP_PACKET0_GET_REG(header);
1467         crtc = drm_crtc_find(p->rdev->ddev, crtc_id);
1468         if (!crtc) {
1469                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1470                 return -ENOENT;
1471         }
1472         radeon_crtc = to_radeon_crtc(crtc);
1473         crtc_id = radeon_crtc->crtc_id;
1474
1475         if (!crtc->enabled) {
1476                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1477                 ib[h_idx + 2] = PACKET2(0);
1478                 ib[h_idx + 3] = PACKET2(0);
1479         } else if (crtc_id == 1) {
1480                 switch (reg) {
1481                 case AVIVO_D1MODE_VLINE_START_END:
1482                         header &= ~R300_CP_PACKET0_REG_MASK;
1483                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1484                         break;
1485                 case RADEON_CRTC_GUI_TRIG_VLINE:
1486                         header &= ~R300_CP_PACKET0_REG_MASK;
1487                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1488                         break;
1489                 default:
1490                         DRM_ERROR("unknown crtc reloc\n");
1491                         return -EINVAL;
1492                 }
1493                 ib[h_idx] = header;
1494                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1495         }
1496
1497         return 0;
1498 }
1499
1500 static int r100_get_vtx_size(uint32_t vtx_fmt)
1501 {
1502         int vtx_size;
1503         vtx_size = 2;
1504         /* ordered according to bits in spec */
1505         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1506                 vtx_size++;
1507         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1508                 vtx_size += 3;
1509         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1510                 vtx_size++;
1511         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1512                 vtx_size++;
1513         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1514                 vtx_size += 3;
1515         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1516                 vtx_size++;
1517         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1518                 vtx_size++;
1519         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1520                 vtx_size += 2;
1521         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1522                 vtx_size += 2;
1523         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1524                 vtx_size++;
1525         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1526                 vtx_size += 2;
1527         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1528                 vtx_size++;
1529         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1530                 vtx_size += 2;
1531         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1532                 vtx_size++;
1533         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1534                 vtx_size++;
1535         /* blend weight */
1536         if (vtx_fmt & (0x7 << 15))
1537                 vtx_size += (vtx_fmt >> 15) & 0x7;
1538         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1539                 vtx_size += 3;
1540         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1541                 vtx_size += 2;
1542         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1543                 vtx_size++;
1544         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1545                 vtx_size++;
1546         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1547                 vtx_size++;
1548         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1549                 vtx_size++;
1550         return vtx_size;
1551 }
1552
1553 static int r100_packet0_check(struct radeon_cs_parser *p,
1554                               struct radeon_cs_packet *pkt,
1555                               unsigned idx, unsigned reg)
1556 {
1557         struct radeon_bo_list *reloc;
1558         struct r100_cs_track *track;
1559         volatile uint32_t *ib;
1560         uint32_t tmp;
1561         int r;
1562         int i, face;
1563         u32 tile_flags = 0;
1564         u32 idx_value;
1565
1566         ib = p->ib.ptr;
1567         track = (struct r100_cs_track *)p->track;
1568
1569         idx_value = radeon_get_ib_value(p, idx);
1570
1571         switch (reg) {
1572         case RADEON_CRTC_GUI_TRIG_VLINE:
1573                 r = r100_cs_packet_parse_vline(p);
1574                 if (r) {
1575                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1576                                   idx, reg);
1577                         radeon_cs_dump_packet(p, pkt);
1578                         return r;
1579                 }
1580                 break;
1581                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1582                  * range access */
1583         case RADEON_DST_PITCH_OFFSET:
1584         case RADEON_SRC_PITCH_OFFSET:
1585                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1586                 if (r)
1587                         return r;
1588                 break;
1589         case RADEON_RB3D_DEPTHOFFSET:
1590                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1591                 if (r) {
1592                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1593                                   idx, reg);
1594                         radeon_cs_dump_packet(p, pkt);
1595                         return r;
1596                 }
1597                 track->zb.robj = reloc->robj;
1598                 track->zb.offset = idx_value;
1599                 track->zb_dirty = true;
1600                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1601                 break;
1602         case RADEON_RB3D_COLOROFFSET:
1603                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1604                 if (r) {
1605                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1606                                   idx, reg);
1607                         radeon_cs_dump_packet(p, pkt);
1608                         return r;
1609                 }
1610                 track->cb[0].robj = reloc->robj;
1611                 track->cb[0].offset = idx_value;
1612                 track->cb_dirty = true;
1613                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1614                 break;
1615         case RADEON_PP_TXOFFSET_0:
1616         case RADEON_PP_TXOFFSET_1:
1617         case RADEON_PP_TXOFFSET_2:
1618                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1619                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1620                 if (r) {
1621                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1622                                   idx, reg);
1623                         radeon_cs_dump_packet(p, pkt);
1624                         return r;
1625                 }
1626                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1627                         if (reloc->tiling_flags & RADEON_TILING_MACRO)
1628                                 tile_flags |= RADEON_TXO_MACRO_TILE;
1629                         if (reloc->tiling_flags & RADEON_TILING_MICRO)
1630                                 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1631
1632                         tmp = idx_value & ~(0x7 << 2);
1633                         tmp |= tile_flags;
1634                         ib[idx] = tmp + ((u32)reloc->gpu_offset);
1635                 } else
1636                         ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1637                 track->textures[i].robj = reloc->robj;
1638                 track->tex_dirty = true;
1639                 break;
1640         case RADEON_PP_CUBIC_OFFSET_T0_0:
1641         case RADEON_PP_CUBIC_OFFSET_T0_1:
1642         case RADEON_PP_CUBIC_OFFSET_T0_2:
1643         case RADEON_PP_CUBIC_OFFSET_T0_3:
1644         case RADEON_PP_CUBIC_OFFSET_T0_4:
1645                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1646                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1647                 if (r) {
1648                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1649                                   idx, reg);
1650                         radeon_cs_dump_packet(p, pkt);
1651                         return r;
1652                 }
1653                 track->textures[0].cube_info[i].offset = idx_value;
1654                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1655                 track->textures[0].cube_info[i].robj = reloc->robj;
1656                 track->tex_dirty = true;
1657                 break;
1658         case RADEON_PP_CUBIC_OFFSET_T1_0:
1659         case RADEON_PP_CUBIC_OFFSET_T1_1:
1660         case RADEON_PP_CUBIC_OFFSET_T1_2:
1661         case RADEON_PP_CUBIC_OFFSET_T1_3:
1662         case RADEON_PP_CUBIC_OFFSET_T1_4:
1663                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1664                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1665                 if (r) {
1666                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1667                                   idx, reg);
1668                         radeon_cs_dump_packet(p, pkt);
1669                         return r;
1670                 }
1671                 track->textures[1].cube_info[i].offset = idx_value;
1672                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1673                 track->textures[1].cube_info[i].robj = reloc->robj;
1674                 track->tex_dirty = true;
1675                 break;
1676         case RADEON_PP_CUBIC_OFFSET_T2_0:
1677         case RADEON_PP_CUBIC_OFFSET_T2_1:
1678         case RADEON_PP_CUBIC_OFFSET_T2_2:
1679         case RADEON_PP_CUBIC_OFFSET_T2_3:
1680         case RADEON_PP_CUBIC_OFFSET_T2_4:
1681                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1682                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1683                 if (r) {
1684                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1685                                   idx, reg);
1686                         radeon_cs_dump_packet(p, pkt);
1687                         return r;
1688                 }
1689                 track->textures[2].cube_info[i].offset = idx_value;
1690                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1691                 track->textures[2].cube_info[i].robj = reloc->robj;
1692                 track->tex_dirty = true;
1693                 break;
1694         case RADEON_RE_WIDTH_HEIGHT:
1695                 track->maxy = ((idx_value >> 16) & 0x7FF);
1696                 track->cb_dirty = true;
1697                 track->zb_dirty = true;
1698                 break;
1699         case RADEON_RB3D_COLORPITCH:
1700                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1701                 if (r) {
1702                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1703                                   idx, reg);
1704                         radeon_cs_dump_packet(p, pkt);
1705                         return r;
1706                 }
1707                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1708                         if (reloc->tiling_flags & RADEON_TILING_MACRO)
1709                                 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1710                         if (reloc->tiling_flags & RADEON_TILING_MICRO)
1711                                 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1712
1713                         tmp = idx_value & ~(0x7 << 16);
1714                         tmp |= tile_flags;
1715                         ib[idx] = tmp;
1716                 } else
1717                         ib[idx] = idx_value;
1718
1719                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1720                 track->cb_dirty = true;
1721                 break;
1722         case RADEON_RB3D_DEPTHPITCH:
1723                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1724                 track->zb_dirty = true;
1725                 break;
1726         case RADEON_RB3D_CNTL:
1727                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1728                 case 7:
1729                 case 8:
1730                 case 9:
1731                 case 11:
1732                 case 12:
1733                         track->cb[0].cpp = 1;
1734                         break;
1735                 case 3:
1736                 case 4:
1737                 case 15:
1738                         track->cb[0].cpp = 2;
1739                         break;
1740                 case 6:
1741                         track->cb[0].cpp = 4;
1742                         break;
1743                 default:
1744                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1745                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1746                         return -EINVAL;
1747                 }
1748                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1749                 track->cb_dirty = true;
1750                 track->zb_dirty = true;
1751                 break;
1752         case RADEON_RB3D_ZSTENCILCNTL:
1753                 switch (idx_value & 0xf) {
1754                 case 0:
1755                         track->zb.cpp = 2;
1756                         break;
1757                 case 2:
1758                 case 3:
1759                 case 4:
1760                 case 5:
1761                 case 9:
1762                 case 11:
1763                         track->zb.cpp = 4;
1764                         break;
1765                 default:
1766                         break;
1767                 }
1768                 track->zb_dirty = true;
1769                 break;
1770         case RADEON_RB3D_ZPASS_ADDR:
1771                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1772                 if (r) {
1773                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1774                                   idx, reg);
1775                         radeon_cs_dump_packet(p, pkt);
1776                         return r;
1777                 }
1778                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1779                 break;
1780         case RADEON_PP_CNTL:
1781                 {
1782                         uint32_t temp = idx_value >> 4;
1783                         for (i = 0; i < track->num_texture; i++)
1784                                 track->textures[i].enabled = !!(temp & (1 << i));
1785                         track->tex_dirty = true;
1786                 }
1787                 break;
1788         case RADEON_SE_VF_CNTL:
1789                 track->vap_vf_cntl = idx_value;
1790                 break;
1791         case RADEON_SE_VTX_FMT:
1792                 track->vtx_size = r100_get_vtx_size(idx_value);
1793                 break;
1794         case RADEON_PP_TEX_SIZE_0:
1795         case RADEON_PP_TEX_SIZE_1:
1796         case RADEON_PP_TEX_SIZE_2:
1797                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1798                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1799                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1800                 track->tex_dirty = true;
1801                 break;
1802         case RADEON_PP_TEX_PITCH_0:
1803         case RADEON_PP_TEX_PITCH_1:
1804         case RADEON_PP_TEX_PITCH_2:
1805                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1806                 track->textures[i].pitch = idx_value + 32;
1807                 track->tex_dirty = true;
1808                 break;
1809         case RADEON_PP_TXFILTER_0:
1810         case RADEON_PP_TXFILTER_1:
1811         case RADEON_PP_TXFILTER_2:
1812                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1813                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1814                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1815                 tmp = (idx_value >> 23) & 0x7;
1816                 if (tmp == 2 || tmp == 6)
1817                         track->textures[i].roundup_w = false;
1818                 tmp = (idx_value >> 27) & 0x7;
1819                 if (tmp == 2 || tmp == 6)
1820                         track->textures[i].roundup_h = false;
1821                 track->tex_dirty = true;
1822                 break;
1823         case RADEON_PP_TXFORMAT_0:
1824         case RADEON_PP_TXFORMAT_1:
1825         case RADEON_PP_TXFORMAT_2:
1826                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1827                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1828                         track->textures[i].use_pitch = 1;
1829                 } else {
1830                         track->textures[i].use_pitch = 0;
1831                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1832                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1833                 }
1834                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1835                         track->textures[i].tex_coord_type = 2;
1836                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1837                 case RADEON_TXFORMAT_I8:
1838                 case RADEON_TXFORMAT_RGB332:
1839                 case RADEON_TXFORMAT_Y8:
1840                         track->textures[i].cpp = 1;
1841                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1842                         break;
1843                 case RADEON_TXFORMAT_AI88:
1844                 case RADEON_TXFORMAT_ARGB1555:
1845                 case RADEON_TXFORMAT_RGB565:
1846                 case RADEON_TXFORMAT_ARGB4444:
1847                 case RADEON_TXFORMAT_VYUY422:
1848                 case RADEON_TXFORMAT_YVYU422:
1849                 case RADEON_TXFORMAT_SHADOW16:
1850                 case RADEON_TXFORMAT_LDUDV655:
1851                 case RADEON_TXFORMAT_DUDV88:
1852                         track->textures[i].cpp = 2;
1853                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1854                         break;
1855                 case RADEON_TXFORMAT_ARGB8888:
1856                 case RADEON_TXFORMAT_RGBA8888:
1857                 case RADEON_TXFORMAT_SHADOW32:
1858                 case RADEON_TXFORMAT_LDUDUV8888:
1859                         track->textures[i].cpp = 4;
1860                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1861                         break;
1862                 case RADEON_TXFORMAT_DXT1:
1863                         track->textures[i].cpp = 1;
1864                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1865                         break;
1866                 case RADEON_TXFORMAT_DXT23:
1867                 case RADEON_TXFORMAT_DXT45:
1868                         track->textures[i].cpp = 1;
1869                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1870                         break;
1871                 }
1872                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1873                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1874                 track->tex_dirty = true;
1875                 break;
1876         case RADEON_PP_CUBIC_FACES_0:
1877         case RADEON_PP_CUBIC_FACES_1:
1878         case RADEON_PP_CUBIC_FACES_2:
1879                 tmp = idx_value;
1880                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1881                 for (face = 0; face < 4; face++) {
1882                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1883                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1884                 }
1885                 track->tex_dirty = true;
1886                 break;
1887         default:
1888                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1889                        reg, idx);
1890                 return -EINVAL;
1891         }
1892         return 0;
1893 }
1894
1895 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1896                                          struct radeon_cs_packet *pkt,
1897                                          struct radeon_bo *robj)
1898 {
1899         unsigned idx;
1900         u32 value;
1901         idx = pkt->idx + 1;
1902         value = radeon_get_ib_value(p, idx + 2);
1903         if ((value + 1) > radeon_bo_size(robj)) {
1904                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1905                           "(need %u have %lu) !\n",
1906                           value + 1,
1907                           radeon_bo_size(robj));
1908                 return -EINVAL;
1909         }
1910         return 0;
1911 }
1912
1913 static int r100_packet3_check(struct radeon_cs_parser *p,
1914                               struct radeon_cs_packet *pkt)
1915 {
1916         struct radeon_bo_list *reloc;
1917         struct r100_cs_track *track;
1918         unsigned idx;
1919         volatile uint32_t *ib;
1920         int r;
1921
1922         ib = p->ib.ptr;
1923         idx = pkt->idx + 1;
1924         track = (struct r100_cs_track *)p->track;
1925         switch (pkt->opcode) {
1926         case PACKET3_3D_LOAD_VBPNTR:
1927                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1928                 if (r)
1929                         return r;
1930                 break;
1931         case PACKET3_INDX_BUFFER:
1932                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1933                 if (r) {
1934                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1935                         radeon_cs_dump_packet(p, pkt);
1936                         return r;
1937                 }
1938                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
1939                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1940                 if (r) {
1941                         return r;
1942                 }
1943                 break;
1944         case 0x23:
1945                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1946                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1947                 if (r) {
1948                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1949                         radeon_cs_dump_packet(p, pkt);
1950                         return r;
1951                 }
1952                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
1953                 track->num_arrays = 1;
1954                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1955
1956                 track->arrays[0].robj = reloc->robj;
1957                 track->arrays[0].esize = track->vtx_size;
1958
1959                 track->max_indx = radeon_get_ib_value(p, idx+1);
1960
1961                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1962                 track->immd_dwords = pkt->count - 1;
1963                 r = r100_cs_track_check(p->rdev, track);
1964                 if (r)
1965                         return r;
1966                 break;
1967         case PACKET3_3D_DRAW_IMMD:
1968                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1969                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1970                         return -EINVAL;
1971                 }
1972                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1973                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1974                 track->immd_dwords = pkt->count - 1;
1975                 r = r100_cs_track_check(p->rdev, track);
1976                 if (r)
1977                         return r;
1978                 break;
1979                 /* triggers drawing using in-packet vertex data */
1980         case PACKET3_3D_DRAW_IMMD_2:
1981                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1982                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1983                         return -EINVAL;
1984                 }
1985                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1986                 track->immd_dwords = pkt->count;
1987                 r = r100_cs_track_check(p->rdev, track);
1988                 if (r)
1989                         return r;
1990                 break;
1991                 /* triggers drawing using in-packet vertex data */
1992         case PACKET3_3D_DRAW_VBUF_2:
1993                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1994                 r = r100_cs_track_check(p->rdev, track);
1995                 if (r)
1996                         return r;
1997                 break;
1998                 /* triggers drawing of vertex buffers setup elsewhere */
1999         case PACKET3_3D_DRAW_INDX_2:
2000                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2001                 r = r100_cs_track_check(p->rdev, track);
2002                 if (r)
2003                         return r;
2004                 break;
2005                 /* triggers drawing using indices to vertex buffer */
2006         case PACKET3_3D_DRAW_VBUF:
2007                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2008                 r = r100_cs_track_check(p->rdev, track);
2009                 if (r)
2010                         return r;
2011                 break;
2012                 /* triggers drawing of vertex buffers setup elsewhere */
2013         case PACKET3_3D_DRAW_INDX:
2014                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2015                 r = r100_cs_track_check(p->rdev, track);
2016                 if (r)
2017                         return r;
2018                 break;
2019                 /* triggers drawing using indices to vertex buffer */
2020         case PACKET3_3D_CLEAR_HIZ:
2021         case PACKET3_3D_CLEAR_ZMASK:
2022                 if (p->rdev->hyperz_filp != p->filp)
2023                         return -EINVAL;
2024                 break;
2025         case PACKET3_NOP:
2026                 break;
2027         default:
2028                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2029                 return -EINVAL;
2030         }
2031         return 0;
2032 }
2033
2034 int r100_cs_parse(struct radeon_cs_parser *p)
2035 {
2036         struct radeon_cs_packet pkt;
2037         struct r100_cs_track *track;
2038         int r;
2039
2040         track = kzalloc(sizeof(*track), GFP_KERNEL);
2041         if (!track)
2042                 return -ENOMEM;
2043         r100_cs_track_clear(p->rdev, track);
2044         p->track = track;
2045         do {
2046                 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2047                 if (r) {
2048                         return r;
2049                 }
2050                 p->idx += pkt.count + 2;
2051                 switch (pkt.type) {
2052                 case RADEON_PACKET_TYPE0:
2053                         if (p->rdev->family >= CHIP_R200)
2054                                 r = r100_cs_parse_packet0(p, &pkt,
2055                                         p->rdev->config.r100.reg_safe_bm,
2056                                         p->rdev->config.r100.reg_safe_bm_size,
2057                                         &r200_packet0_check);
2058                         else
2059                                 r = r100_cs_parse_packet0(p, &pkt,
2060                                         p->rdev->config.r100.reg_safe_bm,
2061                                         p->rdev->config.r100.reg_safe_bm_size,
2062                                         &r100_packet0_check);
2063                         break;
2064                 case RADEON_PACKET_TYPE2:
2065                         break;
2066                 case RADEON_PACKET_TYPE3:
2067                         r = r100_packet3_check(p, &pkt);
2068                         break;
2069                 default:
2070                         DRM_ERROR("Unknown packet type %d !\n",
2071                                   pkt.type);
2072                         return -EINVAL;
2073                 }
2074                 if (r)
2075                         return r;
2076         } while (p->idx < p->chunk_ib->length_dw);
2077         return 0;
2078 }
2079
2080 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2081 {
2082         DRM_ERROR("pitch                      %d\n", t->pitch);
2083         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
2084         DRM_ERROR("width                      %d\n", t->width);
2085         DRM_ERROR("width_11                   %d\n", t->width_11);
2086         DRM_ERROR("height                     %d\n", t->height);
2087         DRM_ERROR("height_11                  %d\n", t->height_11);
2088         DRM_ERROR("num levels                 %d\n", t->num_levels);
2089         DRM_ERROR("depth                      %d\n", t->txdepth);
2090         DRM_ERROR("bpp                        %d\n", t->cpp);
2091         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
2092         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
2093         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2094         DRM_ERROR("compress format            %d\n", t->compress_format);
2095 }
2096
2097 static int r100_track_compress_size(int compress_format, int w, int h)
2098 {
2099         int block_width, block_height, block_bytes;
2100         int wblocks, hblocks;
2101         int min_wblocks;
2102         int sz;
2103
2104         block_width = 4;
2105         block_height = 4;
2106
2107         switch (compress_format) {
2108         case R100_TRACK_COMP_DXT1:
2109                 block_bytes = 8;
2110                 min_wblocks = 4;
2111                 break;
2112         default:
2113         case R100_TRACK_COMP_DXT35:
2114                 block_bytes = 16;
2115                 min_wblocks = 2;
2116                 break;
2117         }
2118
2119         hblocks = (h + block_height - 1) / block_height;
2120         wblocks = (w + block_width - 1) / block_width;
2121         if (wblocks < min_wblocks)
2122                 wblocks = min_wblocks;
2123         sz = wblocks * hblocks * block_bytes;
2124         return sz;
2125 }
2126
2127 static int r100_cs_track_cube(struct radeon_device *rdev,
2128                               struct r100_cs_track *track, unsigned idx)
2129 {
2130         unsigned face, w, h;
2131         struct radeon_bo *cube_robj;
2132         unsigned long size;
2133         unsigned compress_format = track->textures[idx].compress_format;
2134
2135         for (face = 0; face < 5; face++) {
2136                 cube_robj = track->textures[idx].cube_info[face].robj;
2137                 w = track->textures[idx].cube_info[face].width;
2138                 h = track->textures[idx].cube_info[face].height;
2139
2140                 if (compress_format) {
2141                         size = r100_track_compress_size(compress_format, w, h);
2142                 } else
2143                         size = w * h;
2144                 size *= track->textures[idx].cpp;
2145
2146                 size += track->textures[idx].cube_info[face].offset;
2147
2148                 if (size > radeon_bo_size(cube_robj)) {
2149                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2150                                   size, radeon_bo_size(cube_robj));
2151                         r100_cs_track_texture_print(&track->textures[idx]);
2152                         return -1;
2153                 }
2154         }
2155         return 0;
2156 }
2157
2158 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2159                                        struct r100_cs_track *track)
2160 {
2161         struct radeon_bo *robj;
2162         unsigned long size;
2163         unsigned u, i, w, h, d;
2164         int ret;
2165
2166         for (u = 0; u < track->num_texture; u++) {
2167                 if (!track->textures[u].enabled)
2168                         continue;
2169                 if (track->textures[u].lookup_disable)
2170                         continue;
2171                 robj = track->textures[u].robj;
2172                 if (robj == NULL) {
2173                         DRM_ERROR("No texture bound to unit %u\n", u);
2174                         return -EINVAL;
2175                 }
2176                 size = 0;
2177                 for (i = 0; i <= track->textures[u].num_levels; i++) {
2178                         if (track->textures[u].use_pitch) {
2179                                 if (rdev->family < CHIP_R300)
2180                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2181                                 else
2182                                         w = track->textures[u].pitch / (1 << i);
2183                         } else {
2184                                 w = track->textures[u].width;
2185                                 if (rdev->family >= CHIP_RV515)
2186                                         w |= track->textures[u].width_11;
2187                                 w = w / (1 << i);
2188                                 if (track->textures[u].roundup_w)
2189                                         w = roundup_pow_of_two(w);
2190                         }
2191                         h = track->textures[u].height;
2192                         if (rdev->family >= CHIP_RV515)
2193                                 h |= track->textures[u].height_11;
2194                         h = h / (1 << i);
2195                         if (track->textures[u].roundup_h)
2196                                 h = roundup_pow_of_two(h);
2197                         if (track->textures[u].tex_coord_type == 1) {
2198                                 d = (1 << track->textures[u].txdepth) / (1 << i);
2199                                 if (!d)
2200                                         d = 1;
2201                         } else {
2202                                 d = 1;
2203                         }
2204                         if (track->textures[u].compress_format) {
2205
2206                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2207                                 /* compressed textures are block based */
2208                         } else
2209                                 size += w * h * d;
2210                 }
2211                 size *= track->textures[u].cpp;
2212
2213                 switch (track->textures[u].tex_coord_type) {
2214                 case 0:
2215                 case 1:
2216                         break;
2217                 case 2:
2218                         if (track->separate_cube) {
2219                                 ret = r100_cs_track_cube(rdev, track, u);
2220                                 if (ret)
2221                                         return ret;
2222                         } else
2223                                 size *= 6;
2224                         break;
2225                 default:
2226                         DRM_ERROR("Invalid texture coordinate type %u for unit "
2227                                   "%u\n", track->textures[u].tex_coord_type, u);
2228                         return -EINVAL;
2229                 }
2230                 if (size > radeon_bo_size(robj)) {
2231                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2232                                   "%lu\n", u, size, radeon_bo_size(robj));
2233                         r100_cs_track_texture_print(&track->textures[u]);
2234                         return -EINVAL;
2235                 }
2236         }
2237         return 0;
2238 }
2239
2240 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2241 {
2242         unsigned i;
2243         unsigned long size;
2244         unsigned prim_walk;
2245         unsigned nverts;
2246         unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2247
2248         if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2249             !track->blend_read_enable)
2250                 num_cb = 0;
2251
2252         for (i = 0; i < num_cb; i++) {
2253                 if (track->cb[i].robj == NULL) {
2254                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2255                         return -EINVAL;
2256                 }
2257                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2258                 size += track->cb[i].offset;
2259                 if (size > radeon_bo_size(track->cb[i].robj)) {
2260                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
2261                                   "(need %lu have %lu) !\n", i, size,
2262                                   radeon_bo_size(track->cb[i].robj));
2263                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2264                                   i, track->cb[i].pitch, track->cb[i].cpp,
2265                                   track->cb[i].offset, track->maxy);
2266                         return -EINVAL;
2267                 }
2268         }
2269         track->cb_dirty = false;
2270
2271         if (track->zb_dirty && track->z_enabled) {
2272                 if (track->zb.robj == NULL) {
2273                         DRM_ERROR("[drm] No buffer for z buffer !\n");
2274                         return -EINVAL;
2275                 }
2276                 size = track->zb.pitch * track->zb.cpp * track->maxy;
2277                 size += track->zb.offset;
2278                 if (size > radeon_bo_size(track->zb.robj)) {
2279                         DRM_ERROR("[drm] Buffer too small for z buffer "
2280                                   "(need %lu have %lu) !\n", size,
2281                                   radeon_bo_size(track->zb.robj));
2282                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2283                                   track->zb.pitch, track->zb.cpp,
2284                                   track->zb.offset, track->maxy);
2285                         return -EINVAL;
2286                 }
2287         }
2288         track->zb_dirty = false;
2289
2290         if (track->aa_dirty && track->aaresolve) {
2291                 if (track->aa.robj == NULL) {
2292                         DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2293                         return -EINVAL;
2294                 }
2295                 /* I believe the format comes from colorbuffer0. */
2296                 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2297                 size += track->aa.offset;
2298                 if (size > radeon_bo_size(track->aa.robj)) {
2299                         DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2300                                   "(need %lu have %lu) !\n", i, size,
2301                                   radeon_bo_size(track->aa.robj));
2302                         DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2303                                   i, track->aa.pitch, track->cb[0].cpp,
2304                                   track->aa.offset, track->maxy);
2305                         return -EINVAL;
2306                 }
2307         }
2308         track->aa_dirty = false;
2309
2310         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2311         if (track->vap_vf_cntl & (1 << 14)) {
2312                 nverts = track->vap_alt_nverts;
2313         } else {
2314                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2315         }
2316         switch (prim_walk) {
2317         case 1:
2318                 for (i = 0; i < track->num_arrays; i++) {
2319                         size = track->arrays[i].esize * track->max_indx * 4;
2320                         if (track->arrays[i].robj == NULL) {
2321                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2322                                           "bound\n", prim_walk, i);
2323                                 return -EINVAL;
2324                         }
2325                         if (size > radeon_bo_size(track->arrays[i].robj)) {
2326                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2327                                         "need %lu dwords have %lu dwords\n",
2328                                         prim_walk, i, size >> 2,
2329                                         radeon_bo_size(track->arrays[i].robj)
2330                                         >> 2);
2331                                 DRM_ERROR("Max indices %u\n", track->max_indx);
2332                                 return -EINVAL;
2333                         }
2334                 }
2335                 break;
2336         case 2:
2337                 for (i = 0; i < track->num_arrays; i++) {
2338                         size = track->arrays[i].esize * (nverts - 1) * 4;
2339                         if (track->arrays[i].robj == NULL) {
2340                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2341                                           "bound\n", prim_walk, i);
2342                                 return -EINVAL;
2343                         }
2344                         if (size > radeon_bo_size(track->arrays[i].robj)) {
2345                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2346                                         "need %lu dwords have %lu dwords\n",
2347                                         prim_walk, i, size >> 2,
2348                                         radeon_bo_size(track->arrays[i].robj)
2349                                         >> 2);
2350                                 return -EINVAL;
2351                         }
2352                 }
2353                 break;
2354         case 3:
2355                 size = track->vtx_size * nverts;
2356                 if (size != track->immd_dwords) {
2357                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2358                                   track->immd_dwords, size);
2359                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2360                                   nverts, track->vtx_size);
2361                         return -EINVAL;
2362                 }
2363                 break;
2364         default:
2365                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2366                           prim_walk);
2367                 return -EINVAL;
2368         }
2369
2370         if (track->tex_dirty) {
2371                 track->tex_dirty = false;
2372                 return r100_cs_track_texture_check(rdev, track);
2373         }
2374         return 0;
2375 }
2376
2377 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2378 {
2379         unsigned i, face;
2380
2381         track->cb_dirty = true;
2382         track->zb_dirty = true;
2383         track->tex_dirty = true;
2384         track->aa_dirty = true;
2385
2386         if (rdev->family < CHIP_R300) {
2387                 track->num_cb = 1;
2388                 if (rdev->family <= CHIP_RS200)
2389                         track->num_texture = 3;
2390                 else
2391                         track->num_texture = 6;
2392                 track->maxy = 2048;
2393                 track->separate_cube = 1;
2394         } else {
2395                 track->num_cb = 4;
2396                 track->num_texture = 16;
2397                 track->maxy = 4096;
2398                 track->separate_cube = 0;
2399                 track->aaresolve = false;
2400                 track->aa.robj = NULL;
2401         }
2402
2403         for (i = 0; i < track->num_cb; i++) {
2404                 track->cb[i].robj = NULL;
2405                 track->cb[i].pitch = 8192;
2406                 track->cb[i].cpp = 16;
2407                 track->cb[i].offset = 0;
2408         }
2409         track->z_enabled = true;
2410         track->zb.robj = NULL;
2411         track->zb.pitch = 8192;
2412         track->zb.cpp = 4;
2413         track->zb.offset = 0;
2414         track->vtx_size = 0x7F;
2415         track->immd_dwords = 0xFFFFFFFFUL;
2416         track->num_arrays = 11;
2417         track->max_indx = 0x00FFFFFFUL;
2418         for (i = 0; i < track->num_arrays; i++) {
2419                 track->arrays[i].robj = NULL;
2420                 track->arrays[i].esize = 0x7F;
2421         }
2422         for (i = 0; i < track->num_texture; i++) {
2423                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2424                 track->textures[i].pitch = 16536;
2425                 track->textures[i].width = 16536;
2426                 track->textures[i].height = 16536;
2427                 track->textures[i].width_11 = 1 << 11;
2428                 track->textures[i].height_11 = 1 << 11;
2429                 track->textures[i].num_levels = 12;
2430                 if (rdev->family <= CHIP_RS200) {
2431                         track->textures[i].tex_coord_type = 0;
2432                         track->textures[i].txdepth = 0;
2433                 } else {
2434                         track->textures[i].txdepth = 16;
2435                         track->textures[i].tex_coord_type = 1;
2436                 }
2437                 track->textures[i].cpp = 64;
2438                 track->textures[i].robj = NULL;
2439                 /* CS IB emission code makes sure texture unit are disabled */
2440                 track->textures[i].enabled = false;
2441                 track->textures[i].lookup_disable = false;
2442                 track->textures[i].roundup_w = true;
2443                 track->textures[i].roundup_h = true;
2444                 if (track->separate_cube)
2445                         for (face = 0; face < 5; face++) {
2446                                 track->textures[i].cube_info[face].robj = NULL;
2447                                 track->textures[i].cube_info[face].width = 16536;
2448                                 track->textures[i].cube_info[face].height = 16536;
2449                                 track->textures[i].cube_info[face].offset = 0;
2450                         }
2451         }
2452 }
2453
2454 /*
2455  * Global GPU functions
2456  */
2457 static void r100_errata(struct radeon_device *rdev)
2458 {
2459         rdev->pll_errata = 0;
2460
2461         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2462                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2463         }
2464
2465         if (rdev->family == CHIP_RV100 ||
2466             rdev->family == CHIP_RS100 ||
2467             rdev->family == CHIP_RS200) {
2468                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2469         }
2470 }
2471
2472 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2473 {
2474         unsigned i;
2475         uint32_t tmp;
2476
2477         for (i = 0; i < rdev->usec_timeout; i++) {
2478                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2479                 if (tmp >= n) {
2480                         return 0;
2481                 }
2482                 DRM_UDELAY(1);
2483         }
2484         return -1;
2485 }
2486
2487 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2488 {
2489         unsigned i;
2490         uint32_t tmp;
2491
2492         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2493                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2494                        " Bad things might happen.\n");
2495         }
2496         for (i = 0; i < rdev->usec_timeout; i++) {
2497                 tmp = RREG32(RADEON_RBBM_STATUS);
2498                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2499                         return 0;
2500                 }
2501                 DRM_UDELAY(1);
2502         }
2503         return -1;
2504 }
2505
2506 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2507 {
2508         unsigned i;
2509         uint32_t tmp;
2510
2511         for (i = 0; i < rdev->usec_timeout; i++) {
2512                 /* read MC_STATUS */
2513                 tmp = RREG32(RADEON_MC_STATUS);
2514                 if (tmp & RADEON_MC_IDLE) {
2515                         return 0;
2516                 }
2517                 DRM_UDELAY(1);
2518         }
2519         return -1;
2520 }
2521
2522 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2523 {
2524         u32 rbbm_status;
2525
2526         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2527         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2528                 radeon_ring_lockup_update(rdev, ring);
2529                 return false;
2530         }
2531         return radeon_ring_test_lockup(rdev, ring);
2532 }
2533
2534 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2535 void r100_enable_bm(struct radeon_device *rdev)
2536 {
2537         uint32_t tmp;
2538         /* Enable bus mastering */
2539         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2540         WREG32(RADEON_BUS_CNTL, tmp);
2541 }
2542
2543 void r100_bm_disable(struct radeon_device *rdev)
2544 {
2545         u32 tmp;
2546
2547         /* disable bus mastering */
2548         tmp = RREG32(R_000030_BUS_CNTL);
2549         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2550         mdelay(1);
2551         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2552         mdelay(1);
2553         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2554         tmp = RREG32(RADEON_BUS_CNTL);
2555         mdelay(1);
2556         pci_clear_master(rdev->pdev);
2557         mdelay(1);
2558 }
2559
2560 int r100_asic_reset(struct radeon_device *rdev, bool hard)
2561 {
2562         struct r100_mc_save save;
2563         u32 status, tmp;
2564         int ret = 0;
2565
2566         status = RREG32(R_000E40_RBBM_STATUS);
2567         if (!G_000E40_GUI_ACTIVE(status)) {
2568                 return 0;
2569         }
2570         r100_mc_stop(rdev, &save);
2571         status = RREG32(R_000E40_RBBM_STATUS);
2572         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2573         /* stop CP */
2574         WREG32(RADEON_CP_CSQ_CNTL, 0);
2575         tmp = RREG32(RADEON_CP_RB_CNTL);
2576         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2577         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2578         WREG32(RADEON_CP_RB_WPTR, 0);
2579         WREG32(RADEON_CP_RB_CNTL, tmp);
2580         /* save PCI state */
2581         pci_save_state(rdev->pdev);
2582         /* disable bus mastering */
2583         r100_bm_disable(rdev);
2584         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2585                                         S_0000F0_SOFT_RESET_RE(1) |
2586                                         S_0000F0_SOFT_RESET_PP(1) |
2587                                         S_0000F0_SOFT_RESET_RB(1));
2588         RREG32(R_0000F0_RBBM_SOFT_RESET);
2589         mdelay(500);
2590         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2591         mdelay(1);
2592         status = RREG32(R_000E40_RBBM_STATUS);
2593         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2594         /* reset CP */
2595         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2596         RREG32(R_0000F0_RBBM_SOFT_RESET);
2597         mdelay(500);
2598         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2599         mdelay(1);
2600         status = RREG32(R_000E40_RBBM_STATUS);
2601         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2602         /* restore PCI & busmastering */
2603         pci_restore_state(rdev->pdev);
2604         r100_enable_bm(rdev);
2605         /* Check if GPU is idle */
2606         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2607                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2608                 dev_err(rdev->dev, "failed to reset GPU\n");
2609                 ret = -1;
2610         } else
2611                 dev_info(rdev->dev, "GPU reset succeed\n");
2612         r100_mc_resume(rdev, &save);
2613         return ret;
2614 }
2615
2616 void r100_set_common_regs(struct radeon_device *rdev)
2617 {
2618         struct drm_device *dev = rdev->ddev;
2619         bool force_dac2 = false;
2620         u32 tmp;
2621
2622         /* set these so they don't interfere with anything */
2623         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2624         WREG32(RADEON_SUBPIC_CNTL, 0);
2625         WREG32(RADEON_VIPH_CONTROL, 0);
2626         WREG32(RADEON_I2C_CNTL_1, 0);
2627         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2628         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2629         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2630
2631         /* always set up dac2 on rn50 and some rv100 as lots
2632          * of servers seem to wire it up to a VGA port but
2633          * don't report it in the bios connector
2634          * table.
2635          */
2636         switch (dev->pdev->device) {
2637                 /* RN50 */
2638         case 0x515e:
2639         case 0x5969:
2640                 force_dac2 = true;
2641                 break;
2642                 /* RV100*/
2643         case 0x5159:
2644         case 0x515a:
2645                 /* DELL triple head servers */
2646                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2647                     ((dev->pdev->subsystem_device == 0x016c) ||
2648                      (dev->pdev->subsystem_device == 0x016d) ||
2649                      (dev->pdev->subsystem_device == 0x016e) ||
2650                      (dev->pdev->subsystem_device == 0x016f) ||
2651                      (dev->pdev->subsystem_device == 0x0170) ||
2652                      (dev->pdev->subsystem_device == 0x017d) ||
2653                      (dev->pdev->subsystem_device == 0x017e) ||
2654                      (dev->pdev->subsystem_device == 0x0183) ||
2655                      (dev->pdev->subsystem_device == 0x018a) ||
2656                      (dev->pdev->subsystem_device == 0x019a)))
2657                         force_dac2 = true;
2658                 break;
2659         }
2660
2661         if (force_dac2) {
2662                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2663                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2664                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2665
2666                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2667                    enable it, even it's detected.
2668                 */
2669
2670                 /* force it to crtc0 */
2671                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2672                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2673                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2674
2675                 /* set up the TV DAC */
2676                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2677                                  RADEON_TV_DAC_STD_MASK |
2678                                  RADEON_TV_DAC_RDACPD |
2679                                  RADEON_TV_DAC_GDACPD |
2680                                  RADEON_TV_DAC_BDACPD |
2681                                  RADEON_TV_DAC_BGADJ_MASK |
2682                                  RADEON_TV_DAC_DACADJ_MASK);
2683                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2684                                 RADEON_TV_DAC_NHOLD |
2685                                 RADEON_TV_DAC_STD_PS2 |
2686                                 (0x58 << 16));
2687
2688                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2689                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2690                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2691         }
2692
2693         /* switch PM block to ACPI mode */
2694         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2695         tmp &= ~RADEON_PM_MODE_SEL;
2696         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2697
2698 }
2699
2700 /*
2701  * VRAM info
2702  */
2703 static void r100_vram_get_type(struct radeon_device *rdev)
2704 {
2705         uint32_t tmp;
2706
2707         rdev->mc.vram_is_ddr = false;
2708         if (rdev->flags & RADEON_IS_IGP)
2709                 rdev->mc.vram_is_ddr = true;
2710         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2711                 rdev->mc.vram_is_ddr = true;
2712         if ((rdev->family == CHIP_RV100) ||
2713             (rdev->family == CHIP_RS100) ||
2714             (rdev->family == CHIP_RS200)) {
2715                 tmp = RREG32(RADEON_MEM_CNTL);
2716                 if (tmp & RV100_HALF_MODE) {
2717                         rdev->mc.vram_width = 32;
2718                 } else {
2719                         rdev->mc.vram_width = 64;
2720                 }
2721                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2722                         rdev->mc.vram_width /= 4;
2723                         rdev->mc.vram_is_ddr = true;
2724                 }
2725         } else if (rdev->family <= CHIP_RV280) {
2726                 tmp = RREG32(RADEON_MEM_CNTL);
2727                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2728                         rdev->mc.vram_width = 128;
2729                 } else {
2730                         rdev->mc.vram_width = 64;
2731                 }
2732         } else {
2733                 /* newer IGPs */
2734                 rdev->mc.vram_width = 128;
2735         }
2736 }
2737
2738 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2739 {
2740         u32 aper_size;
2741         u8 byte;
2742
2743         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2744
2745         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2746          * that is has the 2nd generation multifunction PCI interface
2747          */
2748         if (rdev->family == CHIP_RV280 ||
2749             rdev->family >= CHIP_RV350) {
2750                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2751                        ~RADEON_HDP_APER_CNTL);
2752                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2753                 return aper_size * 2;
2754         }
2755
2756         /* Older cards have all sorts of funny issues to deal with. First
2757          * check if it's a multifunction card by reading the PCI config
2758          * header type... Limit those to one aperture size
2759          */
2760         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2761         if (byte & 0x80) {
2762                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2763                 DRM_INFO("Limiting VRAM to one aperture\n");
2764                 return aper_size;
2765         }
2766
2767         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2768          * have set it up. We don't write this as it's broken on some ASICs but
2769          * we expect the BIOS to have done the right thing (might be too optimistic...)
2770          */
2771         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2772                 return aper_size * 2;
2773         return aper_size;
2774 }
2775
2776 void r100_vram_init_sizes(struct radeon_device *rdev)
2777 {
2778         u64 config_aper_size;
2779
2780         /* work out accessible VRAM */
2781         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2782         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2783         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2784         /* FIXME we don't use the second aperture yet when we could use it */
2785         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2786                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2787         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2788         if (rdev->flags & RADEON_IS_IGP) {
2789                 uint32_t tom;
2790                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2791                 tom = RREG32(RADEON_NB_TOM);
2792                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2793                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2794                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2795         } else {
2796                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2797                 /* Some production boards of m6 will report 0
2798                  * if it's 8 MB
2799                  */
2800                 if (rdev->mc.real_vram_size == 0) {
2801                         rdev->mc.real_vram_size = 8192 * 1024;
2802                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2803                 }
2804                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2805                  * Novell bug 204882 + along with lots of ubuntu ones
2806                  */
2807                 if (rdev->mc.aper_size > config_aper_size)
2808                         config_aper_size = rdev->mc.aper_size;
2809
2810                 if (config_aper_size > rdev->mc.real_vram_size)
2811                         rdev->mc.mc_vram_size = config_aper_size;
2812                 else
2813                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2814         }
2815 }
2816
2817 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2818 {
2819         uint32_t temp;
2820
2821         temp = RREG32(RADEON_CONFIG_CNTL);
2822         if (state == false) {
2823                 temp &= ~RADEON_CFG_VGA_RAM_EN;
2824                 temp |= RADEON_CFG_VGA_IO_DIS;
2825         } else {
2826                 temp &= ~RADEON_CFG_VGA_IO_DIS;
2827         }
2828         WREG32(RADEON_CONFIG_CNTL, temp);
2829 }
2830
2831 static void r100_mc_init(struct radeon_device *rdev)
2832 {
2833         u64 base;
2834
2835         r100_vram_get_type(rdev);
2836         r100_vram_init_sizes(rdev);
2837         base = rdev->mc.aper_base;
2838         if (rdev->flags & RADEON_IS_IGP)
2839                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2840         radeon_vram_location(rdev, &rdev->mc, base);
2841         rdev->mc.gtt_base_align = 0;
2842         if (!(rdev->flags & RADEON_IS_AGP))
2843                 radeon_gtt_location(rdev, &rdev->mc);
2844         radeon_update_bandwidth_info(rdev);
2845 }
2846
2847
2848 /*
2849  * Indirect registers accessor
2850  */
2851 void r100_pll_errata_after_index(struct radeon_device *rdev)
2852 {
2853         if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2854                 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2855                 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2856         }
2857 }
2858
2859 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2860 {
2861         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2862          * or the chip could hang on a subsequent access
2863          */
2864         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2865                 mdelay(5);
2866         }
2867
2868         /* This function is required to workaround a hardware bug in some (all?)
2869          * revisions of the R300.  This workaround should be called after every
2870          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2871          * may not be correct.
2872          */
2873         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2874                 uint32_t save, tmp;
2875
2876                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2877                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2878                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2879                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2880                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2881         }
2882 }
2883
2884 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2885 {
2886         unsigned long flags;
2887         uint32_t data;
2888
2889         spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2890         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2891         r100_pll_errata_after_index(rdev);
2892         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2893         r100_pll_errata_after_data(rdev);
2894         spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2895         return data;
2896 }
2897
2898 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2899 {
2900         unsigned long flags;
2901
2902         spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2903         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2904         r100_pll_errata_after_index(rdev);
2905         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2906         r100_pll_errata_after_data(rdev);
2907         spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2908 }
2909
2910 static void r100_set_safe_registers(struct radeon_device *rdev)
2911 {
2912         if (ASIC_IS_RN50(rdev)) {
2913                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2914                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2915         } else if (rdev->family < CHIP_R200) {
2916                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2917                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2918         } else {
2919                 r200_set_safe_registers(rdev);
2920         }
2921 }
2922
2923 /*
2924  * Debugfs info
2925  */
2926 #if defined(CONFIG_DEBUG_FS)
2927 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2928 {
2929         struct drm_info_node *node = (struct drm_info_node *) m->private;
2930         struct drm_device *dev = node->minor->dev;
2931         struct radeon_device *rdev = dev->dev_private;
2932         uint32_t reg, value;
2933         unsigned i;
2934
2935         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2936         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2937         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2938         for (i = 0; i < 64; i++) {
2939                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2940                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2941                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2942                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2943                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2944         }
2945         return 0;
2946 }
2947
2948 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2949 {
2950         struct drm_info_node *node = (struct drm_info_node *) m->private;
2951         struct drm_device *dev = node->minor->dev;
2952         struct radeon_device *rdev = dev->dev_private;
2953         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2954         uint32_t rdp, wdp;
2955         unsigned count, i, j;
2956
2957         radeon_ring_free_size(rdev, ring);
2958         rdp = RREG32(RADEON_CP_RB_RPTR);
2959         wdp = RREG32(RADEON_CP_RB_WPTR);
2960         count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2961         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2962         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2963         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2964         seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2965         seq_printf(m, "%u dwords in ring\n", count);
2966         if (ring->ready) {
2967                 for (j = 0; j <= count; j++) {
2968                         i = (rdp + j) & ring->ptr_mask;
2969                         seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2970                 }
2971         }
2972         return 0;
2973 }
2974
2975
2976 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2977 {
2978         struct drm_info_node *node = (struct drm_info_node *) m->private;
2979         struct drm_device *dev = node->minor->dev;
2980         struct radeon_device *rdev = dev->dev_private;
2981         uint32_t csq_stat, csq2_stat, tmp;
2982         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2983         unsigned i;
2984
2985         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2986         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2987         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2988         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2989         r_rptr = (csq_stat >> 0) & 0x3ff;
2990         r_wptr = (csq_stat >> 10) & 0x3ff;
2991         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2992         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2993         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2994         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2995         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2996         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2997         seq_printf(m, "Ring rptr %u\n", r_rptr);
2998         seq_printf(m, "Ring wptr %u\n", r_wptr);
2999         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
3000         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
3001         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
3002         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
3003         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
3004          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
3005         seq_printf(m, "Ring fifo:\n");
3006         for (i = 0; i < 256; i++) {
3007                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3008                 tmp = RREG32(RADEON_CP_CSQ_DATA);
3009                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3010         }
3011         seq_printf(m, "Indirect1 fifo:\n");
3012         for (i = 256; i <= 512; i++) {
3013                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3014                 tmp = RREG32(RADEON_CP_CSQ_DATA);
3015                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3016         }
3017         seq_printf(m, "Indirect2 fifo:\n");
3018         for (i = 640; i < ib1_wptr; i++) {
3019                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3020                 tmp = RREG32(RADEON_CP_CSQ_DATA);
3021                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3022         }
3023         return 0;
3024 }
3025
3026 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3027 {
3028         struct drm_info_node *node = (struct drm_info_node *) m->private;
3029         struct drm_device *dev = node->minor->dev;
3030         struct radeon_device *rdev = dev->dev_private;
3031         uint32_t tmp;
3032
3033         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3034         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3035         tmp = RREG32(RADEON_MC_FB_LOCATION);
3036         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3037         tmp = RREG32(RADEON_BUS_CNTL);
3038         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3039         tmp = RREG32(RADEON_MC_AGP_LOCATION);
3040         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3041         tmp = RREG32(RADEON_AGP_BASE);
3042         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3043         tmp = RREG32(RADEON_HOST_PATH_CNTL);
3044         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3045         tmp = RREG32(0x01D0);
3046         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3047         tmp = RREG32(RADEON_AIC_LO_ADDR);
3048         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3049         tmp = RREG32(RADEON_AIC_HI_ADDR);
3050         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3051         tmp = RREG32(0x01E4);
3052         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3053         return 0;
3054 }
3055
3056 static struct drm_info_list r100_debugfs_rbbm_list[] = {
3057         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3058 };
3059
3060 static struct drm_info_list r100_debugfs_cp_list[] = {
3061         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3062         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3063 };
3064
3065 static struct drm_info_list r100_debugfs_mc_info_list[] = {
3066         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3067 };
3068 #endif
3069
3070 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3071 {
3072 #if defined(CONFIG_DEBUG_FS)
3073         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3074 #else
3075         return 0;
3076 #endif
3077 }
3078
3079 int r100_debugfs_cp_init(struct radeon_device *rdev)
3080 {
3081 #if defined(CONFIG_DEBUG_FS)
3082         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3083 #else
3084         return 0;
3085 #endif
3086 }
3087
3088 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3089 {
3090 #if defined(CONFIG_DEBUG_FS)
3091         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3092 #else
3093         return 0;
3094 #endif
3095 }
3096
3097 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3098                          uint32_t tiling_flags, uint32_t pitch,
3099                          uint32_t offset, uint32_t obj_size)
3100 {
3101         int surf_index = reg * 16;
3102         int flags = 0;
3103
3104         if (rdev->family <= CHIP_RS200) {
3105                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3106                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3107                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
3108                 if (tiling_flags & RADEON_TILING_MACRO)
3109                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
3110                 /* setting pitch to 0 disables tiling */
3111                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3112                                 == 0)
3113                         pitch = 0;
3114         } else if (rdev->family <= CHIP_RV280) {
3115                 if (tiling_flags & (RADEON_TILING_MACRO))
3116                         flags |= R200_SURF_TILE_COLOR_MACRO;
3117                 if (tiling_flags & RADEON_TILING_MICRO)
3118                         flags |= R200_SURF_TILE_COLOR_MICRO;
3119         } else {
3120                 if (tiling_flags & RADEON_TILING_MACRO)
3121                         flags |= R300_SURF_TILE_MACRO;
3122                 if (tiling_flags & RADEON_TILING_MICRO)
3123                         flags |= R300_SURF_TILE_MICRO;
3124         }
3125
3126         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3127                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3128         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3129                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3130
3131         /* r100/r200 divide by 16 */
3132         if (rdev->family < CHIP_R300)
3133                 flags |= pitch / 16;
3134         else
3135                 flags |= pitch / 8;
3136
3137
3138         DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3139         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3140         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3141         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3142         return 0;
3143 }
3144
3145 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3146 {
3147         int surf_index = reg * 16;
3148         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3149 }
3150
3151 void r100_bandwidth_update(struct radeon_device *rdev)
3152 {
3153         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3154         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3155         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff;
3156         fixed20_12 crit_point_ff = {0};
3157         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3158         fixed20_12 memtcas_ff[8] = {
3159                 dfixed_init(1),
3160                 dfixed_init(2),
3161                 dfixed_init(3),
3162                 dfixed_init(0),
3163                 dfixed_init_half(1),
3164                 dfixed_init_half(2),
3165                 dfixed_init(0),
3166         };
3167         fixed20_12 memtcas_rs480_ff[8] = {
3168                 dfixed_init(0),
3169                 dfixed_init(1),
3170                 dfixed_init(2),
3171                 dfixed_init(3),
3172                 dfixed_init(0),
3173                 dfixed_init_half(1),
3174                 dfixed_init_half(2),
3175                 dfixed_init_half(3),
3176         };
3177         fixed20_12 memtcas2_ff[8] = {
3178                 dfixed_init(0),
3179                 dfixed_init(1),
3180                 dfixed_init(2),
3181                 dfixed_init(3),
3182                 dfixed_init(4),
3183                 dfixed_init(5),
3184                 dfixed_init(6),
3185                 dfixed_init(7),
3186         };
3187         fixed20_12 memtrbs[8] = {
3188                 dfixed_init(1),
3189                 dfixed_init_half(1),
3190                 dfixed_init(2),
3191                 dfixed_init_half(2),
3192                 dfixed_init(3),
3193                 dfixed_init_half(3),
3194                 dfixed_init(4),
3195                 dfixed_init_half(4)
3196         };
3197         fixed20_12 memtrbs_r4xx[8] = {
3198                 dfixed_init(4),
3199                 dfixed_init(5),
3200                 dfixed_init(6),
3201                 dfixed_init(7),
3202                 dfixed_init(8),
3203                 dfixed_init(9),
3204                 dfixed_init(10),
3205                 dfixed_init(11)
3206         };
3207         fixed20_12 min_mem_eff;
3208         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3209         fixed20_12 cur_latency_mclk, cur_latency_sclk;
3210         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate = {0},
3211                 disp_drain_rate2, read_return_rate;
3212         fixed20_12 time_disp1_drop_priority;
3213         int c;
3214         int cur_size = 16;       /* in octawords */
3215         int critical_point = 0, critical_point2;
3216 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
3217         int stop_req, max_stop_req;
3218         struct drm_display_mode *mode1 = NULL;
3219         struct drm_display_mode *mode2 = NULL;
3220         uint32_t pixel_bytes1 = 0;
3221         uint32_t pixel_bytes2 = 0;
3222
3223         /* Guess line buffer size to be 8192 pixels */
3224         u32 lb_size = 8192;
3225
3226         if (!rdev->mode_info.mode_config_initialized)
3227                 return;
3228
3229         radeon_update_display_priority(rdev);
3230
3231         if (rdev->mode_info.crtcs[0]->base.enabled) {
3232                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3233                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.primary->fb->bits_per_pixel / 8;
3234         }
3235         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3236                 if (rdev->mode_info.crtcs[1]->base.enabled) {
3237                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3238                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.primary->fb->bits_per_pixel / 8;
3239                 }
3240         }
3241
3242         min_mem_eff.full = dfixed_const_8(0);
3243         /* get modes */
3244         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3245                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3246                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3247                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3248                 /* check crtc enables */
3249                 if (mode2)
3250                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3251                 if (mode1)
3252                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3253                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3254         }
3255
3256         /*
3257          * determine is there is enough bw for current mode
3258          */
3259         sclk_ff = rdev->pm.sclk;
3260         mclk_ff = rdev->pm.mclk;
3261
3262         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3263         temp_ff.full = dfixed_const(temp);
3264         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3265
3266         pix_clk.full = 0;
3267         pix_clk2.full = 0;
3268         peak_disp_bw.full = 0;
3269         if (mode1) {
3270                 temp_ff.full = dfixed_const(1000);
3271                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3272                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3273                 temp_ff.full = dfixed_const(pixel_bytes1);
3274                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3275         }
3276         if (mode2) {
3277                 temp_ff.full = dfixed_const(1000);
3278                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3279                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3280                 temp_ff.full = dfixed_const(pixel_bytes2);
3281                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3282         }
3283
3284         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3285         if (peak_disp_bw.full >= mem_bw.full) {
3286                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3287                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3288         }
3289
3290         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
3291         temp = RREG32(RADEON_MEM_TIMING_CNTL);
3292         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3293                 mem_trcd = ((temp >> 2) & 0x3) + 1;
3294                 mem_trp  = ((temp & 0x3)) + 1;
3295                 mem_tras = ((temp & 0x70) >> 4) + 1;
3296         } else if (rdev->family == CHIP_R300 ||
3297                    rdev->family == CHIP_R350) { /* r300, r350 */
3298                 mem_trcd = (temp & 0x7) + 1;
3299                 mem_trp = ((temp >> 8) & 0x7) + 1;
3300                 mem_tras = ((temp >> 11) & 0xf) + 4;
3301         } else if (rdev->family == CHIP_RV350 ||
3302                    rdev->family <= CHIP_RV380) {
3303                 /* rv3x0 */
3304                 mem_trcd = (temp & 0x7) + 3;
3305                 mem_trp = ((temp >> 8) & 0x7) + 3;
3306                 mem_tras = ((temp >> 11) & 0xf) + 6;
3307         } else if (rdev->family == CHIP_R420 ||
3308                    rdev->family == CHIP_R423 ||
3309                    rdev->family == CHIP_RV410) {
3310                 /* r4xx */
3311                 mem_trcd = (temp & 0xf) + 3;
3312                 if (mem_trcd > 15)
3313                         mem_trcd = 15;
3314                 mem_trp = ((temp >> 8) & 0xf) + 3;
3315                 if (mem_trp > 15)
3316                         mem_trp = 15;
3317                 mem_tras = ((temp >> 12) & 0x1f) + 6;
3318                 if (mem_tras > 31)
3319                         mem_tras = 31;
3320         } else { /* RV200, R200 */
3321                 mem_trcd = (temp & 0x7) + 1;
3322                 mem_trp = ((temp >> 8) & 0x7) + 1;
3323                 mem_tras = ((temp >> 12) & 0xf) + 4;
3324         }
3325         /* convert to FF */
3326         trcd_ff.full = dfixed_const(mem_trcd);
3327         trp_ff.full = dfixed_const(mem_trp);
3328         tras_ff.full = dfixed_const(mem_tras);
3329
3330         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3331         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3332         data = (temp & (7 << 20)) >> 20;
3333         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3334                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3335                         tcas_ff = memtcas_rs480_ff[data];
3336                 else
3337                         tcas_ff = memtcas_ff[data];
3338         } else
3339                 tcas_ff = memtcas2_ff[data];
3340
3341         if (rdev->family == CHIP_RS400 ||
3342             rdev->family == CHIP_RS480) {
3343                 /* extra cas latency stored in bits 23-25 0-4 clocks */
3344                 data = (temp >> 23) & 0x7;
3345                 if (data < 5)
3346                         tcas_ff.full += dfixed_const(data);
3347         }
3348
3349         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3350                 /* on the R300, Tcas is included in Trbs.
3351                  */
3352                 temp = RREG32(RADEON_MEM_CNTL);
3353                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3354                 if (data == 1) {
3355                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
3356                                 temp = RREG32(R300_MC_IND_INDEX);
3357                                 temp &= ~R300_MC_IND_ADDR_MASK;
3358                                 temp |= R300_MC_READ_CNTL_CD_mcind;
3359                                 WREG32(R300_MC_IND_INDEX, temp);
3360                                 temp = RREG32(R300_MC_IND_DATA);
3361                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3362                         } else {
3363                                 temp = RREG32(R300_MC_READ_CNTL_AB);
3364                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3365                         }
3366                 } else {
3367                         temp = RREG32(R300_MC_READ_CNTL_AB);
3368                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3369                 }
3370                 if (rdev->family == CHIP_RV410 ||
3371                     rdev->family == CHIP_R420 ||
3372                     rdev->family == CHIP_R423)
3373                         trbs_ff = memtrbs_r4xx[data];
3374                 else
3375                         trbs_ff = memtrbs[data];
3376                 tcas_ff.full += trbs_ff.full;
3377         }
3378
3379         sclk_eff_ff.full = sclk_ff.full;
3380
3381         if (rdev->flags & RADEON_IS_AGP) {
3382                 fixed20_12 agpmode_ff;
3383                 agpmode_ff.full = dfixed_const(radeon_agpmode);
3384                 temp_ff.full = dfixed_const_666(16);
3385                 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3386         }
3387         /* TODO PCIE lanes may affect this - agpmode == 16?? */
3388
3389         if (ASIC_IS_R300(rdev)) {
3390                 sclk_delay_ff.full = dfixed_const(250);
3391         } else {
3392                 if ((rdev->family == CHIP_RV100) ||
3393                     rdev->flags & RADEON_IS_IGP) {
3394                         if (rdev->mc.vram_is_ddr)
3395                                 sclk_delay_ff.full = dfixed_const(41);
3396                         else
3397                                 sclk_delay_ff.full = dfixed_const(33);
3398                 } else {
3399                         if (rdev->mc.vram_width == 128)
3400                                 sclk_delay_ff.full = dfixed_const(57);
3401                         else
3402                                 sclk_delay_ff.full = dfixed_const(41);
3403                 }
3404         }
3405
3406         mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3407
3408         if (rdev->mc.vram_is_ddr) {
3409                 if (rdev->mc.vram_width == 32) {
3410                         k1.full = dfixed_const(40);
3411                         c  = 3;
3412                 } else {
3413                         k1.full = dfixed_const(20);
3414                         c  = 1;
3415                 }
3416         } else {
3417                 k1.full = dfixed_const(40);
3418                 c  = 3;
3419         }
3420
3421         temp_ff.full = dfixed_const(2);
3422         mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3423         temp_ff.full = dfixed_const(c);
3424         mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3425         temp_ff.full = dfixed_const(4);
3426         mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3427         mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3428         mc_latency_mclk.full += k1.full;
3429
3430         mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3431         mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3432
3433         /*
3434           HW cursor time assuming worst case of full size colour cursor.
3435         */
3436         temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3437         temp_ff.full += trcd_ff.full;
3438         if (temp_ff.full < tras_ff.full)
3439                 temp_ff.full = tras_ff.full;
3440         cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3441
3442         temp_ff.full = dfixed_const(cur_size);
3443         cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3444         /*
3445           Find the total latency for the display data.
3446         */
3447         disp_latency_overhead.full = dfixed_const(8);
3448         disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3449         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3450         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3451
3452         if (mc_latency_mclk.full > mc_latency_sclk.full)
3453                 disp_latency.full = mc_latency_mclk.full;
3454         else
3455                 disp_latency.full = mc_latency_sclk.full;
3456
3457         /* setup Max GRPH_STOP_REQ default value */
3458         if (ASIC_IS_RV100(rdev))
3459                 max_stop_req = 0x5c;
3460         else
3461                 max_stop_req = 0x7c;
3462
3463         if (mode1) {
3464                 /*  CRTC1
3465                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3466                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3467                 */
3468                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3469
3470                 if (stop_req > max_stop_req)
3471                         stop_req = max_stop_req;
3472
3473                 /*
3474                   Find the drain rate of the display buffer.
3475                 */
3476                 temp_ff.full = dfixed_const((16/pixel_bytes1));
3477                 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3478
3479                 /*
3480                   Find the critical point of the display buffer.
3481                 */
3482                 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3483                 crit_point_ff.full += dfixed_const_half(0);
3484
3485                 critical_point = dfixed_trunc(crit_point_ff);
3486
3487                 if (rdev->disp_priority == 2) {
3488                         critical_point = 0;
3489                 }
3490
3491                 /*
3492                   The critical point should never be above max_stop_req-4.  Setting
3493                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3494                 */
3495                 if (max_stop_req - critical_point < 4)
3496                         critical_point = 0;
3497
3498                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3499                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3500                         critical_point = 0x10;
3501                 }
3502
3503                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3504                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3505                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3506                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3507                 if ((rdev->family == CHIP_R350) &&
3508                     (stop_req > 0x15)) {
3509                         stop_req -= 0x10;
3510                 }
3511                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3512                 temp |= RADEON_GRPH_BUFFER_SIZE;
3513                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3514                           RADEON_GRPH_CRITICAL_AT_SOF |
3515                           RADEON_GRPH_STOP_CNTL);
3516                 /*
3517                   Write the result into the register.
3518                 */
3519                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3520                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3521
3522 #if 0
3523                 if ((rdev->family == CHIP_RS400) ||
3524                     (rdev->family == CHIP_RS480)) {
3525                         /* attempt to program RS400 disp regs correctly ??? */
3526                         temp = RREG32(RS400_DISP1_REG_CNTL);
3527                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3528                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3529                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3530                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3531                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3532                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3533                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3534                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3535                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3536                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3537                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3538                 }
3539 #endif
3540
3541                 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3542                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3543                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3544         }
3545
3546         if (mode2) {
3547                 u32 grph2_cntl;
3548                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3549
3550                 if (stop_req > max_stop_req)
3551                         stop_req = max_stop_req;
3552
3553                 /*
3554                   Find the drain rate of the display buffer.
3555                 */
3556                 temp_ff.full = dfixed_const((16/pixel_bytes2));
3557                 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3558
3559                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3560                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3561                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3562                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3563                 if ((rdev->family == CHIP_R350) &&
3564                     (stop_req > 0x15)) {
3565                         stop_req -= 0x10;
3566                 }
3567                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3568                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3569                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3570                           RADEON_GRPH_CRITICAL_AT_SOF |
3571                           RADEON_GRPH_STOP_CNTL);
3572
3573                 if ((rdev->family == CHIP_RS100) ||
3574                     (rdev->family == CHIP_RS200))
3575                         critical_point2 = 0;
3576                 else {
3577                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3578                         temp_ff.full = dfixed_const(temp);
3579                         temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3580                         if (sclk_ff.full < temp_ff.full)
3581                                 temp_ff.full = sclk_ff.full;
3582
3583                         read_return_rate.full = temp_ff.full;
3584
3585                         if (mode1) {
3586                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3587                                 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3588                         } else {
3589                                 time_disp1_drop_priority.full = 0;
3590                         }
3591                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3592                         crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3593                         crit_point_ff.full += dfixed_const_half(0);
3594
3595                         critical_point2 = dfixed_trunc(crit_point_ff);
3596
3597                         if (rdev->disp_priority == 2) {
3598                                 critical_point2 = 0;
3599                         }
3600
3601                         if (max_stop_req - critical_point2 < 4)
3602                                 critical_point2 = 0;
3603
3604                 }
3605
3606                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3607                         /* some R300 cards have problem with this set to 0 */
3608                         critical_point2 = 0x10;
3609                 }
3610
3611                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3612                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3613
3614                 if ((rdev->family == CHIP_RS400) ||
3615                     (rdev->family == CHIP_RS480)) {
3616 #if 0
3617                         /* attempt to program RS400 disp2 regs correctly ??? */
3618                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3619                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3620                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3621                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3622                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3623                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3624                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3625                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3626                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3627                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3628                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3629                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3630 #endif
3631                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3632                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3633                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3634                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3635                 }
3636
3637                 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3638                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3639         }
3640
3641         /* Save number of lines the linebuffer leads before the scanout */
3642         if (mode1)
3643             rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
3644
3645         if (mode2)
3646             rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
3647 }
3648
3649 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3650 {
3651         uint32_t scratch;
3652         uint32_t tmp = 0;
3653         unsigned i;
3654         int r;
3655
3656         r = radeon_scratch_get(rdev, &scratch);
3657         if (r) {
3658                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3659                 return r;
3660         }
3661         WREG32(scratch, 0xCAFEDEAD);
3662         r = radeon_ring_lock(rdev, ring, 2);
3663         if (r) {
3664                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3665                 radeon_scratch_free(rdev, scratch);
3666                 return r;
3667         }
3668         radeon_ring_write(ring, PACKET0(scratch, 0));
3669         radeon_ring_write(ring, 0xDEADBEEF);
3670         radeon_ring_unlock_commit(rdev, ring, false);
3671         for (i = 0; i < rdev->usec_timeout; i++) {
3672                 tmp = RREG32(scratch);
3673                 if (tmp == 0xDEADBEEF) {
3674                         break;
3675                 }
3676                 DRM_UDELAY(1);
3677         }
3678         if (i < rdev->usec_timeout) {
3679                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3680         } else {
3681                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3682                           scratch, tmp);
3683                 r = -EINVAL;
3684         }
3685         radeon_scratch_free(rdev, scratch);
3686         return r;
3687 }
3688
3689 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3690 {
3691         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3692
3693         if (ring->rptr_save_reg) {
3694                 u32 next_rptr = ring->wptr + 2 + 3;
3695                 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3696                 radeon_ring_write(ring, next_rptr);
3697         }
3698
3699         radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3700         radeon_ring_write(ring, ib->gpu_addr);
3701         radeon_ring_write(ring, ib->length_dw);
3702 }
3703
3704 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3705 {
3706         struct radeon_ib ib;
3707         uint32_t scratch;
3708         uint32_t tmp = 0;
3709         unsigned i;
3710         int r;
3711
3712         r = radeon_scratch_get(rdev, &scratch);
3713         if (r) {
3714                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3715                 return r;
3716         }
3717         WREG32(scratch, 0xCAFEDEAD);
3718         r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3719         if (r) {
3720                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3721                 goto free_scratch;
3722         }
3723         ib.ptr[0] = PACKET0(scratch, 0);
3724         ib.ptr[1] = 0xDEADBEEF;
3725         ib.ptr[2] = PACKET2(0);
3726         ib.ptr[3] = PACKET2(0);
3727         ib.ptr[4] = PACKET2(0);
3728         ib.ptr[5] = PACKET2(0);
3729         ib.ptr[6] = PACKET2(0);
3730         ib.ptr[7] = PACKET2(0);
3731         ib.length_dw = 8;
3732         r = radeon_ib_schedule(rdev, &ib, NULL, false);
3733         if (r) {
3734                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3735                 goto free_ib;
3736         }
3737         r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
3738                 RADEON_USEC_IB_TEST_TIMEOUT));
3739         if (r < 0) {
3740                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3741                 goto free_ib;
3742         } else if (r == 0) {
3743                 DRM_ERROR("radeon: fence wait timed out.\n");
3744                 r = -ETIMEDOUT;
3745                 goto free_ib;
3746         }
3747         r = 0;
3748         for (i = 0; i < rdev->usec_timeout; i++) {
3749                 tmp = RREG32(scratch);
3750                 if (tmp == 0xDEADBEEF) {
3751                         break;
3752                 }
3753                 DRM_UDELAY(1);
3754         }
3755         if (i < rdev->usec_timeout) {
3756                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3757         } else {
3758                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3759                           scratch, tmp);
3760                 r = -EINVAL;
3761         }
3762 free_ib:
3763         radeon_ib_free(rdev, &ib);
3764 free_scratch:
3765         radeon_scratch_free(rdev, scratch);
3766         return r;
3767 }
3768
3769 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3770 {
3771         /* Shutdown CP we shouldn't need to do that but better be safe than
3772          * sorry
3773          */
3774         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3775         WREG32(R_000740_CP_CSQ_CNTL, 0);
3776
3777         /* Save few CRTC registers */
3778         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3779         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3780         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3781         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3782         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3783                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3784                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3785         }
3786
3787         /* Disable VGA aperture access */
3788         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3789         /* Disable cursor, overlay, crtc */
3790         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3791         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3792                                         S_000054_CRTC_DISPLAY_DIS(1));
3793         WREG32(R_000050_CRTC_GEN_CNTL,
3794                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3795                         S_000050_CRTC_DISP_REQ_EN_B(1));
3796         WREG32(R_000420_OV0_SCALE_CNTL,
3797                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3798         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3799         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3800                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3801                                                 S_000360_CUR2_LOCK(1));
3802                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3803                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3804                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3805                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3806                 WREG32(R_000360_CUR2_OFFSET,
3807                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3808         }
3809 }
3810
3811 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3812 {
3813         /* Update base address for crtc */
3814         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3815         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3816                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3817         }
3818         /* Restore CRTC registers */
3819         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3820         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3821         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3822         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3823                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3824         }
3825 }
3826
3827 void r100_vga_render_disable(struct radeon_device *rdev)
3828 {
3829         u32 tmp;
3830
3831         tmp = RREG8(R_0003C2_GENMO_WT);
3832         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3833 }
3834
3835 static void r100_debugfs(struct radeon_device *rdev)
3836 {
3837         int r;
3838
3839         r = r100_debugfs_mc_info_init(rdev);
3840         if (r)
3841                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3842 }
3843
3844 static void r100_mc_program(struct radeon_device *rdev)
3845 {
3846         struct r100_mc_save save;
3847
3848         /* Stops all mc clients */
3849         r100_mc_stop(rdev, &save);
3850         if (rdev->flags & RADEON_IS_AGP) {
3851                 WREG32(R_00014C_MC_AGP_LOCATION,
3852                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3853                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3854                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3855                 if (rdev->family > CHIP_RV200)
3856                         WREG32(R_00015C_AGP_BASE_2,
3857                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3858         } else {
3859                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3860                 WREG32(R_000170_AGP_BASE, 0);
3861                 if (rdev->family > CHIP_RV200)
3862                         WREG32(R_00015C_AGP_BASE_2, 0);
3863         }
3864         /* Wait for mc idle */
3865         if (r100_mc_wait_for_idle(rdev))
3866                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3867         /* Program MC, should be a 32bits limited address space */
3868         WREG32(R_000148_MC_FB_LOCATION,
3869                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3870                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3871         r100_mc_resume(rdev, &save);
3872 }
3873
3874 static void r100_clock_startup(struct radeon_device *rdev)
3875 {
3876         u32 tmp;
3877
3878         if (radeon_dynclks != -1 && radeon_dynclks)
3879                 radeon_legacy_set_clock_gating(rdev, 1);
3880         /* We need to force on some of the block */
3881         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3882         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3883         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3884                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3885         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3886 }
3887
3888 static int r100_startup(struct radeon_device *rdev)
3889 {
3890         int r;
3891
3892         /* set common regs */
3893         r100_set_common_regs(rdev);
3894         /* program mc */
3895         r100_mc_program(rdev);
3896         /* Resume clock */
3897         r100_clock_startup(rdev);
3898         /* Initialize GART (initialize after TTM so we can allocate
3899          * memory through TTM but finalize after TTM) */
3900         r100_enable_bm(rdev);
3901         if (rdev->flags & RADEON_IS_PCI) {
3902                 r = r100_pci_gart_enable(rdev);
3903                 if (r)
3904                         return r;
3905         }
3906
3907         /* allocate wb buffer */
3908         r = radeon_wb_init(rdev);
3909         if (r)
3910                 return r;
3911
3912         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3913         if (r) {
3914                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3915                 return r;
3916         }
3917
3918         /* Enable IRQ */
3919         if (!rdev->irq.installed) {
3920                 r = radeon_irq_kms_init(rdev);
3921                 if (r)
3922                         return r;
3923         }
3924
3925         r100_irq_set(rdev);
3926         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3927         /* 1M ring buffer */
3928         r = r100_cp_init(rdev, 1024 * 1024);
3929         if (r) {
3930                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3931                 return r;
3932         }
3933
3934         r = radeon_ib_pool_init(rdev);
3935         if (r) {
3936                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3937                 return r;
3938         }
3939
3940         return 0;
3941 }
3942
3943 int r100_resume(struct radeon_device *rdev)
3944 {
3945         int r;
3946
3947         /* Make sur GART are not working */
3948         if (rdev->flags & RADEON_IS_PCI)
3949                 r100_pci_gart_disable(rdev);
3950         /* Resume clock before doing reset */
3951         r100_clock_startup(rdev);
3952         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3953         if (radeon_asic_reset(rdev)) {
3954                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3955                         RREG32(R_000E40_RBBM_STATUS),
3956                         RREG32(R_0007C0_CP_STAT));
3957         }
3958         /* post */
3959         radeon_combios_asic_init(rdev->ddev);
3960         /* Resume clock after posting */
3961         r100_clock_startup(rdev);
3962         /* Initialize surface registers */
3963         radeon_surface_init(rdev);
3964
3965         rdev->accel_working = true;
3966         r = r100_startup(rdev);
3967         if (r) {
3968                 rdev->accel_working = false;
3969         }
3970         return r;
3971 }
3972
3973 int r100_suspend(struct radeon_device *rdev)
3974 {
3975         radeon_pm_suspend(rdev);
3976         r100_cp_disable(rdev);
3977         radeon_wb_disable(rdev);
3978         r100_irq_disable(rdev);
3979         if (rdev->flags & RADEON_IS_PCI)
3980                 r100_pci_gart_disable(rdev);
3981         return 0;
3982 }
3983
3984 void r100_fini(struct radeon_device *rdev)
3985 {
3986         radeon_pm_fini(rdev);
3987         r100_cp_fini(rdev);
3988         radeon_wb_fini(rdev);
3989         radeon_ib_pool_fini(rdev);
3990         radeon_gem_fini(rdev);
3991         if (rdev->flags & RADEON_IS_PCI)
3992                 r100_pci_gart_fini(rdev);
3993         radeon_agp_fini(rdev);
3994         radeon_irq_kms_fini(rdev);
3995         radeon_fence_driver_fini(rdev);
3996         radeon_bo_fini(rdev);
3997         radeon_atombios_fini(rdev);
3998         kfree(rdev->bios);
3999         rdev->bios = NULL;
4000 }
4001
4002 /*
4003  * Due to how kexec works, it can leave the hw fully initialised when it
4004  * boots the new kernel. However doing our init sequence with the CP and
4005  * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
4006  * do some quick sanity checks and restore sane values to avoid this
4007  * problem.
4008  */
4009 void r100_restore_sanity(struct radeon_device *rdev)
4010 {
4011         u32 tmp;
4012
4013         tmp = RREG32(RADEON_CP_CSQ_CNTL);
4014         if (tmp) {
4015                 WREG32(RADEON_CP_CSQ_CNTL, 0);
4016         }
4017         tmp = RREG32(RADEON_CP_RB_CNTL);
4018         if (tmp) {
4019                 WREG32(RADEON_CP_RB_CNTL, 0);
4020         }
4021         tmp = RREG32(RADEON_SCRATCH_UMSK);
4022         if (tmp) {
4023                 WREG32(RADEON_SCRATCH_UMSK, 0);
4024         }
4025 }
4026
4027 int r100_init(struct radeon_device *rdev)
4028 {
4029         int r;
4030
4031         /* Register debugfs file specific to this group of asics */
4032         r100_debugfs(rdev);
4033         /* Disable VGA */
4034         r100_vga_render_disable(rdev);
4035         /* Initialize scratch registers */
4036         radeon_scratch_init(rdev);
4037         /* Initialize surface registers */
4038         radeon_surface_init(rdev);
4039         /* sanity check some register to avoid hangs like after kexec */
4040         r100_restore_sanity(rdev);
4041         /* TODO: disable VGA need to use VGA request */
4042         /* BIOS*/
4043         if (!radeon_get_bios(rdev)) {
4044                 if (ASIC_IS_AVIVO(rdev))
4045                         return -EINVAL;
4046         }
4047         if (rdev->is_atom_bios) {
4048                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4049                 return -EINVAL;
4050         } else {
4051                 r = radeon_combios_init(rdev);
4052                 if (r)
4053                         return r;
4054         }
4055         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4056         if (radeon_asic_reset(rdev)) {
4057                 dev_warn(rdev->dev,
4058                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4059                         RREG32(R_000E40_RBBM_STATUS),
4060                         RREG32(R_0007C0_CP_STAT));
4061         }
4062         /* check if cards are posted or not */
4063         if (radeon_boot_test_post_card(rdev) == false)
4064                 return -EINVAL;
4065         /* Set asic errata */
4066         r100_errata(rdev);
4067         /* Initialize clocks */
4068         radeon_get_clock_info(rdev->ddev);
4069         /* initialize AGP */
4070         if (rdev->flags & RADEON_IS_AGP) {
4071                 r = radeon_agp_init(rdev);
4072                 if (r) {
4073                         radeon_agp_disable(rdev);
4074                 }
4075         }
4076         /* initialize VRAM */
4077         r100_mc_init(rdev);
4078         /* Fence driver */
4079         r = radeon_fence_driver_init(rdev);
4080         if (r)
4081                 return r;
4082         /* Memory manager */
4083         r = radeon_bo_init(rdev);
4084         if (r)
4085                 return r;
4086         if (rdev->flags & RADEON_IS_PCI) {
4087                 r = r100_pci_gart_init(rdev);
4088                 if (r)
4089                         return r;
4090         }
4091         r100_set_safe_registers(rdev);
4092
4093         /* Initialize power management */
4094         radeon_pm_init(rdev);
4095
4096         rdev->accel_working = true;
4097         r = r100_startup(rdev);
4098         if (r) {
4099                 /* Somethings want wront with the accel init stop accel */
4100                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4101                 r100_cp_fini(rdev);
4102                 radeon_wb_fini(rdev);
4103                 radeon_ib_pool_fini(rdev);
4104                 radeon_irq_kms_fini(rdev);
4105                 if (rdev->flags & RADEON_IS_PCI)
4106                         r100_pci_gart_fini(rdev);
4107                 rdev->accel_working = false;
4108         }
4109         return 0;
4110 }
4111
4112 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)
4113 {
4114         unsigned long flags;
4115         uint32_t ret;
4116
4117         spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4118         writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4119         ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4120         spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4121         return ret;
4122 }
4123
4124 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4125 {
4126         unsigned long flags;
4127
4128         spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4129         writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4130         writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4131         spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4132 }
4133
4134 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4135 {
4136         if (reg < rdev->rio_mem_size)
4137                 return ioread32(rdev->rio_mem + reg);
4138         else {
4139                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4140                 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4141         }
4142 }
4143
4144 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4145 {
4146         if (reg < rdev->rio_mem_size)
4147                 iowrite32(v, rdev->rio_mem + reg);
4148         else {
4149                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4150                 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4151         }
4152 }