drivers/gpu/drm/radeon/r600_cs.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/kernel.h>
  29 #include "drmP.h"
  30 #include "radeon.h"
  31 #include "r600d.h"
  32 #include "r600_reg_safe.h"
  33
  34 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
  35                                         struct radeon_cs_reloc **cs_reloc);
  36 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
  37                                         struct radeon_cs_reloc **cs_reloc);
  38 typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
  39 static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
  40 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
  41
  42
  43 struct r600_cs_track {
  44         /* configuration we miror so that we use same code btw kms/ums */
  45         u32                     group_size;
  46         u32                     nbanks;
  47         u32                     npipes;
  48         /* value we track */
  49         u32                     sq_config;
  50         u32                     nsamples;
  51         u32                     cb_color_base_last[8];
  52         struct radeon_bo        *cb_color_bo[8];
  53         u64                     cb_color_bo_mc[8];
  54         u32                     cb_color_bo_offset[8];
  55         struct radeon_bo        *cb_color_frag_bo[8]; /* unused */
  56         struct radeon_bo        *cb_color_tile_bo[8]; /* unused */
  57         u32                     cb_color_info[8];
  58         u32                     cb_color_view[8];
  59         u32                     cb_color_size_idx[8]; /* unused */
  60         u32                     cb_target_mask;
  61         u32                     cb_shader_mask;  /* unused */
  62         u32                     cb_color_size[8];
  63         u32                     vgt_strmout_en;
  64         u32                     vgt_strmout_buffer_en;
  65         struct radeon_bo        *vgt_strmout_bo[4];
  66         u64                     vgt_strmout_bo_mc[4]; /* unused */
  67         u32                     vgt_strmout_bo_offset[4];
  68         u32                     vgt_strmout_size[4];
  69         u32                     db_depth_control;
  70         u32                     db_depth_info;
  71         u32                     db_depth_size_idx;
  72         u32                     db_depth_view;
  73         u32                     db_depth_size;
  74         u32                     db_offset;
  75         struct radeon_bo        *db_bo;
  76         u64                     db_bo_mc;
  77         bool                    sx_misc_kill_all_prims;
  78         bool                    cb_dirty;
  79         bool                    db_dirty;
  80         bool                    streamout_dirty;
  81         struct radeon_bo        *htile_bo;
  82         u64                     htile_offset;
  83         u32                     htile_surface;
  84 };
  85
  86 #define FMT_8_BIT(fmt, vc)   [fmt] = { 1, 1, 1, vc, CHIP_R600 }
  87 #define FMT_16_BIT(fmt, vc)  [fmt] = { 1, 1, 2, vc, CHIP_R600 }
  88 #define FMT_24_BIT(fmt)      [fmt] = { 1, 1, 4,  0, CHIP_R600 }
  89 #define FMT_32_BIT(fmt, vc)  [fmt] = { 1, 1, 4, vc, CHIP_R600 }
  90 #define FMT_48_BIT(fmt)      [fmt] = { 1, 1, 8,  0, CHIP_R600 }
  91 #define FMT_64_BIT(fmt, vc)  [fmt] = { 1, 1, 8, vc, CHIP_R600 }
  92 #define FMT_96_BIT(fmt)      [fmt] = { 1, 1, 12, 0, CHIP_R600 }
  93 #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
  94
  95 struct gpu_formats {
  96         unsigned blockwidth;
  97         unsigned blockheight;
  98         unsigned blocksize;
  99         unsigned valid_color;
 100         enum radeon_family min_family;
 101 };
 102
 103 static const struct gpu_formats color_formats_table[] = {
 104         /* 8 bit */
 105         FMT_8_BIT(V_038004_COLOR_8, 1),
 106         FMT_8_BIT(V_038004_COLOR_4_4, 1),
 107         FMT_8_BIT(V_038004_COLOR_3_3_2, 1),
 108         FMT_8_BIT(V_038004_FMT_1, 0),
 109
 110         /* 16-bit */
 111         FMT_16_BIT(V_038004_COLOR_16, 1),
 112         FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1),
 113         FMT_16_BIT(V_038004_COLOR_8_8, 1),
 114         FMT_16_BIT(V_038004_COLOR_5_6_5, 1),
 115         FMT_16_BIT(V_038004_COLOR_6_5_5, 1),
 116         FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1),
 117         FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1),
 118         FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1),
 119
 120         /* 24-bit */
 121         FMT_24_BIT(V_038004_FMT_8_8_8),
 122
 123         /* 32-bit */
 124         FMT_32_BIT(V_038004_COLOR_32, 1),
 125         FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),
 126         FMT_32_BIT(V_038004_COLOR_16_16, 1),
 127         FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1),
 128         FMT_32_BIT(V_038004_COLOR_8_24, 1),
 129         FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1),
 130         FMT_32_BIT(V_038004_COLOR_24_8, 1),
 131         FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1),
 132         FMT_32_BIT(V_038004_COLOR_10_11_11, 1),
 133         FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1),
 134         FMT_32_BIT(V_038004_COLOR_11_11_10, 1),
 135         FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1),
 136         FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1),
 137         FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1),
 138         FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1),
 139         FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0),
 140         FMT_32_BIT(V_038004_FMT_32_AS_8, 0),
 141         FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0),
 142
 143         /* 48-bit */
 144         FMT_48_BIT(V_038004_FMT_16_16_16),
 145         FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT),
 146
 147         /* 64-bit */
 148         FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1),
 149         FMT_64_BIT(V_038004_COLOR_32_32, 1),
 150         FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1),
 151         FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1),
 152         FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1),
 153
 154         FMT_96_BIT(V_038004_FMT_32_32_32),
 155         FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT),
 156
 157         /* 128-bit */
 158         FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1),
 159         FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1),
 160
 161         [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 },
 162         [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 },
 163
 164         /* block compressed formats */
 165         [V_038004_FMT_BC1] = { 4, 4, 8, 0 },
 166         [V_038004_FMT_BC2] = { 4, 4, 16, 0 },
 167         [V_038004_FMT_BC3] = { 4, 4, 16, 0 },
 168         [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
 169         [V_038004_FMT_BC5] = { 4, 4, 16, 0},
 170         [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
 171         [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
 172
 173         /* The other Evergreen formats */
 174         [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},
 175 };
 176
 177 bool r600_fmt_is_valid_color(u32 format)
 178 {
 179         if (format >= ARRAY_SIZE(color_formats_table))
 180                 return false;
 181
 182         if (color_formats_table[format].valid_color)
 183                 return true;
 184
 185         return false;
 186 }
 187
 188 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)
 189 {
 190         if (format >= ARRAY_SIZE(color_formats_table))
 191                 return false;
 192
 193         if (family < color_formats_table[format].min_family)
 194                 return false;
 195
 196         if (color_formats_table[format].blockwidth > 0)
 197                 return true;
 198
 199         return false;
 200 }
 201
 202 int r600_fmt_get_blocksize(u32 format)
 203 {
 204         if (format >= ARRAY_SIZE(color_formats_table))
 205                 return 0;
 206
 207         return color_formats_table[format].blocksize;
 208 }
 209
 210 int r600_fmt_get_nblocksx(u32 format, u32 w)
 211 {
 212         unsigned bw;
 213
 214         if (format >= ARRAY_SIZE(color_formats_table))
 215                 return 0;
 216
 217         bw = color_formats_table[format].blockwidth;
 218         if (bw == 0)
 219                 return 0;
 220
 221         return (w + bw - 1) / bw;
 222 }
 223
 224 int r600_fmt_get_nblocksy(u32 format, u32 h)
 225 {
 226         unsigned bh;
 227
 228         if (format >= ARRAY_SIZE(color_formats_table))
 229                 return 0;
 230
 231         bh = color_formats_table[format].blockheight;
 232         if (bh == 0)
 233                 return 0;
 234
 235         return (h + bh - 1) / bh;
 236 }
 237
 238 struct array_mode_checker {
 239         int array_mode;
 240         u32 group_size;
 241         u32 nbanks;
 242         u32 npipes;
 243         u32 nsamples;
 244         u32 blocksize;
 245 };
 246
 247 /* returns alignment in pixels for pitch/height/depth and bytes for base */
 248 static int r600_get_array_mode_alignment(struct array_mode_checker *values,
 249                                                 u32 *pitch_align,
 250                                                 u32 *height_align,
 251                                                 u32 *depth_align,
 252                                                 u64 *base_align)
 253 {
 254         u32 tile_width = 8;
 255         u32 tile_height = 8;
 256         u32 macro_tile_width = values->nbanks;
 257         u32 macro_tile_height = values->npipes;
 258         u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;
 259         u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
 260
 261         switch (values->array_mode) {
 262         case ARRAY_LINEAR_GENERAL:
 263                 /* technically tile_width/_height for pitch/height */
 264                 *pitch_align = 1; /* tile_width */
 265                 *height_align = 1; /* tile_height */
 266                 *depth_align = 1;
 267                 *base_align = 1;
 268                 break;
 269         case ARRAY_LINEAR_ALIGNED:
 270                 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
 271                 *height_align = 1;
 272                 *depth_align = 1;
 273                 *base_align = values->group_size;
 274                 break;
 275         case ARRAY_1D_TILED_THIN1:
 276                 *pitch_align = max((u32)tile_width,
 277                                    (u32)(values->group_size /
 278                                          (tile_height * values->blocksize * values->nsamples)));
 279                 *height_align = tile_height;
 280                 *depth_align = 1;
 281                 *base_align = values->group_size;
 282                 break;
 283         case ARRAY_2D_TILED_THIN1:
 284                 *pitch_align = max((u32)macro_tile_width * tile_width,
 285                                 (u32)((values->group_size * values->nbanks) /
 286                                 (values->blocksize * values->nsamples * tile_width)));
 287                 *height_align = macro_tile_height * tile_height;
 288                 *depth_align = 1;
 289                 *base_align = max(macro_tile_bytes,
 290                                   (*pitch_align) * values->blocksize * (*height_align) * values->nsamples);
 291                 break;
 292         default:
 293                 return -EINVAL;
 294         }
 295
 296         return 0;
 297 }
 298
 299 static void r600_cs_track_init(struct r600_cs_track *track)
 300 {
 301         int i;
 302
 303         /* assume DX9 mode */
 304         track->sq_config = DX9_CONSTS;
 305         for (i = 0; i < 8; i++) {
 306                 track->cb_color_base_last[i] = 0;
 307                 track->cb_color_size[i] = 0;
 308                 track->cb_color_size_idx[i] = 0;
 309                 track->cb_color_info[i] = 0;
 310                 track->cb_color_view[i] = 0xFFFFFFFF;
 311                 track->cb_color_bo[i] = NULL;
 312                 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
 313                 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
 314         }
 315         track->cb_target_mask = 0xFFFFFFFF;
 316         track->cb_shader_mask = 0xFFFFFFFF;
 317         track->cb_dirty = true;
 318         track->db_bo = NULL;
 319         track->db_bo_mc = 0xFFFFFFFF;
 320         /* assume the biggest format and that htile is enabled */
 321         track->db_depth_info = 7 | (1 << 25);
 322         track->db_depth_view = 0xFFFFC000;
 323         track->db_depth_size = 0xFFFFFFFF;
 324         track->db_depth_size_idx = 0;
 325         track->db_depth_control = 0xFFFFFFFF;
 326         track->db_dirty = true;
 327         track->htile_bo = NULL;
 328         track->htile_offset = 0xFFFFFFFF;
 329         track->htile_surface = 0;
 330
 331         for (i = 0; i < 4; i++) {
 332                 track->vgt_strmout_size[i] = 0;
 333                 track->vgt_strmout_bo[i] = NULL;
 334                 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
 335                 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
 336         }
 337         track->streamout_dirty = true;
 338         track->sx_misc_kill_all_prims = false;
 339 }
 340
 341 static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
 342 {
 343         struct r600_cs_track *track = p->track;
 344         u32 slice_tile_max, size, tmp;
 345         u32 height, height_align, pitch, pitch_align, depth_align;
 346         u64 base_offset, base_align;
 347         struct array_mode_checker array_check;
 348         volatile u32 *ib = p->ib.ptr;
 349         unsigned array_mode;
 350         u32 format;
 351
 352         if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
 353                 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
 354                 return -EINVAL;
 355         }
 356         size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
 357         format = G_0280A0_FORMAT(track->cb_color_info[i]);
 358         if (!r600_fmt_is_valid_color(format)) {
 359                 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
 360                          __func__, __LINE__, format,
 361                         i, track->cb_color_info[i]);
 362                 return -EINVAL;
 363         }
 364         /* pitch in pixels */
 365         pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
 366         slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
 367         slice_tile_max *= 64;
 368         height = slice_tile_max / pitch;
 369         if (height > 8192)
 370                 height = 8192;
 371         array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
 372
 373         base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
 374         array_check.array_mode = array_mode;
 375         array_check.group_size = track->group_size;
 376         array_check.nbanks = track->nbanks;
 377         array_check.npipes = track->npipes;
 378         array_check.nsamples = track->nsamples;
 379         array_check.blocksize = r600_fmt_get_blocksize(format);
 380         if (r600_get_array_mode_alignment(&array_check,
 381                                           &pitch_align, &height_align, &depth_align, &base_align)) {
 382                 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
 383                          G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
 384                          track->cb_color_info[i]);
 385                 return -EINVAL;
 386         }
 387         switch (array_mode) {
 388         case V_0280A0_ARRAY_LINEAR_GENERAL:
 389                 break;
 390         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 391                 break;
 392         case V_0280A0_ARRAY_1D_TILED_THIN1:
 393                 /* avoid breaking userspace */
 394                 if (height > 7)
 395                         height &= ~0x7;
 396                 break;
 397         case V_0280A0_ARRAY_2D_TILED_THIN1:
 398                 break;
 399         default:
 400                 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
 401                         G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
 402                         track->cb_color_info[i]);
 403                 return -EINVAL;
 404         }
 405
 406         if (!IS_ALIGNED(pitch, pitch_align)) {
 407                 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",
 408                          __func__, __LINE__, pitch, pitch_align, array_mode);
 409                 return -EINVAL;
 410         }
 411         if (!IS_ALIGNED(height, height_align)) {
 412                 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n",
 413                          __func__, __LINE__, height, height_align, array_mode);
 414                 return -EINVAL;
 415         }
 416         if (!IS_ALIGNED(base_offset, base_align)) {
 417                 dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i,
 418                          base_offset, base_align, array_mode);
 419                 return -EINVAL;
 420         }
 421
 422         /* check offset */
 423         tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) * r600_fmt_get_blocksize(format);
 424         switch (array_mode) {
 425         default:
 426         case V_0280A0_ARRAY_LINEAR_GENERAL:
 427         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 428                 tmp += track->cb_color_view[i] & 0xFF;
 429                 break;
 430         case V_0280A0_ARRAY_1D_TILED_THIN1:
 431         case V_0280A0_ARRAY_2D_TILED_THIN1:
 432                 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
 433                 break;
 434         }
 435         if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
 436                 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
 437                         /* the initial DDX does bad things with the CB size occasionally */
 438                         /* it rounds up height too far for slice tile max but the BO is smaller */
 439                         /* r600c,g also seem to flush at bad times in some apps resulting in
 440                          * bogus values here. So for linear just allow anything to avoid breaking
 441                          * broken userspace.
 442                          */
 443                 } else {
 444                         dev_warn(p->dev, "%s offset[%d] %d %d %d %lu too big (%d %d) (%d %d %d)\n",
 445                                  __func__, i, array_mode,
 446                                  track->cb_color_bo_offset[i], tmp,
 447                                  radeon_bo_size(track->cb_color_bo[i]),
 448                                  pitch, height, r600_fmt_get_nblocksx(format, pitch),
 449                                  r600_fmt_get_nblocksy(format, height),
 450                                  r600_fmt_get_blocksize(format));
 451                         return -EINVAL;
 452                 }
 453         }
 454         /* limit max tile */
 455         tmp = (height * pitch) >> 6;
 456         if (tmp < slice_tile_max)
 457                 slice_tile_max = tmp;
 458         tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
 459                 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
 460         ib[track->cb_color_size_idx[i]] = tmp;
 461         return 0;
 462 }
 463
 464 static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
 465 {
 466         struct r600_cs_track *track = p->track;
 467         u32 nviews, bpe, ntiles, size, slice_tile_max, tmp;
 468         u32 height_align, pitch_align, depth_align;
 469         u32 pitch = 8192;
 470         u32 height = 8192;
 471         u64 base_offset, base_align;
 472         struct array_mode_checker array_check;
 473         int array_mode;
 474         volatile u32 *ib = p->ib.ptr;
 475
 476
 477         if (track->db_bo == NULL) {
 478                 dev_warn(p->dev, "z/stencil with no depth buffer\n");
 479                 return -EINVAL;
 480         }
 481         switch (G_028010_FORMAT(track->db_depth_info)) {
 482         case V_028010_DEPTH_16:
 483                 bpe = 2;
 484                 break;
 485         case V_028010_DEPTH_X8_24:
 486         case V_028010_DEPTH_8_24:
 487         case V_028010_DEPTH_X8_24_FLOAT:
 488         case V_028010_DEPTH_8_24_FLOAT:
 489         case V_028010_DEPTH_32_FLOAT:
 490                 bpe = 4;
 491                 break;
 492         case V_028010_DEPTH_X24_8_32_FLOAT:
 493                 bpe = 8;
 494                 break;
 495         default:
 496                 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
 497                 return -EINVAL;
 498         }
 499         if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
 500                 if (!track->db_depth_size_idx) {
 501                         dev_warn(p->dev, "z/stencil buffer size not set\n");
 502                         return -EINVAL;
 503                 }
 504                 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
 505                 tmp = (tmp / bpe) >> 6;
 506                 if (!tmp) {
 507                         dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
 508                                         track->db_depth_size, bpe, track->db_offset,
 509                                         radeon_bo_size(track->db_bo));
 510                         return -EINVAL;
 511                 }
 512                 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
 513         } else {
 514                 size = radeon_bo_size(track->db_bo);
 515                 /* pitch in pixels */
 516                 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
 517                 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
 518                 slice_tile_max *= 64;
 519                 height = slice_tile_max / pitch;
 520                 if (height > 8192)
 521                         height = 8192;
 522                 base_offset = track->db_bo_mc + track->db_offset;
 523                 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
 524                 array_check.array_mode = array_mode;
 525                 array_check.group_size = track->group_size;
 526                 array_check.nbanks = track->nbanks;
 527                 array_check.npipes = track->npipes;
 528                 array_check.nsamples = track->nsamples;
 529                 array_check.blocksize = bpe;
 530                 if (r600_get_array_mode_alignment(&array_check,
 531                                         &pitch_align, &height_align, &depth_align, &base_align)) {
 532                         dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
 533                                         G_028010_ARRAY_MODE(track->db_depth_info),
 534                                         track->db_depth_info);
 535                         return -EINVAL;
 536                 }
 537                 switch (array_mode) {
 538                 case V_028010_ARRAY_1D_TILED_THIN1:
 539                         /* don't break userspace */
 540                         height &= ~0x7;
 541                         break;
 542                 case V_028010_ARRAY_2D_TILED_THIN1:
 543                         break;
 544                 default:
 545                         dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
 546                                         G_028010_ARRAY_MODE(track->db_depth_info),
 547                                         track->db_depth_info);
 548                         return -EINVAL;
 549                 }
 550
 551                 if (!IS_ALIGNED(pitch, pitch_align)) {
 552                         dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
 553                                         __func__, __LINE__, pitch, pitch_align, array_mode);
 554                         return -EINVAL;
 555                 }
 556                 if (!IS_ALIGNED(height, height_align)) {
 557                         dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
 558                                         __func__, __LINE__, height, height_align, array_mode);
 559                         return -EINVAL;
 560                 }
 561                 if (!IS_ALIGNED(base_offset, base_align)) {
 562                         dev_warn(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__,
 563                                         base_offset, base_align, array_mode);
 564                         return -EINVAL;
 565                 }
 566
 567                 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
 568                 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
 569                 tmp = ntiles * bpe * 64 * nviews;
 570                 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
 571                         dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
 572                                         array_mode,
 573                                         track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
 574                                         radeon_bo_size(track->db_bo));
 575                         return -EINVAL;
 576                 }
 577         }
 578
 579         /* hyperz */
 580         if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
 581                 unsigned long size;
 582                 unsigned nbx, nby;
 583
 584                 if (track->htile_bo == NULL) {
 585                         dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
 586                                  __func__, __LINE__, track->db_depth_info);
 587                         return -EINVAL;
 588                 }
 589                 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
 590                         dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n",
 591                                  __func__, __LINE__, track->db_depth_size);
 592                         return -EINVAL;
 593                 }
 594
 595                 nbx = pitch;
 596                 nby = height;
 597                 if (G_028D24_LINEAR(track->htile_surface)) {
 598                         /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */
 599                         nbx = round_up(nbx, 16 * 8);
 600                         /* nby is npipes htiles aligned == npipes * 8 pixel aligned */
 601                         nby = round_up(nby, track->npipes * 8);
 602                 } else {
 603                         /* htile widht & nby (8 or 4) make 2 bits number */
 604                         tmp = track->htile_surface & 3;
 605                         /* align is htile align * 8, htile align vary according to
 606                          * number of pipe and tile width and nby
 607                          */
 608                         switch (track->npipes) {
 609                         case 8:
 610                                 switch (tmp) {
 611                                 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
 612                                         nbx = round_up(nbx, 64 * 8);
 613                                         nby = round_up(nby, 64 * 8);
 614                                         break;
 615                                 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
 616                                 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
 617                                         nbx = round_up(nbx, 64 * 8);
 618                                         nby = round_up(nby, 32 * 8);
 619                                         break;
 620                                 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
 621                                         nbx = round_up(nbx, 32 * 8);
 622                                         nby = round_up(nby, 32 * 8);
 623                                         break;
 624                                 default:
 625                                         return -EINVAL;
 626                                 }
 627                                 break;
 628                         case 4:
 629                                 switch (tmp) {
 630                                 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
 631                                         nbx = round_up(nbx, 64 * 8);
 632                                         nby = round_up(nby, 32 * 8);
 633                                         break;
 634                                 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
 635                                 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
 636                                         nbx = round_up(nbx, 32 * 8);
 637                                         nby = round_up(nby, 32 * 8);
 638                                         break;
 639                                 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
 640                                         nbx = round_up(nbx, 32 * 8);
 641                                         nby = round_up(nby, 16 * 8);
 642                                         break;
 643                                 default:
 644                                         return -EINVAL;
 645                                 }
 646                                 break;
 647                         case 2:
 648                                 switch (tmp) {
 649                                 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
 650                                         nbx = round_up(nbx, 32 * 8);
 651                                         nby = round_up(nby, 32 * 8);
 652                                         break;
 653                                 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
 654                                 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
 655                                         nbx = round_up(nbx, 32 * 8);
 656                                         nby = round_up(nby, 16 * 8);
 657                                         break;
 658                                 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
 659                                         nbx = round_up(nbx, 16 * 8);
 660                                         nby = round_up(nby, 16 * 8);
 661                                         break;
 662                                 default:
 663                                         return -EINVAL;
 664                                 }
 665                                 break;
 666                         case 1:
 667                                 switch (tmp) {
 668                                 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
 669                                         nbx = round_up(nbx, 32 * 8);
 670                                         nby = round_up(nby, 16 * 8);
 671                                         break;
 672                                 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
 673                                 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
 674                                         nbx = round_up(nbx, 16 * 8);
 675                                         nby = round_up(nby, 16 * 8);
 676                                         break;
 677                                 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
 678                                         nbx = round_up(nbx, 16 * 8);
 679                                         nby = round_up(nby, 8 * 8);
 680                                         break;
 681                                 default:
 682                                         return -EINVAL;
 683                                 }
 684                                 break;
 685                         default:
 686                                 dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
 687                                          __func__, __LINE__, track->npipes);
 688                                 return -EINVAL;
 689                         }
 690                 }
 691                 /* compute number of htile */
 692                 nbx = G_028D24_HTILE_WIDTH(track->htile_surface) ? nbx / 8 : nbx / 4;
 693                 nby = G_028D24_HTILE_HEIGHT(track->htile_surface) ? nby / 8 : nby / 4;
 694                 size = nbx * nby * 4;
 695                 size += track->htile_offset;
 696
 697                 if (size > radeon_bo_size(track->htile_bo)) {
 698                         dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
 699                                  __func__, __LINE__, radeon_bo_size(track->htile_bo),
 700                                  size, nbx, nby);
 701                         return -EINVAL;
 702                 }
 703         }
 704
 705         track->db_dirty = false;
 706         return 0;
 707 }
 708
 709 static int r600_cs_track_check(struct radeon_cs_parser *p)
 710 {
 711         struct r600_cs_track *track = p->track;
 712         u32 tmp;
 713         int r, i;
 714
 715         /* on legacy kernel we don't perform advanced check */
 716         if (p->rdev == NULL)
 717                 return 0;
 718
 719         /* check streamout */
 720         if (track->streamout_dirty && track->vgt_strmout_en) {
 721                 for (i = 0; i < 4; i++) {
 722                         if (track->vgt_strmout_buffer_en & (1 << i)) {
 723                                 if (track->vgt_strmout_bo[i]) {
 724                                         u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
 725                                                 (u64)track->vgt_strmout_size[i];
 726                                         if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
 727                                                 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
 728                                                           i, offset,
 729                                                           radeon_bo_size(track->vgt_strmout_bo[i]));
 730                                                 return -EINVAL;
 731                                         }
 732                                 } else {
 733                                         dev_warn(p->dev, "No buffer for streamout %d\n", i);
 734                                         return -EINVAL;
 735                                 }
 736                         }
 737                 }
 738                 track->streamout_dirty = false;
 739         }
 740
 741         if (track->sx_misc_kill_all_prims)
 742                 return 0;
 743
 744         /* check that we have a cb for each enabled target, we don't check
 745          * shader_mask because it seems mesa isn't always setting it :(
 746          */
 747         if (track->cb_dirty) {
 748                 tmp = track->cb_target_mask;
 749                 for (i = 0; i < 8; i++) {
 750                         if ((tmp >> (i * 4)) & 0xF) {
 751                                 /* at least one component is enabled */
 752                                 if (track->cb_color_bo[i] == NULL) {
 753                                         dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
 754                                                 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
 755                                         return -EINVAL;
 756                                 }
 757                                 /* perform rewrite of CB_COLOR[0-7]_SIZE */
 758                                 r = r600_cs_track_validate_cb(p, i);
 759                                 if (r)
 760                                         return r;
 761                         }
 762                 }
 763                 track->cb_dirty = false;
 764         }
 765
 766         /* Check depth buffer */
 767         if (track->db_dirty &&
 768             G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID &&
 769             (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
 770              G_028800_Z_ENABLE(track->db_depth_control))) {
 771                 r = r600_cs_track_validate_db(p);
 772                 if (r)
 773                         return r;
 774         }
 775
 776         return 0;
 777 }
 778
 779 /**
 780  * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
 781  * @parser:     parser structure holding parsing context.
 782  * @pkt:        where to store packet informations
 783  *
 784  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 785  * if packet is bigger than remaining ib size. or if packets is unknown.
 786  **/
 787 int r600_cs_packet_parse(struct radeon_cs_parser *p,
 788                         struct radeon_cs_packet *pkt,
 789                         unsigned idx)
 790 {
 791         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 792         uint32_t header;
 793
 794         if (idx >= ib_chunk->length_dw) {
 795                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 796                           idx, ib_chunk->length_dw);
 797                 return -EINVAL;
 798         }
 799         header = radeon_get_ib_value(p, idx);
 800         pkt->idx = idx;
 801         pkt->type = CP_PACKET_GET_TYPE(header);
 802         pkt->count = CP_PACKET_GET_COUNT(header);
 803         pkt->one_reg_wr = 0;
 804         switch (pkt->type) {
 805         case PACKET_TYPE0:
 806                 pkt->reg = CP_PACKET0_GET_REG(header);
 807                 break;
 808         case PACKET_TYPE3:
 809                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
 810                 break;
 811         case PACKET_TYPE2:
 812                 pkt->count = -1;
 813                 break;
 814         default:
 815                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 816                 return -EINVAL;
 817         }
 818         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 819                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 820                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 821                 return -EINVAL;
 822         }
 823         return 0;
 824 }
 825
 826 /**
 827  * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
 828  * @parser:             parser structure holding parsing context.
 829  * @data:               pointer to relocation data
 830  * @offset_start:       starting offset
 831  * @offset_mask:        offset mask (to align start offset on)
 832  * @reloc:              reloc informations
 833  *
 834  * Check next packet is relocation packet3, do bo validation and compute
 835  * GPU offset using the provided start.
 836  **/
 837 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
 838                                         struct radeon_cs_reloc **cs_reloc)
 839 {
 840         struct radeon_cs_chunk *relocs_chunk;
 841         struct radeon_cs_packet p3reloc;
 842         unsigned idx;
 843         int r;
 844
 845         if (p->chunk_relocs_idx == -1) {
 846                 DRM_ERROR("No relocation chunk !\n");
 847                 return -EINVAL;
 848         }
 849         *cs_reloc = NULL;
 850         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 851         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
 852         if (r) {
 853                 return r;
 854         }
 855         p->idx += p3reloc.count + 2;
 856         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 857                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 858                           p3reloc.idx);
 859                 return -EINVAL;
 860         }
 861         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
 862         if (idx >= relocs_chunk->length_dw) {
 863                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 864                           idx, relocs_chunk->length_dw);
 865                 return -EINVAL;
 866         }
 867         /* FIXME: we assume reloc size is 4 dwords */
 868         *cs_reloc = p->relocs_ptr[(idx / 4)];
 869         return 0;
 870 }
 871
 872 /**
 873  * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
 874  * @parser:             parser structure holding parsing context.
 875  * @data:               pointer to relocation data
 876  * @offset_start:       starting offset
 877  * @offset_mask:        offset mask (to align start offset on)
 878  * @reloc:              reloc informations
 879  *
 880  * Check next packet is relocation packet3, do bo validation and compute
 881  * GPU offset using the provided start.
 882  **/
 883 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
 884                                         struct radeon_cs_reloc **cs_reloc)
 885 {
 886         struct radeon_cs_chunk *relocs_chunk;
 887         struct radeon_cs_packet p3reloc;
 888         unsigned idx;
 889         int r;
 890
 891         if (p->chunk_relocs_idx == -1) {
 892                 DRM_ERROR("No relocation chunk !\n");
 893                 return -EINVAL;
 894         }
 895         *cs_reloc = NULL;
 896         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 897         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
 898         if (r) {
 899                 return r;
 900         }
 901         p->idx += p3reloc.count + 2;
 902         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 903                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 904                           p3reloc.idx);
 905                 return -EINVAL;
 906         }
 907         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
 908         if (idx >= relocs_chunk->length_dw) {
 909                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 910                           idx, relocs_chunk->length_dw);
 911                 return -EINVAL;
 912         }
 913         *cs_reloc = p->relocs;
 914         (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
 915         (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
 916         return 0;
 917 }
 918
 919 /**
 920  * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
 921  * @parser:             parser structure holding parsing context.
 922  *
 923  * Check next packet is relocation packet3, do bo validation and compute
 924  * GPU offset using the provided start.
 925  **/
 926 static int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
 927 {
 928         struct radeon_cs_packet p3reloc;
 929         int r;
 930
 931         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
 932         if (r) {
 933                 return 0;
 934         }
 935         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 936                 return 0;
 937         }
 938         return 1;
 939 }
 940
 941 /**
 942  * r600_cs_packet_next_vline() - parse userspace VLINE packet
 943  * @parser:             parser structure holding parsing context.
 944  *
 945  * Userspace sends a special sequence for VLINE waits.
 946  * PACKET0 - VLINE_START_END + value
 947  * PACKET3 - WAIT_REG_MEM poll vline status reg
 948  * RELOC (P3) - crtc_id in reloc.
 949  *
 950  * This function parses this and relocates the VLINE START END
 951  * and WAIT_REG_MEM packets to the correct crtc.
 952  * It also detects a switched off crtc and nulls out the
 953  * wait in that case.
 954  */
 955 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
 956 {
 957         struct drm_mode_object *obj;
 958         struct drm_crtc *crtc;
 959         struct radeon_crtc *radeon_crtc;
 960         struct radeon_cs_packet p3reloc, wait_reg_mem;
 961         int crtc_id;
 962         int r;
 963         uint32_t header, h_idx, reg, wait_reg_mem_info;
 964         volatile uint32_t *ib;
 965
 966         ib = p->ib.ptr;
 967
 968         /* parse the WAIT_REG_MEM */
 969         r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
 970         if (r)
 971                 return r;
 972
 973         /* check its a WAIT_REG_MEM */
 974         if (wait_reg_mem.type != PACKET_TYPE3 ||
 975             wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
 976                 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
 977                 return -EINVAL;
 978         }
 979
 980         wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
 981         /* bit 4 is reg (0) or mem (1) */
 982         if (wait_reg_mem_info & 0x10) {
 983                 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
 984                 return -EINVAL;
 985         }
 986         /* waiting for value to be equal */
 987         if ((wait_reg_mem_info & 0x7) != 0x3) {
 988                 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
 989                 return -EINVAL;
 990         }
 991         if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
 992                 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
 993                 return -EINVAL;
 994         }
 995
 996         if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
 997                 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
 998                 return -EINVAL;
 999         }
1000
1001         /* jump over the NOP */
1002         r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
1003         if (r)
1004                 return r;
1005
1006         h_idx = p->idx - 2;
1007         p->idx += wait_reg_mem.count + 2;
1008         p->idx += p3reloc.count + 2;
1009
1010         header = radeon_get_ib_value(p, h_idx);
1011         crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
1012         reg = CP_PACKET0_GET_REG(header);
1013
1014         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1015         if (!obj) {
1016                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1017                 return -EINVAL;
1018         }
1019         crtc = obj_to_crtc(obj);
1020         radeon_crtc = to_radeon_crtc(crtc);
1021         crtc_id = radeon_crtc->crtc_id;
1022
1023         if (!crtc->enabled) {
1024                 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
1025                 ib[h_idx + 2] = PACKET2(0);
1026                 ib[h_idx + 3] = PACKET2(0);
1027                 ib[h_idx + 4] = PACKET2(0);
1028                 ib[h_idx + 5] = PACKET2(0);
1029                 ib[h_idx + 6] = PACKET2(0);
1030                 ib[h_idx + 7] = PACKET2(0);
1031                 ib[h_idx + 8] = PACKET2(0);
1032         } else if (crtc_id == 1) {
1033                 switch (reg) {
1034                 case AVIVO_D1MODE_VLINE_START_END:
1035                         header &= ~R600_CP_PACKET0_REG_MASK;
1036                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1037                         break;
1038                 default:
1039                         DRM_ERROR("unknown crtc reloc\n");
1040                         return -EINVAL;
1041                 }
1042                 ib[h_idx] = header;
1043                 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
1044         }
1045
1046         return 0;
1047 }
1048
1049 static int r600_packet0_check(struct radeon_cs_parser *p,
1050                                 struct radeon_cs_packet *pkt,
1051                                 unsigned idx, unsigned reg)
1052 {
1053         int r;
1054
1055         switch (reg) {
1056         case AVIVO_D1MODE_VLINE_START_END:
1057                 r = r600_cs_packet_parse_vline(p);
1058                 if (r) {
1059                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1060                                         idx, reg);
1061                         return r;
1062                 }
1063                 break;
1064         default:
1065                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1066                        reg, idx);
1067                 return -EINVAL;
1068         }
1069         return 0;
1070 }
1071
1072 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
1073                                 struct radeon_cs_packet *pkt)
1074 {
1075         unsigned reg, i;
1076         unsigned idx;
1077         int r;
1078
1079         idx = pkt->idx + 1;
1080         reg = pkt->reg;
1081         for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
1082                 r = r600_packet0_check(p, pkt, idx, reg);
1083                 if (r) {
1084                         return r;
1085                 }
1086         }
1087         return 0;
1088 }
1089
1090 /**
1091  * r600_cs_check_reg() - check if register is authorized or not
1092  * @parser: parser structure holding parsing context
1093  * @reg: register we are testing
1094  * @idx: index into the cs buffer
1095  *
1096  * This function will test against r600_reg_safe_bm and return 0
1097  * if register is safe. If register is not flag as safe this function
1098  * will test it against a list of register needind special handling.
1099  */
1100 static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1101 {
1102         struct r600_cs_track *track = (struct r600_cs_track *)p->track;
1103         struct radeon_cs_reloc *reloc;
1104         u32 m, i, tmp, *ib;
1105         int r;
1106
1107         i = (reg >> 7);
1108         if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
1109                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1110                 return -EINVAL;
1111         }
1112         m = 1 << ((reg >> 2) & 31);
1113         if (!(r600_reg_safe_bm[i] & m))
1114                 return 0;
1115         ib = p->ib.ptr;
1116         switch (reg) {
1117         /* force following reg to 0 in an attempt to disable out buffer
1118          * which will need us to better understand how it works to perform
1119          * security check on it (Jerome)
1120          */
1121         case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
1122         case R_008C44_SQ_ESGS_RING_SIZE:
1123         case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
1124         case R_008C54_SQ_ESTMP_RING_SIZE:
1125         case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
1126         case R_008C74_SQ_FBUF_RING_SIZE:
1127         case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
1128         case R_008C5C_SQ_GSTMP_RING_SIZE:
1129         case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
1130         case R_008C4C_SQ_GSVS_RING_SIZE:
1131         case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
1132         case R_008C6C_SQ_PSTMP_RING_SIZE:
1133         case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
1134         case R_008C7C_SQ_REDUC_RING_SIZE:
1135         case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
1136         case R_008C64_SQ_VSTMP_RING_SIZE:
1137         case R_0288C8_SQ_GS_VERT_ITEMSIZE:
1138                 /* get value to populate the IB don't remove */
1139                 tmp =radeon_get_ib_value(p, idx);
1140                 ib[idx] = 0;
1141                 break;
1142         case SQ_CONFIG:
1143                 track->sq_config = radeon_get_ib_value(p, idx);
1144                 break;
1145         case R_028800_DB_DEPTH_CONTROL:
1146                 track->db_depth_control = radeon_get_ib_value(p, idx);
1147                 track->db_dirty = true;
1148                 break;
1149         case R_028010_DB_DEPTH_INFO:
1150                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
1151                     r600_cs_packet_next_is_pkt3_nop(p)) {
1152                         r = r600_cs_packet_next_reloc(p, &reloc);
1153                         if (r) {
1154                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1155                                          "0x%04X\n", reg);
1156                                 return -EINVAL;
1157                         }
1158                         track->db_depth_info = radeon_get_ib_value(p, idx);
1159                         ib[idx] &= C_028010_ARRAY_MODE;
1160                         track->db_depth_info &= C_028010_ARRAY_MODE;
1161                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1162                                 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1163                                 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1164                         } else {
1165                                 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1166                                 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1167                         }
1168                 } else {
1169                         track->db_depth_info = radeon_get_ib_value(p, idx);
1170                 }
1171                 track->db_dirty = true;
1172                 break;
1173         case R_028004_DB_DEPTH_VIEW:
1174                 track->db_depth_view = radeon_get_ib_value(p, idx);
1175                 track->db_dirty = true;
1176                 break;
1177         case R_028000_DB_DEPTH_SIZE:
1178                 track->db_depth_size = radeon_get_ib_value(p, idx);
1179                 track->db_depth_size_idx = idx;
1180                 track->db_dirty = true;
1181                 break;
1182         case R_028AB0_VGT_STRMOUT_EN:
1183                 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
1184                 track->streamout_dirty = true;
1185                 break;
1186         case R_028B20_VGT_STRMOUT_BUFFER_EN:
1187                 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
1188                 track->streamout_dirty = true;
1189                 break;
1190         case VGT_STRMOUT_BUFFER_BASE_0:
1191         case VGT_STRMOUT_BUFFER_BASE_1:
1192         case VGT_STRMOUT_BUFFER_BASE_2:
1193         case VGT_STRMOUT_BUFFER_BASE_3:
1194                 r = r600_cs_packet_next_reloc(p, &reloc);
1195                 if (r) {
1196                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1197                                         "0x%04X\n", reg);
1198                         return -EINVAL;
1199                 }
1200                 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1201                 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1202                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1203                 track->vgt_strmout_bo[tmp] = reloc->robj;
1204                 track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset;
1205                 track->streamout_dirty = true;
1206                 break;
1207         case VGT_STRMOUT_BUFFER_SIZE_0:
1208         case VGT_STRMOUT_BUFFER_SIZE_1:
1209         case VGT_STRMOUT_BUFFER_SIZE_2:
1210         case VGT_STRMOUT_BUFFER_SIZE_3:
1211                 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1212                 /* size in register is DWs, convert to bytes */
1213                 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1214                 track->streamout_dirty = true;
1215                 break;
1216         case CP_COHER_BASE:
1217                 r = r600_cs_packet_next_reloc(p, &reloc);
1218                 if (r) {
1219                         dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1220                                         "0x%04X\n", reg);
1221                         return -EINVAL;
1222                 }
1223                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1224                 break;
1225         case R_028238_CB_TARGET_MASK:
1226                 track->cb_target_mask = radeon_get_ib_value(p, idx);
1227                 track->cb_dirty = true;
1228                 break;
1229         case R_02823C_CB_SHADER_MASK:
1230                 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1231                 break;
1232         case R_028C04_PA_SC_AA_CONFIG:
1233                 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
1234                 track->nsamples = 1 << tmp;
1235                 track->cb_dirty = true;
1236                 break;
1237         case R_0280A0_CB_COLOR0_INFO:
1238         case R_0280A4_CB_COLOR1_INFO:
1239         case R_0280A8_CB_COLOR2_INFO:
1240         case R_0280AC_CB_COLOR3_INFO:
1241         case R_0280B0_CB_COLOR4_INFO:
1242         case R_0280B4_CB_COLOR5_INFO:
1243         case R_0280B8_CB_COLOR6_INFO:
1244         case R_0280BC_CB_COLOR7_INFO:
1245                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
1246                      r600_cs_packet_next_is_pkt3_nop(p)) {
1247                         r = r600_cs_packet_next_reloc(p, &reloc);
1248                         if (r) {
1249                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1250                                 return -EINVAL;
1251                         }
1252                         tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1253                         track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1254                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1255                                 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1256                                 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1257                         } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1258                                 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1259                                 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1260                         }
1261                 } else {
1262                         tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1263                         track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1264                 }
1265                 track->cb_dirty = true;
1266                 break;
1267         case R_028080_CB_COLOR0_VIEW:
1268         case R_028084_CB_COLOR1_VIEW:
1269         case R_028088_CB_COLOR2_VIEW:
1270         case R_02808C_CB_COLOR3_VIEW:
1271         case R_028090_CB_COLOR4_VIEW:
1272         case R_028094_CB_COLOR5_VIEW:
1273         case R_028098_CB_COLOR6_VIEW:
1274         case R_02809C_CB_COLOR7_VIEW:
1275                 tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
1276                 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1277                 track->cb_dirty = true;
1278                 break;
1279         case R_028060_CB_COLOR0_SIZE:
1280         case R_028064_CB_COLOR1_SIZE:
1281         case R_028068_CB_COLOR2_SIZE:
1282         case R_02806C_CB_COLOR3_SIZE:
1283         case R_028070_CB_COLOR4_SIZE:
1284         case R_028074_CB_COLOR5_SIZE:
1285         case R_028078_CB_COLOR6_SIZE:
1286         case R_02807C_CB_COLOR7_SIZE:
1287                 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1288                 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1289                 track->cb_color_size_idx[tmp] = idx;
1290                 track->cb_dirty = true;
1291                 break;
1292                 /* This register were added late, there is userspace
1293                  * which does provide relocation for those but set
1294                  * 0 offset. In order to avoid breaking old userspace
1295                  * we detect this and set address to point to last
1296                  * CB_COLOR0_BASE, note that if userspace doesn't set
1297                  * CB_COLOR0_BASE before this register we will report
1298                  * error. Old userspace always set CB_COLOR0_BASE
1299                  * before any of this.
1300                  */
1301         case R_0280E0_CB_COLOR0_FRAG:
1302         case R_0280E4_CB_COLOR1_FRAG:
1303         case R_0280E8_CB_COLOR2_FRAG:
1304         case R_0280EC_CB_COLOR3_FRAG:
1305         case R_0280F0_CB_COLOR4_FRAG:
1306         case R_0280F4_CB_COLOR5_FRAG:
1307         case R_0280F8_CB_COLOR6_FRAG:
1308         case R_0280FC_CB_COLOR7_FRAG:
1309                 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
1310                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1311                         if (!track->cb_color_base_last[tmp]) {
1312                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1313                                 return -EINVAL;
1314                         }
1315                         ib[idx] = track->cb_color_base_last[tmp];
1316                         track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1317                 } else {
1318                         r = r600_cs_packet_next_reloc(p, &reloc);
1319                         if (r) {
1320                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1321                                 return -EINVAL;
1322                         }
1323                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1324                         track->cb_color_frag_bo[tmp] = reloc->robj;
1325                 }
1326                 break;
1327         case R_0280C0_CB_COLOR0_TILE:
1328         case R_0280C4_CB_COLOR1_TILE:
1329         case R_0280C8_CB_COLOR2_TILE:
1330         case R_0280CC_CB_COLOR3_TILE:
1331         case R_0280D0_CB_COLOR4_TILE:
1332         case R_0280D4_CB_COLOR5_TILE:
1333         case R_0280D8_CB_COLOR6_TILE:
1334         case R_0280DC_CB_COLOR7_TILE:
1335                 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
1336                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1337                         if (!track->cb_color_base_last[tmp]) {
1338                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1339                                 return -EINVAL;
1340                         }
1341                         ib[idx] = track->cb_color_base_last[tmp];
1342                         track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1343                 } else {
1344                         r = r600_cs_packet_next_reloc(p, &reloc);
1345                         if (r) {
1346                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1347                                 return -EINVAL;
1348                         }
1349                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1350                         track->cb_color_tile_bo[tmp] = reloc->robj;
1351                 }
1352                 break;
1353         case CB_COLOR0_BASE:
1354         case CB_COLOR1_BASE:
1355         case CB_COLOR2_BASE:
1356         case CB_COLOR3_BASE:
1357         case CB_COLOR4_BASE:
1358         case CB_COLOR5_BASE:
1359         case CB_COLOR6_BASE:
1360         case CB_COLOR7_BASE:
1361                 r = r600_cs_packet_next_reloc(p, &reloc);
1362                 if (r) {
1363                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1364                                         "0x%04X\n", reg);
1365                         return -EINVAL;
1366                 }
1367                 tmp = (reg - CB_COLOR0_BASE) / 4;
1368                 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1369                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1370                 track->cb_color_base_last[tmp] = ib[idx];
1371                 track->cb_color_bo[tmp] = reloc->robj;
1372                 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
1373                 track->cb_dirty = true;
1374                 break;
1375         case DB_DEPTH_BASE:
1376                 r = r600_cs_packet_next_reloc(p, &reloc);
1377                 if (r) {
1378                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1379                                         "0x%04X\n", reg);
1380                         return -EINVAL;
1381                 }
1382                 track->db_offset = radeon_get_ib_value(p, idx) << 8;
1383                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1384                 track->db_bo = reloc->robj;
1385                 track->db_bo_mc = reloc->lobj.gpu_offset;
1386                 track->db_dirty = true;
1387                 break;
1388         case DB_HTILE_DATA_BASE:
1389                 r = r600_cs_packet_next_reloc(p, &reloc);
1390                 if (r) {
1391                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1392                                         "0x%04X\n", reg);
1393                         return -EINVAL;
1394                 }
1395                 track->htile_offset = radeon_get_ib_value(p, idx) << 8;
1396                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1397                 track->htile_bo = reloc->robj;
1398                 track->db_dirty = true;
1399                 break;
1400         case DB_HTILE_SURFACE:
1401                 track->htile_surface = radeon_get_ib_value(p, idx);
1402                 track->db_dirty = true;
1403                 break;
1404         case SQ_PGM_START_FS:
1405         case SQ_PGM_START_ES:
1406         case SQ_PGM_START_VS:
1407         case SQ_PGM_START_GS:
1408         case SQ_PGM_START_PS:
1409         case SQ_ALU_CONST_CACHE_GS_0:
1410         case SQ_ALU_CONST_CACHE_GS_1:
1411         case SQ_ALU_CONST_CACHE_GS_2:
1412         case SQ_ALU_CONST_CACHE_GS_3:
1413         case SQ_ALU_CONST_CACHE_GS_4:
1414         case SQ_ALU_CONST_CACHE_GS_5:
1415         case SQ_ALU_CONST_CACHE_GS_6:
1416         case SQ_ALU_CONST_CACHE_GS_7:
1417         case SQ_ALU_CONST_CACHE_GS_8:
1418         case SQ_ALU_CONST_CACHE_GS_9:
1419         case SQ_ALU_CONST_CACHE_GS_10:
1420         case SQ_ALU_CONST_CACHE_GS_11:
1421         case SQ_ALU_CONST_CACHE_GS_12:
1422         case SQ_ALU_CONST_CACHE_GS_13:
1423         case SQ_ALU_CONST_CACHE_GS_14:
1424         case SQ_ALU_CONST_CACHE_GS_15:
1425         case SQ_ALU_CONST_CACHE_PS_0:
1426         case SQ_ALU_CONST_CACHE_PS_1:
1427         case SQ_ALU_CONST_CACHE_PS_2:
1428         case SQ_ALU_CONST_CACHE_PS_3:
1429         case SQ_ALU_CONST_CACHE_PS_4:
1430         case SQ_ALU_CONST_CACHE_PS_5:
1431         case SQ_ALU_CONST_CACHE_PS_6:
1432         case SQ_ALU_CONST_CACHE_PS_7:
1433         case SQ_ALU_CONST_CACHE_PS_8:
1434         case SQ_ALU_CONST_CACHE_PS_9:
1435         case SQ_ALU_CONST_CACHE_PS_10:
1436         case SQ_ALU_CONST_CACHE_PS_11:
1437         case SQ_ALU_CONST_CACHE_PS_12:
1438         case SQ_ALU_CONST_CACHE_PS_13:
1439         case SQ_ALU_CONST_CACHE_PS_14:
1440         case SQ_ALU_CONST_CACHE_PS_15:
1441         case SQ_ALU_CONST_CACHE_VS_0:
1442         case SQ_ALU_CONST_CACHE_VS_1:
1443         case SQ_ALU_CONST_CACHE_VS_2:
1444         case SQ_ALU_CONST_CACHE_VS_3:
1445         case SQ_ALU_CONST_CACHE_VS_4:
1446         case SQ_ALU_CONST_CACHE_VS_5:
1447         case SQ_ALU_CONST_CACHE_VS_6:
1448         case SQ_ALU_CONST_CACHE_VS_7:
1449         case SQ_ALU_CONST_CACHE_VS_8:
1450         case SQ_ALU_CONST_CACHE_VS_9:
1451         case SQ_ALU_CONST_CACHE_VS_10:
1452         case SQ_ALU_CONST_CACHE_VS_11:
1453         case SQ_ALU_CONST_CACHE_VS_12:
1454         case SQ_ALU_CONST_CACHE_VS_13:
1455         case SQ_ALU_CONST_CACHE_VS_14:
1456         case SQ_ALU_CONST_CACHE_VS_15:
1457                 r = r600_cs_packet_next_reloc(p, &reloc);
1458                 if (r) {
1459                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1460                                         "0x%04X\n", reg);
1461                         return -EINVAL;
1462                 }
1463                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1464                 break;
1465         case SX_MEMORY_EXPORT_BASE:
1466                 r = r600_cs_packet_next_reloc(p, &reloc);
1467                 if (r) {
1468                         dev_warn(p->dev, "bad SET_CONFIG_REG "
1469                                         "0x%04X\n", reg);
1470                         return -EINVAL;
1471                 }
1472                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1473                 break;
1474         case SX_MISC:
1475                 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1476                 break;
1477         default:
1478                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1479                 return -EINVAL;
1480         }
1481         return 0;
1482 }
1483
1484 unsigned r600_mip_minify(unsigned size, unsigned level)
1485 {
1486         unsigned val;
1487
1488         val = max(1U, size >> level);
1489         if (level > 0)
1490                 val = roundup_pow_of_two(val);
1491         return val;
1492 }
1493
1494 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
1495                               unsigned w0, unsigned h0, unsigned d0, unsigned format,
1496                               unsigned block_align, unsigned height_align, unsigned base_align,
1497                               unsigned *l0_size, unsigned *mipmap_size)
1498 {
1499         unsigned offset, i, level;
1500         unsigned width, height, depth, size;
1501         unsigned blocksize;
1502         unsigned nbx, nby;
1503         unsigned nlevels = llevel - blevel + 1;
1504
1505         *l0_size = -1;
1506         blocksize = r600_fmt_get_blocksize(format);
1507
1508         w0 = r600_mip_minify(w0, 0);
1509         h0 = r600_mip_minify(h0, 0);
1510         d0 = r600_mip_minify(d0, 0);
1511         for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
1512                 width = r600_mip_minify(w0, i);
1513                 nbx = r600_fmt_get_nblocksx(format, width);
1514
1515                 nbx = round_up(nbx, block_align);
1516
1517                 height = r600_mip_minify(h0, i);
1518                 nby = r600_fmt_get_nblocksy(format, height);
1519                 nby = round_up(nby, height_align);
1520
1521                 depth = r600_mip_minify(d0, i);
1522
1523                 size = nbx * nby * blocksize;
1524                 if (nfaces)
1525                         size *= nfaces;
1526                 else
1527                         size *= depth;
1528
1529                 if (i == 0)
1530                         *l0_size = size;
1531
1532                 if (i == 0 || i == 1)
1533                         offset = round_up(offset, base_align);
1534
1535                 offset += size;
1536         }
1537         *mipmap_size = offset;
1538         if (llevel == 0)
1539                 *mipmap_size = *l0_size;
1540         if (!blevel)
1541                 *mipmap_size -= *l0_size;
1542 }
1543
1544 /**
1545  * r600_check_texture_resource() - check if register is authorized or not
1546  * @p: parser structure holding parsing context
1547  * @idx: index into the cs buffer
1548  * @texture: texture's bo structure
1549  * @mipmap: mipmap's bo structure
1550  *
1551  * This function will check that the resource has valid field and that
1552  * the texture and mipmap bo object are big enough to cover this resource.
1553  */
1554 static int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 idx,
1555                                               struct radeon_bo *texture,
1556                                               struct radeon_bo *mipmap,
1557                                               u64 base_offset,
1558                                               u64 mip_offset,
1559                                               u32 tiling_flags)
1560 {
1561         struct r600_cs_track *track = p->track;
1562         u32 dim, nfaces, llevel, blevel, w0, h0, d0;
1563         u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5;
1564         u32 height_align, pitch, pitch_align, depth_align;
1565         u32 barray, larray;
1566         u64 base_align;
1567         struct array_mode_checker array_check;
1568         u32 format;
1569         bool is_array;
1570
1571         /* on legacy kernel we don't perform advanced check */
1572         if (p->rdev == NULL)
1573                 return 0;
1574
1575         /* convert to bytes */
1576         base_offset <<= 8;
1577         mip_offset <<= 8;
1578
1579         word0 = radeon_get_ib_value(p, idx + 0);
1580         if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1581                 if (tiling_flags & RADEON_TILING_MACRO)
1582                         word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1583                 else if (tiling_flags & RADEON_TILING_MICRO)
1584                         word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1585         }
1586         word1 = radeon_get_ib_value(p, idx + 1);
1587         word2 = radeon_get_ib_value(p, idx + 2) << 8;
1588         word3 = radeon_get_ib_value(p, idx + 3) << 8;
1589         word4 = radeon_get_ib_value(p, idx + 4);
1590         word5 = radeon_get_ib_value(p, idx + 5);
1591         dim = G_038000_DIM(word0);
1592         w0 = G_038000_TEX_WIDTH(word0) + 1;
1593         pitch = (G_038000_PITCH(word0) + 1) * 8;
1594         h0 = G_038004_TEX_HEIGHT(word1) + 1;
1595         d0 = G_038004_TEX_DEPTH(word1);
1596         format = G_038004_DATA_FORMAT(word1);
1597         blevel = G_038010_BASE_LEVEL(word4);
1598         llevel = G_038014_LAST_LEVEL(word5);
1599         /* pitch in texels */
1600         array_check.array_mode = G_038000_TILE_MODE(word0);
1601         array_check.group_size = track->group_size;
1602         array_check.nbanks = track->nbanks;
1603         array_check.npipes = track->npipes;
1604         array_check.nsamples = 1;
1605         array_check.blocksize = r600_fmt_get_blocksize(format);
1606         nfaces = 1;
1607         is_array = false;
1608         switch (dim) {
1609         case V_038000_SQ_TEX_DIM_1D:
1610         case V_038000_SQ_TEX_DIM_2D:
1611         case V_038000_SQ_TEX_DIM_3D:
1612                 break;
1613         case V_038000_SQ_TEX_DIM_CUBEMAP:
1614                 if (p->family >= CHIP_RV770)
1615                         nfaces = 8;
1616                 else
1617                         nfaces = 6;
1618                 break;
1619         case V_038000_SQ_TEX_DIM_1D_ARRAY:
1620         case V_038000_SQ_TEX_DIM_2D_ARRAY:
1621                 is_array = true;
1622                 break;
1623         case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1624                 is_array = true;
1625                 /* fall through */
1626         case V_038000_SQ_TEX_DIM_2D_MSAA:
1627                 array_check.nsamples = 1 << llevel;
1628                 llevel = 0;
1629                 break;
1630         default:
1631                 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1632                 return -EINVAL;
1633         }
1634         if (!r600_fmt_is_valid_texture(format, p->family)) {
1635                 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1636                          __func__, __LINE__, format);
1637                 return -EINVAL;
1638         }
1639
1640         if (r600_get_array_mode_alignment(&array_check,
1641                                           &pitch_align, &height_align, &depth_align, &base_align)) {
1642                 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
1643                          __func__, __LINE__, G_038000_TILE_MODE(word0));
1644                 return -EINVAL;
1645         }
1646
1647         /* XXX check height as well... */
1648
1649         if (!IS_ALIGNED(pitch, pitch_align)) {
1650                 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",
1651                          __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0));
1652                 return -EINVAL;
1653         }
1654         if (!IS_ALIGNED(base_offset, base_align)) {
1655                 dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n",
1656                          __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0));
1657                 return -EINVAL;
1658         }
1659         if (!IS_ALIGNED(mip_offset, base_align)) {
1660                 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n",
1661                          __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0));
1662                 return -EINVAL;
1663         }
1664
1665         if (blevel > llevel) {
1666                 dev_warn(p->dev, "texture blevel %d > llevel %d\n",
1667                          blevel, llevel);
1668         }
1669         if (is_array) {
1670                 barray = G_038014_BASE_ARRAY(word5);
1671                 larray = G_038014_LAST_ARRAY(word5);
1672
1673                 nfaces = larray - barray + 1;
1674         }
1675         r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, format,
1676                           pitch_align, height_align, base_align,
1677                           &l0_size, &mipmap_size);
1678         /* using get ib will give us the offset into the texture bo */
1679         if ((l0_size + word2) > radeon_bo_size(texture)) {
1680                 dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n",
1681                          w0, h0, pitch_align, height_align,
1682                          array_check.array_mode, format, word2,
1683                          l0_size, radeon_bo_size(texture));
1684                 dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);
1685                 return -EINVAL;
1686         }
1687         /* using get ib will give us the offset into the mipmap bo */
1688         if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
1689                 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1690                   w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
1691         }
1692         return 0;
1693 }
1694
1695 static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1696 {
1697         u32 m, i;
1698
1699         i = (reg >> 7);
1700         if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
1701                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1702                 return false;
1703         }
1704         m = 1 << ((reg >> 2) & 31);
1705         if (!(r600_reg_safe_bm[i] & m))
1706                 return true;
1707         dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1708         return false;
1709 }
1710
1711 static int r600_packet3_check(struct radeon_cs_parser *p,
1712                                 struct radeon_cs_packet *pkt)
1713 {
1714         struct radeon_cs_reloc *reloc;
1715         struct r600_cs_track *track;
1716         volatile u32 *ib;
1717         unsigned idx;
1718         unsigned i;
1719         unsigned start_reg, end_reg, reg;
1720         int r;
1721         u32 idx_value;
1722
1723         track = (struct r600_cs_track *)p->track;
1724         ib = p->ib.ptr;
1725         idx = pkt->idx + 1;
1726         idx_value = radeon_get_ib_value(p, idx);
1727
1728         switch (pkt->opcode) {
1729         case PACKET3_SET_PREDICATION:
1730         {
1731                 int pred_op;
1732                 int tmp;
1733                 uint64_t offset;
1734
1735                 if (pkt->count != 1) {
1736                         DRM_ERROR("bad SET PREDICATION\n");
1737                         return -EINVAL;
1738                 }
1739
1740                 tmp = radeon_get_ib_value(p, idx + 1);
1741                 pred_op = (tmp >> 16) & 0x7;
1742
1743                 /* for the clear predicate operation */
1744                 if (pred_op == 0)
1745                         return 0;
1746
1747                 if (pred_op > 2) {
1748                         DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1749                         return -EINVAL;
1750                 }
1751
1752                 r = r600_cs_packet_next_reloc(p, &reloc);
1753                 if (r) {
1754                         DRM_ERROR("bad SET PREDICATION\n");
1755                         return -EINVAL;
1756                 }
1757
1758                 offset = reloc->lobj.gpu_offset +
1759                          (idx_value & 0xfffffff0) +
1760                          ((u64)(tmp & 0xff) << 32);
1761
1762                 ib[idx + 0] = offset;
1763                 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1764         }
1765         break;
1766
1767         case PACKET3_START_3D_CMDBUF:
1768                 if (p->family >= CHIP_RV770 || pkt->count) {
1769                         DRM_ERROR("bad START_3D\n");
1770                         return -EINVAL;
1771                 }
1772                 break;
1773         case PACKET3_CONTEXT_CONTROL:
1774                 if (pkt->count != 1) {
1775                         DRM_ERROR("bad CONTEXT_CONTROL\n");
1776                         return -EINVAL;
1777                 }
1778                 break;
1779         case PACKET3_INDEX_TYPE:
1780         case PACKET3_NUM_INSTANCES:
1781                 if (pkt->count) {
1782                         DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1783                         return -EINVAL;
1784                 }
1785                 break;
1786         case PACKET3_DRAW_INDEX:
1787         {
1788                 uint64_t offset;
1789                 if (pkt->count != 3) {
1790                         DRM_ERROR("bad DRAW_INDEX\n");
1791                         return -EINVAL;
1792                 }
1793                 r = r600_cs_packet_next_reloc(p, &reloc);
1794                 if (r) {
1795                         DRM_ERROR("bad DRAW_INDEX\n");
1796                         return -EINVAL;
1797                 }
1798
1799                 offset = reloc->lobj.gpu_offset +
1800                          idx_value +
1801                          ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1802
1803                 ib[idx+0] = offset;
1804                 ib[idx+1] = upper_32_bits(offset) & 0xff;
1805
1806                 r = r600_cs_track_check(p);
1807                 if (r) {
1808                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1809                         return r;
1810                 }
1811                 break;
1812         }
1813         case PACKET3_DRAW_INDEX_AUTO:
1814                 if (pkt->count != 1) {
1815                         DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1816                         return -EINVAL;
1817                 }
1818                 r = r600_cs_track_check(p);
1819                 if (r) {
1820                         dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1821                         return r;
1822                 }
1823                 break;
1824         case PACKET3_DRAW_INDEX_IMMD_BE:
1825         case PACKET3_DRAW_INDEX_IMMD:
1826                 if (pkt->count < 2) {
1827                         DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1828                         return -EINVAL;
1829                 }
1830                 r = r600_cs_track_check(p);
1831                 if (r) {
1832                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1833                         return r;
1834                 }
1835                 break;
1836         case PACKET3_WAIT_REG_MEM:
1837                 if (pkt->count != 5) {
1838                         DRM_ERROR("bad WAIT_REG_MEM\n");
1839                         return -EINVAL;
1840                 }
1841                 /* bit 4 is reg (0) or mem (1) */
1842                 if (idx_value & 0x10) {
1843                         uint64_t offset;
1844
1845                         r = r600_cs_packet_next_reloc(p, &reloc);
1846                         if (r) {
1847                                 DRM_ERROR("bad WAIT_REG_MEM\n");
1848                                 return -EINVAL;
1849                         }
1850
1851                         offset = reloc->lobj.gpu_offset +
1852                                  (radeon_get_ib_value(p, idx+1) & 0xfffffff0) +
1853                                  ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1854
1855                         ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0);
1856                         ib[idx+2] = upper_32_bits(offset) & 0xff;
1857                 }
1858                 break;
1859         case PACKET3_SURFACE_SYNC:
1860                 if (pkt->count != 3) {
1861                         DRM_ERROR("bad SURFACE_SYNC\n");
1862                         return -EINVAL;
1863                 }
1864                 /* 0xffffffff/0x0 is flush all cache flag */
1865                 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1866                     radeon_get_ib_value(p, idx + 2) != 0) {
1867                         r = r600_cs_packet_next_reloc(p, &reloc);
1868                         if (r) {
1869                                 DRM_ERROR("bad SURFACE_SYNC\n");
1870                                 return -EINVAL;
1871                         }
1872                         ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1873                 }
1874                 break;
1875         case PACKET3_EVENT_WRITE:
1876                 if (pkt->count != 2 && pkt->count != 0) {
1877                         DRM_ERROR("bad EVENT_WRITE\n");
1878                         return -EINVAL;
1879                 }
1880                 if (pkt->count) {
1881                         uint64_t offset;
1882
1883                         r = r600_cs_packet_next_reloc(p, &reloc);
1884                         if (r) {
1885                                 DRM_ERROR("bad EVENT_WRITE\n");
1886                                 return -EINVAL;
1887                         }
1888                         offset = reloc->lobj.gpu_offset +
1889                                  (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
1890                                  ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1891
1892                         ib[idx+1] = offset & 0xfffffff8;
1893                         ib[idx+2] = upper_32_bits(offset) & 0xff;
1894                 }
1895                 break;
1896         case PACKET3_EVENT_WRITE_EOP:
1897         {
1898                 uint64_t offset;
1899
1900                 if (pkt->count != 4) {
1901                         DRM_ERROR("bad EVENT_WRITE_EOP\n");
1902                         return -EINVAL;
1903                 }
1904                 r = r600_cs_packet_next_reloc(p, &reloc);
1905                 if (r) {
1906                         DRM_ERROR("bad EVENT_WRITE\n");
1907                         return -EINVAL;
1908                 }
1909
1910                 offset = reloc->lobj.gpu_offset +
1911                          (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
1912                          ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1913
1914                 ib[idx+1] = offset & 0xfffffffc;
1915                 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1916                 break;
1917         }
1918         case PACKET3_SET_CONFIG_REG:
1919                 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
1920                 end_reg = 4 * pkt->count + start_reg - 4;
1921                 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1922                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1923                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1924                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1925                         return -EINVAL;
1926                 }
1927                 for (i = 0; i < pkt->count; i++) {
1928                         reg = start_reg + (4 * i);
1929                         r = r600_cs_check_reg(p, reg, idx+1+i);
1930                         if (r)
1931                                 return r;
1932                 }
1933                 break;
1934         case PACKET3_SET_CONTEXT_REG:
1935                 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
1936                 end_reg = 4 * pkt->count + start_reg - 4;
1937                 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
1938                     (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1939                     (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1940                         DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1941                         return -EINVAL;
1942                 }
1943                 for (i = 0; i < pkt->count; i++) {
1944                         reg = start_reg + (4 * i);
1945                         r = r600_cs_check_reg(p, reg, idx+1+i);
1946                         if (r)
1947                                 return r;
1948                 }
1949                 break;
1950         case PACKET3_SET_RESOURCE:
1951                 if (pkt->count % 7) {
1952                         DRM_ERROR("bad SET_RESOURCE\n");
1953                         return -EINVAL;
1954                 }
1955                 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
1956                 end_reg = 4 * pkt->count + start_reg - 4;
1957                 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
1958                     (start_reg >= PACKET3_SET_RESOURCE_END) ||
1959                     (end_reg >= PACKET3_SET_RESOURCE_END)) {
1960                         DRM_ERROR("bad SET_RESOURCE\n");
1961                         return -EINVAL;
1962                 }
1963                 for (i = 0; i < (pkt->count / 7); i++) {
1964                         struct radeon_bo *texture, *mipmap;
1965                         u32 size, offset, base_offset, mip_offset;
1966
1967                         switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
1968                         case SQ_TEX_VTX_VALID_TEXTURE:
1969                                 /* tex base */
1970                                 r = r600_cs_packet_next_reloc(p, &reloc);
1971                                 if (r) {
1972                                         DRM_ERROR("bad SET_RESOURCE\n");
1973                                         return -EINVAL;
1974                                 }
1975                                 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1976                                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1977                                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1978                                                 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1979                                         else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1980                                                 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1981                                 }
1982                                 texture = reloc->robj;
1983                                 /* tex mip base */
1984                                 r = r600_cs_packet_next_reloc(p, &reloc);
1985                                 if (r) {
1986                                         DRM_ERROR("bad SET_RESOURCE\n");
1987                                         return -EINVAL;
1988                                 }
1989                                 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1990                                 mipmap = reloc->robj;
1991                                 r = r600_check_texture_resource(p,  idx+(i*7)+1,
1992                                                                 texture, mipmap,
1993                                                                 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
1994                                                                 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
1995                                                                 reloc->lobj.tiling_flags);
1996                                 if (r)
1997                                         return r;
1998                                 ib[idx+1+(i*7)+2] += base_offset;
1999                                 ib[idx+1+(i*7)+3] += mip_offset;
2000                                 break;
2001                         case SQ_TEX_VTX_VALID_BUFFER:
2002                         {
2003                                 uint64_t offset64;
2004                                 /* vtx base */
2005                                 r = r600_cs_packet_next_reloc(p, &reloc);
2006                                 if (r) {
2007                                         DRM_ERROR("bad SET_RESOURCE\n");
2008                                         return -EINVAL;
2009                                 }
2010                                 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
2011                                 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
2012                                 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2013                                         /* force size to size of the buffer */
2014                                         dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
2015                                                  size + offset, radeon_bo_size(reloc->robj));
2016                                         ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset;
2017                                 }
2018
2019                                 offset64 = reloc->lobj.gpu_offset + offset;
2020                                 ib[idx+1+(i*8)+0] = offset64;
2021                                 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
2022                                                     (upper_32_bits(offset64) & 0xff);
2023                                 break;
2024                         }
2025                         case SQ_TEX_VTX_INVALID_TEXTURE:
2026                         case SQ_TEX_VTX_INVALID_BUFFER:
2027                         default:
2028                                 DRM_ERROR("bad SET_RESOURCE\n");
2029                                 return -EINVAL;
2030                         }
2031                 }
2032                 break;
2033         case PACKET3_SET_ALU_CONST:
2034                 if (track->sq_config & DX9_CONSTS) {
2035                         start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
2036                         end_reg = 4 * pkt->count + start_reg - 4;
2037                         if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
2038                             (start_reg >= PACKET3_SET_ALU_CONST_END) ||
2039                             (end_reg >= PACKET3_SET_ALU_CONST_END)) {
2040                                 DRM_ERROR("bad SET_ALU_CONST\n");
2041                                 return -EINVAL;
2042                         }
2043                 }
2044                 break;
2045         case PACKET3_SET_BOOL_CONST:
2046                 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
2047                 end_reg = 4 * pkt->count + start_reg - 4;
2048                 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
2049                     (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
2050                     (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
2051                         DRM_ERROR("bad SET_BOOL_CONST\n");
2052                         return -EINVAL;
2053                 }
2054                 break;
2055         case PACKET3_SET_LOOP_CONST:
2056                 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
2057                 end_reg = 4 * pkt->count + start_reg - 4;
2058                 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
2059                     (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
2060                     (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
2061                         DRM_ERROR("bad SET_LOOP_CONST\n");
2062                         return -EINVAL;
2063                 }
2064                 break;
2065         case PACKET3_SET_CTL_CONST:
2066                 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
2067                 end_reg = 4 * pkt->count + start_reg - 4;
2068                 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
2069                     (start_reg >= PACKET3_SET_CTL_CONST_END) ||
2070                     (end_reg >= PACKET3_SET_CTL_CONST_END)) {
2071                         DRM_ERROR("bad SET_CTL_CONST\n");
2072                         return -EINVAL;
2073                 }
2074                 break;
2075         case PACKET3_SET_SAMPLER:
2076                 if (pkt->count % 3) {
2077                         DRM_ERROR("bad SET_SAMPLER\n");
2078                         return -EINVAL;
2079                 }
2080                 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
2081                 end_reg = 4 * pkt->count + start_reg - 4;
2082                 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
2083                     (start_reg >= PACKET3_SET_SAMPLER_END) ||
2084                     (end_reg >= PACKET3_SET_SAMPLER_END)) {
2085                         DRM_ERROR("bad SET_SAMPLER\n");
2086                         return -EINVAL;
2087                 }
2088                 break;
2089         case PACKET3_STRMOUT_BASE_UPDATE:
2090                 if (p->family < CHIP_RV770) {
2091                         DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n");
2092                         return -EINVAL;
2093                 }
2094                 if (pkt->count != 1) {
2095                         DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n");
2096                         return -EINVAL;
2097                 }
2098                 if (idx_value > 3) {
2099                         DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n");
2100                         return -EINVAL;
2101                 }
2102                 {
2103                         u64 offset;
2104
2105                         r = r600_cs_packet_next_reloc(p, &reloc);
2106                         if (r) {
2107                                 DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n");
2108                                 return -EINVAL;
2109                         }
2110
2111                         if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
2112                                 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n");
2113                                 return -EINVAL;
2114                         }
2115
2116                         offset = radeon_get_ib_value(p, idx+1) << 8;
2117                         if (offset != track->vgt_strmout_bo_offset[idx_value]) {
2118                                 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n",
2119                                           offset, track->vgt_strmout_bo_offset[idx_value]);
2120                                 return -EINVAL;
2121                         }
2122
2123                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2124                                 DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%llx, 0x%lx\n",
2125                                           offset + 4, radeon_bo_size(reloc->robj));
2126                                 return -EINVAL;
2127                         }
2128                         ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2129                 }
2130                 break;
2131         case PACKET3_SURFACE_BASE_UPDATE:
2132                 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
2133                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2134                         return -EINVAL;
2135                 }
2136                 if (pkt->count) {
2137                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2138                         return -EINVAL;
2139                 }
2140                 break;
2141         case PACKET3_STRMOUT_BUFFER_UPDATE:
2142                 if (pkt->count != 4) {
2143                         DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2144                         return -EINVAL;
2145                 }
2146                 /* Updating memory at DST_ADDRESS. */
2147                 if (idx_value & 0x1) {
2148                         u64 offset;
2149                         r = r600_cs_packet_next_reloc(p, &reloc);
2150                         if (r) {
2151                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2152                                 return -EINVAL;
2153                         }
2154                         offset = radeon_get_ib_value(p, idx+1);
2155                         offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2156                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2157                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
2158                                           offset + 4, radeon_bo_size(reloc->robj));
2159                                 return -EINVAL;
2160                         }
2161                         offset += reloc->lobj.gpu_offset;
2162                         ib[idx+1] = offset;
2163                         ib[idx+2] = upper_32_bits(offset) & 0xff;
2164                 }
2165                 /* Reading data from SRC_ADDRESS. */
2166                 if (((idx_value >> 1) & 0x3) == 2) {
2167                         u64 offset;
2168                         r = r600_cs_packet_next_reloc(p, &reloc);
2169                         if (r) {
2170                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2171                                 return -EINVAL;
2172                         }
2173                         offset = radeon_get_ib_value(p, idx+3);
2174                         offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2175                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2176                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
2177                                           offset + 4, radeon_bo_size(reloc->robj));
2178                                 return -EINVAL;
2179                         }
2180                         offset += reloc->lobj.gpu_offset;
2181                         ib[idx+3] = offset;
2182                         ib[idx+4] = upper_32_bits(offset) & 0xff;
2183                 }
2184                 break;
2185         case PACKET3_COPY_DW:
2186                 if (pkt->count != 4) {
2187                         DRM_ERROR("bad COPY_DW (invalid count)\n");
2188                         return -EINVAL;
2189                 }
2190                 if (idx_value & 0x1) {
2191                         u64 offset;
2192                         /* SRC is memory. */
2193                         r = r600_cs_packet_next_reloc(p, &reloc);
2194                         if (r) {
2195                                 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2196                                 return -EINVAL;
2197                         }
2198                         offset = radeon_get_ib_value(p, idx+1);
2199                         offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2200                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2201                                 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
2202                                           offset + 4, radeon_bo_size(reloc->robj));
2203                                 return -EINVAL;
2204                         }
2205                         offset += reloc->lobj.gpu_offset;
2206                         ib[idx+1] = offset;
2207                         ib[idx+2] = upper_32_bits(offset) & 0xff;
2208                 } else {
2209                         /* SRC is a reg. */
2210                         reg = radeon_get_ib_value(p, idx+1) << 2;
2211                         if (!r600_is_safe_reg(p, reg, idx+1))
2212                                 return -EINVAL;
2213                 }
2214                 if (idx_value & 0x2) {
2215                         u64 offset;
2216                         /* DST is memory. */
2217                         r = r600_cs_packet_next_reloc(p, &reloc);
2218                         if (r) {
2219                                 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2220                                 return -EINVAL;
2221                         }
2222                         offset = radeon_get_ib_value(p, idx+3);
2223                         offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2224                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2225                                 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
2226                                           offset + 4, radeon_bo_size(reloc->robj));
2227                                 return -EINVAL;
2228                         }
2229                         offset += reloc->lobj.gpu_offset;
2230                         ib[idx+3] = offset;
2231                         ib[idx+4] = upper_32_bits(offset) & 0xff;
2232                 } else {
2233                         /* DST is a reg. */
2234                         reg = radeon_get_ib_value(p, idx+3) << 2;
2235                         if (!r600_is_safe_reg(p, reg, idx+3))
2236                                 return -EINVAL;
2237                 }
2238                 break;
2239         case PACKET3_NOP:
2240                 break;
2241         default:
2242                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2243                 return -EINVAL;
2244         }
2245         return 0;
2246 }
2247
2248 int r600_cs_parse(struct radeon_cs_parser *p)
2249 {
2250         struct radeon_cs_packet pkt;
2251         struct r600_cs_track *track;
2252         int r;
2253
2254         if (p->track == NULL) {
2255                 /* initialize tracker, we are in kms */
2256                 track = kzalloc(sizeof(*track), GFP_KERNEL);
2257                 if (track == NULL)
2258                         return -ENOMEM;
2259                 r600_cs_track_init(track);
2260                 if (p->rdev->family < CHIP_RV770) {
2261                         track->npipes = p->rdev->config.r600.tiling_npipes;
2262                         track->nbanks = p->rdev->config.r600.tiling_nbanks;
2263                         track->group_size = p->rdev->config.r600.tiling_group_size;
2264                 } else if (p->rdev->family <= CHIP_RV740) {
2265                         track->npipes = p->rdev->config.rv770.tiling_npipes;
2266                         track->nbanks = p->rdev->config.rv770.tiling_nbanks;
2267                         track->group_size = p->rdev->config.rv770.tiling_group_size;
2268                 }
2269                 p->track = track;
2270         }
2271         do {
2272                 r = r600_cs_packet_parse(p, &pkt, p->idx);
2273                 if (r) {
2274                         kfree(p->track);
2275                         p->track = NULL;
2276                         return r;
2277                 }
2278                 p->idx += pkt.count + 2;
2279                 switch (pkt.type) {
2280                 case PACKET_TYPE0:
2281                         r = r600_cs_parse_packet0(p, &pkt);
2282                         break;
2283                 case PACKET_TYPE2:
2284                         break;
2285                 case PACKET_TYPE3:
2286                         r = r600_packet3_check(p, &pkt);
2287                         break;
2288                 default:
2289                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
2290                         kfree(p->track);
2291                         p->track = NULL;
2292                         return -EINVAL;
2293                 }
2294                 if (r) {
2295                         kfree(p->track);
2296                         p->track = NULL;
2297                         return r;
2298                 }
2299         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2300 #if 0
2301         for (r = 0; r < p->ib.length_dw; r++) {
2302                 printk(KERN_INFO "%05d  0x%08X\n", r, p->ib.ptr[r]);
2303                 mdelay(1);
2304         }
2305 #endif
2306         kfree(p->track);
2307         p->track = NULL;
2308         return 0;
2309 }
2310
2311 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
2312 {
2313         if (p->chunk_relocs_idx == -1) {
2314                 return 0;
2315         }
2316         p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
2317         if (p->relocs == NULL) {
2318                 return -ENOMEM;
2319         }
2320         return 0;
2321 }
2322
2323 /**
2324  * cs_parser_fini() - clean parser states
2325  * @parser:     parser structure holding parsing context.
2326  * @error:      error number
2327  *
2328  * If error is set than unvalidate buffer, otherwise just free memory
2329  * used by parsing context.
2330  **/
2331 static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
2332 {
2333         unsigned i;
2334
2335         kfree(parser->relocs);
2336         for (i = 0; i < parser->nchunks; i++) {
2337                 kfree(parser->chunks[i].kdata);
2338                 kfree(parser->chunks[i].kpage[0]);
2339                 kfree(parser->chunks[i].kpage[1]);
2340         }
2341         kfree(parser->chunks);
2342         kfree(parser->chunks_array);
2343 }
2344
2345 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
2346                         unsigned family, u32 *ib, int *l)
2347 {
2348         struct radeon_cs_parser parser;
2349         struct radeon_cs_chunk *ib_chunk;
2350         struct r600_cs_track *track;
2351         int r;
2352
2353         /* initialize tracker */
2354         track = kzalloc(sizeof(*track), GFP_KERNEL);
2355         if (track == NULL)
2356                 return -ENOMEM;
2357         r600_cs_track_init(track);
2358         r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
2359         /* initialize parser */
2360         memset(&parser, 0, sizeof(struct radeon_cs_parser));
2361         parser.filp = filp;
2362         parser.dev = &dev->pdev->dev;
2363         parser.rdev = NULL;
2364         parser.family = family;
2365         parser.track = track;
2366         parser.ib.ptr = ib;
2367         r = radeon_cs_parser_init(&parser, data);
2368         if (r) {
2369                 DRM_ERROR("Failed to initialize parser !\n");
2370                 r600_cs_parser_fini(&parser, r);
2371                 return r;
2372         }
2373         r = r600_cs_parser_relocs_legacy(&parser);
2374         if (r) {
2375                 DRM_ERROR("Failed to parse relocation !\n");
2376                 r600_cs_parser_fini(&parser, r);
2377                 return r;
2378         }
2379         /* Copy the packet into the IB, the parser will read from the
2380          * input memory (cached) and write to the IB (which can be
2381          * uncached). */
2382         ib_chunk = &parser.chunks[parser.chunk_ib_idx];
2383         parser.ib.length_dw = ib_chunk->length_dw;
2384         *l = parser.ib.length_dw;
2385         r = r600_cs_parse(&parser);
2386         if (r) {
2387                 DRM_ERROR("Invalid command stream !\n");
2388                 r600_cs_parser_fini(&parser, r);
2389                 return r;
2390         }
2391         r = radeon_cs_finish_pages(&parser);
2392         if (r) {
2393                 DRM_ERROR("Invalid command stream !\n");
2394                 r600_cs_parser_fini(&parser, r);
2395                 return r;
2396         }
2397         r600_cs_parser_fini(&parser, r);
2398         return r;
2399 }
2400
2401 void r600_cs_legacy_init(void)
2402 {
2403         r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
2404 }