drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include "drm_crtc_helper.h"
  34 #include "drm_edid.h"
  35
  36 static int radeon_ddc_dump(struct drm_connector *connector);
  37
  38 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  39 {
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         struct drm_device *dev = crtc->dev;
  42         struct radeon_device *rdev = dev->dev_private;
  43         int i;
  44
  45         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  46         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  47
  48         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  49         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  51
  52         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  53         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  55
  56         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  57         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  58         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  59
  60         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  61         for (i = 0; i < 256; i++) {
  62                 WREG32(AVIVO_DC_LUT_30_COLOR,
  63                              (radeon_crtc->lut_r[i] << 20) |
  64                              (radeon_crtc->lut_g[i] << 10) |
  65                              (radeon_crtc->lut_b[i] << 0));
  66         }
  67
  68         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
  69 }
  70
  71 static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
  72 {
  73         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  74         struct drm_device *dev = crtc->dev;
  75         struct radeon_device *rdev = dev->dev_private;
  76         int i;
  77
  78         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  79         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  80
  81         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  82         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  83         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  84
  85         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  86         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  87         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  88
  89         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  90         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  91
  92         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  93         for (i = 0; i < 256; i++) {
  94                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  95                        (radeon_crtc->lut_r[i] << 20) |
  96                        (radeon_crtc->lut_g[i] << 10) |
  97                        (radeon_crtc->lut_b[i] << 0));
  98         }
  99 }
 100
 101 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 102 {
 103         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 104         struct drm_device *dev = crtc->dev;
 105         struct radeon_device *rdev = dev->dev_private;
 106         int i;
 107         uint32_t dac2_cntl;
 108
 109         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 110         if (radeon_crtc->crtc_id == 0)
 111                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 112         else
 113                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 114         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 115
 116         WREG8(RADEON_PALETTE_INDEX, 0);
 117         for (i = 0; i < 256; i++) {
 118                 WREG32(RADEON_PALETTE_30_DATA,
 119                              (radeon_crtc->lut_r[i] << 20) |
 120                              (radeon_crtc->lut_g[i] << 10) |
 121                              (radeon_crtc->lut_b[i] << 0));
 122         }
 123 }
 124
 125 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 126 {
 127         struct drm_device *dev = crtc->dev;
 128         struct radeon_device *rdev = dev->dev_private;
 129
 130         if (!crtc->enabled)
 131                 return;
 132
 133         if (ASIC_IS_DCE4(rdev))
 134                 evergreen_crtc_load_lut(crtc);
 135         else if (ASIC_IS_AVIVO(rdev))
 136                 avivo_crtc_load_lut(crtc);
 137         else
 138                 legacy_crtc_load_lut(crtc);
 139 }
 140
 141 /** Sets the color ramps on behalf of fbcon */
 142 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 143                               u16 blue, int regno)
 144 {
 145         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 146
 147         radeon_crtc->lut_r[regno] = red >> 6;
 148         radeon_crtc->lut_g[regno] = green >> 6;
 149         radeon_crtc->lut_b[regno] = blue >> 6;
 150 }
 151
 152 /** Gets the color ramps on behalf of fbcon */
 153 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 154                               u16 *blue, int regno)
 155 {
 156         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 157
 158         *red = radeon_crtc->lut_r[regno] << 6;
 159         *green = radeon_crtc->lut_g[regno] << 6;
 160         *blue = radeon_crtc->lut_b[regno] << 6;
 161 }
 162
 163 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 164                                   u16 *blue, uint32_t start, uint32_t size)
 165 {
 166         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 167         int end = (start + size > 256) ? 256 : start + size, i;
 168
 169         /* userspace palettes are always correct as is */
 170         for (i = start; i < end; i++) {
 171                 radeon_crtc->lut_r[i] = red[i] >> 6;
 172                 radeon_crtc->lut_g[i] = green[i] >> 6;
 173                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 174         }
 175         radeon_crtc_load_lut(crtc);
 176 }
 177
 178 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 179 {
 180         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 181
 182         drm_crtc_cleanup(crtc);
 183         kfree(radeon_crtc);
 184 }
 185
 186 /*
 187  * Handle unpin events outside the interrupt handler proper.
 188  */
 189 static void radeon_unpin_work_func(struct work_struct *__work)
 190 {
 191         struct radeon_unpin_work *work =
 192                 container_of(__work, struct radeon_unpin_work, work);
 193         int r;
 194
 195         /* unpin of the old buffer */
 196         r = radeon_bo_reserve(work->old_rbo, false);
 197         if (likely(r == 0)) {
 198                 r = radeon_bo_unpin(work->old_rbo);
 199                 if (unlikely(r != 0)) {
 200                         DRM_ERROR("failed to unpin buffer after flip\n");
 201                 }
 202                 radeon_bo_unreserve(work->old_rbo);
 203         } else
 204                 DRM_ERROR("failed to reserve buffer after flip\n");
 205         kfree(work);
 206 }
 207
 208 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 209 {
 210         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 211         struct radeon_unpin_work *work;
 212         struct drm_pending_vblank_event *e;
 213         struct timeval now;
 214         unsigned long flags;
 215         u32 update_pending;
 216         int vpos, hpos;
 217
 218         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 219         work = radeon_crtc->unpin_work;
 220         if (work == NULL ||
 221             !radeon_fence_signaled(work->fence)) {
 222                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 223                 return;
 224         }
 225         /* New pageflip, or just completion of a previous one? */
 226         if (!radeon_crtc->deferred_flip_completion) {
 227                 /* do the flip (mmio) */
 228                 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
 229         } else {
 230                 /* This is just a completion of a flip queued in crtc
 231                  * at last invocation. Make sure we go directly to
 232                  * completion routine.
 233                  */
 234                 update_pending = 0;
 235                 radeon_crtc->deferred_flip_completion = 0;
 236         }
 237
 238         /* Has the pageflip already completed in crtc, or is it certain
 239          * to complete in this vblank?
 240          */
 241         if (update_pending &&
 242             (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
 243                                                                &vpos, &hpos)) &&
 244             (vpos >=0) &&
 245             (vpos < (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100)) {
 246                 /* crtc didn't flip in this target vblank interval,
 247                  * but flip is pending in crtc. It will complete it
 248                  * in next vblank interval, so complete the flip at
 249                  * next vblank irq.
 250                  */
 251                 radeon_crtc->deferred_flip_completion = 1;
 252                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 253                 return;
 254         }
 255
 256         /* Pageflip (will be) certainly completed in this vblank. Clean up. */
 257         radeon_crtc->unpin_work = NULL;
 258
 259         /* wakeup userspace */
 260         if (work->event) {
 261                 e = work->event;
 262                 do_gettimeofday(&now);
 263                 e->event.sequence = drm_vblank_count(rdev->ddev, radeon_crtc->crtc_id);
 264                 e->event.tv_sec = now.tv_sec;
 265                 e->event.tv_usec = now.tv_usec;
 266                 list_add_tail(&e->base.link, &e->base.file_priv->event_list);
 267                 wake_up_interruptible(&e->base.file_priv->event_wait);
 268         }
 269         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 270
 271         drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
 272         radeon_fence_unref(&work->fence);
 273         radeon_post_page_flip(work->rdev, work->crtc_id);
 274         schedule_work(&work->work);
 275 }
 276
 277 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
 278                                  struct drm_framebuffer *fb,
 279                                  struct drm_pending_vblank_event *event)
 280 {
 281         struct drm_device *dev = crtc->dev;
 282         struct radeon_device *rdev = dev->dev_private;
 283         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 284         struct radeon_framebuffer *old_radeon_fb;
 285         struct radeon_framebuffer *new_radeon_fb;
 286         struct drm_gem_object *obj;
 287         struct radeon_bo *rbo;
 288         struct radeon_fence *fence;
 289         struct radeon_unpin_work *work;
 290         unsigned long flags;
 291         u32 tiling_flags, pitch_pixels;
 292         u64 base;
 293         int r;
 294
 295         work = kzalloc(sizeof *work, GFP_KERNEL);
 296         if (work == NULL)
 297                 return -ENOMEM;
 298
 299         r = radeon_fence_create(rdev, &fence);
 300         if (unlikely(r != 0)) {
 301                 kfree(work);
 302                 DRM_ERROR("flip queue: failed to create fence.\n");
 303                 return -ENOMEM;
 304         }
 305         work->event = event;
 306         work->rdev = rdev;
 307         work->crtc_id = radeon_crtc->crtc_id;
 308         work->fence = radeon_fence_ref(fence);
 309         old_radeon_fb = to_radeon_framebuffer(crtc->fb);
 310         new_radeon_fb = to_radeon_framebuffer(fb);
 311         /* schedule unpin of the old buffer */
 312         obj = old_radeon_fb->obj;
 313         rbo = obj->driver_private;
 314         work->old_rbo = rbo;
 315         INIT_WORK(&work->work, radeon_unpin_work_func);
 316
 317         /* We borrow the event spin lock for protecting unpin_work */
 318         spin_lock_irqsave(&dev->event_lock, flags);
 319         if (radeon_crtc->unpin_work) {
 320                 spin_unlock_irqrestore(&dev->event_lock, flags);
 321                 kfree(work);
 322                 radeon_fence_unref(&fence);
 323
 324                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 325                 return -EBUSY;
 326         }
 327         radeon_crtc->unpin_work = work;
 328         radeon_crtc->deferred_flip_completion = 0;
 329         spin_unlock_irqrestore(&dev->event_lock, flags);
 330
 331         /* pin the new buffer */
 332         obj = new_radeon_fb->obj;
 333         rbo = obj->driver_private;
 334
 335         DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
 336                          work->old_rbo, rbo);
 337
 338         r = radeon_bo_reserve(rbo, false);
 339         if (unlikely(r != 0)) {
 340                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 341                 goto pflip_cleanup;
 342         }
 343         r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
 344         if (unlikely(r != 0)) {
 345                 radeon_bo_unreserve(rbo);
 346                 r = -EINVAL;
 347                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 348                 goto pflip_cleanup;
 349         }
 350         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 351         radeon_bo_unreserve(rbo);
 352
 353         if (!ASIC_IS_AVIVO(rdev)) {
 354                 /* crtc offset is from display base addr not FB location */
 355                 base -= radeon_crtc->legacy_display_base_addr;
 356                 pitch_pixels = fb->pitch / (fb->bits_per_pixel / 8);
 357
 358                 if (tiling_flags & RADEON_TILING_MACRO) {
 359                         if (ASIC_IS_R300(rdev)) {
 360                                 base &= ~0x7ff;
 361                         } else {
 362                                 int byteshift = fb->bits_per_pixel >> 4;
 363                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 364                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 365                         }
 366                 } else {
 367                         int offset = crtc->y * pitch_pixels + crtc->x;
 368                         switch (fb->bits_per_pixel) {
 369                         case 8:
 370                         default:
 371                                 offset *= 1;
 372                                 break;
 373                         case 15:
 374                         case 16:
 375                                 offset *= 2;
 376                                 break;
 377                         case 24:
 378                                 offset *= 3;
 379                                 break;
 380                         case 32:
 381                                 offset *= 4;
 382                                 break;
 383                         }
 384                         base += offset;
 385                 }
 386                 base &= ~7;
 387         }
 388
 389         spin_lock_irqsave(&dev->event_lock, flags);
 390         work->new_crtc_base = base;
 391         spin_unlock_irqrestore(&dev->event_lock, flags);
 392
 393         /* update crtc fb */
 394         crtc->fb = fb;
 395
 396         r = drm_vblank_get(dev, radeon_crtc->crtc_id);
 397         if (r) {
 398                 DRM_ERROR("failed to get vblank before flip\n");
 399                 goto pflip_cleanup1;
 400         }
 401
 402         /* 32 ought to cover us */
 403         r = radeon_ring_lock(rdev, 32);
 404         if (r) {
 405                 DRM_ERROR("failed to lock the ring before flip\n");
 406                 goto pflip_cleanup2;
 407         }
 408
 409         /* emit the fence */
 410         radeon_fence_emit(rdev, fence);
 411         /* set the proper interrupt */
 412         radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
 413         /* fire the ring */
 414         radeon_ring_unlock_commit(rdev);
 415
 416         return 0;
 417
 418 pflip_cleanup2:
 419         drm_vblank_put(dev, radeon_crtc->crtc_id);
 420
 421 pflip_cleanup1:
 422         r = radeon_bo_reserve(rbo, false);
 423         if (unlikely(r != 0)) {
 424                 DRM_ERROR("failed to reserve new rbo in error path\n");
 425                 goto pflip_cleanup;
 426         }
 427         r = radeon_bo_unpin(rbo);
 428         if (unlikely(r != 0)) {
 429                 radeon_bo_unreserve(rbo);
 430                 r = -EINVAL;
 431                 DRM_ERROR("failed to unpin new rbo in error path\n");
 432                 goto pflip_cleanup;
 433         }
 434         radeon_bo_unreserve(rbo);
 435
 436 pflip_cleanup:
 437         spin_lock_irqsave(&dev->event_lock, flags);
 438         radeon_crtc->unpin_work = NULL;
 439         spin_unlock_irqrestore(&dev->event_lock, flags);
 440         radeon_fence_unref(&fence);
 441         kfree(work);
 442
 443         return r;
 444 }
 445
 446 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 447         .cursor_set = radeon_crtc_cursor_set,
 448         .cursor_move = radeon_crtc_cursor_move,
 449         .gamma_set = radeon_crtc_gamma_set,
 450         .set_config = drm_crtc_helper_set_config,
 451         .destroy = radeon_crtc_destroy,
 452         .page_flip = radeon_crtc_page_flip,
 453 };
 454
 455 static void radeon_crtc_init(struct drm_device *dev, int index)
 456 {
 457         struct radeon_device *rdev = dev->dev_private;
 458         struct radeon_crtc *radeon_crtc;
 459         int i;
 460
 461         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 462         if (radeon_crtc == NULL)
 463                 return;
 464
 465         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 466
 467         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 468         radeon_crtc->crtc_id = index;
 469         rdev->mode_info.crtcs[index] = radeon_crtc;
 470
 471 #if 0
 472         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 473         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 474         radeon_crtc->mode_set.num_connectors = 0;
 475 #endif
 476
 477         for (i = 0; i < 256; i++) {
 478                 radeon_crtc->lut_r[i] = i << 2;
 479                 radeon_crtc->lut_g[i] = i << 2;
 480                 radeon_crtc->lut_b[i] = i << 2;
 481         }
 482
 483         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 484                 radeon_atombios_init_crtc(dev, radeon_crtc);
 485         else
 486                 radeon_legacy_init_crtc(dev, radeon_crtc);
 487 }
 488
 489 static const char *encoder_names[34] = {
 490         "NONE",
 491         "INTERNAL_LVDS",
 492         "INTERNAL_TMDS1",
 493         "INTERNAL_TMDS2",
 494         "INTERNAL_DAC1",
 495         "INTERNAL_DAC2",
 496         "INTERNAL_SDVOA",
 497         "INTERNAL_SDVOB",
 498         "SI170B",
 499         "CH7303",
 500         "CH7301",
 501         "INTERNAL_DVO1",
 502         "EXTERNAL_SDVOA",
 503         "EXTERNAL_SDVOB",
 504         "TITFP513",
 505         "INTERNAL_LVTM1",
 506         "VT1623",
 507         "HDMI_SI1930",
 508         "HDMI_INTERNAL",
 509         "INTERNAL_KLDSCP_TMDS1",
 510         "INTERNAL_KLDSCP_DVO1",
 511         "INTERNAL_KLDSCP_DAC1",
 512         "INTERNAL_KLDSCP_DAC2",
 513         "SI178",
 514         "MVPU_FPGA",
 515         "INTERNAL_DDI",
 516         "VT1625",
 517         "HDMI_SI1932",
 518         "DP_AN9801",
 519         "DP_DP501",
 520         "INTERNAL_UNIPHY",
 521         "INTERNAL_KLDSCP_LVTMA",
 522         "INTERNAL_UNIPHY1",
 523         "INTERNAL_UNIPHY2",
 524 };
 525
 526 static const char *connector_names[15] = {
 527         "Unknown",
 528         "VGA",
 529         "DVI-I",
 530         "DVI-D",
 531         "DVI-A",
 532         "Composite",
 533         "S-video",
 534         "LVDS",
 535         "Component",
 536         "DIN",
 537         "DisplayPort",
 538         "HDMI-A",
 539         "HDMI-B",
 540         "TV",
 541         "eDP",
 542 };
 543
 544 static const char *hpd_names[6] = {
 545         "HPD1",
 546         "HPD2",
 547         "HPD3",
 548         "HPD4",
 549         "HPD5",
 550         "HPD6",
 551 };
 552
 553 static void radeon_print_display_setup(struct drm_device *dev)
 554 {
 555         struct drm_connector *connector;
 556         struct radeon_connector *radeon_connector;
 557         struct drm_encoder *encoder;
 558         struct radeon_encoder *radeon_encoder;
 559         uint32_t devices;
 560         int i = 0;
 561
 562         DRM_INFO("Radeon Display Connectors\n");
 563         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 564                 radeon_connector = to_radeon_connector(connector);
 565                 DRM_INFO("Connector %d:\n", i);
 566                 DRM_INFO("  %s\n", connector_names[connector->connector_type]);
 567                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 568                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 569                 if (radeon_connector->ddc_bus) {
 570                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 571                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 572                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 573                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 574                                  radeon_connector->ddc_bus->rec.a_data_reg,
 575                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 576                                  radeon_connector->ddc_bus->rec.en_data_reg,
 577                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 578                                  radeon_connector->ddc_bus->rec.y_data_reg);
 579                         if (radeon_connector->router.ddc_valid)
 580                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 581                                          radeon_connector->router.ddc_mux_control_pin,
 582                                          radeon_connector->router.ddc_mux_state);
 583                         if (radeon_connector->router.cd_valid)
 584                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 585                                          radeon_connector->router.cd_mux_control_pin,
 586                                          radeon_connector->router.cd_mux_state);
 587                 } else {
 588                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 589                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 590                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 591                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 592                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 593                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 594                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 595                 }
 596                 DRM_INFO("  Encoders:\n");
 597                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 598                         radeon_encoder = to_radeon_encoder(encoder);
 599                         devices = radeon_encoder->devices & radeon_connector->devices;
 600                         if (devices) {
 601                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 602                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 603                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 604                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 605                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 606                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 607                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 608                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 609                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 610                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 611                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 612                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 613                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 614                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 615                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 616                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 617                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 618                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 619                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 620                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 621                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 622                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 623                         }
 624                 }
 625                 i++;
 626         }
 627 }
 628
 629 static bool radeon_setup_enc_conn(struct drm_device *dev)
 630 {
 631         struct radeon_device *rdev = dev->dev_private;
 632         struct drm_connector *drm_connector;
 633         bool ret = false;
 634
 635         if (rdev->bios) {
 636                 if (rdev->is_atom_bios) {
 637                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 638                         if (ret == false)
 639                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 640                 } else {
 641                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 642                         if (ret == false)
 643                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 644                 }
 645         } else {
 646                 if (!ASIC_IS_AVIVO(rdev))
 647                         ret = radeon_get_legacy_connector_info_from_table(dev);
 648         }
 649         if (ret) {
 650                 radeon_setup_encoder_clones(dev);
 651                 radeon_print_display_setup(dev);
 652                 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
 653                         radeon_ddc_dump(drm_connector);
 654         }
 655
 656         return ret;
 657 }
 658
 659 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 660 {
 661         struct drm_device *dev = radeon_connector->base.dev;
 662         struct radeon_device *rdev = dev->dev_private;
 663         int ret = 0;
 664
 665         /* on hw with routers, select right port */
 666         if (radeon_connector->router.ddc_valid)
 667                 radeon_router_select_ddc_port(radeon_connector);
 668
 669         if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 670             (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 671                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 672                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 673                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
 674                         radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
 675         }
 676         if (!radeon_connector->ddc_bus)
 677                 return -1;
 678         if (!radeon_connector->edid) {
 679                 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
 680         }
 681         /* some servers provide a hardcoded edid in rom for KVMs */
 682         if (!radeon_connector->edid)
 683                 radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev);
 684         if (radeon_connector->edid) {
 685                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 686                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 687                 return ret;
 688         }
 689         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 690         return 0;
 691 }
 692
 693 static int radeon_ddc_dump(struct drm_connector *connector)
 694 {
 695         struct edid *edid;
 696         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 697         int ret = 0;
 698
 699         /* on hw with routers, select right port */
 700         if (radeon_connector->router.ddc_valid)
 701                 radeon_router_select_ddc_port(radeon_connector);
 702
 703         if (!radeon_connector->ddc_bus)
 704                 return -1;
 705         edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
 706         if (edid) {
 707                 kfree(edid);
 708         }
 709         return ret;
 710 }
 711
 712 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
 713 {
 714         uint64_t mod;
 715
 716         n += d / 2;
 717
 718         mod = do_div(n, d);
 719         return n;
 720 }
 721
 722 void radeon_compute_pll(struct radeon_pll *pll,
 723                         uint64_t freq,
 724                         uint32_t *dot_clock_p,
 725                         uint32_t *fb_div_p,
 726                         uint32_t *frac_fb_div_p,
 727                         uint32_t *ref_div_p,
 728                         uint32_t *post_div_p)
 729 {
 730         uint32_t min_ref_div = pll->min_ref_div;
 731         uint32_t max_ref_div = pll->max_ref_div;
 732         uint32_t min_post_div = pll->min_post_div;
 733         uint32_t max_post_div = pll->max_post_div;
 734         uint32_t min_fractional_feed_div = 0;
 735         uint32_t max_fractional_feed_div = 0;
 736         uint32_t best_vco = pll->best_vco;
 737         uint32_t best_post_div = 1;
 738         uint32_t best_ref_div = 1;
 739         uint32_t best_feedback_div = 1;
 740         uint32_t best_frac_feedback_div = 0;
 741         uint32_t best_freq = -1;
 742         uint32_t best_error = 0xffffffff;
 743         uint32_t best_vco_diff = 1;
 744         uint32_t post_div;
 745         u32 pll_out_min, pll_out_max;
 746
 747         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
 748         freq = freq * 1000;
 749
 750         if (pll->flags & RADEON_PLL_IS_LCD) {
 751                 pll_out_min = pll->lcd_pll_out_min;
 752                 pll_out_max = pll->lcd_pll_out_max;
 753         } else {
 754                 pll_out_min = pll->pll_out_min;
 755                 pll_out_max = pll->pll_out_max;
 756         }
 757
 758         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 759                 min_ref_div = max_ref_div = pll->reference_div;
 760         else {
 761                 while (min_ref_div < max_ref_div-1) {
 762                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
 763                         uint32_t pll_in = pll->reference_freq / mid;
 764                         if (pll_in < pll->pll_in_min)
 765                                 max_ref_div = mid;
 766                         else if (pll_in > pll->pll_in_max)
 767                                 min_ref_div = mid;
 768                         else
 769                                 break;
 770                 }
 771         }
 772
 773         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 774                 min_post_div = max_post_div = pll->post_div;
 775
 776         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 777                 min_fractional_feed_div = pll->min_frac_feedback_div;
 778                 max_fractional_feed_div = pll->max_frac_feedback_div;
 779         }
 780
 781         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
 782                 uint32_t ref_div;
 783
 784                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
 785                         continue;
 786
 787                 /* legacy radeons only have a few post_divs */
 788                 if (pll->flags & RADEON_PLL_LEGACY) {
 789                         if ((post_div == 5) ||
 790                             (post_div == 7) ||
 791                             (post_div == 9) ||
 792                             (post_div == 10) ||
 793                             (post_div == 11) ||
 794                             (post_div == 13) ||
 795                             (post_div == 14) ||
 796                             (post_div == 15))
 797                                 continue;
 798                 }
 799
 800                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
 801                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
 802                         uint32_t pll_in = pll->reference_freq / ref_div;
 803                         uint32_t min_feed_div = pll->min_feedback_div;
 804                         uint32_t max_feed_div = pll->max_feedback_div + 1;
 805
 806                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
 807                                 continue;
 808
 809                         while (min_feed_div < max_feed_div) {
 810                                 uint32_t vco;
 811                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
 812                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
 813                                 uint32_t frac_feedback_div;
 814                                 uint64_t tmp;
 815
 816                                 feedback_div = (min_feed_div + max_feed_div) / 2;
 817
 818                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
 819                                 vco = radeon_div(tmp, ref_div);
 820
 821                                 if (vco < pll_out_min) {
 822                                         min_feed_div = feedback_div + 1;
 823                                         continue;
 824                                 } else if (vco > pll_out_max) {
 825                                         max_feed_div = feedback_div;
 826                                         continue;
 827                                 }
 828
 829                                 while (min_frac_feed_div < max_frac_feed_div) {
 830                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
 831                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
 832                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
 833                                         current_freq = radeon_div(tmp, ref_div * post_div);
 834
 835                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
 836                                                 if (freq < current_freq)
 837                                                         error = 0xffffffff;
 838                                                 else
 839                                                         error = freq - current_freq;
 840                                         } else
 841                                                 error = abs(current_freq - freq);
 842                                         vco_diff = abs(vco - best_vco);
 843
 844                                         if ((best_vco == 0 && error < best_error) ||
 845                                             (best_vco != 0 &&
 846                                              ((best_error > 100 && error < best_error - 100) ||
 847                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
 848                                                 best_post_div = post_div;
 849                                                 best_ref_div = ref_div;
 850                                                 best_feedback_div = feedback_div;
 851                                                 best_frac_feedback_div = frac_feedback_div;
 852                                                 best_freq = current_freq;
 853                                                 best_error = error;
 854                                                 best_vco_diff = vco_diff;
 855                                         } else if (current_freq == freq) {
 856                                                 if (best_freq == -1) {
 857                                                         best_post_div = post_div;
 858                                                         best_ref_div = ref_div;
 859                                                         best_feedback_div = feedback_div;
 860                                                         best_frac_feedback_div = frac_feedback_div;
 861                                                         best_freq = current_freq;
 862                                                         best_error = error;
 863                                                         best_vco_diff = vco_diff;
 864                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
 865                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
 866                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
 867                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
 868                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
 869                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
 870                                                         best_post_div = post_div;
 871                                                         best_ref_div = ref_div;
 872                                                         best_feedback_div = feedback_div;
 873                                                         best_frac_feedback_div = frac_feedback_div;
 874                                                         best_freq = current_freq;
 875                                                         best_error = error;
 876                                                         best_vco_diff = vco_diff;
 877                                                 }
 878                                         }
 879                                         if (current_freq < freq)
 880                                                 min_frac_feed_div = frac_feedback_div + 1;
 881                                         else
 882                                                 max_frac_feed_div = frac_feedback_div;
 883                                 }
 884                                 if (current_freq < freq)
 885                                         min_feed_div = feedback_div + 1;
 886                                 else
 887                                         max_feed_div = feedback_div;
 888                         }
 889                 }
 890         }
 891
 892         *dot_clock_p = best_freq / 10000;
 893         *fb_div_p = best_feedback_div;
 894         *frac_fb_div_p = best_frac_feedback_div;
 895         *ref_div_p = best_ref_div;
 896         *post_div_p = best_post_div;
 897 }
 898
 899 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
 900 {
 901         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
 902
 903         if (radeon_fb->obj) {
 904                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
 905         }
 906         drm_framebuffer_cleanup(fb);
 907         kfree(radeon_fb);
 908 }
 909
 910 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
 911                                                   struct drm_file *file_priv,
 912                                                   unsigned int *handle)
 913 {
 914         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
 915
 916         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
 917 }
 918
 919 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
 920         .destroy = radeon_user_framebuffer_destroy,
 921         .create_handle = radeon_user_framebuffer_create_handle,
 922 };
 923
 924 void
 925 radeon_framebuffer_init(struct drm_device *dev,
 926                         struct radeon_framebuffer *rfb,
 927                         struct drm_mode_fb_cmd *mode_cmd,
 928                         struct drm_gem_object *obj)
 929 {
 930         rfb->obj = obj;
 931         drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
 932         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
 933 }
 934
 935 static struct drm_framebuffer *
 936 radeon_user_framebuffer_create(struct drm_device *dev,
 937                                struct drm_file *file_priv,
 938                                struct drm_mode_fb_cmd *mode_cmd)
 939 {
 940         struct drm_gem_object *obj;
 941         struct radeon_framebuffer *radeon_fb;
 942
 943         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
 944         if (obj ==  NULL) {
 945                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
 946                         "can't create framebuffer\n", mode_cmd->handle);
 947                 return ERR_PTR(-ENOENT);
 948         }
 949
 950         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
 951         if (radeon_fb == NULL)
 952                 return ERR_PTR(-ENOMEM);
 953
 954         radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
 955
 956         return &radeon_fb->base;
 957 }
 958
 959 static void radeon_output_poll_changed(struct drm_device *dev)
 960 {
 961         struct radeon_device *rdev = dev->dev_private;
 962         radeon_fb_output_poll_changed(rdev);
 963 }
 964
 965 static const struct drm_mode_config_funcs radeon_mode_funcs = {
 966         .fb_create = radeon_user_framebuffer_create,
 967         .output_poll_changed = radeon_output_poll_changed
 968 };
 969
 970 struct drm_prop_enum_list {
 971         int type;
 972         char *name;
 973 };
 974
 975 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
 976 {       { 0, "driver" },
 977         { 1, "bios" },
 978 };
 979
 980 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
 981 {       { TV_STD_NTSC, "ntsc" },
 982         { TV_STD_PAL, "pal" },
 983         { TV_STD_PAL_M, "pal-m" },
 984         { TV_STD_PAL_60, "pal-60" },
 985         { TV_STD_NTSC_J, "ntsc-j" },
 986         { TV_STD_SCART_PAL, "scart-pal" },
 987         { TV_STD_PAL_CN, "pal-cn" },
 988         { TV_STD_SECAM, "secam" },
 989 };
 990
 991 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
 992 {       { UNDERSCAN_OFF, "off" },
 993         { UNDERSCAN_ON, "on" },
 994         { UNDERSCAN_AUTO, "auto" },
 995 };
 996
 997 static int radeon_modeset_create_props(struct radeon_device *rdev)
 998 {
 999         int i, sz;
1000
1001         if (rdev->is_atom_bios) {
1002                 rdev->mode_info.coherent_mode_property =
1003                         drm_property_create(rdev->ddev,
1004                                             DRM_MODE_PROP_RANGE,
1005                                             "coherent", 2);
1006                 if (!rdev->mode_info.coherent_mode_property)
1007                         return -ENOMEM;
1008
1009                 rdev->mode_info.coherent_mode_property->values[0] = 0;
1010                 rdev->mode_info.coherent_mode_property->values[1] = 1;
1011         }
1012
1013         if (!ASIC_IS_AVIVO(rdev)) {
1014                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1015                 rdev->mode_info.tmds_pll_property =
1016                         drm_property_create(rdev->ddev,
1017                                             DRM_MODE_PROP_ENUM,
1018                                             "tmds_pll", sz);
1019                 for (i = 0; i < sz; i++) {
1020                         drm_property_add_enum(rdev->mode_info.tmds_pll_property,
1021                                               i,
1022                                               radeon_tmds_pll_enum_list[i].type,
1023                                               radeon_tmds_pll_enum_list[i].name);
1024                 }
1025         }
1026
1027         rdev->mode_info.load_detect_property =
1028                 drm_property_create(rdev->ddev,
1029                                     DRM_MODE_PROP_RANGE,
1030                                     "load detection", 2);
1031         if (!rdev->mode_info.load_detect_property)
1032                 return -ENOMEM;
1033         rdev->mode_info.load_detect_property->values[0] = 0;
1034         rdev->mode_info.load_detect_property->values[1] = 1;
1035
1036         drm_mode_create_scaling_mode_property(rdev->ddev);
1037
1038         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1039         rdev->mode_info.tv_std_property =
1040                 drm_property_create(rdev->ddev,
1041                                     DRM_MODE_PROP_ENUM,
1042                                     "tv standard", sz);
1043         for (i = 0; i < sz; i++) {
1044                 drm_property_add_enum(rdev->mode_info.tv_std_property,
1045                                       i,
1046                                       radeon_tv_std_enum_list[i].type,
1047                                       radeon_tv_std_enum_list[i].name);
1048         }
1049
1050         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1051         rdev->mode_info.underscan_property =
1052                 drm_property_create(rdev->ddev,
1053                                     DRM_MODE_PROP_ENUM,
1054                                     "underscan", sz);
1055         for (i = 0; i < sz; i++) {
1056                 drm_property_add_enum(rdev->mode_info.underscan_property,
1057                                       i,
1058                                       radeon_underscan_enum_list[i].type,
1059                                       radeon_underscan_enum_list[i].name);
1060         }
1061
1062         rdev->mode_info.underscan_hborder_property =
1063                 drm_property_create(rdev->ddev,
1064                                         DRM_MODE_PROP_RANGE,
1065                                         "underscan hborder", 2);
1066         if (!rdev->mode_info.underscan_hborder_property)
1067                 return -ENOMEM;
1068         rdev->mode_info.underscan_hborder_property->values[0] = 0;
1069         rdev->mode_info.underscan_hborder_property->values[1] = 128;
1070
1071         rdev->mode_info.underscan_vborder_property =
1072                 drm_property_create(rdev->ddev,
1073                                         DRM_MODE_PROP_RANGE,
1074                                         "underscan vborder", 2);
1075         if (!rdev->mode_info.underscan_vborder_property)
1076                 return -ENOMEM;
1077         rdev->mode_info.underscan_vborder_property->values[0] = 0;
1078         rdev->mode_info.underscan_vborder_property->values[1] = 128;
1079
1080         return 0;
1081 }
1082
1083 void radeon_update_display_priority(struct radeon_device *rdev)
1084 {
1085         /* adjustment options for the display watermarks */
1086         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1087                 /* set display priority to high for r3xx, rv515 chips
1088                  * this avoids flickering due to underflow to the
1089                  * display controllers during heavy acceleration.
1090                  * Don't force high on rs4xx igp chips as it seems to
1091                  * affect the sound card.  See kernel bug 15982.
1092                  */
1093                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1094                     !(rdev->flags & RADEON_IS_IGP))
1095                         rdev->disp_priority = 2;
1096                 else
1097                         rdev->disp_priority = 0;
1098         } else
1099                 rdev->disp_priority = radeon_disp_priority;
1100
1101 }
1102
1103 int radeon_modeset_init(struct radeon_device *rdev)
1104 {
1105         int i;
1106         int ret;
1107
1108         drm_mode_config_init(rdev->ddev);
1109         rdev->mode_info.mode_config_initialized = true;
1110
1111         rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
1112
1113         if (ASIC_IS_AVIVO(rdev)) {
1114                 rdev->ddev->mode_config.max_width = 8192;
1115                 rdev->ddev->mode_config.max_height = 8192;
1116         } else {
1117                 rdev->ddev->mode_config.max_width = 4096;
1118                 rdev->ddev->mode_config.max_height = 4096;
1119         }
1120
1121         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1122
1123         ret = radeon_modeset_create_props(rdev);
1124         if (ret) {
1125                 return ret;
1126         }
1127
1128         /* init i2c buses */
1129         radeon_i2c_init(rdev);
1130
1131         /* check combios for a valid hardcoded EDID - Sun servers */
1132         if (!rdev->is_atom_bios) {
1133                 /* check for hardcoded EDID in BIOS */
1134                 radeon_combios_check_hardcoded_edid(rdev);
1135         }
1136
1137         /* allocate crtcs */
1138         for (i = 0; i < rdev->num_crtc; i++) {
1139                 radeon_crtc_init(rdev->ddev, i);
1140         }
1141
1142         /* okay we should have all the bios connectors */
1143         ret = radeon_setup_enc_conn(rdev->ddev);
1144         if (!ret) {
1145                 return ret;
1146         }
1147         /* initialize hpd */
1148         radeon_hpd_init(rdev);
1149
1150         /* Initialize power management */
1151         radeon_pm_init(rdev);
1152
1153         radeon_fbdev_init(rdev);
1154         drm_kms_helper_poll_init(rdev->ddev);
1155
1156         return 0;
1157 }
1158
1159 void radeon_modeset_fini(struct radeon_device *rdev)
1160 {
1161         radeon_fbdev_fini(rdev);
1162         kfree(rdev->mode_info.bios_hardcoded_edid);
1163         radeon_pm_fini(rdev);
1164
1165         if (rdev->mode_info.mode_config_initialized) {
1166                 drm_kms_helper_poll_fini(rdev->ddev);
1167                 radeon_hpd_fini(rdev);
1168                 drm_mode_config_cleanup(rdev->ddev);
1169                 rdev->mode_info.mode_config_initialized = false;
1170         }
1171         /* free i2c buses */
1172         radeon_i2c_fini(rdev);
1173 }
1174
1175 static bool is_hdtv_mode(struct drm_display_mode *mode)
1176 {
1177         /* try and guess if this is a tv or a monitor */
1178         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1179             (mode->vdisplay == 576) || /* 576p */
1180             (mode->vdisplay == 720) || /* 720p */
1181             (mode->vdisplay == 1080)) /* 1080p */
1182                 return true;
1183         else
1184                 return false;
1185 }
1186
1187 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1188                                 struct drm_display_mode *mode,
1189                                 struct drm_display_mode *adjusted_mode)
1190 {
1191         struct drm_device *dev = crtc->dev;
1192         struct radeon_device *rdev = dev->dev_private;
1193         struct drm_encoder *encoder;
1194         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1195         struct radeon_encoder *radeon_encoder;
1196         struct drm_connector *connector;
1197         struct radeon_connector *radeon_connector;
1198         bool first = true;
1199         u32 src_v = 1, dst_v = 1;
1200         u32 src_h = 1, dst_h = 1;
1201
1202         radeon_crtc->h_border = 0;
1203         radeon_crtc->v_border = 0;
1204
1205         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1206                 if (encoder->crtc != crtc)
1207                         continue;
1208                 radeon_encoder = to_radeon_encoder(encoder);
1209                 connector = radeon_get_connector_for_encoder(encoder);
1210                 radeon_connector = to_radeon_connector(connector);
1211
1212                 if (first) {
1213                         /* set scaling */
1214                         if (radeon_encoder->rmx_type == RMX_OFF)
1215                                 radeon_crtc->rmx_type = RMX_OFF;
1216                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1217                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1218                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1219                         else
1220                                 radeon_crtc->rmx_type = RMX_OFF;
1221                         /* copy native mode */
1222                         memcpy(&radeon_crtc->native_mode,
1223                                &radeon_encoder->native_mode,
1224                                 sizeof(struct drm_display_mode));
1225                         src_v = crtc->mode.vdisplay;
1226                         dst_v = radeon_crtc->native_mode.vdisplay;
1227                         src_h = crtc->mode.hdisplay;
1228                         dst_h = radeon_crtc->native_mode.hdisplay;
1229
1230                         /* fix up for overscan on hdmi */
1231                         if (ASIC_IS_AVIVO(rdev) &&
1232                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1233                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1234                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1235                               drm_detect_hdmi_monitor(radeon_connector->edid) &&
1236                               is_hdtv_mode(mode)))) {
1237                                 if (radeon_encoder->underscan_hborder != 0)
1238                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1239                                 else
1240                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1241                                 if (radeon_encoder->underscan_vborder != 0)
1242                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1243                                 else
1244                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1245                                 radeon_crtc->rmx_type = RMX_FULL;
1246                                 src_v = crtc->mode.vdisplay;
1247                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1248                                 src_h = crtc->mode.hdisplay;
1249                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1250                         }
1251                         first = false;
1252                 } else {
1253                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1254                                 /* WARNING: Right now this can't happen but
1255                                  * in the future we need to check that scaling
1256                                  * are consistent across different encoder
1257                                  * (ie all encoder can work with the same
1258                                  *  scaling).
1259                                  */
1260                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1261                                 return false;
1262                         }
1263                 }
1264         }
1265         if (radeon_crtc->rmx_type != RMX_OFF) {
1266                 fixed20_12 a, b;
1267                 a.full = dfixed_const(src_v);
1268                 b.full = dfixed_const(dst_v);
1269                 radeon_crtc->vsc.full = dfixed_div(a, b);
1270                 a.full = dfixed_const(src_h);
1271                 b.full = dfixed_const(dst_h);
1272                 radeon_crtc->hsc.full = dfixed_div(a, b);
1273         } else {
1274                 radeon_crtc->vsc.full = dfixed_const(1);
1275                 radeon_crtc->hsc.full = dfixed_const(1);
1276         }
1277         return true;
1278 }
1279
1280 /*
1281  * Retrieve current video scanout position of crtc on a given gpu.
1282  *
1283  * \param dev Device to query.
1284  * \param crtc Crtc to query.
1285  * \param *vpos Location where vertical scanout position should be stored.
1286  * \param *hpos Location where horizontal scanout position should go.
1287  *
1288  * Returns vpos as a positive number while in active scanout area.
1289  * Returns vpos as a negative number inside vblank, counting the number
1290  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1291  * until start of active scanout / end of vblank."
1292  *
1293  * \return Flags, or'ed together as follows:
1294  *
1295  * DRM_SCANOUTPOS_VALID = Query successfull.
1296  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1297  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1298  * this flag means that returned position may be offset by a constant but
1299  * unknown small number of scanlines wrt. real scanout position.
1300  *
1301  */
1302 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
1303 {
1304         u32 stat_crtc = 0, vbl = 0, position = 0;
1305         int vbl_start, vbl_end, vtotal, ret = 0;
1306         bool in_vbl = true;
1307
1308         struct radeon_device *rdev = dev->dev_private;
1309
1310         if (ASIC_IS_DCE4(rdev)) {
1311                 if (crtc == 0) {
1312                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1313                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1314                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1315                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1316                         ret |= DRM_SCANOUTPOS_VALID;
1317                 }
1318                 if (crtc == 1) {
1319                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1320                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1321                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1322                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1323                         ret |= DRM_SCANOUTPOS_VALID;
1324                 }
1325                 if (crtc == 2) {
1326                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1327                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1328                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1329                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1330                         ret |= DRM_SCANOUTPOS_VALID;
1331                 }
1332                 if (crtc == 3) {
1333                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1334                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1335                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1336                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1337                         ret |= DRM_SCANOUTPOS_VALID;
1338                 }
1339                 if (crtc == 4) {
1340                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1341                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1342                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1343                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1344                         ret |= DRM_SCANOUTPOS_VALID;
1345                 }
1346                 if (crtc == 5) {
1347                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1348                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1349                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1350                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1351                         ret |= DRM_SCANOUTPOS_VALID;
1352                 }
1353         } else if (ASIC_IS_AVIVO(rdev)) {
1354                 if (crtc == 0) {
1355                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1356                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1357                         ret |= DRM_SCANOUTPOS_VALID;
1358                 }
1359                 if (crtc == 1) {
1360                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1361                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1362                         ret |= DRM_SCANOUTPOS_VALID;
1363                 }
1364         } else {
1365                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1366                 if (crtc == 0) {
1367                         /* Assume vbl_end == 0, get vbl_start from
1368                          * upper 16 bits.
1369                          */
1370                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1371                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1372                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1373                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1374                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1375                         if (!(stat_crtc & 1))
1376                                 in_vbl = false;
1377
1378                         ret |= DRM_SCANOUTPOS_VALID;
1379                 }
1380                 if (crtc == 1) {
1381                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1382                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1383                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1384                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1385                         if (!(stat_crtc & 1))
1386                                 in_vbl = false;
1387
1388                         ret |= DRM_SCANOUTPOS_VALID;
1389                 }
1390         }
1391
1392         /* Decode into vertical and horizontal scanout position. */
1393         *vpos = position & 0x1fff;
1394         *hpos = (position >> 16) & 0x1fff;
1395
1396         /* Valid vblank area boundaries from gpu retrieved? */
1397         if (vbl > 0) {
1398                 /* Yes: Decode. */
1399                 ret |= DRM_SCANOUTPOS_ACCURATE;
1400                 vbl_start = vbl & 0x1fff;
1401                 vbl_end = (vbl >> 16) & 0x1fff;
1402         }
1403         else {
1404                 /* No: Fake something reasonable which gives at least ok results. */
1405                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1406                 vbl_end = 0;
1407         }
1408
1409         /* Test scanout position against vblank region. */
1410         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1411                 in_vbl = false;
1412
1413         /* Check if inside vblank area and apply corrective offsets:
1414          * vpos will then be >=0 in video scanout area, but negative
1415          * within vblank area, counting down the number of lines until
1416          * start of scanout.
1417          */
1418
1419         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1420         if (in_vbl && (*vpos >= vbl_start)) {
1421                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1422                 *vpos = *vpos - vtotal;
1423         }
1424
1425         /* Correct for shifted end of vbl at vbl_end. */
1426         *vpos = *vpos - vbl_end;
1427
1428         /* In vblank? */
1429         if (in_vbl)
1430                 ret |= DRM_SCANOUTPOS_INVBL;
1431
1432         return ret;
1433 }