drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include <linux/pm_runtime.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_plane_helper.h>
  36 #include <drm/drm_edid.h>
  37
  38 #include <linux/gcd.h>
  39
  40 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  41 {
  42         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  43         struct drm_device *dev = crtc->dev;
  44         struct radeon_device *rdev = dev->dev_private;
  45         int i;
  46
  47         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  48         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  49
  50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  51         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  52         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  53
  54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  55         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  56         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  57
  58         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  59         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  60         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  61
  62         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  63         for (i = 0; i < 256; i++) {
  64                 WREG32(AVIVO_DC_LUT_30_COLOR,
  65                              (radeon_crtc->lut_r[i] << 20) |
  66                              (radeon_crtc->lut_g[i] << 10) |
  67                              (radeon_crtc->lut_b[i] << 0));
  68         }
  69
  70         /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
  71         WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
  72 }
  73
  74 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  75 {
  76         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  77         struct drm_device *dev = crtc->dev;
  78         struct radeon_device *rdev = dev->dev_private;
  79         int i;
  80
  81         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  82         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  83
  84         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  85         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  86         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  87
  88         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  89         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  90         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  91
  92         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  93         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  94
  95         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  96         for (i = 0; i < 256; i++) {
  97                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  98                        (radeon_crtc->lut_r[i] << 20) |
  99                        (radeon_crtc->lut_g[i] << 10) |
 100                        (radeon_crtc->lut_b[i] << 0));
 101         }
 102 }
 103
 104 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 105 {
 106         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 107         struct drm_device *dev = crtc->dev;
 108         struct radeon_device *rdev = dev->dev_private;
 109         int i;
 110
 111         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 112
 113         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 114                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 115                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 116         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 117                NI_GRPH_PRESCALE_BYPASS);
 118         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 119                NI_OVL_PRESCALE_BYPASS);
 120         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 121                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 122                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 123
 124         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 125
 126         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 127         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 128         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 129
 130         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 131         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 132         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 133
 134         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 135         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 136
 137         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 138         for (i = 0; i < 256; i++) {
 139                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 140                        (radeon_crtc->lut_r[i] << 20) |
 141                        (radeon_crtc->lut_g[i] << 10) |
 142                        (radeon_crtc->lut_b[i] << 0));
 143         }
 144
 145         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 146                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 147                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 148                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 149                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 150         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 151                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 152                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 153         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 154                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 155                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 156         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 157                (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
 158                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 159         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 160         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 161         if (ASIC_IS_DCE8(rdev)) {
 162                 /* XXX this only needs to be programmed once per crtc at startup,
 163                  * not sure where the best place for it is
 164                  */
 165                 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
 166                        CIK_CURSOR_ALPHA_BLND_ENA);
 167         }
 168 }
 169
 170 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 171 {
 172         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 173         struct drm_device *dev = crtc->dev;
 174         struct radeon_device *rdev = dev->dev_private;
 175         int i;
 176         uint32_t dac2_cntl;
 177
 178         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 179         if (radeon_crtc->crtc_id == 0)
 180                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 181         else
 182                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 183         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 184
 185         WREG8(RADEON_PALETTE_INDEX, 0);
 186         for (i = 0; i < 256; i++) {
 187                 WREG32(RADEON_PALETTE_30_DATA,
 188                              (radeon_crtc->lut_r[i] << 20) |
 189                              (radeon_crtc->lut_g[i] << 10) |
 190                              (radeon_crtc->lut_b[i] << 0));
 191         }
 192 }
 193
 194 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 195 {
 196         struct drm_device *dev = crtc->dev;
 197         struct radeon_device *rdev = dev->dev_private;
 198
 199         if (!crtc->enabled)
 200                 return;
 201
 202         if (ASIC_IS_DCE5(rdev))
 203                 dce5_crtc_load_lut(crtc);
 204         else if (ASIC_IS_DCE4(rdev))
 205                 dce4_crtc_load_lut(crtc);
 206         else if (ASIC_IS_AVIVO(rdev))
 207                 avivo_crtc_load_lut(crtc);
 208         else
 209                 legacy_crtc_load_lut(crtc);
 210 }
 211
 212 /** Sets the color ramps on behalf of fbcon */
 213 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 214                               u16 blue, int regno)
 215 {
 216         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 217
 218         radeon_crtc->lut_r[regno] = red >> 6;
 219         radeon_crtc->lut_g[regno] = green >> 6;
 220         radeon_crtc->lut_b[regno] = blue >> 6;
 221 }
 222
 223 /** Gets the color ramps on behalf of fbcon */
 224 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 225                               u16 *blue, int regno)
 226 {
 227         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 228
 229         *red = radeon_crtc->lut_r[regno] << 6;
 230         *green = radeon_crtc->lut_g[regno] << 6;
 231         *blue = radeon_crtc->lut_b[regno] << 6;
 232 }
 233
 234 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 235                                  u16 *blue, uint32_t size)
 236 {
 237         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 238         int i;
 239
 240         /* userspace palettes are always correct as is */
 241         for (i = 0; i < size; i++) {
 242                 radeon_crtc->lut_r[i] = red[i] >> 6;
 243                 radeon_crtc->lut_g[i] = green[i] >> 6;
 244                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 245         }
 246         radeon_crtc_load_lut(crtc);
 247
 248         return 0;
 249 }
 250
 251 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 252 {
 253         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 254
 255         drm_crtc_cleanup(crtc);
 256         destroy_workqueue(radeon_crtc->flip_queue);
 257         kfree(radeon_crtc);
 258 }
 259
 260 /**
 261  * radeon_unpin_work_func - unpin old buffer object
 262  *
 263  * @__work - kernel work item
 264  *
 265  * Unpin the old frame buffer object outside of the interrupt handler
 266  */
 267 static void radeon_unpin_work_func(struct work_struct *__work)
 268 {
 269         struct radeon_flip_work *work =
 270                 container_of(__work, struct radeon_flip_work, unpin_work);
 271         int r;
 272
 273         /* unpin of the old buffer */
 274         r = radeon_bo_reserve(work->old_rbo, false);
 275         if (likely(r == 0)) {
 276                 r = radeon_bo_unpin(work->old_rbo);
 277                 if (unlikely(r != 0)) {
 278                         DRM_ERROR("failed to unpin buffer after flip\n");
 279                 }
 280                 radeon_bo_unreserve(work->old_rbo);
 281         } else
 282                 DRM_ERROR("failed to reserve buffer after flip\n");
 283
 284         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 285         kfree(work);
 286 }
 287
 288 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
 289 {
 290         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 291         unsigned long flags;
 292         u32 update_pending;
 293         int vpos, hpos;
 294
 295         /* can happen during initialization */
 296         if (radeon_crtc == NULL)
 297                 return;
 298
 299         /* Skip the pageflip completion check below (based on polling) on
 300          * asics which reliably support hw pageflip completion irqs. pflip
 301          * irqs are a reliable and race-free method of handling pageflip
 302          * completion detection. A use_pflipirq module parameter < 2 allows
 303          * to override this in case of asics with faulty pflip irqs.
 304          * A module parameter of 0 would only use this polling based path,
 305          * a parameter of 1 would use pflip irq only as a backup to this
 306          * path, as in Linux 3.16.
 307          */
 308         if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
 309                 return;
 310
 311         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 312         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 313                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 314                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 315                                  radeon_crtc->flip_status,
 316                                  RADEON_FLIP_SUBMITTED);
 317                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 318                 return;
 319         }
 320
 321         update_pending = radeon_page_flip_pending(rdev, crtc_id);
 322
 323         /* Has the pageflip already completed in crtc, or is it certain
 324          * to complete in this vblank?
 325          */
 326         if (update_pending &&
 327             (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev,
 328                                                                crtc_id,
 329                                                                USE_REAL_VBLANKSTART,
 330                                                                &vpos, &hpos, NULL, NULL,
 331                                                                &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
 332             ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
 333              (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
 334                 /* crtc didn't flip in this target vblank interval,
 335                  * but flip is pending in crtc. Based on the current
 336                  * scanout position we know that the current frame is
 337                  * (nearly) complete and the flip will (likely)
 338                  * complete before the start of the next frame.
 339                  */
 340                 update_pending = 0;
 341         }
 342         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 343         if (!update_pending)
 344                 radeon_crtc_handle_flip(rdev, crtc_id);
 345 }
 346
 347 /**
 348  * radeon_crtc_handle_flip - page flip completed
 349  *
 350  * @rdev: radeon device pointer
 351  * @crtc_id: crtc number this event is for
 352  *
 353  * Called when we are sure that a page flip for this crtc is completed.
 354  */
 355 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 356 {
 357         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 358         struct radeon_flip_work *work;
 359         unsigned long flags;
 360
 361         /* this can happen at init */
 362         if (radeon_crtc == NULL)
 363                 return;
 364
 365         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 366         work = radeon_crtc->flip_work;
 367         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 368                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 369                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 370                                  radeon_crtc->flip_status,
 371                                  RADEON_FLIP_SUBMITTED);
 372                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 373                 return;
 374         }
 375
 376         /* Pageflip completed. Clean up. */
 377         radeon_crtc->flip_status = RADEON_FLIP_NONE;
 378         radeon_crtc->flip_work = NULL;
 379
 380         /* wakeup userspace */
 381         if (work->event)
 382                 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
 383
 384         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 385
 386         drm_crtc_vblank_put(&radeon_crtc->base);
 387         radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
 388         queue_work(radeon_crtc->flip_queue, &work->unpin_work);
 389 }
 390
 391 /**
 392  * radeon_flip_work_func - page flip framebuffer
 393  *
 394  * @work - kernel work item
 395  *
 396  * Wait for the buffer object to become idle and do the actual page flip
 397  */
 398 static void radeon_flip_work_func(struct work_struct *__work)
 399 {
 400         struct radeon_flip_work *work =
 401                 container_of(__work, struct radeon_flip_work, flip_work);
 402         struct radeon_device *rdev = work->rdev;
 403         struct drm_device *dev = rdev->ddev;
 404         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
 405
 406         struct drm_crtc *crtc = &radeon_crtc->base;
 407         unsigned long flags;
 408         int r;
 409         int vpos, hpos;
 410
 411         down_read(&rdev->exclusive_lock);
 412         if (work->fence) {
 413                 struct radeon_fence *fence;
 414
 415                 fence = to_radeon_fence(work->fence);
 416                 if (fence && fence->rdev == rdev) {
 417                         r = radeon_fence_wait(fence, false);
 418                         if (r == -EDEADLK) {
 419                                 up_read(&rdev->exclusive_lock);
 420                                 do {
 421                                         r = radeon_gpu_reset(rdev);
 422                                 } while (r == -EAGAIN);
 423                                 down_read(&rdev->exclusive_lock);
 424                         }
 425                 } else
 426                         r = fence_wait(work->fence, false);
 427
 428                 if (r)
 429                         DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
 430
 431                 /* We continue with the page flip even if we failed to wait on
 432                  * the fence, otherwise the DRM core and userspace will be
 433                  * confused about which BO the CRTC is scanning out
 434                  */
 435
 436                 fence_put(work->fence);
 437                 work->fence = NULL;
 438         }
 439
 440         /* Wait until we're out of the vertical blank period before the one
 441          * targeted by the flip
 442          */
 443         while (radeon_crtc->enabled &&
 444                (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0,
 445                                            &vpos, &hpos, NULL, NULL,
 446                                            &crtc->hwmode)
 447                 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
 448                (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
 449                (int)(work->target_vblank -
 450                      dev->driver->get_vblank_counter(dev, work->crtc_id)) > 0)
 451                 usleep_range(1000, 2000);
 452
 453         /* We borrow the event spin lock for protecting flip_status */
 454         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 455
 456         /* set the proper interrupt */
 457         radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
 458
 459         /* do the flip (mmio) */
 460         radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
 461
 462         radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
 463         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 464         up_read(&rdev->exclusive_lock);
 465 }
 466
 467 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
 468                                         struct drm_framebuffer *fb,
 469                                         struct drm_pending_vblank_event *event,
 470                                         uint32_t page_flip_flags,
 471                                         uint32_t target)
 472 {
 473         struct drm_device *dev = crtc->dev;
 474         struct radeon_device *rdev = dev->dev_private;
 475         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 476         struct radeon_framebuffer *old_radeon_fb;
 477         struct radeon_framebuffer *new_radeon_fb;
 478         struct drm_gem_object *obj;
 479         struct radeon_flip_work *work;
 480         struct radeon_bo *new_rbo;
 481         uint32_t tiling_flags, pitch_pixels;
 482         uint64_t base;
 483         unsigned long flags;
 484         int r;
 485
 486         work = kzalloc(sizeof *work, GFP_KERNEL);
 487         if (work == NULL)
 488                 return -ENOMEM;
 489
 490         INIT_WORK(&work->flip_work, radeon_flip_work_func);
 491         INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
 492
 493         work->rdev = rdev;
 494         work->crtc_id = radeon_crtc->crtc_id;
 495         work->event = event;
 496         work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 497
 498         /* schedule unpin of the old buffer */
 499         old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
 500         obj = old_radeon_fb->obj;
 501
 502         /* take a reference to the old object */
 503         drm_gem_object_reference(obj);
 504         work->old_rbo = gem_to_radeon_bo(obj);
 505
 506         new_radeon_fb = to_radeon_framebuffer(fb);
 507         obj = new_radeon_fb->obj;
 508         new_rbo = gem_to_radeon_bo(obj);
 509
 510         /* pin the new buffer */
 511         DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
 512                          work->old_rbo, new_rbo);
 513
 514         r = radeon_bo_reserve(new_rbo, false);
 515         if (unlikely(r != 0)) {
 516                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 517                 goto cleanup;
 518         }
 519         /* Only 27 bit offset for legacy CRTC */
 520         r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
 521                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 522         if (unlikely(r != 0)) {
 523                 radeon_bo_unreserve(new_rbo);
 524                 r = -EINVAL;
 525                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 526                 goto cleanup;
 527         }
 528         work->fence = fence_get(reservation_object_get_excl(new_rbo->tbo.resv));
 529         radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
 530         radeon_bo_unreserve(new_rbo);
 531
 532         if (!ASIC_IS_AVIVO(rdev)) {
 533                 /* crtc offset is from display base addr not FB location */
 534                 base -= radeon_crtc->legacy_display_base_addr;
 535                 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 536
 537                 if (tiling_flags & RADEON_TILING_MACRO) {
 538                         if (ASIC_IS_R300(rdev)) {
 539                                 base &= ~0x7ff;
 540                         } else {
 541                                 int byteshift = fb->bits_per_pixel >> 4;
 542                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 543                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 544                         }
 545                 } else {
 546                         int offset = crtc->y * pitch_pixels + crtc->x;
 547                         switch (fb->bits_per_pixel) {
 548                         case 8:
 549                         default:
 550                                 offset *= 1;
 551                                 break;
 552                         case 15:
 553                         case 16:
 554                                 offset *= 2;
 555                                 break;
 556                         case 24:
 557                                 offset *= 3;
 558                                 break;
 559                         case 32:
 560                                 offset *= 4;
 561                                 break;
 562                         }
 563                         base += offset;
 564                 }
 565                 base &= ~7;
 566         }
 567         work->base = base;
 568         work->target_vblank = target - drm_crtc_vblank_count(crtc) +
 569                 dev->driver->get_vblank_counter(dev, work->crtc_id);
 570
 571         /* We borrow the event spin lock for protecting flip_work */
 572         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 573
 574         if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
 575                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 576                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 577                 r = -EBUSY;
 578                 goto pflip_cleanup;
 579         }
 580         radeon_crtc->flip_status = RADEON_FLIP_PENDING;
 581         radeon_crtc->flip_work = work;
 582
 583         /* update crtc fb */
 584         crtc->primary->fb = fb;
 585
 586         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 587
 588         queue_work(radeon_crtc->flip_queue, &work->flip_work);
 589         return 0;
 590
 591 pflip_cleanup:
 592         if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
 593                 DRM_ERROR("failed to reserve new rbo in error path\n");
 594                 goto cleanup;
 595         }
 596         if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
 597                 DRM_ERROR("failed to unpin new rbo in error path\n");
 598         }
 599         radeon_bo_unreserve(new_rbo);
 600
 601 cleanup:
 602         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 603         fence_put(work->fence);
 604         kfree(work);
 605         return r;
 606 }
 607
 608 static int
 609 radeon_crtc_set_config(struct drm_mode_set *set)
 610 {
 611         struct drm_device *dev;
 612         struct radeon_device *rdev;
 613         struct drm_crtc *crtc;
 614         bool active = false;
 615         int ret;
 616
 617         if (!set || !set->crtc)
 618                 return -EINVAL;
 619
 620         dev = set->crtc->dev;
 621
 622         ret = pm_runtime_get_sync(dev->dev);
 623         if (ret < 0)
 624                 return ret;
 625
 626         ret = drm_crtc_helper_set_config(set);
 627
 628         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 629                 if (crtc->enabled)
 630                         active = true;
 631
 632         pm_runtime_mark_last_busy(dev->dev);
 633
 634         rdev = dev->dev_private;
 635         /* if we have active crtcs and we don't have a power ref,
 636            take the current one */
 637         if (active && !rdev->have_disp_power_ref) {
 638                 rdev->have_disp_power_ref = true;
 639                 return ret;
 640         }
 641         /* if we have no active crtcs, then drop the power ref
 642            we got before */
 643         if (!active && rdev->have_disp_power_ref) {
 644                 pm_runtime_put_autosuspend(dev->dev);
 645                 rdev->have_disp_power_ref = false;
 646         }
 647
 648         /* drop the power reference we got coming in here */
 649         pm_runtime_put_autosuspend(dev->dev);
 650         return ret;
 651 }
 652
 653 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 654         .cursor_set2 = radeon_crtc_cursor_set2,
 655         .cursor_move = radeon_crtc_cursor_move,
 656         .gamma_set = radeon_crtc_gamma_set,
 657         .set_config = radeon_crtc_set_config,
 658         .destroy = radeon_crtc_destroy,
 659         .page_flip_target = radeon_crtc_page_flip_target,
 660 };
 661
 662 static void radeon_crtc_init(struct drm_device *dev, int index)
 663 {
 664         struct radeon_device *rdev = dev->dev_private;
 665         struct radeon_crtc *radeon_crtc;
 666         int i;
 667
 668         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 669         if (radeon_crtc == NULL)
 670                 return;
 671
 672         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 673
 674         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 675         radeon_crtc->crtc_id = index;
 676         radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
 677         rdev->mode_info.crtcs[index] = radeon_crtc;
 678
 679         if (rdev->family >= CHIP_BONAIRE) {
 680                 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
 681                 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
 682         } else {
 683                 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
 684                 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
 685         }
 686         dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
 687         dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
 688
 689 #if 0
 690         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 691         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 692         radeon_crtc->mode_set.num_connectors = 0;
 693 #endif
 694
 695         for (i = 0; i < 256; i++) {
 696                 radeon_crtc->lut_r[i] = i << 2;
 697                 radeon_crtc->lut_g[i] = i << 2;
 698                 radeon_crtc->lut_b[i] = i << 2;
 699         }
 700
 701         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 702                 radeon_atombios_init_crtc(dev, radeon_crtc);
 703         else
 704                 radeon_legacy_init_crtc(dev, radeon_crtc);
 705 }
 706
 707 static const char *encoder_names[38] = {
 708         "NONE",
 709         "INTERNAL_LVDS",
 710         "INTERNAL_TMDS1",
 711         "INTERNAL_TMDS2",
 712         "INTERNAL_DAC1",
 713         "INTERNAL_DAC2",
 714         "INTERNAL_SDVOA",
 715         "INTERNAL_SDVOB",
 716         "SI170B",
 717         "CH7303",
 718         "CH7301",
 719         "INTERNAL_DVO1",
 720         "EXTERNAL_SDVOA",
 721         "EXTERNAL_SDVOB",
 722         "TITFP513",
 723         "INTERNAL_LVTM1",
 724         "VT1623",
 725         "HDMI_SI1930",
 726         "HDMI_INTERNAL",
 727         "INTERNAL_KLDSCP_TMDS1",
 728         "INTERNAL_KLDSCP_DVO1",
 729         "INTERNAL_KLDSCP_DAC1",
 730         "INTERNAL_KLDSCP_DAC2",
 731         "SI178",
 732         "MVPU_FPGA",
 733         "INTERNAL_DDI",
 734         "VT1625",
 735         "HDMI_SI1932",
 736         "DP_AN9801",
 737         "DP_DP501",
 738         "INTERNAL_UNIPHY",
 739         "INTERNAL_KLDSCP_LVTMA",
 740         "INTERNAL_UNIPHY1",
 741         "INTERNAL_UNIPHY2",
 742         "NUTMEG",
 743         "TRAVIS",
 744         "INTERNAL_VCE",
 745         "INTERNAL_UNIPHY3",
 746 };
 747
 748 static const char *hpd_names[6] = {
 749         "HPD1",
 750         "HPD2",
 751         "HPD3",
 752         "HPD4",
 753         "HPD5",
 754         "HPD6",
 755 };
 756
 757 static void radeon_print_display_setup(struct drm_device *dev)
 758 {
 759         struct drm_connector *connector;
 760         struct radeon_connector *radeon_connector;
 761         struct drm_encoder *encoder;
 762         struct radeon_encoder *radeon_encoder;
 763         uint32_t devices;
 764         int i = 0;
 765
 766         DRM_INFO("Radeon Display Connectors\n");
 767         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 768                 radeon_connector = to_radeon_connector(connector);
 769                 DRM_INFO("Connector %d:\n", i);
 770                 DRM_INFO("  %s\n", connector->name);
 771                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 772                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 773                 if (radeon_connector->ddc_bus) {
 774                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 775                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 776                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 777                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 778                                  radeon_connector->ddc_bus->rec.a_data_reg,
 779                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 780                                  radeon_connector->ddc_bus->rec.en_data_reg,
 781                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 782                                  radeon_connector->ddc_bus->rec.y_data_reg);
 783                         if (radeon_connector->router.ddc_valid)
 784                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 785                                          radeon_connector->router.ddc_mux_control_pin,
 786                                          radeon_connector->router.ddc_mux_state);
 787                         if (radeon_connector->router.cd_valid)
 788                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 789                                          radeon_connector->router.cd_mux_control_pin,
 790                                          radeon_connector->router.cd_mux_state);
 791                 } else {
 792                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 793                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 794                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 795                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 796                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 797                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 798                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 799                 }
 800                 DRM_INFO("  Encoders:\n");
 801                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 802                         radeon_encoder = to_radeon_encoder(encoder);
 803                         devices = radeon_encoder->devices & radeon_connector->devices;
 804                         if (devices) {
 805                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 806                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 807                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 808                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 809                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 810                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 811                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 812                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 813                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 814                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 815                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 816                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 817                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 818                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 819                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 820                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 821                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 822                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 823                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 824                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 825                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 826                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 827                         }
 828                 }
 829                 i++;
 830         }
 831 }
 832
 833 static bool radeon_setup_enc_conn(struct drm_device *dev)
 834 {
 835         struct radeon_device *rdev = dev->dev_private;
 836         bool ret = false;
 837
 838         if (rdev->bios) {
 839                 if (rdev->is_atom_bios) {
 840                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 841                         if (ret == false)
 842                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 843                 } else {
 844                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 845                         if (ret == false)
 846                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 847                 }
 848         } else {
 849                 if (!ASIC_IS_AVIVO(rdev))
 850                         ret = radeon_get_legacy_connector_info_from_table(dev);
 851         }
 852         if (ret) {
 853                 radeon_setup_encoder_clones(dev);
 854                 radeon_print_display_setup(dev);
 855         }
 856
 857         return ret;
 858 }
 859
 860 /* avivo */
 861
 862 /**
 863  * avivo_reduce_ratio - fractional number reduction
 864  *
 865  * @nom: nominator
 866  * @den: denominator
 867  * @nom_min: minimum value for nominator
 868  * @den_min: minimum value for denominator
 869  *
 870  * Find the greatest common divisor and apply it on both nominator and
 871  * denominator, but make nominator and denominator are at least as large
 872  * as their minimum values.
 873  */
 874 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
 875                                unsigned nom_min, unsigned den_min)
 876 {
 877         unsigned tmp;
 878
 879         /* reduce the numbers to a simpler ratio */
 880         tmp = gcd(*nom, *den);
 881         *nom /= tmp;
 882         *den /= tmp;
 883
 884         /* make sure nominator is large enough */
 885         if (*nom < nom_min) {
 886                 tmp = DIV_ROUND_UP(nom_min, *nom);
 887                 *nom *= tmp;
 888                 *den *= tmp;
 889         }
 890
 891         /* make sure the denominator is large enough */
 892         if (*den < den_min) {
 893                 tmp = DIV_ROUND_UP(den_min, *den);
 894                 *nom *= tmp;
 895                 *den *= tmp;
 896         }
 897 }
 898
 899 /**
 900  * avivo_get_fb_ref_div - feedback and ref divider calculation
 901  *
 902  * @nom: nominator
 903  * @den: denominator
 904  * @post_div: post divider
 905  * @fb_div_max: feedback divider maximum
 906  * @ref_div_max: reference divider maximum
 907  * @fb_div: resulting feedback divider
 908  * @ref_div: resulting reference divider
 909  *
 910  * Calculate feedback and reference divider for a given post divider. Makes
 911  * sure we stay within the limits.
 912  */
 913 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
 914                                  unsigned fb_div_max, unsigned ref_div_max,
 915                                  unsigned *fb_div, unsigned *ref_div)
 916 {
 917         /* limit reference * post divider to a maximum */
 918         ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
 919
 920         /* get matching reference and feedback divider */
 921         *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
 922         *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
 923
 924         /* limit fb divider to its maximum */
 925         if (*fb_div > fb_div_max) {
 926                 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
 927                 *fb_div = fb_div_max;
 928         }
 929 }
 930
 931 /**
 932  * radeon_compute_pll_avivo - compute PLL paramaters
 933  *
 934  * @pll: information about the PLL
 935  * @dot_clock_p: resulting pixel clock
 936  * fb_div_p: resulting feedback divider
 937  * frac_fb_div_p: fractional part of the feedback divider
 938  * ref_div_p: resulting reference divider
 939  * post_div_p: resulting reference divider
 940  *
 941  * Try to calculate the PLL parameters to generate the given frequency:
 942  * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
 943  */
 944 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 945                               u32 freq,
 946                               u32 *dot_clock_p,
 947                               u32 *fb_div_p,
 948                               u32 *frac_fb_div_p,
 949                               u32 *ref_div_p,
 950                               u32 *post_div_p)
 951 {
 952         unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
 953                 freq : freq / 10;
 954
 955         unsigned fb_div_min, fb_div_max, fb_div;
 956         unsigned post_div_min, post_div_max, post_div;
 957         unsigned ref_div_min, ref_div_max, ref_div;
 958         unsigned post_div_best, diff_best;
 959         unsigned nom, den;
 960
 961         /* determine allowed feedback divider range */
 962         fb_div_min = pll->min_feedback_div;
 963         fb_div_max = pll->max_feedback_div;
 964
 965         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 966                 fb_div_min *= 10;
 967                 fb_div_max *= 10;
 968         }
 969
 970         /* determine allowed ref divider range */
 971         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 972                 ref_div_min = pll->reference_div;
 973         else
 974                 ref_div_min = pll->min_ref_div;
 975
 976         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
 977             pll->flags & RADEON_PLL_USE_REF_DIV)
 978                 ref_div_max = pll->reference_div;
 979         else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
 980                 /* fix for problems on RS880 */
 981                 ref_div_max = min(pll->max_ref_div, 7u);
 982         else
 983                 ref_div_max = pll->max_ref_div;
 984
 985         /* determine allowed post divider range */
 986         if (pll->flags & RADEON_PLL_USE_POST_DIV) {
 987                 post_div_min = pll->post_div;
 988                 post_div_max = pll->post_div;
 989         } else {
 990                 unsigned vco_min, vco_max;
 991
 992                 if (pll->flags & RADEON_PLL_IS_LCD) {
 993                         vco_min = pll->lcd_pll_out_min;
 994                         vco_max = pll->lcd_pll_out_max;
 995                 } else {
 996                         vco_min = pll->pll_out_min;
 997                         vco_max = pll->pll_out_max;
 998                 }
 999
1000                 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1001                         vco_min *= 10;
1002                         vco_max *= 10;
1003                 }
1004
1005                 post_div_min = vco_min / target_clock;
1006                 if ((target_clock * post_div_min) < vco_min)
1007                         ++post_div_min;
1008                 if (post_div_min < pll->min_post_div)
1009                         post_div_min = pll->min_post_div;
1010
1011                 post_div_max = vco_max / target_clock;
1012                 if ((target_clock * post_div_max) > vco_max)
1013                         --post_div_max;
1014                 if (post_div_max > pll->max_post_div)
1015                         post_div_max = pll->max_post_div;
1016         }
1017
1018         /* represent the searched ratio as fractional number */
1019         nom = target_clock;
1020         den = pll->reference_freq;
1021
1022         /* reduce the numbers to a simpler ratio */
1023         avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1024
1025         /* now search for a post divider */
1026         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1027                 post_div_best = post_div_min;
1028         else
1029                 post_div_best = post_div_max;
1030         diff_best = ~0;
1031
1032         for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1033                 unsigned diff;
1034                 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1035                                      ref_div_max, &fb_div, &ref_div);
1036                 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1037                         (ref_div * post_div));
1038
1039                 if (diff < diff_best || (diff == diff_best &&
1040                     !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1041
1042                         post_div_best = post_div;
1043                         diff_best = diff;
1044                 }
1045         }
1046         post_div = post_div_best;
1047
1048         /* get the feedback and reference divider for the optimal value */
1049         avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1050                              &fb_div, &ref_div);
1051
1052         /* reduce the numbers to a simpler ratio once more */
1053         /* this also makes sure that the reference divider is large enough */
1054         avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1055
1056         /* avoid high jitter with small fractional dividers */
1057         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1058                 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1059                 if (fb_div < fb_div_min) {
1060                         unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1061                         fb_div *= tmp;
1062                         ref_div *= tmp;
1063                 }
1064         }
1065
1066         /* and finally save the result */
1067         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1068                 *fb_div_p = fb_div / 10;
1069                 *frac_fb_div_p = fb_div % 10;
1070         } else {
1071                 *fb_div_p = fb_div;
1072                 *frac_fb_div_p = 0;
1073         }
1074
1075         *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1076                         (pll->reference_freq * *frac_fb_div_p)) /
1077                        (ref_div * post_div * 10);
1078         *ref_div_p = ref_div;
1079         *post_div_p = post_div;
1080
1081         DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1082                       freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1083                       ref_div, post_div);
1084 }
1085
1086 /* pre-avivo */
1087 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1088 {
1089         uint64_t mod;
1090
1091         n += d / 2;
1092
1093         mod = do_div(n, d);
1094         return n;
1095 }
1096
1097 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1098                                uint64_t freq,
1099                                uint32_t *dot_clock_p,
1100                                uint32_t *fb_div_p,
1101                                uint32_t *frac_fb_div_p,
1102                                uint32_t *ref_div_p,
1103                                uint32_t *post_div_p)
1104 {
1105         uint32_t min_ref_div = pll->min_ref_div;
1106         uint32_t max_ref_div = pll->max_ref_div;
1107         uint32_t min_post_div = pll->min_post_div;
1108         uint32_t max_post_div = pll->max_post_div;
1109         uint32_t min_fractional_feed_div = 0;
1110         uint32_t max_fractional_feed_div = 0;
1111         uint32_t best_vco = pll->best_vco;
1112         uint32_t best_post_div = 1;
1113         uint32_t best_ref_div = 1;
1114         uint32_t best_feedback_div = 1;
1115         uint32_t best_frac_feedback_div = 0;
1116         uint32_t best_freq = -1;
1117         uint32_t best_error = 0xffffffff;
1118         uint32_t best_vco_diff = 1;
1119         uint32_t post_div;
1120         u32 pll_out_min, pll_out_max;
1121
1122         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1123         freq = freq * 1000;
1124
1125         if (pll->flags & RADEON_PLL_IS_LCD) {
1126                 pll_out_min = pll->lcd_pll_out_min;
1127                 pll_out_max = pll->lcd_pll_out_max;
1128         } else {
1129                 pll_out_min = pll->pll_out_min;
1130                 pll_out_max = pll->pll_out_max;
1131         }
1132
1133         if (pll_out_min > 64800)
1134                 pll_out_min = 64800;
1135
1136         if (pll->flags & RADEON_PLL_USE_REF_DIV)
1137                 min_ref_div = max_ref_div = pll->reference_div;
1138         else {
1139                 while (min_ref_div < max_ref_div-1) {
1140                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
1141                         uint32_t pll_in = pll->reference_freq / mid;
1142                         if (pll_in < pll->pll_in_min)
1143                                 max_ref_div = mid;
1144                         else if (pll_in > pll->pll_in_max)
1145                                 min_ref_div = mid;
1146                         else
1147                                 break;
1148                 }
1149         }
1150
1151         if (pll->flags & RADEON_PLL_USE_POST_DIV)
1152                 min_post_div = max_post_div = pll->post_div;
1153
1154         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1155                 min_fractional_feed_div = pll->min_frac_feedback_div;
1156                 max_fractional_feed_div = pll->max_frac_feedback_div;
1157         }
1158
1159         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1160                 uint32_t ref_div;
1161
1162                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1163                         continue;
1164
1165                 /* legacy radeons only have a few post_divs */
1166                 if (pll->flags & RADEON_PLL_LEGACY) {
1167                         if ((post_div == 5) ||
1168                             (post_div == 7) ||
1169                             (post_div == 9) ||
1170                             (post_div == 10) ||
1171                             (post_div == 11) ||
1172                             (post_div == 13) ||
1173                             (post_div == 14) ||
1174                             (post_div == 15))
1175                                 continue;
1176                 }
1177
1178                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1179                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
1180                         uint32_t pll_in = pll->reference_freq / ref_div;
1181                         uint32_t min_feed_div = pll->min_feedback_div;
1182                         uint32_t max_feed_div = pll->max_feedback_div + 1;
1183
1184                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1185                                 continue;
1186
1187                         while (min_feed_div < max_feed_div) {
1188                                 uint32_t vco;
1189                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
1190                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1191                                 uint32_t frac_feedback_div;
1192                                 uint64_t tmp;
1193
1194                                 feedback_div = (min_feed_div + max_feed_div) / 2;
1195
1196                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
1197                                 vco = radeon_div(tmp, ref_div);
1198
1199                                 if (vco < pll_out_min) {
1200                                         min_feed_div = feedback_div + 1;
1201                                         continue;
1202                                 } else if (vco > pll_out_max) {
1203                                         max_feed_div = feedback_div;
1204                                         continue;
1205                                 }
1206
1207                                 while (min_frac_feed_div < max_frac_feed_div) {
1208                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1209                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1210                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1211                                         current_freq = radeon_div(tmp, ref_div * post_div);
1212
1213                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1214                                                 if (freq < current_freq)
1215                                                         error = 0xffffffff;
1216                                                 else
1217                                                         error = freq - current_freq;
1218                                         } else
1219                                                 error = abs(current_freq - freq);
1220                                         vco_diff = abs(vco - best_vco);
1221
1222                                         if ((best_vco == 0 && error < best_error) ||
1223                                             (best_vco != 0 &&
1224                                              ((best_error > 100 && error < best_error - 100) ||
1225                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1226                                                 best_post_div = post_div;
1227                                                 best_ref_div = ref_div;
1228                                                 best_feedback_div = feedback_div;
1229                                                 best_frac_feedback_div = frac_feedback_div;
1230                                                 best_freq = current_freq;
1231                                                 best_error = error;
1232                                                 best_vco_diff = vco_diff;
1233                                         } else if (current_freq == freq) {
1234                                                 if (best_freq == -1) {
1235                                                         best_post_div = post_div;
1236                                                         best_ref_div = ref_div;
1237                                                         best_feedback_div = feedback_div;
1238                                                         best_frac_feedback_div = frac_feedback_div;
1239                                                         best_freq = current_freq;
1240                                                         best_error = error;
1241                                                         best_vco_diff = vco_diff;
1242                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1243                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1244                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1245                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1246                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1247                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1248                                                         best_post_div = post_div;
1249                                                         best_ref_div = ref_div;
1250                                                         best_feedback_div = feedback_div;
1251                                                         best_frac_feedback_div = frac_feedback_div;
1252                                                         best_freq = current_freq;
1253                                                         best_error = error;
1254                                                         best_vco_diff = vco_diff;
1255                                                 }
1256                                         }
1257                                         if (current_freq < freq)
1258                                                 min_frac_feed_div = frac_feedback_div + 1;
1259                                         else
1260                                                 max_frac_feed_div = frac_feedback_div;
1261                                 }
1262                                 if (current_freq < freq)
1263                                         min_feed_div = feedback_div + 1;
1264                                 else
1265                                         max_feed_div = feedback_div;
1266                         }
1267                 }
1268         }
1269
1270         *dot_clock_p = best_freq / 10000;
1271         *fb_div_p = best_feedback_div;
1272         *frac_fb_div_p = best_frac_feedback_div;
1273         *ref_div_p = best_ref_div;
1274         *post_div_p = best_post_div;
1275         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1276                       (long long)freq,
1277                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1278                       best_ref_div, best_post_div);
1279
1280 }
1281
1282 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1283 {
1284         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1285
1286         drm_gem_object_unreference_unlocked(radeon_fb->obj);
1287         drm_framebuffer_cleanup(fb);
1288         kfree(radeon_fb);
1289 }
1290
1291 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1292                                                   struct drm_file *file_priv,
1293                                                   unsigned int *handle)
1294 {
1295         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1296
1297         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1298 }
1299
1300 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1301         .destroy = radeon_user_framebuffer_destroy,
1302         .create_handle = radeon_user_framebuffer_create_handle,
1303 };
1304
1305 int
1306 radeon_framebuffer_init(struct drm_device *dev,
1307                         struct radeon_framebuffer *rfb,
1308                         const struct drm_mode_fb_cmd2 *mode_cmd,
1309                         struct drm_gem_object *obj)
1310 {
1311         int ret;
1312         rfb->obj = obj;
1313         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1314         ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1315         if (ret) {
1316                 rfb->obj = NULL;
1317                 return ret;
1318         }
1319         return 0;
1320 }
1321
1322 static struct drm_framebuffer *
1323 radeon_user_framebuffer_create(struct drm_device *dev,
1324                                struct drm_file *file_priv,
1325                                const struct drm_mode_fb_cmd2 *mode_cmd)
1326 {
1327         struct drm_gem_object *obj;
1328         struct radeon_framebuffer *radeon_fb;
1329         int ret;
1330
1331         obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1332         if (obj ==  NULL) {
1333                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1334                         "can't create framebuffer\n", mode_cmd->handles[0]);
1335                 return ERR_PTR(-ENOENT);
1336         }
1337
1338         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1339         if (radeon_fb == NULL) {
1340                 drm_gem_object_unreference_unlocked(obj);
1341                 return ERR_PTR(-ENOMEM);
1342         }
1343
1344         ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1345         if (ret) {
1346                 kfree(radeon_fb);
1347                 drm_gem_object_unreference_unlocked(obj);
1348                 return ERR_PTR(ret);
1349         }
1350
1351         return &radeon_fb->base;
1352 }
1353
1354 static void radeon_output_poll_changed(struct drm_device *dev)
1355 {
1356         struct radeon_device *rdev = dev->dev_private;
1357         radeon_fb_output_poll_changed(rdev);
1358 }
1359
1360 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1361         .fb_create = radeon_user_framebuffer_create,
1362         .output_poll_changed = radeon_output_poll_changed
1363 };
1364
1365 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1366 {       { 0, "driver" },
1367         { 1, "bios" },
1368 };
1369
1370 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1371 {       { TV_STD_NTSC, "ntsc" },
1372         { TV_STD_PAL, "pal" },
1373         { TV_STD_PAL_M, "pal-m" },
1374         { TV_STD_PAL_60, "pal-60" },
1375         { TV_STD_NTSC_J, "ntsc-j" },
1376         { TV_STD_SCART_PAL, "scart-pal" },
1377         { TV_STD_PAL_CN, "pal-cn" },
1378         { TV_STD_SECAM, "secam" },
1379 };
1380
1381 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1382 {       { UNDERSCAN_OFF, "off" },
1383         { UNDERSCAN_ON, "on" },
1384         { UNDERSCAN_AUTO, "auto" },
1385 };
1386
1387 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1388 {       { RADEON_AUDIO_DISABLE, "off" },
1389         { RADEON_AUDIO_ENABLE, "on" },
1390         { RADEON_AUDIO_AUTO, "auto" },
1391 };
1392
1393 /* XXX support different dither options? spatial, temporal, both, etc. */
1394 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1395 {       { RADEON_FMT_DITHER_DISABLE, "off" },
1396         { RADEON_FMT_DITHER_ENABLE, "on" },
1397 };
1398
1399 static struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1400 {       { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1401         { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1402         { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1403         { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1404 };
1405
1406 static int radeon_modeset_create_props(struct radeon_device *rdev)
1407 {
1408         int sz;
1409
1410         if (rdev->is_atom_bios) {
1411                 rdev->mode_info.coherent_mode_property =
1412                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1413                 if (!rdev->mode_info.coherent_mode_property)
1414                         return -ENOMEM;
1415         }
1416
1417         if (!ASIC_IS_AVIVO(rdev)) {
1418                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1419                 rdev->mode_info.tmds_pll_property =
1420                         drm_property_create_enum(rdev->ddev, 0,
1421                                             "tmds_pll",
1422                                             radeon_tmds_pll_enum_list, sz);
1423         }
1424
1425         rdev->mode_info.load_detect_property =
1426                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1427         if (!rdev->mode_info.load_detect_property)
1428                 return -ENOMEM;
1429
1430         drm_mode_create_scaling_mode_property(rdev->ddev);
1431
1432         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1433         rdev->mode_info.tv_std_property =
1434                 drm_property_create_enum(rdev->ddev, 0,
1435                                     "tv standard",
1436                                     radeon_tv_std_enum_list, sz);
1437
1438         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1439         rdev->mode_info.underscan_property =
1440                 drm_property_create_enum(rdev->ddev, 0,
1441                                     "underscan",
1442                                     radeon_underscan_enum_list, sz);
1443
1444         rdev->mode_info.underscan_hborder_property =
1445                 drm_property_create_range(rdev->ddev, 0,
1446                                         "underscan hborder", 0, 128);
1447         if (!rdev->mode_info.underscan_hborder_property)
1448                 return -ENOMEM;
1449
1450         rdev->mode_info.underscan_vborder_property =
1451                 drm_property_create_range(rdev->ddev, 0,
1452                                         "underscan vborder", 0, 128);
1453         if (!rdev->mode_info.underscan_vborder_property)
1454                 return -ENOMEM;
1455
1456         sz = ARRAY_SIZE(radeon_audio_enum_list);
1457         rdev->mode_info.audio_property =
1458                 drm_property_create_enum(rdev->ddev, 0,
1459                                          "audio",
1460                                          radeon_audio_enum_list, sz);
1461
1462         sz = ARRAY_SIZE(radeon_dither_enum_list);
1463         rdev->mode_info.dither_property =
1464                 drm_property_create_enum(rdev->ddev, 0,
1465                                          "dither",
1466                                          radeon_dither_enum_list, sz);
1467
1468         sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1469         rdev->mode_info.output_csc_property =
1470                 drm_property_create_enum(rdev->ddev, 0,
1471                                          "output_csc",
1472                                          radeon_output_csc_enum_list, sz);
1473
1474         return 0;
1475 }
1476
1477 void radeon_update_display_priority(struct radeon_device *rdev)
1478 {
1479         /* adjustment options for the display watermarks */
1480         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1481                 /* set display priority to high for r3xx, rv515 chips
1482                  * this avoids flickering due to underflow to the
1483                  * display controllers during heavy acceleration.
1484                  * Don't force high on rs4xx igp chips as it seems to
1485                  * affect the sound card.  See kernel bug 15982.
1486                  */
1487                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1488                     !(rdev->flags & RADEON_IS_IGP))
1489                         rdev->disp_priority = 2;
1490                 else
1491                         rdev->disp_priority = 0;
1492         } else
1493                 rdev->disp_priority = radeon_disp_priority;
1494
1495 }
1496
1497 /*
1498  * Allocate hdmi structs and determine register offsets
1499  */
1500 static void radeon_afmt_init(struct radeon_device *rdev)
1501 {
1502         int i;
1503
1504         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1505                 rdev->mode_info.afmt[i] = NULL;
1506
1507         if (ASIC_IS_NODCE(rdev)) {
1508                 /* nothing to do */
1509         } else if (ASIC_IS_DCE4(rdev)) {
1510                 static uint32_t eg_offsets[] = {
1511                         EVERGREEN_CRTC0_REGISTER_OFFSET,
1512                         EVERGREEN_CRTC1_REGISTER_OFFSET,
1513                         EVERGREEN_CRTC2_REGISTER_OFFSET,
1514                         EVERGREEN_CRTC3_REGISTER_OFFSET,
1515                         EVERGREEN_CRTC4_REGISTER_OFFSET,
1516                         EVERGREEN_CRTC5_REGISTER_OFFSET,
1517                         0x13830 - 0x7030,
1518                 };
1519                 int num_afmt;
1520
1521                 /* DCE8 has 7 audio blocks tied to DIG encoders */
1522                 /* DCE6 has 6 audio blocks tied to DIG encoders */
1523                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1524                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1525                 if (ASIC_IS_DCE8(rdev))
1526                         num_afmt = 7;
1527                 else if (ASIC_IS_DCE6(rdev))
1528                         num_afmt = 6;
1529                 else if (ASIC_IS_DCE5(rdev))
1530                         num_afmt = 6;
1531                 else if (ASIC_IS_DCE41(rdev))
1532                         num_afmt = 2;
1533                 else /* DCE4 */
1534                         num_afmt = 6;
1535
1536                 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1537                 for (i = 0; i < num_afmt; i++) {
1538                         rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1539                         if (rdev->mode_info.afmt[i]) {
1540                                 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1541                                 rdev->mode_info.afmt[i]->id = i;
1542                         }
1543                 }
1544         } else if (ASIC_IS_DCE3(rdev)) {
1545                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1546                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1547                 if (rdev->mode_info.afmt[0]) {
1548                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1549                         rdev->mode_info.afmt[0]->id = 0;
1550                 }
1551                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1552                 if (rdev->mode_info.afmt[1]) {
1553                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1554                         rdev->mode_info.afmt[1]->id = 1;
1555                 }
1556         } else if (ASIC_IS_DCE2(rdev)) {
1557                 /* DCE2 has at least 1 routable audio block */
1558                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1559                 if (rdev->mode_info.afmt[0]) {
1560                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1561                         rdev->mode_info.afmt[0]->id = 0;
1562                 }
1563                 /* r6xx has 2 routable audio blocks */
1564                 if (rdev->family >= CHIP_R600) {
1565                         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1566                         if (rdev->mode_info.afmt[1]) {
1567                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1568                                 rdev->mode_info.afmt[1]->id = 1;
1569                         }
1570                 }
1571         }
1572 }
1573
1574 static void radeon_afmt_fini(struct radeon_device *rdev)
1575 {
1576         int i;
1577
1578         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1579                 kfree(rdev->mode_info.afmt[i]);
1580                 rdev->mode_info.afmt[i] = NULL;
1581         }
1582 }
1583
1584 int radeon_modeset_init(struct radeon_device *rdev)
1585 {
1586         int i;
1587         int ret;
1588
1589         drm_mode_config_init(rdev->ddev);
1590         rdev->mode_info.mode_config_initialized = true;
1591
1592         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1593
1594         if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1595                 rdev->ddev->mode_config.async_page_flip = true;
1596
1597         if (ASIC_IS_DCE5(rdev)) {
1598                 rdev->ddev->mode_config.max_width = 16384;
1599                 rdev->ddev->mode_config.max_height = 16384;
1600         } else if (ASIC_IS_AVIVO(rdev)) {
1601                 rdev->ddev->mode_config.max_width = 8192;
1602                 rdev->ddev->mode_config.max_height = 8192;
1603         } else {
1604                 rdev->ddev->mode_config.max_width = 4096;
1605                 rdev->ddev->mode_config.max_height = 4096;
1606         }
1607
1608         rdev->ddev->mode_config.preferred_depth = 24;
1609         rdev->ddev->mode_config.prefer_shadow = 1;
1610
1611         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1612
1613         ret = radeon_modeset_create_props(rdev);
1614         if (ret) {
1615                 return ret;
1616         }
1617
1618         /* init i2c buses */
1619         radeon_i2c_init(rdev);
1620
1621         /* check combios for a valid hardcoded EDID - Sun servers */
1622         if (!rdev->is_atom_bios) {
1623                 /* check for hardcoded EDID in BIOS */
1624                 radeon_combios_check_hardcoded_edid(rdev);
1625         }
1626
1627         /* allocate crtcs */
1628         for (i = 0; i < rdev->num_crtc; i++) {
1629                 radeon_crtc_init(rdev->ddev, i);
1630         }
1631
1632         /* okay we should have all the bios connectors */
1633         ret = radeon_setup_enc_conn(rdev->ddev);
1634         if (!ret) {
1635                 return ret;
1636         }
1637
1638         /* init dig PHYs, disp eng pll */
1639         if (rdev->is_atom_bios) {
1640                 radeon_atom_encoder_init(rdev);
1641                 radeon_atom_disp_eng_pll_init(rdev);
1642         }
1643
1644         /* initialize hpd */
1645         radeon_hpd_init(rdev);
1646
1647         /* setup afmt */
1648         radeon_afmt_init(rdev);
1649
1650         radeon_fbdev_init(rdev);
1651         drm_kms_helper_poll_init(rdev->ddev);
1652
1653         /* do pm late init */
1654         ret = radeon_pm_late_init(rdev);
1655
1656         return 0;
1657 }
1658
1659 void radeon_modeset_fini(struct radeon_device *rdev)
1660 {
1661         radeon_fbdev_fini(rdev);
1662         kfree(rdev->mode_info.bios_hardcoded_edid);
1663
1664         /* free i2c buses */
1665         radeon_i2c_fini(rdev);
1666
1667         if (rdev->mode_info.mode_config_initialized) {
1668                 radeon_afmt_fini(rdev);
1669                 drm_kms_helper_poll_fini(rdev->ddev);
1670                 radeon_hpd_fini(rdev);
1671                 drm_crtc_force_disable_all(rdev->ddev);
1672                 drm_mode_config_cleanup(rdev->ddev);
1673                 rdev->mode_info.mode_config_initialized = false;
1674         }
1675 }
1676
1677 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1678 {
1679         /* try and guess if this is a tv or a monitor */
1680         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1681             (mode->vdisplay == 576) || /* 576p */
1682             (mode->vdisplay == 720) || /* 720p */
1683             (mode->vdisplay == 1080)) /* 1080p */
1684                 return true;
1685         else
1686                 return false;
1687 }
1688
1689 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1690                                 const struct drm_display_mode *mode,
1691                                 struct drm_display_mode *adjusted_mode)
1692 {
1693         struct drm_device *dev = crtc->dev;
1694         struct radeon_device *rdev = dev->dev_private;
1695         struct drm_encoder *encoder;
1696         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1697         struct radeon_encoder *radeon_encoder;
1698         struct drm_connector *connector;
1699         struct radeon_connector *radeon_connector;
1700         bool first = true;
1701         u32 src_v = 1, dst_v = 1;
1702         u32 src_h = 1, dst_h = 1;
1703
1704         radeon_crtc->h_border = 0;
1705         radeon_crtc->v_border = 0;
1706
1707         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1708                 if (encoder->crtc != crtc)
1709                         continue;
1710                 radeon_encoder = to_radeon_encoder(encoder);
1711                 connector = radeon_get_connector_for_encoder(encoder);
1712                 radeon_connector = to_radeon_connector(connector);
1713
1714                 if (first) {
1715                         /* set scaling */
1716                         if (radeon_encoder->rmx_type == RMX_OFF)
1717                                 radeon_crtc->rmx_type = RMX_OFF;
1718                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1719                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1720                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1721                         else
1722                                 radeon_crtc->rmx_type = RMX_OFF;
1723                         /* copy native mode */
1724                         memcpy(&radeon_crtc->native_mode,
1725                                &radeon_encoder->native_mode,
1726                                 sizeof(struct drm_display_mode));
1727                         src_v = crtc->mode.vdisplay;
1728                         dst_v = radeon_crtc->native_mode.vdisplay;
1729                         src_h = crtc->mode.hdisplay;
1730                         dst_h = radeon_crtc->native_mode.hdisplay;
1731
1732                         /* fix up for overscan on hdmi */
1733                         if (ASIC_IS_AVIVO(rdev) &&
1734                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1735                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1736                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1737                               drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1738                               is_hdtv_mode(mode)))) {
1739                                 if (radeon_encoder->underscan_hborder != 0)
1740                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1741                                 else
1742                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1743                                 if (radeon_encoder->underscan_vborder != 0)
1744                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1745                                 else
1746                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1747                                 radeon_crtc->rmx_type = RMX_FULL;
1748                                 src_v = crtc->mode.vdisplay;
1749                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1750                                 src_h = crtc->mode.hdisplay;
1751                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1752                         }
1753                         first = false;
1754                 } else {
1755                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1756                                 /* WARNING: Right now this can't happen but
1757                                  * in the future we need to check that scaling
1758                                  * are consistent across different encoder
1759                                  * (ie all encoder can work with the same
1760                                  *  scaling).
1761                                  */
1762                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1763                                 return false;
1764                         }
1765                 }
1766         }
1767         if (radeon_crtc->rmx_type != RMX_OFF) {
1768                 fixed20_12 a, b;
1769                 a.full = dfixed_const(src_v);
1770                 b.full = dfixed_const(dst_v);
1771                 radeon_crtc->vsc.full = dfixed_div(a, b);
1772                 a.full = dfixed_const(src_h);
1773                 b.full = dfixed_const(dst_h);
1774                 radeon_crtc->hsc.full = dfixed_div(a, b);
1775         } else {
1776                 radeon_crtc->vsc.full = dfixed_const(1);
1777                 radeon_crtc->hsc.full = dfixed_const(1);
1778         }
1779         return true;
1780 }
1781
1782 /*
1783  * Retrieve current video scanout position of crtc on a given gpu, and
1784  * an optional accurate timestamp of when query happened.
1785  *
1786  * \param dev Device to query.
1787  * \param crtc Crtc to query.
1788  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1789  *              For driver internal use only also supports these flags:
1790  *
1791  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
1792  *              of a fudged earlier start of vblank.
1793  *
1794  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
1795  *              fudged earlier start of vblank in *vpos and the distance
1796  *              to true start of vblank in *hpos.
1797  *
1798  * \param *vpos Location where vertical scanout position should be stored.
1799  * \param *hpos Location where horizontal scanout position should go.
1800  * \param *stime Target location for timestamp taken immediately before
1801  *               scanout position query. Can be NULL to skip timestamp.
1802  * \param *etime Target location for timestamp taken immediately after
1803  *               scanout position query. Can be NULL to skip timestamp.
1804  *
1805  * Returns vpos as a positive number while in active scanout area.
1806  * Returns vpos as a negative number inside vblank, counting the number
1807  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1808  * until start of active scanout / end of vblank."
1809  *
1810  * \return Flags, or'ed together as follows:
1811  *
1812  * DRM_SCANOUTPOS_VALID = Query successful.
1813  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1814  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1815  * this flag means that returned position may be offset by a constant but
1816  * unknown small number of scanlines wrt. real scanout position.
1817  *
1818  */
1819 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1820                                unsigned int flags, int *vpos, int *hpos,
1821                                ktime_t *stime, ktime_t *etime,
1822                                const struct drm_display_mode *mode)
1823 {
1824         u32 stat_crtc = 0, vbl = 0, position = 0;
1825         int vbl_start, vbl_end, vtotal, ret = 0;
1826         bool in_vbl = true;
1827
1828         struct radeon_device *rdev = dev->dev_private;
1829
1830         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1831
1832         /* Get optional system timestamp before query. */
1833         if (stime)
1834                 *stime = ktime_get();
1835
1836         if (ASIC_IS_DCE4(rdev)) {
1837                 if (pipe == 0) {
1838                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1839                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1840                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1841                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1842                         ret |= DRM_SCANOUTPOS_VALID;
1843                 }
1844                 if (pipe == 1) {
1845                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1846                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1847                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1848                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1849                         ret |= DRM_SCANOUTPOS_VALID;
1850                 }
1851                 if (pipe == 2) {
1852                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1853                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1854                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1855                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1856                         ret |= DRM_SCANOUTPOS_VALID;
1857                 }
1858                 if (pipe == 3) {
1859                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1860                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1861                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1862                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1863                         ret |= DRM_SCANOUTPOS_VALID;
1864                 }
1865                 if (pipe == 4) {
1866                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1867                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1868                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1869                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1870                         ret |= DRM_SCANOUTPOS_VALID;
1871                 }
1872                 if (pipe == 5) {
1873                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1874                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1875                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1876                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1877                         ret |= DRM_SCANOUTPOS_VALID;
1878                 }
1879         } else if (ASIC_IS_AVIVO(rdev)) {
1880                 if (pipe == 0) {
1881                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1882                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1883                         ret |= DRM_SCANOUTPOS_VALID;
1884                 }
1885                 if (pipe == 1) {
1886                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1887                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1888                         ret |= DRM_SCANOUTPOS_VALID;
1889                 }
1890         } else {
1891                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1892                 if (pipe == 0) {
1893                         /* Assume vbl_end == 0, get vbl_start from
1894                          * upper 16 bits.
1895                          */
1896                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1897                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1898                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1899                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1900                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1901                         if (!(stat_crtc & 1))
1902                                 in_vbl = false;
1903
1904                         ret |= DRM_SCANOUTPOS_VALID;
1905                 }
1906                 if (pipe == 1) {
1907                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1908                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1909                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1910                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1911                         if (!(stat_crtc & 1))
1912                                 in_vbl = false;
1913
1914                         ret |= DRM_SCANOUTPOS_VALID;
1915                 }
1916         }
1917
1918         /* Get optional system timestamp after query. */
1919         if (etime)
1920                 *etime = ktime_get();
1921
1922         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1923
1924         /* Decode into vertical and horizontal scanout position. */
1925         *vpos = position & 0x1fff;
1926         *hpos = (position >> 16) & 0x1fff;
1927
1928         /* Valid vblank area boundaries from gpu retrieved? */
1929         if (vbl > 0) {
1930                 /* Yes: Decode. */
1931                 ret |= DRM_SCANOUTPOS_ACCURATE;
1932                 vbl_start = vbl & 0x1fff;
1933                 vbl_end = (vbl >> 16) & 0x1fff;
1934         }
1935         else {
1936                 /* No: Fake something reasonable which gives at least ok results. */
1937                 vbl_start = mode->crtc_vdisplay;
1938                 vbl_end = 0;
1939         }
1940
1941         /* Called from driver internal vblank counter query code? */
1942         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1943             /* Caller wants distance from real vbl_start in *hpos */
1944             *hpos = *vpos - vbl_start;
1945         }
1946
1947         /* Fudge vblank to start a few scanlines earlier to handle the
1948          * problem that vblank irqs fire a few scanlines before start
1949          * of vblank. Some driver internal callers need the true vblank
1950          * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1951          *
1952          * The cause of the "early" vblank irq is that the irq is triggered
1953          * by the line buffer logic when the line buffer read position enters
1954          * the vblank, whereas our crtc scanout position naturally lags the
1955          * line buffer read position.
1956          */
1957         if (!(flags & USE_REAL_VBLANKSTART))
1958                 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1959
1960         /* Test scanout position against vblank region. */
1961         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1962                 in_vbl = false;
1963
1964         /* In vblank? */
1965         if (in_vbl)
1966             ret |= DRM_SCANOUTPOS_IN_VBLANK;
1967
1968         /* Called from driver internal vblank counter query code? */
1969         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1970                 /* Caller wants distance from fudged earlier vbl_start */
1971                 *vpos -= vbl_start;
1972                 return ret;
1973         }
1974
1975         /* Check if inside vblank area and apply corrective offsets:
1976          * vpos will then be >=0 in video scanout area, but negative
1977          * within vblank area, counting down the number of lines until
1978          * start of scanout.
1979          */
1980
1981         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1982         if (in_vbl && (*vpos >= vbl_start)) {
1983                 vtotal = mode->crtc_vtotal;
1984                 *vpos = *vpos - vtotal;
1985         }
1986
1987         /* Correct for shifted end of vbl at vbl_end. */
1988         *vpos = *vpos - vbl_end;
1989
1990         return ret;
1991 }