drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include <linux/pm_runtime.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_plane_helper.h>
  36 #include <drm/drm_edid.h>
  37
  38 #include <linux/gcd.h>
  39
  40 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  41 {
  42         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  43         struct drm_device *dev = crtc->dev;
  44         struct radeon_device *rdev = dev->dev_private;
  45         int i;
  46
  47         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  48         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  49
  50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  51         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  52         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  53
  54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  55         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  56         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  57
  58         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  59         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  60         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  61
  62         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  63         for (i = 0; i < 256; i++) {
  64                 WREG32(AVIVO_DC_LUT_30_COLOR,
  65                              (radeon_crtc->lut_r[i] << 20) |
  66                              (radeon_crtc->lut_g[i] << 10) |
  67                              (radeon_crtc->lut_b[i] << 0));
  68         }
  69
  70         /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
  71         WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
  72 }
  73
  74 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  75 {
  76         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  77         struct drm_device *dev = crtc->dev;
  78         struct radeon_device *rdev = dev->dev_private;
  79         int i;
  80
  81         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  82         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  83
  84         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  85         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  86         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  87
  88         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  89         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  90         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  91
  92         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  93         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  94
  95         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  96         for (i = 0; i < 256; i++) {
  97                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  98                        (radeon_crtc->lut_r[i] << 20) |
  99                        (radeon_crtc->lut_g[i] << 10) |
 100                        (radeon_crtc->lut_b[i] << 0));
 101         }
 102 }
 103
 104 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 105 {
 106         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 107         struct drm_device *dev = crtc->dev;
 108         struct radeon_device *rdev = dev->dev_private;
 109         int i;
 110
 111         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 112
 113         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 114                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 115                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 116         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 117                NI_GRPH_PRESCALE_BYPASS);
 118         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 119                NI_OVL_PRESCALE_BYPASS);
 120         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 121                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 122                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 123
 124         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 125
 126         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 127         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 128         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 129
 130         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 131         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 132         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 133
 134         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 135         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 136
 137         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 138         for (i = 0; i < 256; i++) {
 139                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 140                        (radeon_crtc->lut_r[i] << 20) |
 141                        (radeon_crtc->lut_g[i] << 10) |
 142                        (radeon_crtc->lut_b[i] << 0));
 143         }
 144
 145         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 146                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 147                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 148                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 149                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 150         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 151                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 152                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 153         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 154                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 155                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 156         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 157                (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
 158                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 159         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 160         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 161         if (ASIC_IS_DCE8(rdev)) {
 162                 /* XXX this only needs to be programmed once per crtc at startup,
 163                  * not sure where the best place for it is
 164                  */
 165                 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
 166                        CIK_CURSOR_ALPHA_BLND_ENA);
 167         }
 168 }
 169
 170 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 171 {
 172         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 173         struct drm_device *dev = crtc->dev;
 174         struct radeon_device *rdev = dev->dev_private;
 175         int i;
 176         uint32_t dac2_cntl;
 177
 178         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 179         if (radeon_crtc->crtc_id == 0)
 180                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 181         else
 182                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 183         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 184
 185         WREG8(RADEON_PALETTE_INDEX, 0);
 186         for (i = 0; i < 256; i++) {
 187                 WREG32(RADEON_PALETTE_30_DATA,
 188                              (radeon_crtc->lut_r[i] << 20) |
 189                              (radeon_crtc->lut_g[i] << 10) |
 190                              (radeon_crtc->lut_b[i] << 0));
 191         }
 192 }
 193
 194 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 195 {
 196         struct drm_device *dev = crtc->dev;
 197         struct radeon_device *rdev = dev->dev_private;
 198
 199         if (!crtc->enabled)
 200                 return;
 201
 202         if (ASIC_IS_DCE5(rdev))
 203                 dce5_crtc_load_lut(crtc);
 204         else if (ASIC_IS_DCE4(rdev))
 205                 dce4_crtc_load_lut(crtc);
 206         else if (ASIC_IS_AVIVO(rdev))
 207                 avivo_crtc_load_lut(crtc);
 208         else
 209                 legacy_crtc_load_lut(crtc);
 210 }
 211
 212 /** Sets the color ramps on behalf of fbcon */
 213 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 214                               u16 blue, int regno)
 215 {
 216         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 217
 218         radeon_crtc->lut_r[regno] = red >> 6;
 219         radeon_crtc->lut_g[regno] = green >> 6;
 220         radeon_crtc->lut_b[regno] = blue >> 6;
 221 }
 222
 223 /** Gets the color ramps on behalf of fbcon */
 224 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 225                               u16 *blue, int regno)
 226 {
 227         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 228
 229         *red = radeon_crtc->lut_r[regno] << 6;
 230         *green = radeon_crtc->lut_g[regno] << 6;
 231         *blue = radeon_crtc->lut_b[regno] << 6;
 232 }
 233
 234 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 235                                  u16 *blue, uint32_t size)
 236 {
 237         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 238         int i;
 239
 240         /* userspace palettes are always correct as is */
 241         for (i = 0; i < size; i++) {
 242                 radeon_crtc->lut_r[i] = red[i] >> 6;
 243                 radeon_crtc->lut_g[i] = green[i] >> 6;
 244                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 245         }
 246         radeon_crtc_load_lut(crtc);
 247
 248         return 0;
 249 }
 250
 251 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 252 {
 253         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 254
 255         drm_crtc_cleanup(crtc);
 256         destroy_workqueue(radeon_crtc->flip_queue);
 257         kfree(radeon_crtc);
 258 }
 259
 260 /**
 261  * radeon_unpin_work_func - unpin old buffer object
 262  *
 263  * @__work - kernel work item
 264  *
 265  * Unpin the old frame buffer object outside of the interrupt handler
 266  */
 267 static void radeon_unpin_work_func(struct work_struct *__work)
 268 {
 269         struct radeon_flip_work *work =
 270                 container_of(__work, struct radeon_flip_work, unpin_work);
 271         int r;
 272
 273         /* unpin of the old buffer */
 274         r = radeon_bo_reserve(work->old_rbo, false);
 275         if (likely(r == 0)) {
 276                 r = radeon_bo_unpin(work->old_rbo);
 277                 if (unlikely(r != 0)) {
 278                         DRM_ERROR("failed to unpin buffer after flip\n");
 279                 }
 280                 radeon_bo_unreserve(work->old_rbo);
 281         } else
 282                 DRM_ERROR("failed to reserve buffer after flip\n");
 283
 284         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 285         kfree(work);
 286 }
 287
 288 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
 289 {
 290         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 291         unsigned long flags;
 292         u32 update_pending;
 293         int vpos, hpos;
 294
 295         /* can happen during initialization */
 296         if (radeon_crtc == NULL)
 297                 return;
 298
 299         /* Skip the pageflip completion check below (based on polling) on
 300          * asics which reliably support hw pageflip completion irqs. pflip
 301          * irqs are a reliable and race-free method of handling pageflip
 302          * completion detection. A use_pflipirq module parameter < 2 allows
 303          * to override this in case of asics with faulty pflip irqs.
 304          * A module parameter of 0 would only use this polling based path,
 305          * a parameter of 1 would use pflip irq only as a backup to this
 306          * path, as in Linux 3.16.
 307          */
 308         if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
 309                 return;
 310
 311         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 312         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 313                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 314                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 315                                  radeon_crtc->flip_status,
 316                                  RADEON_FLIP_SUBMITTED);
 317                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 318                 return;
 319         }
 320
 321         update_pending = radeon_page_flip_pending(rdev, crtc_id);
 322
 323         /* Has the pageflip already completed in crtc, or is it certain
 324          * to complete in this vblank?
 325          */
 326         if (update_pending &&
 327             (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev,
 328                                                                crtc_id,
 329                                                                USE_REAL_VBLANKSTART,
 330                                                                &vpos, &hpos, NULL, NULL,
 331                                                                &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
 332             ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
 333              (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
 334                 /* crtc didn't flip in this target vblank interval,
 335                  * but flip is pending in crtc. Based on the current
 336                  * scanout position we know that the current frame is
 337                  * (nearly) complete and the flip will (likely)
 338                  * complete before the start of the next frame.
 339                  */
 340                 update_pending = 0;
 341         }
 342         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 343         if (!update_pending)
 344                 radeon_crtc_handle_flip(rdev, crtc_id);
 345 }
 346
 347 /**
 348  * radeon_crtc_handle_flip - page flip completed
 349  *
 350  * @rdev: radeon device pointer
 351  * @crtc_id: crtc number this event is for
 352  *
 353  * Called when we are sure that a page flip for this crtc is completed.
 354  */
 355 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 356 {
 357         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 358         struct radeon_flip_work *work;
 359         unsigned long flags;
 360
 361         /* this can happen at init */
 362         if (radeon_crtc == NULL)
 363                 return;
 364
 365         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 366         work = radeon_crtc->flip_work;
 367         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 368                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 369                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 370                                  radeon_crtc->flip_status,
 371                                  RADEON_FLIP_SUBMITTED);
 372                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 373                 return;
 374         }
 375
 376         /* Pageflip completed. Clean up. */
 377         radeon_crtc->flip_status = RADEON_FLIP_NONE;
 378         radeon_crtc->flip_work = NULL;
 379
 380         /* wakeup userspace */
 381         if (work->event)
 382                 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
 383
 384         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 385
 386         drm_crtc_vblank_put(&radeon_crtc->base);
 387         radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
 388         queue_work(radeon_crtc->flip_queue, &work->unpin_work);
 389 }
 390
 391 /**
 392  * radeon_flip_work_func - page flip framebuffer
 393  *
 394  * @work - kernel work item
 395  *
 396  * Wait for the buffer object to become idle and do the actual page flip
 397  */
 398 static void radeon_flip_work_func(struct work_struct *__work)
 399 {
 400         struct radeon_flip_work *work =
 401                 container_of(__work, struct radeon_flip_work, flip_work);
 402         struct radeon_device *rdev = work->rdev;
 403         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
 404
 405         struct drm_crtc *crtc = &radeon_crtc->base;
 406         unsigned long flags;
 407         int r;
 408         int vpos, hpos, stat, min_udelay = 0;
 409         unsigned repcnt = 4;
 410         struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id];
 411
 412         down_read(&rdev->exclusive_lock);
 413         if (work->fence) {
 414                 struct radeon_fence *fence;
 415
 416                 fence = to_radeon_fence(work->fence);
 417                 if (fence && fence->rdev == rdev) {
 418                         r = radeon_fence_wait(fence, false);
 419                         if (r == -EDEADLK) {
 420                                 up_read(&rdev->exclusive_lock);
 421                                 do {
 422                                         r = radeon_gpu_reset(rdev);
 423                                 } while (r == -EAGAIN);
 424                                 down_read(&rdev->exclusive_lock);
 425                         }
 426                 } else
 427                         r = fence_wait(work->fence, false);
 428
 429                 if (r)
 430                         DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
 431
 432                 /* We continue with the page flip even if we failed to wait on
 433                  * the fence, otherwise the DRM core and userspace will be
 434                  * confused about which BO the CRTC is scanning out
 435                  */
 436
 437                 fence_put(work->fence);
 438                 work->fence = NULL;
 439         }
 440
 441         /* We borrow the event spin lock for protecting flip_status */
 442         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 443
 444         /* set the proper interrupt */
 445         radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
 446
 447         /* If this happens to execute within the "virtually extended" vblank
 448          * interval before the start of the real vblank interval then it needs
 449          * to delay programming the mmio flip until the real vblank is entered.
 450          * This prevents completing a flip too early due to the way we fudge
 451          * our vblank counter and vblank timestamps in order to work around the
 452          * problem that the hw fires vblank interrupts before actual start of
 453          * vblank (when line buffer refilling is done for a frame). It
 454          * complements the fudging logic in radeon_get_crtc_scanoutpos() for
 455          * timestamping and radeon_get_vblank_counter_kms() for vblank counts.
 456          *
 457          * In practice this won't execute very often unless on very fast
 458          * machines because the time window for this to happen is very small.
 459          */
 460         while (radeon_crtc->enabled && --repcnt) {
 461                 /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank
 462                  * start in hpos, and to the "fudged earlier" vblank start in
 463                  * vpos.
 464                  */
 465                 stat = radeon_get_crtc_scanoutpos(rdev->ddev, work->crtc_id,
 466                                                   GET_DISTANCE_TO_VBLANKSTART,
 467                                                   &vpos, &hpos, NULL, NULL,
 468                                                   &crtc->hwmode);
 469
 470                 if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
 471                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) ||
 472                     !(vpos >= 0 && hpos <= 0))
 473                         break;
 474
 475                 /* Sleep at least until estimated real start of hw vblank */
 476                 min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5);
 477                 if (min_udelay > vblank->framedur_ns / 2000) {
 478                         /* Don't wait ridiculously long - something is wrong */
 479                         repcnt = 0;
 480                         break;
 481                 }
 482                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 483                 usleep_range(min_udelay, 2 * min_udelay);
 484                 spin_lock_irqsave(&crtc->dev->event_lock, flags);
 485         };
 486
 487         if (!repcnt)
 488                 DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, "
 489                                  "framedur %d, linedur %d, stat %d, vpos %d, "
 490                                  "hpos %d\n", work->crtc_id, min_udelay,
 491                                  vblank->framedur_ns / 1000,
 492                                  vblank->linedur_ns / 1000, stat, vpos, hpos);
 493
 494         /* do the flip (mmio) */
 495         radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
 496
 497         radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
 498         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 499         up_read(&rdev->exclusive_lock);
 500 }
 501
 502 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
 503                                  struct drm_framebuffer *fb,
 504                                  struct drm_pending_vblank_event *event,
 505                                  uint32_t page_flip_flags)
 506 {
 507         struct drm_device *dev = crtc->dev;
 508         struct radeon_device *rdev = dev->dev_private;
 509         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 510         struct radeon_framebuffer *old_radeon_fb;
 511         struct radeon_framebuffer *new_radeon_fb;
 512         struct drm_gem_object *obj;
 513         struct radeon_flip_work *work;
 514         struct radeon_bo *new_rbo;
 515         uint32_t tiling_flags, pitch_pixels;
 516         uint64_t base;
 517         unsigned long flags;
 518         int r;
 519
 520         work = kzalloc(sizeof *work, GFP_KERNEL);
 521         if (work == NULL)
 522                 return -ENOMEM;
 523
 524         INIT_WORK(&work->flip_work, radeon_flip_work_func);
 525         INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
 526
 527         work->rdev = rdev;
 528         work->crtc_id = radeon_crtc->crtc_id;
 529         work->event = event;
 530         work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 531
 532         /* schedule unpin of the old buffer */
 533         old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
 534         obj = old_radeon_fb->obj;
 535
 536         /* take a reference to the old object */
 537         drm_gem_object_reference(obj);
 538         work->old_rbo = gem_to_radeon_bo(obj);
 539
 540         new_radeon_fb = to_radeon_framebuffer(fb);
 541         obj = new_radeon_fb->obj;
 542         new_rbo = gem_to_radeon_bo(obj);
 543
 544         /* pin the new buffer */
 545         DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
 546                          work->old_rbo, new_rbo);
 547
 548         r = radeon_bo_reserve(new_rbo, false);
 549         if (unlikely(r != 0)) {
 550                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 551                 goto cleanup;
 552         }
 553         /* Only 27 bit offset for legacy CRTC */
 554         r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
 555                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 556         if (unlikely(r != 0)) {
 557                 radeon_bo_unreserve(new_rbo);
 558                 r = -EINVAL;
 559                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 560                 goto cleanup;
 561         }
 562         work->fence = fence_get(reservation_object_get_excl(new_rbo->tbo.resv));
 563         radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
 564         radeon_bo_unreserve(new_rbo);
 565
 566         if (!ASIC_IS_AVIVO(rdev)) {
 567                 /* crtc offset is from display base addr not FB location */
 568                 base -= radeon_crtc->legacy_display_base_addr;
 569                 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 570
 571                 if (tiling_flags & RADEON_TILING_MACRO) {
 572                         if (ASIC_IS_R300(rdev)) {
 573                                 base &= ~0x7ff;
 574                         } else {
 575                                 int byteshift = fb->bits_per_pixel >> 4;
 576                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 577                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 578                         }
 579                 } else {
 580                         int offset = crtc->y * pitch_pixels + crtc->x;
 581                         switch (fb->bits_per_pixel) {
 582                         case 8:
 583                         default:
 584                                 offset *= 1;
 585                                 break;
 586                         case 15:
 587                         case 16:
 588                                 offset *= 2;
 589                                 break;
 590                         case 24:
 591                                 offset *= 3;
 592                                 break;
 593                         case 32:
 594                                 offset *= 4;
 595                                 break;
 596                         }
 597                         base += offset;
 598                 }
 599                 base &= ~7;
 600         }
 601         work->base = base;
 602
 603         r = drm_crtc_vblank_get(crtc);
 604         if (r) {
 605                 DRM_ERROR("failed to get vblank before flip\n");
 606                 goto pflip_cleanup;
 607         }
 608
 609         /* We borrow the event spin lock for protecting flip_work */
 610         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 611
 612         if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
 613                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 614                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 615                 r = -EBUSY;
 616                 goto vblank_cleanup;
 617         }
 618         radeon_crtc->flip_status = RADEON_FLIP_PENDING;
 619         radeon_crtc->flip_work = work;
 620
 621         /* update crtc fb */
 622         crtc->primary->fb = fb;
 623
 624         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 625
 626         queue_work(radeon_crtc->flip_queue, &work->flip_work);
 627         return 0;
 628
 629 vblank_cleanup:
 630         drm_crtc_vblank_put(crtc);
 631
 632 pflip_cleanup:
 633         if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
 634                 DRM_ERROR("failed to reserve new rbo in error path\n");
 635                 goto cleanup;
 636         }
 637         if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
 638                 DRM_ERROR("failed to unpin new rbo in error path\n");
 639         }
 640         radeon_bo_unreserve(new_rbo);
 641
 642 cleanup:
 643         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 644         fence_put(work->fence);
 645         kfree(work);
 646         return r;
 647 }
 648
 649 static int
 650 radeon_crtc_set_config(struct drm_mode_set *set)
 651 {
 652         struct drm_device *dev;
 653         struct radeon_device *rdev;
 654         struct drm_crtc *crtc;
 655         bool active = false;
 656         int ret;
 657
 658         if (!set || !set->crtc)
 659                 return -EINVAL;
 660
 661         dev = set->crtc->dev;
 662
 663         ret = pm_runtime_get_sync(dev->dev);
 664         if (ret < 0)
 665                 return ret;
 666
 667         ret = drm_crtc_helper_set_config(set);
 668
 669         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 670                 if (crtc->enabled)
 671                         active = true;
 672
 673         pm_runtime_mark_last_busy(dev->dev);
 674
 675         rdev = dev->dev_private;
 676         /* if we have active crtcs and we don't have a power ref,
 677            take the current one */
 678         if (active && !rdev->have_disp_power_ref) {
 679                 rdev->have_disp_power_ref = true;
 680                 return ret;
 681         }
 682         /* if we have no active crtcs, then drop the power ref
 683            we got before */
 684         if (!active && rdev->have_disp_power_ref) {
 685                 pm_runtime_put_autosuspend(dev->dev);
 686                 rdev->have_disp_power_ref = false;
 687         }
 688
 689         /* drop the power reference we got coming in here */
 690         pm_runtime_put_autosuspend(dev->dev);
 691         return ret;
 692 }
 693
 694 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 695         .cursor_set2 = radeon_crtc_cursor_set2,
 696         .cursor_move = radeon_crtc_cursor_move,
 697         .gamma_set = radeon_crtc_gamma_set,
 698         .set_config = radeon_crtc_set_config,
 699         .destroy = radeon_crtc_destroy,
 700         .page_flip = radeon_crtc_page_flip,
 701 };
 702
 703 static void radeon_crtc_init(struct drm_device *dev, int index)
 704 {
 705         struct radeon_device *rdev = dev->dev_private;
 706         struct radeon_crtc *radeon_crtc;
 707         int i;
 708
 709         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 710         if (radeon_crtc == NULL)
 711                 return;
 712
 713         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 714
 715         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 716         radeon_crtc->crtc_id = index;
 717         radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc");
 718         rdev->mode_info.crtcs[index] = radeon_crtc;
 719
 720         if (rdev->family >= CHIP_BONAIRE) {
 721                 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
 722                 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
 723         } else {
 724                 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
 725                 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
 726         }
 727         dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
 728         dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
 729
 730 #if 0
 731         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 732         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 733         radeon_crtc->mode_set.num_connectors = 0;
 734 #endif
 735
 736         for (i = 0; i < 256; i++) {
 737                 radeon_crtc->lut_r[i] = i << 2;
 738                 radeon_crtc->lut_g[i] = i << 2;
 739                 radeon_crtc->lut_b[i] = i << 2;
 740         }
 741
 742         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 743                 radeon_atombios_init_crtc(dev, radeon_crtc);
 744         else
 745                 radeon_legacy_init_crtc(dev, radeon_crtc);
 746 }
 747
 748 static const char *encoder_names[38] = {
 749         "NONE",
 750         "INTERNAL_LVDS",
 751         "INTERNAL_TMDS1",
 752         "INTERNAL_TMDS2",
 753         "INTERNAL_DAC1",
 754         "INTERNAL_DAC2",
 755         "INTERNAL_SDVOA",
 756         "INTERNAL_SDVOB",
 757         "SI170B",
 758         "CH7303",
 759         "CH7301",
 760         "INTERNAL_DVO1",
 761         "EXTERNAL_SDVOA",
 762         "EXTERNAL_SDVOB",
 763         "TITFP513",
 764         "INTERNAL_LVTM1",
 765         "VT1623",
 766         "HDMI_SI1930",
 767         "HDMI_INTERNAL",
 768         "INTERNAL_KLDSCP_TMDS1",
 769         "INTERNAL_KLDSCP_DVO1",
 770         "INTERNAL_KLDSCP_DAC1",
 771         "INTERNAL_KLDSCP_DAC2",
 772         "SI178",
 773         "MVPU_FPGA",
 774         "INTERNAL_DDI",
 775         "VT1625",
 776         "HDMI_SI1932",
 777         "DP_AN9801",
 778         "DP_DP501",
 779         "INTERNAL_UNIPHY",
 780         "INTERNAL_KLDSCP_LVTMA",
 781         "INTERNAL_UNIPHY1",
 782         "INTERNAL_UNIPHY2",
 783         "NUTMEG",
 784         "TRAVIS",
 785         "INTERNAL_VCE",
 786         "INTERNAL_UNIPHY3",
 787 };
 788
 789 static const char *hpd_names[6] = {
 790         "HPD1",
 791         "HPD2",
 792         "HPD3",
 793         "HPD4",
 794         "HPD5",
 795         "HPD6",
 796 };
 797
 798 static void radeon_print_display_setup(struct drm_device *dev)
 799 {
 800         struct drm_connector *connector;
 801         struct radeon_connector *radeon_connector;
 802         struct drm_encoder *encoder;
 803         struct radeon_encoder *radeon_encoder;
 804         uint32_t devices;
 805         int i = 0;
 806
 807         DRM_INFO("Radeon Display Connectors\n");
 808         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 809                 radeon_connector = to_radeon_connector(connector);
 810                 DRM_INFO("Connector %d:\n", i);
 811                 DRM_INFO("  %s\n", connector->name);
 812                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 813                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 814                 if (radeon_connector->ddc_bus) {
 815                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 816                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 817                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 818                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 819                                  radeon_connector->ddc_bus->rec.a_data_reg,
 820                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 821                                  radeon_connector->ddc_bus->rec.en_data_reg,
 822                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 823                                  radeon_connector->ddc_bus->rec.y_data_reg);
 824                         if (radeon_connector->router.ddc_valid)
 825                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 826                                          radeon_connector->router.ddc_mux_control_pin,
 827                                          radeon_connector->router.ddc_mux_state);
 828                         if (radeon_connector->router.cd_valid)
 829                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 830                                          radeon_connector->router.cd_mux_control_pin,
 831                                          radeon_connector->router.cd_mux_state);
 832                 } else {
 833                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 834                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 835                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 836                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 837                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 838                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 839                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 840                 }
 841                 DRM_INFO("  Encoders:\n");
 842                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 843                         radeon_encoder = to_radeon_encoder(encoder);
 844                         devices = radeon_encoder->devices & radeon_connector->devices;
 845                         if (devices) {
 846                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 847                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 848                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 849                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 850                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 851                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 852                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 853                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 854                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 855                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 856                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 857                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 858                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 859                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 860                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 861                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 862                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 863                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 864                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 865                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 866                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 867                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 868                         }
 869                 }
 870                 i++;
 871         }
 872 }
 873
 874 static bool radeon_setup_enc_conn(struct drm_device *dev)
 875 {
 876         struct radeon_device *rdev = dev->dev_private;
 877         bool ret = false;
 878
 879         if (rdev->bios) {
 880                 if (rdev->is_atom_bios) {
 881                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 882                         if (ret == false)
 883                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 884                 } else {
 885                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 886                         if (ret == false)
 887                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 888                 }
 889         } else {
 890                 if (!ASIC_IS_AVIVO(rdev))
 891                         ret = radeon_get_legacy_connector_info_from_table(dev);
 892         }
 893         if (ret) {
 894                 radeon_setup_encoder_clones(dev);
 895                 radeon_print_display_setup(dev);
 896         }
 897
 898         return ret;
 899 }
 900
 901 /* avivo */
 902
 903 /**
 904  * avivo_reduce_ratio - fractional number reduction
 905  *
 906  * @nom: nominator
 907  * @den: denominator
 908  * @nom_min: minimum value for nominator
 909  * @den_min: minimum value for denominator
 910  *
 911  * Find the greatest common divisor and apply it on both nominator and
 912  * denominator, but make nominator and denominator are at least as large
 913  * as their minimum values.
 914  */
 915 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
 916                                unsigned nom_min, unsigned den_min)
 917 {
 918         unsigned tmp;
 919
 920         /* reduce the numbers to a simpler ratio */
 921         tmp = gcd(*nom, *den);
 922         *nom /= tmp;
 923         *den /= tmp;
 924
 925         /* make sure nominator is large enough */
 926         if (*nom < nom_min) {
 927                 tmp = DIV_ROUND_UP(nom_min, *nom);
 928                 *nom *= tmp;
 929                 *den *= tmp;
 930         }
 931
 932         /* make sure the denominator is large enough */
 933         if (*den < den_min) {
 934                 tmp = DIV_ROUND_UP(den_min, *den);
 935                 *nom *= tmp;
 936                 *den *= tmp;
 937         }
 938 }
 939
 940 /**
 941  * avivo_get_fb_ref_div - feedback and ref divider calculation
 942  *
 943  * @nom: nominator
 944  * @den: denominator
 945  * @post_div: post divider
 946  * @fb_div_max: feedback divider maximum
 947  * @ref_div_max: reference divider maximum
 948  * @fb_div: resulting feedback divider
 949  * @ref_div: resulting reference divider
 950  *
 951  * Calculate feedback and reference divider for a given post divider. Makes
 952  * sure we stay within the limits.
 953  */
 954 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
 955                                  unsigned fb_div_max, unsigned ref_div_max,
 956                                  unsigned *fb_div, unsigned *ref_div)
 957 {
 958         /* limit reference * post divider to a maximum */
 959         ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
 960
 961         /* get matching reference and feedback divider */
 962         *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
 963         *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
 964
 965         /* limit fb divider to its maximum */
 966         if (*fb_div > fb_div_max) {
 967                 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
 968                 *fb_div = fb_div_max;
 969         }
 970 }
 971
 972 /**
 973  * radeon_compute_pll_avivo - compute PLL paramaters
 974  *
 975  * @pll: information about the PLL
 976  * @dot_clock_p: resulting pixel clock
 977  * fb_div_p: resulting feedback divider
 978  * frac_fb_div_p: fractional part of the feedback divider
 979  * ref_div_p: resulting reference divider
 980  * post_div_p: resulting reference divider
 981  *
 982  * Try to calculate the PLL parameters to generate the given frequency:
 983  * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
 984  */
 985 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 986                               u32 freq,
 987                               u32 *dot_clock_p,
 988                               u32 *fb_div_p,
 989                               u32 *frac_fb_div_p,
 990                               u32 *ref_div_p,
 991                               u32 *post_div_p)
 992 {
 993         unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
 994                 freq : freq / 10;
 995
 996         unsigned fb_div_min, fb_div_max, fb_div;
 997         unsigned post_div_min, post_div_max, post_div;
 998         unsigned ref_div_min, ref_div_max, ref_div;
 999         unsigned post_div_best, diff_best;
1000         unsigned nom, den;
1001
1002         /* determine allowed feedback divider range */
1003         fb_div_min = pll->min_feedback_div;
1004         fb_div_max = pll->max_feedback_div;
1005
1006         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1007                 fb_div_min *= 10;
1008                 fb_div_max *= 10;
1009         }
1010
1011         /* determine allowed ref divider range */
1012         if (pll->flags & RADEON_PLL_USE_REF_DIV)
1013                 ref_div_min = pll->reference_div;
1014         else
1015                 ref_div_min = pll->min_ref_div;
1016
1017         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
1018             pll->flags & RADEON_PLL_USE_REF_DIV)
1019                 ref_div_max = pll->reference_div;
1020         else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1021                 /* fix for problems on RS880 */
1022                 ref_div_max = min(pll->max_ref_div, 7u);
1023         else
1024                 ref_div_max = pll->max_ref_div;
1025
1026         /* determine allowed post divider range */
1027         if (pll->flags & RADEON_PLL_USE_POST_DIV) {
1028                 post_div_min = pll->post_div;
1029                 post_div_max = pll->post_div;
1030         } else {
1031                 unsigned vco_min, vco_max;
1032
1033                 if (pll->flags & RADEON_PLL_IS_LCD) {
1034                         vco_min = pll->lcd_pll_out_min;
1035                         vco_max = pll->lcd_pll_out_max;
1036                 } else {
1037                         vco_min = pll->pll_out_min;
1038                         vco_max = pll->pll_out_max;
1039                 }
1040
1041                 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1042                         vco_min *= 10;
1043                         vco_max *= 10;
1044                 }
1045
1046                 post_div_min = vco_min / target_clock;
1047                 if ((target_clock * post_div_min) < vco_min)
1048                         ++post_div_min;
1049                 if (post_div_min < pll->min_post_div)
1050                         post_div_min = pll->min_post_div;
1051
1052                 post_div_max = vco_max / target_clock;
1053                 if ((target_clock * post_div_max) > vco_max)
1054                         --post_div_max;
1055                 if (post_div_max > pll->max_post_div)
1056                         post_div_max = pll->max_post_div;
1057         }
1058
1059         /* represent the searched ratio as fractional number */
1060         nom = target_clock;
1061         den = pll->reference_freq;
1062
1063         /* reduce the numbers to a simpler ratio */
1064         avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1065
1066         /* now search for a post divider */
1067         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1068                 post_div_best = post_div_min;
1069         else
1070                 post_div_best = post_div_max;
1071         diff_best = ~0;
1072
1073         for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1074                 unsigned diff;
1075                 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1076                                      ref_div_max, &fb_div, &ref_div);
1077                 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1078                         (ref_div * post_div));
1079
1080                 if (diff < diff_best || (diff == diff_best &&
1081                     !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1082
1083                         post_div_best = post_div;
1084                         diff_best = diff;
1085                 }
1086         }
1087         post_div = post_div_best;
1088
1089         /* get the feedback and reference divider for the optimal value */
1090         avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1091                              &fb_div, &ref_div);
1092
1093         /* reduce the numbers to a simpler ratio once more */
1094         /* this also makes sure that the reference divider is large enough */
1095         avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1096
1097         /* avoid high jitter with small fractional dividers */
1098         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1099                 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1100                 if (fb_div < fb_div_min) {
1101                         unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1102                         fb_div *= tmp;
1103                         ref_div *= tmp;
1104                 }
1105         }
1106
1107         /* and finally save the result */
1108         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1109                 *fb_div_p = fb_div / 10;
1110                 *frac_fb_div_p = fb_div % 10;
1111         } else {
1112                 *fb_div_p = fb_div;
1113                 *frac_fb_div_p = 0;
1114         }
1115
1116         *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1117                         (pll->reference_freq * *frac_fb_div_p)) /
1118                        (ref_div * post_div * 10);
1119         *ref_div_p = ref_div;
1120         *post_div_p = post_div;
1121
1122         DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1123                       freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1124                       ref_div, post_div);
1125 }
1126
1127 /* pre-avivo */
1128 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1129 {
1130         uint64_t mod;
1131
1132         n += d / 2;
1133
1134         mod = do_div(n, d);
1135         return n;
1136 }
1137
1138 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1139                                uint64_t freq,
1140                                uint32_t *dot_clock_p,
1141                                uint32_t *fb_div_p,
1142                                uint32_t *frac_fb_div_p,
1143                                uint32_t *ref_div_p,
1144                                uint32_t *post_div_p)
1145 {
1146         uint32_t min_ref_div = pll->min_ref_div;
1147         uint32_t max_ref_div = pll->max_ref_div;
1148         uint32_t min_post_div = pll->min_post_div;
1149         uint32_t max_post_div = pll->max_post_div;
1150         uint32_t min_fractional_feed_div = 0;
1151         uint32_t max_fractional_feed_div = 0;
1152         uint32_t best_vco = pll->best_vco;
1153         uint32_t best_post_div = 1;
1154         uint32_t best_ref_div = 1;
1155         uint32_t best_feedback_div = 1;
1156         uint32_t best_frac_feedback_div = 0;
1157         uint32_t best_freq = -1;
1158         uint32_t best_error = 0xffffffff;
1159         uint32_t best_vco_diff = 1;
1160         uint32_t post_div;
1161         u32 pll_out_min, pll_out_max;
1162
1163         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1164         freq = freq * 1000;
1165
1166         if (pll->flags & RADEON_PLL_IS_LCD) {
1167                 pll_out_min = pll->lcd_pll_out_min;
1168                 pll_out_max = pll->lcd_pll_out_max;
1169         } else {
1170                 pll_out_min = pll->pll_out_min;
1171                 pll_out_max = pll->pll_out_max;
1172         }
1173
1174         if (pll_out_min > 64800)
1175                 pll_out_min = 64800;
1176
1177         if (pll->flags & RADEON_PLL_USE_REF_DIV)
1178                 min_ref_div = max_ref_div = pll->reference_div;
1179         else {
1180                 while (min_ref_div < max_ref_div-1) {
1181                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
1182                         uint32_t pll_in = pll->reference_freq / mid;
1183                         if (pll_in < pll->pll_in_min)
1184                                 max_ref_div = mid;
1185                         else if (pll_in > pll->pll_in_max)
1186                                 min_ref_div = mid;
1187                         else
1188                                 break;
1189                 }
1190         }
1191
1192         if (pll->flags & RADEON_PLL_USE_POST_DIV)
1193                 min_post_div = max_post_div = pll->post_div;
1194
1195         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1196                 min_fractional_feed_div = pll->min_frac_feedback_div;
1197                 max_fractional_feed_div = pll->max_frac_feedback_div;
1198         }
1199
1200         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1201                 uint32_t ref_div;
1202
1203                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1204                         continue;
1205
1206                 /* legacy radeons only have a few post_divs */
1207                 if (pll->flags & RADEON_PLL_LEGACY) {
1208                         if ((post_div == 5) ||
1209                             (post_div == 7) ||
1210                             (post_div == 9) ||
1211                             (post_div == 10) ||
1212                             (post_div == 11) ||
1213                             (post_div == 13) ||
1214                             (post_div == 14) ||
1215                             (post_div == 15))
1216                                 continue;
1217                 }
1218
1219                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1220                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
1221                         uint32_t pll_in = pll->reference_freq / ref_div;
1222                         uint32_t min_feed_div = pll->min_feedback_div;
1223                         uint32_t max_feed_div = pll->max_feedback_div + 1;
1224
1225                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1226                                 continue;
1227
1228                         while (min_feed_div < max_feed_div) {
1229                                 uint32_t vco;
1230                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
1231                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1232                                 uint32_t frac_feedback_div;
1233                                 uint64_t tmp;
1234
1235                                 feedback_div = (min_feed_div + max_feed_div) / 2;
1236
1237                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
1238                                 vco = radeon_div(tmp, ref_div);
1239
1240                                 if (vco < pll_out_min) {
1241                                         min_feed_div = feedback_div + 1;
1242                                         continue;
1243                                 } else if (vco > pll_out_max) {
1244                                         max_feed_div = feedback_div;
1245                                         continue;
1246                                 }
1247
1248                                 while (min_frac_feed_div < max_frac_feed_div) {
1249                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1250                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1251                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1252                                         current_freq = radeon_div(tmp, ref_div * post_div);
1253
1254                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1255                                                 if (freq < current_freq)
1256                                                         error = 0xffffffff;
1257                                                 else
1258                                                         error = freq - current_freq;
1259                                         } else
1260                                                 error = abs(current_freq - freq);
1261                                         vco_diff = abs(vco - best_vco);
1262
1263                                         if ((best_vco == 0 && error < best_error) ||
1264                                             (best_vco != 0 &&
1265                                              ((best_error > 100 && error < best_error - 100) ||
1266                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1267                                                 best_post_div = post_div;
1268                                                 best_ref_div = ref_div;
1269                                                 best_feedback_div = feedback_div;
1270                                                 best_frac_feedback_div = frac_feedback_div;
1271                                                 best_freq = current_freq;
1272                                                 best_error = error;
1273                                                 best_vco_diff = vco_diff;
1274                                         } else if (current_freq == freq) {
1275                                                 if (best_freq == -1) {
1276                                                         best_post_div = post_div;
1277                                                         best_ref_div = ref_div;
1278                                                         best_feedback_div = feedback_div;
1279                                                         best_frac_feedback_div = frac_feedback_div;
1280                                                         best_freq = current_freq;
1281                                                         best_error = error;
1282                                                         best_vco_diff = vco_diff;
1283                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1284                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1285                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1286                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1287                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1288                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1289                                                         best_post_div = post_div;
1290                                                         best_ref_div = ref_div;
1291                                                         best_feedback_div = feedback_div;
1292                                                         best_frac_feedback_div = frac_feedback_div;
1293                                                         best_freq = current_freq;
1294                                                         best_error = error;
1295                                                         best_vco_diff = vco_diff;
1296                                                 }
1297                                         }
1298                                         if (current_freq < freq)
1299                                                 min_frac_feed_div = frac_feedback_div + 1;
1300                                         else
1301                                                 max_frac_feed_div = frac_feedback_div;
1302                                 }
1303                                 if (current_freq < freq)
1304                                         min_feed_div = feedback_div + 1;
1305                                 else
1306                                         max_feed_div = feedback_div;
1307                         }
1308                 }
1309         }
1310
1311         *dot_clock_p = best_freq / 10000;
1312         *fb_div_p = best_feedback_div;
1313         *frac_fb_div_p = best_frac_feedback_div;
1314         *ref_div_p = best_ref_div;
1315         *post_div_p = best_post_div;
1316         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1317                       (long long)freq,
1318                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1319                       best_ref_div, best_post_div);
1320
1321 }
1322
1323 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1324 {
1325         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1326
1327         if (radeon_fb->obj) {
1328                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1329         }
1330         drm_framebuffer_cleanup(fb);
1331         kfree(radeon_fb);
1332 }
1333
1334 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1335                                                   struct drm_file *file_priv,
1336                                                   unsigned int *handle)
1337 {
1338         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1339
1340         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1341 }
1342
1343 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1344         .destroy = radeon_user_framebuffer_destroy,
1345         .create_handle = radeon_user_framebuffer_create_handle,
1346 };
1347
1348 int
1349 radeon_framebuffer_init(struct drm_device *dev,
1350                         struct radeon_framebuffer *rfb,
1351                         const struct drm_mode_fb_cmd2 *mode_cmd,
1352                         struct drm_gem_object *obj)
1353 {
1354         int ret;
1355         rfb->obj = obj;
1356         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1357         ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1358         if (ret) {
1359                 rfb->obj = NULL;
1360                 return ret;
1361         }
1362         return 0;
1363 }
1364
1365 static struct drm_framebuffer *
1366 radeon_user_framebuffer_create(struct drm_device *dev,
1367                                struct drm_file *file_priv,
1368                                const struct drm_mode_fb_cmd2 *mode_cmd)
1369 {
1370         struct drm_gem_object *obj;
1371         struct radeon_framebuffer *radeon_fb;
1372         int ret;
1373
1374         obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1375         if (obj ==  NULL) {
1376                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1377                         "can't create framebuffer\n", mode_cmd->handles[0]);
1378                 return ERR_PTR(-ENOENT);
1379         }
1380
1381         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1382         if (radeon_fb == NULL) {
1383                 drm_gem_object_unreference_unlocked(obj);
1384                 return ERR_PTR(-ENOMEM);
1385         }
1386
1387         ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1388         if (ret) {
1389                 kfree(radeon_fb);
1390                 drm_gem_object_unreference_unlocked(obj);
1391                 return ERR_PTR(ret);
1392         }
1393
1394         return &radeon_fb->base;
1395 }
1396
1397 static void radeon_output_poll_changed(struct drm_device *dev)
1398 {
1399         struct radeon_device *rdev = dev->dev_private;
1400         radeon_fb_output_poll_changed(rdev);
1401 }
1402
1403 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1404         .fb_create = radeon_user_framebuffer_create,
1405         .output_poll_changed = radeon_output_poll_changed
1406 };
1407
1408 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1409 {       { 0, "driver" },
1410         { 1, "bios" },
1411 };
1412
1413 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1414 {       { TV_STD_NTSC, "ntsc" },
1415         { TV_STD_PAL, "pal" },
1416         { TV_STD_PAL_M, "pal-m" },
1417         { TV_STD_PAL_60, "pal-60" },
1418         { TV_STD_NTSC_J, "ntsc-j" },
1419         { TV_STD_SCART_PAL, "scart-pal" },
1420         { TV_STD_PAL_CN, "pal-cn" },
1421         { TV_STD_SECAM, "secam" },
1422 };
1423
1424 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1425 {       { UNDERSCAN_OFF, "off" },
1426         { UNDERSCAN_ON, "on" },
1427         { UNDERSCAN_AUTO, "auto" },
1428 };
1429
1430 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1431 {       { RADEON_AUDIO_DISABLE, "off" },
1432         { RADEON_AUDIO_ENABLE, "on" },
1433         { RADEON_AUDIO_AUTO, "auto" },
1434 };
1435
1436 /* XXX support different dither options? spatial, temporal, both, etc. */
1437 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1438 {       { RADEON_FMT_DITHER_DISABLE, "off" },
1439         { RADEON_FMT_DITHER_ENABLE, "on" },
1440 };
1441
1442 static struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1443 {       { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1444         { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1445         { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1446         { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1447 };
1448
1449 static int radeon_modeset_create_props(struct radeon_device *rdev)
1450 {
1451         int sz;
1452
1453         if (rdev->is_atom_bios) {
1454                 rdev->mode_info.coherent_mode_property =
1455                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1456                 if (!rdev->mode_info.coherent_mode_property)
1457                         return -ENOMEM;
1458         }
1459
1460         if (!ASIC_IS_AVIVO(rdev)) {
1461                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1462                 rdev->mode_info.tmds_pll_property =
1463                         drm_property_create_enum(rdev->ddev, 0,
1464                                             "tmds_pll",
1465                                             radeon_tmds_pll_enum_list, sz);
1466         }
1467
1468         rdev->mode_info.load_detect_property =
1469                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1470         if (!rdev->mode_info.load_detect_property)
1471                 return -ENOMEM;
1472
1473         drm_mode_create_scaling_mode_property(rdev->ddev);
1474
1475         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1476         rdev->mode_info.tv_std_property =
1477                 drm_property_create_enum(rdev->ddev, 0,
1478                                     "tv standard",
1479                                     radeon_tv_std_enum_list, sz);
1480
1481         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1482         rdev->mode_info.underscan_property =
1483                 drm_property_create_enum(rdev->ddev, 0,
1484                                     "underscan",
1485                                     radeon_underscan_enum_list, sz);
1486
1487         rdev->mode_info.underscan_hborder_property =
1488                 drm_property_create_range(rdev->ddev, 0,
1489                                         "underscan hborder", 0, 128);
1490         if (!rdev->mode_info.underscan_hborder_property)
1491                 return -ENOMEM;
1492
1493         rdev->mode_info.underscan_vborder_property =
1494                 drm_property_create_range(rdev->ddev, 0,
1495                                         "underscan vborder", 0, 128);
1496         if (!rdev->mode_info.underscan_vborder_property)
1497                 return -ENOMEM;
1498
1499         sz = ARRAY_SIZE(radeon_audio_enum_list);
1500         rdev->mode_info.audio_property =
1501                 drm_property_create_enum(rdev->ddev, 0,
1502                                          "audio",
1503                                          radeon_audio_enum_list, sz);
1504
1505         sz = ARRAY_SIZE(radeon_dither_enum_list);
1506         rdev->mode_info.dither_property =
1507                 drm_property_create_enum(rdev->ddev, 0,
1508                                          "dither",
1509                                          radeon_dither_enum_list, sz);
1510
1511         sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1512         rdev->mode_info.output_csc_property =
1513                 drm_property_create_enum(rdev->ddev, 0,
1514                                          "output_csc",
1515                                          radeon_output_csc_enum_list, sz);
1516
1517         return 0;
1518 }
1519
1520 void radeon_update_display_priority(struct radeon_device *rdev)
1521 {
1522         /* adjustment options for the display watermarks */
1523         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1524                 /* set display priority to high for r3xx, rv515 chips
1525                  * this avoids flickering due to underflow to the
1526                  * display controllers during heavy acceleration.
1527                  * Don't force high on rs4xx igp chips as it seems to
1528                  * affect the sound card.  See kernel bug 15982.
1529                  */
1530                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1531                     !(rdev->flags & RADEON_IS_IGP))
1532                         rdev->disp_priority = 2;
1533                 else
1534                         rdev->disp_priority = 0;
1535         } else
1536                 rdev->disp_priority = radeon_disp_priority;
1537
1538 }
1539
1540 /*
1541  * Allocate hdmi structs and determine register offsets
1542  */
1543 static void radeon_afmt_init(struct radeon_device *rdev)
1544 {
1545         int i;
1546
1547         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1548                 rdev->mode_info.afmt[i] = NULL;
1549
1550         if (ASIC_IS_NODCE(rdev)) {
1551                 /* nothing to do */
1552         } else if (ASIC_IS_DCE4(rdev)) {
1553                 static uint32_t eg_offsets[] = {
1554                         EVERGREEN_CRTC0_REGISTER_OFFSET,
1555                         EVERGREEN_CRTC1_REGISTER_OFFSET,
1556                         EVERGREEN_CRTC2_REGISTER_OFFSET,
1557                         EVERGREEN_CRTC3_REGISTER_OFFSET,
1558                         EVERGREEN_CRTC4_REGISTER_OFFSET,
1559                         EVERGREEN_CRTC5_REGISTER_OFFSET,
1560                         0x13830 - 0x7030,
1561                 };
1562                 int num_afmt;
1563
1564                 /* DCE8 has 7 audio blocks tied to DIG encoders */
1565                 /* DCE6 has 6 audio blocks tied to DIG encoders */
1566                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1567                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1568                 if (ASIC_IS_DCE8(rdev))
1569                         num_afmt = 7;
1570                 else if (ASIC_IS_DCE6(rdev))
1571                         num_afmt = 6;
1572                 else if (ASIC_IS_DCE5(rdev))
1573                         num_afmt = 6;
1574                 else if (ASIC_IS_DCE41(rdev))
1575                         num_afmt = 2;
1576                 else /* DCE4 */
1577                         num_afmt = 6;
1578
1579                 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1580                 for (i = 0; i < num_afmt; i++) {
1581                         rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1582                         if (rdev->mode_info.afmt[i]) {
1583                                 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1584                                 rdev->mode_info.afmt[i]->id = i;
1585                         }
1586                 }
1587         } else if (ASIC_IS_DCE3(rdev)) {
1588                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1589                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1590                 if (rdev->mode_info.afmt[0]) {
1591                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1592                         rdev->mode_info.afmt[0]->id = 0;
1593                 }
1594                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1595                 if (rdev->mode_info.afmt[1]) {
1596                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1597                         rdev->mode_info.afmt[1]->id = 1;
1598                 }
1599         } else if (ASIC_IS_DCE2(rdev)) {
1600                 /* DCE2 has at least 1 routable audio block */
1601                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1602                 if (rdev->mode_info.afmt[0]) {
1603                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1604                         rdev->mode_info.afmt[0]->id = 0;
1605                 }
1606                 /* r6xx has 2 routable audio blocks */
1607                 if (rdev->family >= CHIP_R600) {
1608                         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1609                         if (rdev->mode_info.afmt[1]) {
1610                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1611                                 rdev->mode_info.afmt[1]->id = 1;
1612                         }
1613                 }
1614         }
1615 }
1616
1617 static void radeon_afmt_fini(struct radeon_device *rdev)
1618 {
1619         int i;
1620
1621         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1622                 kfree(rdev->mode_info.afmt[i]);
1623                 rdev->mode_info.afmt[i] = NULL;
1624         }
1625 }
1626
1627 int radeon_modeset_init(struct radeon_device *rdev)
1628 {
1629         int i;
1630         int ret;
1631
1632         drm_mode_config_init(rdev->ddev);
1633         rdev->mode_info.mode_config_initialized = true;
1634
1635         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1636
1637         if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1638                 rdev->ddev->mode_config.async_page_flip = true;
1639
1640         if (ASIC_IS_DCE5(rdev)) {
1641                 rdev->ddev->mode_config.max_width = 16384;
1642                 rdev->ddev->mode_config.max_height = 16384;
1643         } else if (ASIC_IS_AVIVO(rdev)) {
1644                 rdev->ddev->mode_config.max_width = 8192;
1645                 rdev->ddev->mode_config.max_height = 8192;
1646         } else {
1647                 rdev->ddev->mode_config.max_width = 4096;
1648                 rdev->ddev->mode_config.max_height = 4096;
1649         }
1650
1651         rdev->ddev->mode_config.preferred_depth = 24;
1652         rdev->ddev->mode_config.prefer_shadow = 1;
1653
1654         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1655
1656         ret = radeon_modeset_create_props(rdev);
1657         if (ret) {
1658                 return ret;
1659         }
1660
1661         /* init i2c buses */
1662         radeon_i2c_init(rdev);
1663
1664         /* check combios for a valid hardcoded EDID - Sun servers */
1665         if (!rdev->is_atom_bios) {
1666                 /* check for hardcoded EDID in BIOS */
1667                 radeon_combios_check_hardcoded_edid(rdev);
1668         }
1669
1670         /* allocate crtcs */
1671         for (i = 0; i < rdev->num_crtc; i++) {
1672                 radeon_crtc_init(rdev->ddev, i);
1673         }
1674
1675         /* okay we should have all the bios connectors */
1676         ret = radeon_setup_enc_conn(rdev->ddev);
1677         if (!ret) {
1678                 return ret;
1679         }
1680
1681         /* init dig PHYs, disp eng pll */
1682         if (rdev->is_atom_bios) {
1683                 radeon_atom_encoder_init(rdev);
1684                 radeon_atom_disp_eng_pll_init(rdev);
1685         }
1686
1687         /* initialize hpd */
1688         radeon_hpd_init(rdev);
1689
1690         /* setup afmt */
1691         radeon_afmt_init(rdev);
1692
1693         radeon_fbdev_init(rdev);
1694         drm_kms_helper_poll_init(rdev->ddev);
1695
1696         /* do pm late init */
1697         ret = radeon_pm_late_init(rdev);
1698
1699         return 0;
1700 }
1701
1702 void radeon_modeset_fini(struct radeon_device *rdev)
1703 {
1704         radeon_fbdev_fini(rdev);
1705         kfree(rdev->mode_info.bios_hardcoded_edid);
1706
1707         /* free i2c buses */
1708         radeon_i2c_fini(rdev);
1709
1710         if (rdev->mode_info.mode_config_initialized) {
1711                 radeon_afmt_fini(rdev);
1712                 drm_kms_helper_poll_fini(rdev->ddev);
1713                 radeon_hpd_fini(rdev);
1714                 drm_crtc_force_disable_all(rdev->ddev);
1715                 drm_mode_config_cleanup(rdev->ddev);
1716                 rdev->mode_info.mode_config_initialized = false;
1717         }
1718 }
1719
1720 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1721 {
1722         /* try and guess if this is a tv or a monitor */
1723         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1724             (mode->vdisplay == 576) || /* 576p */
1725             (mode->vdisplay == 720) || /* 720p */
1726             (mode->vdisplay == 1080)) /* 1080p */
1727                 return true;
1728         else
1729                 return false;
1730 }
1731
1732 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1733                                 const struct drm_display_mode *mode,
1734                                 struct drm_display_mode *adjusted_mode)
1735 {
1736         struct drm_device *dev = crtc->dev;
1737         struct radeon_device *rdev = dev->dev_private;
1738         struct drm_encoder *encoder;
1739         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1740         struct radeon_encoder *radeon_encoder;
1741         struct drm_connector *connector;
1742         struct radeon_connector *radeon_connector;
1743         bool first = true;
1744         u32 src_v = 1, dst_v = 1;
1745         u32 src_h = 1, dst_h = 1;
1746
1747         radeon_crtc->h_border = 0;
1748         radeon_crtc->v_border = 0;
1749
1750         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1751                 if (encoder->crtc != crtc)
1752                         continue;
1753                 radeon_encoder = to_radeon_encoder(encoder);
1754                 connector = radeon_get_connector_for_encoder(encoder);
1755                 radeon_connector = to_radeon_connector(connector);
1756
1757                 if (first) {
1758                         /* set scaling */
1759                         if (radeon_encoder->rmx_type == RMX_OFF)
1760                                 radeon_crtc->rmx_type = RMX_OFF;
1761                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1762                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1763                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1764                         else
1765                                 radeon_crtc->rmx_type = RMX_OFF;
1766                         /* copy native mode */
1767                         memcpy(&radeon_crtc->native_mode,
1768                                &radeon_encoder->native_mode,
1769                                 sizeof(struct drm_display_mode));
1770                         src_v = crtc->mode.vdisplay;
1771                         dst_v = radeon_crtc->native_mode.vdisplay;
1772                         src_h = crtc->mode.hdisplay;
1773                         dst_h = radeon_crtc->native_mode.hdisplay;
1774
1775                         /* fix up for overscan on hdmi */
1776                         if (ASIC_IS_AVIVO(rdev) &&
1777                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1778                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1779                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1780                               drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1781                               is_hdtv_mode(mode)))) {
1782                                 if (radeon_encoder->underscan_hborder != 0)
1783                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1784                                 else
1785                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1786                                 if (radeon_encoder->underscan_vborder != 0)
1787                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1788                                 else
1789                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1790                                 radeon_crtc->rmx_type = RMX_FULL;
1791                                 src_v = crtc->mode.vdisplay;
1792                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1793                                 src_h = crtc->mode.hdisplay;
1794                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1795                         }
1796                         first = false;
1797                 } else {
1798                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1799                                 /* WARNING: Right now this can't happen but
1800                                  * in the future we need to check that scaling
1801                                  * are consistent across different encoder
1802                                  * (ie all encoder can work with the same
1803                                  *  scaling).
1804                                  */
1805                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1806                                 return false;
1807                         }
1808                 }
1809         }
1810         if (radeon_crtc->rmx_type != RMX_OFF) {
1811                 fixed20_12 a, b;
1812                 a.full = dfixed_const(src_v);
1813                 b.full = dfixed_const(dst_v);
1814                 radeon_crtc->vsc.full = dfixed_div(a, b);
1815                 a.full = dfixed_const(src_h);
1816                 b.full = dfixed_const(dst_h);
1817                 radeon_crtc->hsc.full = dfixed_div(a, b);
1818         } else {
1819                 radeon_crtc->vsc.full = dfixed_const(1);
1820                 radeon_crtc->hsc.full = dfixed_const(1);
1821         }
1822         return true;
1823 }
1824
1825 /*
1826  * Retrieve current video scanout position of crtc on a given gpu, and
1827  * an optional accurate timestamp of when query happened.
1828  *
1829  * \param dev Device to query.
1830  * \param crtc Crtc to query.
1831  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1832  *              For driver internal use only also supports these flags:
1833  *
1834  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
1835  *              of a fudged earlier start of vblank.
1836  *
1837  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
1838  *              fudged earlier start of vblank in *vpos and the distance
1839  *              to true start of vblank in *hpos.
1840  *
1841  * \param *vpos Location where vertical scanout position should be stored.
1842  * \param *hpos Location where horizontal scanout position should go.
1843  * \param *stime Target location for timestamp taken immediately before
1844  *               scanout position query. Can be NULL to skip timestamp.
1845  * \param *etime Target location for timestamp taken immediately after
1846  *               scanout position query. Can be NULL to skip timestamp.
1847  *
1848  * Returns vpos as a positive number while in active scanout area.
1849  * Returns vpos as a negative number inside vblank, counting the number
1850  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1851  * until start of active scanout / end of vblank."
1852  *
1853  * \return Flags, or'ed together as follows:
1854  *
1855  * DRM_SCANOUTPOS_VALID = Query successful.
1856  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1857  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1858  * this flag means that returned position may be offset by a constant but
1859  * unknown small number of scanlines wrt. real scanout position.
1860  *
1861  */
1862 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1863                                unsigned int flags, int *vpos, int *hpos,
1864                                ktime_t *stime, ktime_t *etime,
1865                                const struct drm_display_mode *mode)
1866 {
1867         u32 stat_crtc = 0, vbl = 0, position = 0;
1868         int vbl_start, vbl_end, vtotal, ret = 0;
1869         bool in_vbl = true;
1870
1871         struct radeon_device *rdev = dev->dev_private;
1872
1873         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1874
1875         /* Get optional system timestamp before query. */
1876         if (stime)
1877                 *stime = ktime_get();
1878
1879         if (ASIC_IS_DCE4(rdev)) {
1880                 if (pipe == 0) {
1881                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1882                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1883                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1884                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1885                         ret |= DRM_SCANOUTPOS_VALID;
1886                 }
1887                 if (pipe == 1) {
1888                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1889                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1890                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1891                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1892                         ret |= DRM_SCANOUTPOS_VALID;
1893                 }
1894                 if (pipe == 2) {
1895                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1896                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1897                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1898                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1899                         ret |= DRM_SCANOUTPOS_VALID;
1900                 }
1901                 if (pipe == 3) {
1902                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1903                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1904                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1905                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1906                         ret |= DRM_SCANOUTPOS_VALID;
1907                 }
1908                 if (pipe == 4) {
1909                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1910                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1911                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1912                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1913                         ret |= DRM_SCANOUTPOS_VALID;
1914                 }
1915                 if (pipe == 5) {
1916                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1917                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1918                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1919                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1920                         ret |= DRM_SCANOUTPOS_VALID;
1921                 }
1922         } else if (ASIC_IS_AVIVO(rdev)) {
1923                 if (pipe == 0) {
1924                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1925                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1926                         ret |= DRM_SCANOUTPOS_VALID;
1927                 }
1928                 if (pipe == 1) {
1929                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1930                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1931                         ret |= DRM_SCANOUTPOS_VALID;
1932                 }
1933         } else {
1934                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1935                 if (pipe == 0) {
1936                         /* Assume vbl_end == 0, get vbl_start from
1937                          * upper 16 bits.
1938                          */
1939                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1940                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1941                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1942                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1943                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1944                         if (!(stat_crtc & 1))
1945                                 in_vbl = false;
1946
1947                         ret |= DRM_SCANOUTPOS_VALID;
1948                 }
1949                 if (pipe == 1) {
1950                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1951                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1952                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1953                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1954                         if (!(stat_crtc & 1))
1955                                 in_vbl = false;
1956
1957                         ret |= DRM_SCANOUTPOS_VALID;
1958                 }
1959         }
1960
1961         /* Get optional system timestamp after query. */
1962         if (etime)
1963                 *etime = ktime_get();
1964
1965         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1966
1967         /* Decode into vertical and horizontal scanout position. */
1968         *vpos = position & 0x1fff;
1969         *hpos = (position >> 16) & 0x1fff;
1970
1971         /* Valid vblank area boundaries from gpu retrieved? */
1972         if (vbl > 0) {
1973                 /* Yes: Decode. */
1974                 ret |= DRM_SCANOUTPOS_ACCURATE;
1975                 vbl_start = vbl & 0x1fff;
1976                 vbl_end = (vbl >> 16) & 0x1fff;
1977         }
1978         else {
1979                 /* No: Fake something reasonable which gives at least ok results. */
1980                 vbl_start = mode->crtc_vdisplay;
1981                 vbl_end = 0;
1982         }
1983
1984         /* Called from driver internal vblank counter query code? */
1985         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1986             /* Caller wants distance from real vbl_start in *hpos */
1987             *hpos = *vpos - vbl_start;
1988         }
1989
1990         /* Fudge vblank to start a few scanlines earlier to handle the
1991          * problem that vblank irqs fire a few scanlines before start
1992          * of vblank. Some driver internal callers need the true vblank
1993          * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1994          *
1995          * The cause of the "early" vblank irq is that the irq is triggered
1996          * by the line buffer logic when the line buffer read position enters
1997          * the vblank, whereas our crtc scanout position naturally lags the
1998          * line buffer read position.
1999          */
2000         if (!(flags & USE_REAL_VBLANKSTART))
2001                 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
2002
2003         /* Test scanout position against vblank region. */
2004         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
2005                 in_vbl = false;
2006
2007         /* In vblank? */
2008         if (in_vbl)
2009             ret |= DRM_SCANOUTPOS_IN_VBLANK;
2010
2011         /* Called from driver internal vblank counter query code? */
2012         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
2013                 /* Caller wants distance from fudged earlier vbl_start */
2014                 *vpos -= vbl_start;
2015                 return ret;
2016         }
2017
2018         /* Check if inside vblank area and apply corrective offsets:
2019          * vpos will then be >=0 in video scanout area, but negative
2020          * within vblank area, counting down the number of lines until
2021          * start of scanout.
2022          */
2023
2024         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
2025         if (in_vbl && (*vpos >= vbl_start)) {
2026                 vtotal = mode->crtc_vtotal;
2027                 *vpos = *vpos - vtotal;
2028         }
2029
2030         /* Correct for shifted end of vbl at vbl_end. */
2031         *vpos = *vpos - vbl_end;
2032
2033         return ret;
2034 }