drivers/gpu/drm/radeon/radeon_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
  39 {
  40         struct drm_device *dev = encoder->dev;
  41         struct radeon_device *rdev = dev->dev_private;
  42         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  43         struct drm_encoder *clone_encoder;
  44         uint32_t index_mask = 0;
  45         int count;
  46
  47         /* DIG routing gets problematic */
  48         if (rdev->family >= CHIP_R600)
  49                 return index_mask;
  50         /* LVDS/TV are too wacky */
  51         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
  52                 return index_mask;
  53         /* DVO requires 2x ppll clocks depending on tmds chip */
  54         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
  55                 return index_mask;
  56
  57         count = -1;
  58         list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
  59                 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
  60                 count++;
  61
  62                 if (clone_encoder == encoder)
  63                         continue;
  64                 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
  65                         continue;
  66                 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
  67                         continue;
  68                 else
  69                         index_mask |= (1 << count);
  70         }
  71         return index_mask;
  72 }
  73
  74 void radeon_setup_encoder_clones(struct drm_device *dev)
  75 {
  76         struct drm_encoder *encoder;
  77
  78         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  79                 encoder->possible_clones = radeon_encoder_clones(encoder);
  80         }
  81 }
  82
  83 uint32_t
  84 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
  85 {
  86         struct radeon_device *rdev = dev->dev_private;
  87         uint32_t ret = 0;
  88
  89         switch (supported_device) {
  90         case ATOM_DEVICE_CRT1_SUPPORT:
  91         case ATOM_DEVICE_TV1_SUPPORT:
  92         case ATOM_DEVICE_TV2_SUPPORT:
  93         case ATOM_DEVICE_CRT2_SUPPORT:
  94         case ATOM_DEVICE_CV_SUPPORT:
  95                 switch (dac) {
  96                 case 1: /* dac a */
  97                         if ((rdev->family == CHIP_RS300) ||
  98                             (rdev->family == CHIP_RS400) ||
  99                             (rdev->family == CHIP_RS480))
 100                                 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
 101                         else if (ASIC_IS_AVIVO(rdev))
 102                                 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
 103                         else
 104                                 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
 105                         break;
 106                 case 2: /* dac b */
 107                         if (ASIC_IS_AVIVO(rdev))
 108                                 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
 109                         else {
 110                                 /*if (rdev->family == CHIP_R200)
 111                                   ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 112                                   else*/
 113                                 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
 114                         }
 115                         break;
 116                 case 3: /* external dac */
 117                         if (ASIC_IS_AVIVO(rdev))
 118                                 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
 119                         else
 120                                 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 121                         break;
 122                 }
 123                 break;
 124         case ATOM_DEVICE_LCD1_SUPPORT:
 125                 if (ASIC_IS_AVIVO(rdev))
 126                         ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
 127                 else
 128                         ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
 129                 break;
 130         case ATOM_DEVICE_DFP1_SUPPORT:
 131                 if ((rdev->family == CHIP_RS300) ||
 132                     (rdev->family == CHIP_RS400) ||
 133                     (rdev->family == CHIP_RS480))
 134                         ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 135                 else if (ASIC_IS_AVIVO(rdev))
 136                         ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
 137                 else
 138                         ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
 139                 break;
 140         case ATOM_DEVICE_LCD2_SUPPORT:
 141         case ATOM_DEVICE_DFP2_SUPPORT:
 142                 if ((rdev->family == CHIP_RS600) ||
 143                     (rdev->family == CHIP_RS690) ||
 144                     (rdev->family == CHIP_RS740))
 145                         ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
 146                 else if (ASIC_IS_AVIVO(rdev))
 147                         ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
 148                 else
 149                         ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 150                 break;
 151         case ATOM_DEVICE_DFP3_SUPPORT:
 152                 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
 153                 break;
 154         }
 155
 156         return ret;
 157 }
 158
 159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
 160 {
 161         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 162         switch (radeon_encoder->encoder_id) {
 163         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 164         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 165         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 166         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 167         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 168         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 169         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 170         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 171         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 172         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 173         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 174                 return true;
 175         default:
 176                 return false;
 177         }
 178 }
 179 void
 180 radeon_link_encoder_connector(struct drm_device *dev)
 181 {
 182         struct drm_connector *connector;
 183         struct radeon_connector *radeon_connector;
 184         struct drm_encoder *encoder;
 185         struct radeon_encoder *radeon_encoder;
 186
 187         /* walk the list and link encoders to connectors */
 188         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 189                 radeon_connector = to_radeon_connector(connector);
 190                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 191                         radeon_encoder = to_radeon_encoder(encoder);
 192                         if (radeon_encoder->devices & radeon_connector->devices)
 193                                 drm_mode_connector_attach_encoder(connector, encoder);
 194                 }
 195         }
 196 }
 197
 198 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
 199 {
 200         struct drm_device *dev = encoder->dev;
 201         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 202         struct drm_connector *connector;
 203
 204         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 205                 if (connector->encoder == encoder) {
 206                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 207                         radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
 208                         DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
 209                                   radeon_encoder->active_device, radeon_encoder->devices,
 210                                   radeon_connector->devices, encoder->encoder_type);
 211                 }
 212         }
 213 }
 214
 215 struct drm_connector *
 216 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
 217 {
 218         struct drm_device *dev = encoder->dev;
 219         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 220         struct drm_connector *connector;
 221         struct radeon_connector *radeon_connector;
 222
 223         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 224                 radeon_connector = to_radeon_connector(connector);
 225                 if (radeon_encoder->active_device & radeon_connector->devices)
 226                         return connector;
 227         }
 228         return NULL;
 229 }
 230
 231 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
 232                              struct drm_display_mode *adjusted_mode)
 233 {
 234         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 235         struct drm_device *dev = encoder->dev;
 236         struct radeon_device *rdev = dev->dev_private;
 237         struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 238         unsigned hblank = native_mode->htotal - native_mode->hdisplay;
 239         unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
 240         unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
 241         unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
 242         unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
 243         unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
 244
 245         adjusted_mode->clock = native_mode->clock;
 246         adjusted_mode->flags = native_mode->flags;
 247
 248         if (ASIC_IS_AVIVO(rdev)) {
 249                 adjusted_mode->hdisplay = native_mode->hdisplay;
 250                 adjusted_mode->vdisplay = native_mode->vdisplay;
 251         }
 252
 253         adjusted_mode->htotal = native_mode->hdisplay + hblank;
 254         adjusted_mode->hsync_start = native_mode->hdisplay + hover;
 255         adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
 256
 257         adjusted_mode->vtotal = native_mode->vdisplay + vblank;
 258         adjusted_mode->vsync_start = native_mode->vdisplay + vover;
 259         adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
 260
 261         drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
 262
 263         if (ASIC_IS_AVIVO(rdev)) {
 264                 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
 265                 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
 266         }
 267
 268         adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
 269         adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
 270         adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
 271
 272         adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
 273         adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
 274         adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
 275
 276 }
 277
 278 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 279                                    struct drm_display_mode *mode,
 280                                    struct drm_display_mode *adjusted_mode)
 281 {
 282         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 283         struct drm_device *dev = encoder->dev;
 284         struct radeon_device *rdev = dev->dev_private;
 285
 286         /* set the active encoder to connector routing */
 287         radeon_encoder_set_active_device(encoder);
 288         drm_mode_set_crtcinfo(adjusted_mode, 0);
 289
 290         /* hw bug */
 291         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 292             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 293                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 294
 295         /* get the native mode for LVDS */
 296         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
 297                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 298
 299         /* get the native mode for TV */
 300         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 301                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 302                 if (tv_dac) {
 303                         if (tv_dac->tv_std == TV_STD_NTSC ||
 304                             tv_dac->tv_std == TV_STD_NTSC_J ||
 305                             tv_dac->tv_std == TV_STD_PAL_M)
 306                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 307                         else
 308                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 309                 }
 310         }
 311
 312         if (ASIC_IS_DCE3(rdev) &&
 313             (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
 314                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 315                 radeon_dp_set_link_config(connector, mode);
 316         }
 317
 318         return true;
 319 }
 320
 321 static void
 322 atombios_dac_setup(struct drm_encoder *encoder, int action)
 323 {
 324         struct drm_device *dev = encoder->dev;
 325         struct radeon_device *rdev = dev->dev_private;
 326         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 327         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 328         int index = 0;
 329         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 330
 331         memset(&args, 0, sizeof(args));
 332
 333         switch (radeon_encoder->encoder_id) {
 334         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 335         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 336                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 337                 break;
 338         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 339         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 340                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 341                 break;
 342         }
 343
 344         args.ucAction = action;
 345
 346         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 347                 args.ucDacStandard = ATOM_DAC1_PS2;
 348         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 349                 args.ucDacStandard = ATOM_DAC1_CV;
 350         else {
 351                 switch (dac_info->tv_std) {
 352                 case TV_STD_PAL:
 353                 case TV_STD_PAL_M:
 354                 case TV_STD_SCART_PAL:
 355                 case TV_STD_SECAM:
 356                 case TV_STD_PAL_CN:
 357                         args.ucDacStandard = ATOM_DAC1_PAL;
 358                         break;
 359                 case TV_STD_NTSC:
 360                 case TV_STD_NTSC_J:
 361                 case TV_STD_PAL_60:
 362                 default:
 363                         args.ucDacStandard = ATOM_DAC1_NTSC;
 364                         break;
 365                 }
 366         }
 367         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 368
 369         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 370
 371 }
 372
 373 static void
 374 atombios_tv_setup(struct drm_encoder *encoder, int action)
 375 {
 376         struct drm_device *dev = encoder->dev;
 377         struct radeon_device *rdev = dev->dev_private;
 378         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 379         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 380         int index = 0;
 381         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 382
 383         memset(&args, 0, sizeof(args));
 384
 385         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 386
 387         args.sTVEncoder.ucAction = action;
 388
 389         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 390                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 391         else {
 392                 switch (dac_info->tv_std) {
 393                 case TV_STD_NTSC:
 394                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 395                         break;
 396                 case TV_STD_PAL:
 397                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 398                         break;
 399                 case TV_STD_PAL_M:
 400                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 401                         break;
 402                 case TV_STD_PAL_60:
 403                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 404                         break;
 405                 case TV_STD_NTSC_J:
 406                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 407                         break;
 408                 case TV_STD_SCART_PAL:
 409                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 410                         break;
 411                 case TV_STD_SECAM:
 412                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 413                         break;
 414                 case TV_STD_PAL_CN:
 415                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 416                         break;
 417                 default:
 418                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 419                         break;
 420                 }
 421         }
 422
 423         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 424
 425         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 426
 427 }
 428
 429 void
 430 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
 431 {
 432         struct drm_device *dev = encoder->dev;
 433         struct radeon_device *rdev = dev->dev_private;
 434         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 435         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
 436         int index = 0;
 437
 438         memset(&args, 0, sizeof(args));
 439
 440         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 441
 442         args.sXTmdsEncoder.ucEnable = action;
 443
 444         if (radeon_encoder->pixel_clock > 165000)
 445                 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
 446
 447         /*if (pScrn->rgbBits == 8)*/
 448         args.sXTmdsEncoder.ucMisc |= (1 << 1);
 449
 450         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 451
 452 }
 453
 454 static void
 455 atombios_ddia_setup(struct drm_encoder *encoder, int action)
 456 {
 457         struct drm_device *dev = encoder->dev;
 458         struct radeon_device *rdev = dev->dev_private;
 459         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 460         DVO_ENCODER_CONTROL_PS_ALLOCATION args;
 461         int index = 0;
 462
 463         memset(&args, 0, sizeof(args));
 464
 465         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 466
 467         args.sDVOEncoder.ucAction = action;
 468         args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 469
 470         if (radeon_encoder->pixel_clock > 165000)
 471                 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
 472
 473         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 474
 475 }
 476
 477 union lvds_encoder_control {
 478         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 479         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 480 };
 481
 482 void
 483 atombios_digital_setup(struct drm_encoder *encoder, int action)
 484 {
 485         struct drm_device *dev = encoder->dev;
 486         struct radeon_device *rdev = dev->dev_private;
 487         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 488         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 489         union lvds_encoder_control args;
 490         int index = 0;
 491         int hdmi_detected = 0;
 492         uint8_t frev, crev;
 493
 494         if (!dig)
 495                 return;
 496
 497         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 498                 hdmi_detected = 1;
 499
 500         memset(&args, 0, sizeof(args));
 501
 502         switch (radeon_encoder->encoder_id) {
 503         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 504                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 505                 break;
 506         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 507         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 508                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 509                 break;
 510         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 511                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 512                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 513                 else
 514                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 515                 break;
 516         }
 517
 518         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 519                 return;
 520
 521         switch (frev) {
 522         case 1:
 523         case 2:
 524                 switch (crev) {
 525                 case 1:
 526                         args.v1.ucMisc = 0;
 527                         args.v1.ucAction = action;
 528                         if (hdmi_detected)
 529                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 530                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 531                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 532                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 533                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 534                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 535                                         args.v1.ucMisc |= (1 << 1);
 536                         } else {
 537                                 if (dig->linkb)
 538                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 539                                 if (radeon_encoder->pixel_clock > 165000)
 540                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 541                                 /*if (pScrn->rgbBits == 8) */
 542                                 args.v1.ucMisc |= (1 << 1);
 543                         }
 544                         break;
 545                 case 2:
 546                 case 3:
 547                         args.v2.ucMisc = 0;
 548                         args.v2.ucAction = action;
 549                         if (crev == 3) {
 550                                 if (dig->coherent_mode)
 551                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 552                         }
 553                         if (hdmi_detected)
 554                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 555                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 556                         args.v2.ucTruncate = 0;
 557                         args.v2.ucSpatial = 0;
 558                         args.v2.ucTemporal = 0;
 559                         args.v2.ucFRC = 0;
 560                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 561                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 562                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 563                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 564                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 565                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 566                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 567                                 }
 568                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 569                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 570                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 571                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 572                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 573                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 574                                 }
 575                         } else {
 576                                 if (dig->linkb)
 577                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 578                                 if (radeon_encoder->pixel_clock > 165000)
 579                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 580                         }
 581                         break;
 582                 default:
 583                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 584                         break;
 585                 }
 586                 break;
 587         default:
 588                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 589                 break;
 590         }
 591
 592         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 593 }
 594
 595 int
 596 atombios_get_encoder_mode(struct drm_encoder *encoder)
 597 {
 598         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 599         struct drm_device *dev = encoder->dev;
 600         struct radeon_device *rdev = dev->dev_private;
 601         struct drm_connector *connector;
 602         struct radeon_connector *radeon_connector;
 603         struct radeon_connector_atom_dig *dig_connector;
 604
 605         connector = radeon_get_connector_for_encoder(encoder);
 606         if (!connector) {
 607                 switch (radeon_encoder->encoder_id) {
 608                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 609                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 610                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 611                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 612                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 613                         return ATOM_ENCODER_MODE_DVI;
 614                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 615                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 616                 default:
 617                         return ATOM_ENCODER_MODE_CRT;
 618                 }
 619         }
 620         radeon_connector = to_radeon_connector(connector);
 621
 622         switch (connector->connector_type) {
 623         case DRM_MODE_CONNECTOR_DVII:
 624         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 625                 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
 626                         /* fix me */
 627                         if (ASIC_IS_DCE4(rdev))
 628                                 return ATOM_ENCODER_MODE_DVI;
 629                         else
 630                                 return ATOM_ENCODER_MODE_HDMI;
 631                 } else if (radeon_connector->use_digital)
 632                         return ATOM_ENCODER_MODE_DVI;
 633                 else
 634                         return ATOM_ENCODER_MODE_CRT;
 635                 break;
 636         case DRM_MODE_CONNECTOR_DVID:
 637         case DRM_MODE_CONNECTOR_HDMIA:
 638         default:
 639                 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
 640                         /* fix me */
 641                         if (ASIC_IS_DCE4(rdev))
 642                                 return ATOM_ENCODER_MODE_DVI;
 643                         else
 644                                 return ATOM_ENCODER_MODE_HDMI;
 645                 } else
 646                         return ATOM_ENCODER_MODE_DVI;
 647                 break;
 648         case DRM_MODE_CONNECTOR_LVDS:
 649                 return ATOM_ENCODER_MODE_LVDS;
 650                 break;
 651         case DRM_MODE_CONNECTOR_DisplayPort:
 652         case DRM_MODE_CONNECTOR_eDP:
 653                 dig_connector = radeon_connector->con_priv;
 654                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 655                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 656                         return ATOM_ENCODER_MODE_DP;
 657                 else if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
 658                         /* fix me */
 659                         if (ASIC_IS_DCE4(rdev))
 660                                 return ATOM_ENCODER_MODE_DVI;
 661                         else
 662                                 return ATOM_ENCODER_MODE_HDMI;
 663                 } else
 664                         return ATOM_ENCODER_MODE_DVI;
 665                 break;
 666         case DRM_MODE_CONNECTOR_DVIA:
 667         case DRM_MODE_CONNECTOR_VGA:
 668                 return ATOM_ENCODER_MODE_CRT;
 669                 break;
 670         case DRM_MODE_CONNECTOR_Composite:
 671         case DRM_MODE_CONNECTOR_SVIDEO:
 672         case DRM_MODE_CONNECTOR_9PinDIN:
 673                 /* fix me */
 674                 return ATOM_ENCODER_MODE_TV;
 675                 /*return ATOM_ENCODER_MODE_CV;*/
 676                 break;
 677         }
 678 }
 679
 680 /*
 681  * DIG Encoder/Transmitter Setup
 682  *
 683  * DCE 3.0/3.1
 684  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 685  * Supports up to 3 digital outputs
 686  * - 2 DIG encoder blocks.
 687  * DIG1 can drive UNIPHY link A or link B
 688  * DIG2 can drive UNIPHY link B or LVTMA
 689  *
 690  * DCE 3.2
 691  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 692  * Supports up to 5 digital outputs
 693  * - 2 DIG encoder blocks.
 694  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 695  *
 696  * DCE 4.0
 697  * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
 698  * Supports up to 6 digital outputs
 699  * - 6 DIG encoder blocks.
 700  * - DIG to PHY mapping is hardcoded
 701  * DIG1 drives UNIPHY0 link A, A+B
 702  * DIG2 drives UNIPHY0 link B
 703  * DIG3 drives UNIPHY1 link A, A+B
 704  * DIG4 drives UNIPHY1 link B
 705  * DIG5 drives UNIPHY2 link A, A+B
 706  * DIG6 drives UNIPHY2 link B
 707  *
 708  * Routing
 709  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 710  * Examples:
 711  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 712  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 713  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 714  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 715  */
 716
 717 union dig_encoder_control {
 718         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 719         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 720         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 721 };
 722
 723 void
 724 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 725 {
 726         struct drm_device *dev = encoder->dev;
 727         struct radeon_device *rdev = dev->dev_private;
 728         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 729         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 730         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 731         union dig_encoder_control args;
 732         int index = 0;
 733         uint8_t frev, crev;
 734         int dp_clock = 0;
 735         int dp_lane_count = 0;
 736
 737         if (connector) {
 738                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 739                 struct radeon_connector_atom_dig *dig_connector =
 740                         radeon_connector->con_priv;
 741
 742                 dp_clock = dig_connector->dp_clock;
 743                 dp_lane_count = dig_connector->dp_lane_count;
 744         }
 745
 746         /* no dig encoder assigned */
 747         if (dig->dig_encoder == -1)
 748                 return;
 749
 750         memset(&args, 0, sizeof(args));
 751
 752         if (ASIC_IS_DCE4(rdev))
 753                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 754         else {
 755                 if (dig->dig_encoder)
 756                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 757                 else
 758                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 759         }
 760
 761         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 762                 return;
 763
 764         args.v1.ucAction = action;
 765         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 766         args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 767
 768         if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
 769                 if (dp_clock == 270000)
 770                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 771                 args.v1.ucLaneNum = dp_lane_count;
 772         } else if (radeon_encoder->pixel_clock > 165000)
 773                 args.v1.ucLaneNum = 8;
 774         else
 775                 args.v1.ucLaneNum = 4;
 776
 777         if (ASIC_IS_DCE4(rdev)) {
 778                 args.v3.acConfig.ucDigSel = dig->dig_encoder;
 779                 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 780         } else {
 781                 switch (radeon_encoder->encoder_id) {
 782                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 783                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 784                         break;
 785                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 786                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 787                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 788                         break;
 789                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 790                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 791                         break;
 792                 }
 793                 if (dig->linkb)
 794                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 795                 else
 796                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 797         }
 798
 799         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 800
 801 }
 802
 803 union dig_transmitter_control {
 804         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 805         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 806         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 807 };
 808
 809 void
 810 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 811 {
 812         struct drm_device *dev = encoder->dev;
 813         struct radeon_device *rdev = dev->dev_private;
 814         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 815         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 816         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 817         union dig_transmitter_control args;
 818         int index = 0;
 819         uint8_t frev, crev;
 820         bool is_dp = false;
 821         int pll_id = 0;
 822         int dp_clock = 0;
 823         int dp_lane_count = 0;
 824         int connector_object_id = 0;
 825         int igp_lane_info = 0;
 826
 827         if (connector) {
 828                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 829                 struct radeon_connector_atom_dig *dig_connector =
 830                         radeon_connector->con_priv;
 831
 832                 dp_clock = dig_connector->dp_clock;
 833                 dp_lane_count = dig_connector->dp_lane_count;
 834                 connector_object_id =
 835                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 836                 igp_lane_info = dig_connector->igp_lane_info;
 837         }
 838
 839         /* no dig encoder assigned */
 840         if (dig->dig_encoder == -1)
 841                 return;
 842
 843         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
 844                 is_dp = true;
 845
 846         memset(&args, 0, sizeof(args));
 847
 848         switch (radeon_encoder->encoder_id) {
 849         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 850         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 851         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 852                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 853                 break;
 854         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 855                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
 856                 break;
 857         }
 858
 859         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 860                 return;
 861
 862         args.v1.ucAction = action;
 863         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 864                 args.v1.usInitInfo = connector_object_id;
 865         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 866                 args.v1.asMode.ucLaneSel = lane_num;
 867                 args.v1.asMode.ucLaneSet = lane_set;
 868         } else {
 869                 if (is_dp)
 870                         args.v1.usPixelClock =
 871                                 cpu_to_le16(dp_clock / 10);
 872                 else if (radeon_encoder->pixel_clock > 165000)
 873                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 874                 else
 875                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 876         }
 877         if (ASIC_IS_DCE4(rdev)) {
 878                 if (is_dp)
 879                         args.v3.ucLaneNum = dp_lane_count;
 880                 else if (radeon_encoder->pixel_clock > 165000)
 881                         args.v3.ucLaneNum = 8;
 882                 else
 883                         args.v3.ucLaneNum = 4;
 884
 885                 if (dig->linkb) {
 886                         args.v3.acConfig.ucLinkSel = 1;
 887                         args.v3.acConfig.ucEncoderSel = 1;
 888                 }
 889
 890                 /* Select the PLL for the PHY
 891                  * DP PHY should be clocked from external src if there is
 892                  * one.
 893                  */
 894                 if (encoder->crtc) {
 895                         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 896                         pll_id = radeon_crtc->pll_id;
 897                 }
 898                 if (is_dp && rdev->clock.dp_extclk)
 899                         args.v3.acConfig.ucRefClkSource = 2; /* external src */
 900                 else
 901                         args.v3.acConfig.ucRefClkSource = pll_id;
 902
 903                 switch (radeon_encoder->encoder_id) {
 904                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 905                         args.v3.acConfig.ucTransmitterSel = 0;
 906                         break;
 907                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 908                         args.v3.acConfig.ucTransmitterSel = 1;
 909                         break;
 910                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 911                         args.v3.acConfig.ucTransmitterSel = 2;
 912                         break;
 913                 }
 914
 915                 if (is_dp)
 916                         args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
 917                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 918                         if (dig->coherent_mode)
 919                                 args.v3.acConfig.fCoherentMode = 1;
 920                         if (radeon_encoder->pixel_clock > 165000)
 921                                 args.v3.acConfig.fDualLinkConnector = 1;
 922                 }
 923         } else if (ASIC_IS_DCE32(rdev)) {
 924                 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
 925                 if (dig->linkb)
 926                         args.v2.acConfig.ucLinkSel = 1;
 927
 928                 switch (radeon_encoder->encoder_id) {
 929                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 930                         args.v2.acConfig.ucTransmitterSel = 0;
 931                         break;
 932                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 933                         args.v2.acConfig.ucTransmitterSel = 1;
 934                         break;
 935                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 936                         args.v2.acConfig.ucTransmitterSel = 2;
 937                         break;
 938                 }
 939
 940                 if (is_dp)
 941                         args.v2.acConfig.fCoherentMode = 1;
 942                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 943                         if (dig->coherent_mode)
 944                                 args.v2.acConfig.fCoherentMode = 1;
 945                         if (radeon_encoder->pixel_clock > 165000)
 946                                 args.v2.acConfig.fDualLinkConnector = 1;
 947                 }
 948         } else {
 949                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 950
 951                 if (dig->dig_encoder)
 952                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 953                 else
 954                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 955
 956                 if ((rdev->flags & RADEON_IS_IGP) &&
 957                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
 958                         if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
 959                                 if (igp_lane_info & 0x1)
 960                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 961                                 else if (igp_lane_info & 0x2)
 962                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 963                                 else if (igp_lane_info & 0x4)
 964                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 965                                 else if (igp_lane_info & 0x8)
 966                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 967                         } else {
 968                                 if (igp_lane_info & 0x3)
 969                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 970                                 else if (igp_lane_info & 0xc)
 971                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
 972                         }
 973                 }
 974
 975                 if (dig->linkb)
 976                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
 977                 else
 978                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
 979
 980                 if (is_dp)
 981                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 982                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 983                         if (dig->coherent_mode)
 984                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 985                         if (radeon_encoder->pixel_clock > 165000)
 986                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
 987                 }
 988         }
 989
 990         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 991 }
 992
 993 void
 994 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
 995 {
 996         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 997         struct drm_device *dev = radeon_connector->base.dev;
 998         struct radeon_device *rdev = dev->dev_private;
 999         union dig_transmitter_control args;
1000         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1001         uint8_t frev, crev;
1002
1003         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1004                 return;
1005
1006         if (!ASIC_IS_DCE4(rdev))
1007                 return;
1008
1009         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) ||
1010             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1011                 return;
1012
1013         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1014                 return;
1015
1016         memset(&args, 0, sizeof(args));
1017
1018         args.v1.ucAction = action;
1019
1020         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1021 }
1022
1023 static void
1024 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1025 {
1026         struct drm_device *dev = encoder->dev;
1027         struct radeon_device *rdev = dev->dev_private;
1028         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1029         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1030         ENABLE_YUV_PS_ALLOCATION args;
1031         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1032         uint32_t temp, reg;
1033
1034         memset(&args, 0, sizeof(args));
1035
1036         if (rdev->family >= CHIP_R600)
1037                 reg = R600_BIOS_3_SCRATCH;
1038         else
1039                 reg = RADEON_BIOS_3_SCRATCH;
1040
1041         /* XXX: fix up scratch reg handling */
1042         temp = RREG32(reg);
1043         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1044                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1045                              (radeon_crtc->crtc_id << 18)));
1046         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1047                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1048         else
1049                 WREG32(reg, 0);
1050
1051         if (enable)
1052                 args.ucEnable = ATOM_ENABLE;
1053         args.ucCRTC = radeon_crtc->crtc_id;
1054
1055         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1056
1057         WREG32(reg, temp);
1058 }
1059
1060 static void
1061 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1062 {
1063         struct drm_device *dev = encoder->dev;
1064         struct radeon_device *rdev = dev->dev_private;
1065         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1066         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1067         int index = 0;
1068         bool is_dig = false;
1069
1070         memset(&args, 0, sizeof(args));
1071
1072         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1073                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1074                   radeon_encoder->active_device);
1075         switch (radeon_encoder->encoder_id) {
1076         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1077         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1078                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1079                 break;
1080         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1081         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1082         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1083         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1084                 is_dig = true;
1085                 break;
1086         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1087         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1088         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1089                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1090                 break;
1091         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1092                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1093                 break;
1094         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1095                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1096                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1097                 else
1098                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1099                 break;
1100         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1101         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1102                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1103                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1104                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1105                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1106                 else
1107                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1108                 break;
1109         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1110         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1111                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1112                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1113                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1114                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1115                 else
1116                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1117                 break;
1118         }
1119
1120         if (is_dig) {
1121                 switch (mode) {
1122                 case DRM_MODE_DPMS_ON:
1123                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1124                         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1125                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1126
1127                                 if (connector &&
1128                                     (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1129                                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1130                                         struct radeon_connector_atom_dig *radeon_dig_connector =
1131                                                 radeon_connector->con_priv;
1132                                         atombios_set_edp_panel_power(connector,
1133                                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
1134                                         radeon_dig_connector->edp_on = true;
1135                                 }
1136                                 dp_link_train(encoder, connector);
1137                                 if (ASIC_IS_DCE4(rdev))
1138                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
1139                         }
1140                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1141                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1142                         break;
1143                 case DRM_MODE_DPMS_STANDBY:
1144                 case DRM_MODE_DPMS_SUSPEND:
1145                 case DRM_MODE_DPMS_OFF:
1146                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1147                         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1148                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1149
1150                                 if (ASIC_IS_DCE4(rdev))
1151                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1152                                 if (connector &&
1153                                     (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1154                                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1155                                         struct radeon_connector_atom_dig *radeon_dig_connector =
1156                                                 radeon_connector->con_priv;
1157                                         atombios_set_edp_panel_power(connector,
1158                                                                      ATOM_TRANSMITTER_ACTION_POWER_OFF);
1159                                         radeon_dig_connector->edp_on = false;
1160                                 }
1161                         }
1162                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1163                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1164                         break;
1165                 }
1166         } else {
1167                 switch (mode) {
1168                 case DRM_MODE_DPMS_ON:
1169                         args.ucAction = ATOM_ENABLE;
1170                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1171                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1172                                 args.ucAction = ATOM_LCD_BLON;
1173                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1174                         }
1175                         break;
1176                 case DRM_MODE_DPMS_STANDBY:
1177                 case DRM_MODE_DPMS_SUSPEND:
1178                 case DRM_MODE_DPMS_OFF:
1179                         args.ucAction = ATOM_DISABLE;
1180                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1181                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1182                                 args.ucAction = ATOM_LCD_BLOFF;
1183                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1184                         }
1185                         break;
1186                 }
1187         }
1188         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1189
1190 }
1191
1192 union crtc_source_param {
1193         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1194         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1195 };
1196
1197 static void
1198 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1199 {
1200         struct drm_device *dev = encoder->dev;
1201         struct radeon_device *rdev = dev->dev_private;
1202         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1203         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1204         union crtc_source_param args;
1205         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1206         uint8_t frev, crev;
1207         struct radeon_encoder_atom_dig *dig;
1208
1209         memset(&args, 0, sizeof(args));
1210
1211         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1212                 return;
1213
1214         switch (frev) {
1215         case 1:
1216                 switch (crev) {
1217                 case 1:
1218                 default:
1219                         if (ASIC_IS_AVIVO(rdev))
1220                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1221                         else {
1222                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1223                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1224                                 } else {
1225                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1226                                 }
1227                         }
1228                         switch (radeon_encoder->encoder_id) {
1229                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1230                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1231                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1232                                 break;
1233                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1234                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1235                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1236                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1237                                 else
1238                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1239                                 break;
1240                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1241                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1242                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1243                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1244                                 break;
1245                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1246                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1247                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1248                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1249                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1250                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1251                                 else
1252                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1253                                 break;
1254                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1255                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1256                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1257                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1258                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1259                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1260                                 else
1261                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1262                                 break;
1263                         }
1264                         break;
1265                 case 2:
1266                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1267                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1268                         switch (radeon_encoder->encoder_id) {
1269                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1270                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1271                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1272                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1273                                 dig = radeon_encoder->enc_priv;
1274                                 switch (dig->dig_encoder) {
1275                                 case 0:
1276                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1277                                         break;
1278                                 case 1:
1279                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1280                                         break;
1281                                 case 2:
1282                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1283                                         break;
1284                                 case 3:
1285                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1286                                         break;
1287                                 case 4:
1288                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1289                                         break;
1290                                 case 5:
1291                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1292                                         break;
1293                                 }
1294                                 break;
1295                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1296                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1297                                 break;
1298                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1299                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1300                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1301                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1302                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1303                                 else
1304                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1305                                 break;
1306                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1307                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1308                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1309                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1310                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1311                                 else
1312                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1313                                 break;
1314                         }
1315                         break;
1316                 }
1317                 break;
1318         default:
1319                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1320                 break;
1321         }
1322
1323         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1324
1325         /* update scratch regs with new routing */
1326         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1327 }
1328
1329 static void
1330 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1331                               struct drm_display_mode *mode)
1332 {
1333         struct drm_device *dev = encoder->dev;
1334         struct radeon_device *rdev = dev->dev_private;
1335         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1336         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1337
1338         /* Funky macbooks */
1339         if ((dev->pdev->device == 0x71C5) &&
1340             (dev->pdev->subsystem_vendor == 0x106b) &&
1341             (dev->pdev->subsystem_device == 0x0080)) {
1342                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1343                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1344
1345                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1346                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1347
1348                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1349                 }
1350         }
1351
1352         /* set scaler clears this on some chips */
1353         /* XXX check DCE4 */
1354         if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1355                 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1356                         WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1357                                AVIVO_D1MODE_INTERLEAVE_EN);
1358         }
1359 }
1360
1361 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1362 {
1363         struct drm_device *dev = encoder->dev;
1364         struct radeon_device *rdev = dev->dev_private;
1365         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1366         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1367         struct drm_encoder *test_encoder;
1368         struct radeon_encoder_atom_dig *dig;
1369         uint32_t dig_enc_in_use = 0;
1370
1371         if (ASIC_IS_DCE4(rdev)) {
1372                 dig = radeon_encoder->enc_priv;
1373                 switch (radeon_encoder->encoder_id) {
1374                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1375                         if (dig->linkb)
1376                                 return 1;
1377                         else
1378                                 return 0;
1379                         break;
1380                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1381                         if (dig->linkb)
1382                                 return 3;
1383                         else
1384                                 return 2;
1385                         break;
1386                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1387                         if (dig->linkb)
1388                                 return 5;
1389                         else
1390                                 return 4;
1391                         break;
1392                 }
1393         }
1394
1395         /* on DCE32 and encoder can driver any block so just crtc id */
1396         if (ASIC_IS_DCE32(rdev)) {
1397                 return radeon_crtc->crtc_id;
1398         }
1399
1400         /* on DCE3 - LVTMA can only be driven by DIGB */
1401         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1402                 struct radeon_encoder *radeon_test_encoder;
1403
1404                 if (encoder == test_encoder)
1405                         continue;
1406
1407                 if (!radeon_encoder_is_digital(test_encoder))
1408                         continue;
1409
1410                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1411                 dig = radeon_test_encoder->enc_priv;
1412
1413                 if (dig->dig_encoder >= 0)
1414                         dig_enc_in_use |= (1 << dig->dig_encoder);
1415         }
1416
1417         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1418                 if (dig_enc_in_use & 0x2)
1419                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1420                 return 1;
1421         }
1422         if (!(dig_enc_in_use & 1))
1423                 return 0;
1424         return 1;
1425 }
1426
1427 static void
1428 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1429                              struct drm_display_mode *mode,
1430                              struct drm_display_mode *adjusted_mode)
1431 {
1432         struct drm_device *dev = encoder->dev;
1433         struct radeon_device *rdev = dev->dev_private;
1434         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1435
1436         radeon_encoder->pixel_clock = adjusted_mode->clock;
1437
1438         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1439                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1440                         atombios_yuv_setup(encoder, true);
1441                 else
1442                         atombios_yuv_setup(encoder, false);
1443         }
1444
1445         switch (radeon_encoder->encoder_id) {
1446         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1447         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1448         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1449         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1450                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1451                 break;
1452         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1453         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1454         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1455         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1456                 if (ASIC_IS_DCE4(rdev)) {
1457                         /* disable the transmitter */
1458                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1459                         /* setup and enable the encoder */
1460                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1461
1462                         /* init and enable the transmitter */
1463                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1464                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1465                 } else {
1466                         /* disable the encoder and transmitter */
1467                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1468                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1469
1470                         /* setup and enable the encoder and transmitter */
1471                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1472                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1473                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1474                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1475                 }
1476                 break;
1477         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1478                 atombios_ddia_setup(encoder, ATOM_ENABLE);
1479                 break;
1480         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1481         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1482                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1483                 break;
1484         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1485         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1486         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1487         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1488                 atombios_dac_setup(encoder, ATOM_ENABLE);
1489                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1490                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1491                                 atombios_tv_setup(encoder, ATOM_ENABLE);
1492                         else
1493                                 atombios_tv_setup(encoder, ATOM_DISABLE);
1494                 }
1495                 break;
1496         }
1497         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1498
1499         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1500                 r600_hdmi_enable(encoder);
1501                 r600_hdmi_setmode(encoder, adjusted_mode);
1502         }
1503 }
1504
1505 static bool
1506 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1507 {
1508         struct drm_device *dev = encoder->dev;
1509         struct radeon_device *rdev = dev->dev_private;
1510         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1511         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1512
1513         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1514                                        ATOM_DEVICE_CV_SUPPORT |
1515                                        ATOM_DEVICE_CRT_SUPPORT)) {
1516                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1517                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1518                 uint8_t frev, crev;
1519
1520                 memset(&args, 0, sizeof(args));
1521
1522                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1523                         return false;
1524
1525                 args.sDacload.ucMisc = 0;
1526
1527                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1528                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1529                         args.sDacload.ucDacType = ATOM_DAC_A;
1530                 else
1531                         args.sDacload.ucDacType = ATOM_DAC_B;
1532
1533                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1534                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1535                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1536                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1537                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1538                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1539                         if (crev >= 3)
1540                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1541                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1542                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1543                         if (crev >= 3)
1544                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1545                 }
1546
1547                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1548
1549                 return true;
1550         } else
1551                 return false;
1552 }
1553
1554 static enum drm_connector_status
1555 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1556 {
1557         struct drm_device *dev = encoder->dev;
1558         struct radeon_device *rdev = dev->dev_private;
1559         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1560         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1561         uint32_t bios_0_scratch;
1562
1563         if (!atombios_dac_load_detect(encoder, connector)) {
1564                 DRM_DEBUG_KMS("detect returned false \n");
1565                 return connector_status_unknown;
1566         }
1567
1568         if (rdev->family >= CHIP_R600)
1569                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1570         else
1571                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1572
1573         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1574         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1575                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1576                         return connector_status_connected;
1577         }
1578         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1579                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1580                         return connector_status_connected;
1581         }
1582         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1583                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1584                         return connector_status_connected;
1585         }
1586         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1587                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1588                         return connector_status_connected; /* CTV */
1589                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1590                         return connector_status_connected; /* STV */
1591         }
1592         return connector_status_disconnected;
1593 }
1594
1595 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1596 {
1597         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1598         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1599
1600         if (radeon_encoder->active_device &
1601             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1602                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1603                 if (dig)
1604                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1605         }
1606
1607         radeon_atom_output_lock(encoder, true);
1608         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1609
1610         /* select the clock/data port if it uses a router */
1611         if (connector) {
1612                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1613                 if (radeon_connector->router.cd_valid)
1614                         radeon_router_select_cd_port(radeon_connector);
1615         }
1616
1617         /* this is needed for the pll/ss setup to work correctly in some cases */
1618         atombios_set_encoder_crtc_source(encoder);
1619 }
1620
1621 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1622 {
1623         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1624         radeon_atom_output_lock(encoder, false);
1625 }
1626
1627 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1628 {
1629         struct drm_device *dev = encoder->dev;
1630         struct radeon_device *rdev = dev->dev_private;
1631         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1632         struct radeon_encoder_atom_dig *dig;
1633
1634         /* check for pre-DCE3 cards with shared encoders;
1635          * can't really use the links individually, so don't disable
1636          * the encoder if it's in use by another connector
1637          */
1638         if (!ASIC_IS_DCE3(rdev)) {
1639                 struct drm_encoder *other_encoder;
1640                 struct radeon_encoder *other_radeon_encoder;
1641
1642                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
1643                         other_radeon_encoder = to_radeon_encoder(other_encoder);
1644                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
1645                             drm_helper_encoder_in_use(other_encoder))
1646                                 goto disable_done;
1647                 }
1648         }
1649
1650         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1651
1652         switch (radeon_encoder->encoder_id) {
1653         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1654         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1655         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1656         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1657                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
1658                 break;
1659         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1660         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1661         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1662         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1663                 if (ASIC_IS_DCE4(rdev))
1664                         /* disable the transmitter */
1665                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1666                 else {
1667                         /* disable the encoder and transmitter */
1668                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1669                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1670                 }
1671                 break;
1672         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1673                 atombios_ddia_setup(encoder, ATOM_DISABLE);
1674                 break;
1675         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1676         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1677                 atombios_external_tmds_setup(encoder, ATOM_DISABLE);
1678                 break;
1679         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1680         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1681         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1682         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1683                 atombios_dac_setup(encoder, ATOM_DISABLE);
1684                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1685                         atombios_tv_setup(encoder, ATOM_DISABLE);
1686                 break;
1687         }
1688
1689 disable_done:
1690         if (radeon_encoder_is_digital(encoder)) {
1691                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1692                         r600_hdmi_disable(encoder);
1693                 dig = radeon_encoder->enc_priv;
1694                 dig->dig_encoder = -1;
1695         }
1696         radeon_encoder->active_device = 0;
1697 }
1698
1699 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1700         .dpms = radeon_atom_encoder_dpms,
1701         .mode_fixup = radeon_atom_mode_fixup,
1702         .prepare = radeon_atom_encoder_prepare,
1703         .mode_set = radeon_atom_encoder_mode_set,
1704         .commit = radeon_atom_encoder_commit,
1705         .disable = radeon_atom_encoder_disable,
1706         /* no detect for TMDS/LVDS yet */
1707 };
1708
1709 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1710         .dpms = radeon_atom_encoder_dpms,
1711         .mode_fixup = radeon_atom_mode_fixup,
1712         .prepare = radeon_atom_encoder_prepare,
1713         .mode_set = radeon_atom_encoder_mode_set,
1714         .commit = radeon_atom_encoder_commit,
1715         .detect = radeon_atom_dac_detect,
1716 };
1717
1718 void radeon_enc_destroy(struct drm_encoder *encoder)
1719 {
1720         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1721         kfree(radeon_encoder->enc_priv);
1722         drm_encoder_cleanup(encoder);
1723         kfree(radeon_encoder);
1724 }
1725
1726 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1727         .destroy = radeon_enc_destroy,
1728 };
1729
1730 struct radeon_encoder_atom_dac *
1731 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1732 {
1733         struct drm_device *dev = radeon_encoder->base.dev;
1734         struct radeon_device *rdev = dev->dev_private;
1735         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1736
1737         if (!dac)
1738                 return NULL;
1739
1740         dac->tv_std = radeon_atombios_get_tv_info(rdev);
1741         return dac;
1742 }
1743
1744 struct radeon_encoder_atom_dig *
1745 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1746 {
1747         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1748         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1749
1750         if (!dig)
1751                 return NULL;
1752
1753         /* coherent mode by default */
1754         dig->coherent_mode = true;
1755         dig->dig_encoder = -1;
1756
1757         if (encoder_enum == 2)
1758                 dig->linkb = true;
1759         else
1760                 dig->linkb = false;
1761
1762         return dig;
1763 }
1764
1765 void
1766 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1767 {
1768         struct radeon_device *rdev = dev->dev_private;
1769         struct drm_encoder *encoder;
1770         struct radeon_encoder *radeon_encoder;
1771
1772         /* see if we already added it */
1773         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1774                 radeon_encoder = to_radeon_encoder(encoder);
1775                 if (radeon_encoder->encoder_enum == encoder_enum) {
1776                         radeon_encoder->devices |= supported_device;
1777                         return;
1778                 }
1779
1780         }
1781
1782         /* add a new one */
1783         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1784         if (!radeon_encoder)
1785                 return;
1786
1787         encoder = &radeon_encoder->base;
1788         switch (rdev->num_crtc) {
1789         case 1:
1790                 encoder->possible_crtcs = 0x1;
1791                 break;
1792         case 2:
1793         default:
1794                 encoder->possible_crtcs = 0x3;
1795                 break;
1796         case 6:
1797                 encoder->possible_crtcs = 0x3f;
1798                 break;
1799         }
1800
1801         radeon_encoder->enc_priv = NULL;
1802
1803         radeon_encoder->encoder_enum = encoder_enum;
1804         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1805         radeon_encoder->devices = supported_device;
1806         radeon_encoder->rmx_type = RMX_OFF;
1807         radeon_encoder->underscan_type = UNDERSCAN_OFF;
1808
1809         switch (radeon_encoder->encoder_id) {
1810         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1811         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1812         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1813         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1814                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1815                         radeon_encoder->rmx_type = RMX_FULL;
1816                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1817                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1818                 } else {
1819                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1820                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1821                         if (ASIC_IS_AVIVO(rdev))
1822                                 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
1823                 }
1824                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1825                 break;
1826         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1827                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1828                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1829                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1830                 break;
1831         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1832         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1833         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1834                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1835                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1836                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1837                 break;
1838         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1839         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1840         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1841         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1842         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1843         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1844         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1845                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1846                         radeon_encoder->rmx_type = RMX_FULL;
1847                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1848                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1849                 } else {
1850                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1851                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1852                         if (ASIC_IS_AVIVO(rdev))
1853                                 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
1854                 }
1855                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1856                 break;
1857         }
1858 }