drivers/gpu/drm/radeon/rv515.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "rv515d.h"
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34 #include "atom.h"
  35 #include "rv515_reg_safe.h"
  36
  37 /* This files gather functions specifics to: rv515 */
  38 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
  39 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
  40 void rv515_gpu_init(struct radeon_device *rdev);
  41 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
  42
  43 void rv515_debugfs(struct radeon_device *rdev)
  44 {
  45         if (r100_debugfs_rbbm_init(rdev)) {
  46                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  47         }
  48         if (rv515_debugfs_pipes_info_init(rdev)) {
  49                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  50         }
  51         if (rv515_debugfs_ga_info_init(rdev)) {
  52                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  53         }
  54 }
  55
  56 void rv515_ring_start(struct radeon_device *rdev)
  57 {
  58         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  59         int r;
  60
  61         r = radeon_ring_lock(rdev, ring, 64);
  62         if (r) {
  63                 return;
  64         }
  65         radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
  66         radeon_ring_write(ring,
  67                           ISYNC_ANY2D_IDLE3D |
  68                           ISYNC_ANY3D_IDLE2D |
  69                           ISYNC_WAIT_IDLEGUI |
  70                           ISYNC_CPSCRATCH_IDLEGUI);
  71         radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
  72         radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
  73         radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
  74         radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
  75         radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
  76         radeon_ring_write(ring, 0);
  77         radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
  78         radeon_ring_write(ring, 0);
  79         radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
  80         radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);
  81         radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
  82         radeon_ring_write(ring, 0);
  83         radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
  84         radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
  85         radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
  86         radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
  87         radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
  88         radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
  89         radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));
  90         radeon_ring_write(ring, 0);
  91         radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
  92         radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
  93         radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
  94         radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
  95         radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));
  96         radeon_ring_write(ring,
  97                           ((6 << MS_X0_SHIFT) |
  98                            (6 << MS_Y0_SHIFT) |
  99                            (6 << MS_X1_SHIFT) |
 100                            (6 << MS_Y1_SHIFT) |
 101                            (6 << MS_X2_SHIFT) |
 102                            (6 << MS_Y2_SHIFT) |
 103                            (6 << MSBD0_Y_SHIFT) |
 104                            (6 << MSBD0_X_SHIFT)));
 105         radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));
 106         radeon_ring_write(ring,
 107                           ((6 << MS_X3_SHIFT) |
 108                            (6 << MS_Y3_SHIFT) |
 109                            (6 << MS_X4_SHIFT) |
 110                            (6 << MS_Y4_SHIFT) |
 111                            (6 << MS_X5_SHIFT) |
 112                            (6 << MS_Y5_SHIFT) |
 113                            (6 << MSBD1_SHIFT)));
 114         radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));
 115         radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
 116         radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));
 117         radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
 118         radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));
 119         radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
 120         radeon_ring_write(ring, PACKET0(0x20C8, 0));
 121         radeon_ring_write(ring, 0);
 122         radeon_ring_unlock_commit(rdev, ring);
 123 }
 124
 125 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
 126 {
 127         unsigned i;
 128         uint32_t tmp;
 129
 130         for (i = 0; i < rdev->usec_timeout; i++) {
 131                 /* read MC_STATUS */
 132                 tmp = RREG32_MC(MC_STATUS);
 133                 if (tmp & MC_STATUS_IDLE) {
 134                         return 0;
 135                 }
 136                 DRM_UDELAY(1);
 137         }
 138         return -1;
 139 }
 140
 141 void rv515_vga_render_disable(struct radeon_device *rdev)
 142 {
 143         WREG32(R_000300_VGA_RENDER_CONTROL,
 144                 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
 145 }
 146
 147 void rv515_gpu_init(struct radeon_device *rdev)
 148 {
 149         unsigned pipe_select_current, gb_pipe_select, tmp;
 150
 151         if (r100_gui_wait_for_idle(rdev)) {
 152                 printk(KERN_WARNING "Failed to wait GUI idle while "
 153                        "reseting GPU. Bad things might happen.\n");
 154         }
 155         rv515_vga_render_disable(rdev);
 156         r420_pipes_init(rdev);
 157         gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
 158         tmp = RREG32(R300_DST_PIPE_CONFIG);
 159         pipe_select_current = (tmp >> 2) & 3;
 160         tmp = (1 << pipe_select_current) |
 161               (((gb_pipe_select >> 8) & 0xF) << 4);
 162         WREG32_PLL(0x000D, tmp);
 163         if (r100_gui_wait_for_idle(rdev)) {
 164                 printk(KERN_WARNING "Failed to wait GUI idle while "
 165                        "reseting GPU. Bad things might happen.\n");
 166         }
 167         if (rv515_mc_wait_for_idle(rdev)) {
 168                 printk(KERN_WARNING "Failed to wait MC idle while "
 169                        "programming pipes. Bad things might happen.\n");
 170         }
 171 }
 172
 173 static void rv515_vram_get_type(struct radeon_device *rdev)
 174 {
 175         uint32_t tmp;
 176
 177         rdev->mc.vram_width = 128;
 178         rdev->mc.vram_is_ddr = true;
 179         tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
 180         switch (tmp) {
 181         case 0:
 182                 rdev->mc.vram_width = 64;
 183                 break;
 184         case 1:
 185                 rdev->mc.vram_width = 128;
 186                 break;
 187         default:
 188                 rdev->mc.vram_width = 128;
 189                 break;
 190         }
 191 }
 192
 193 void rv515_mc_init(struct radeon_device *rdev)
 194 {
 195
 196         rv515_vram_get_type(rdev);
 197         r100_vram_init_sizes(rdev);
 198         radeon_vram_location(rdev, &rdev->mc, 0);
 199         rdev->mc.gtt_base_align = 0;
 200         if (!(rdev->flags & RADEON_IS_AGP))
 201                 radeon_gtt_location(rdev, &rdev->mc);
 202         radeon_update_bandwidth_info(rdev);
 203 }
 204
 205 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 206 {
 207         uint32_t r;
 208
 209         WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
 210         r = RREG32(MC_IND_DATA);
 211         WREG32(MC_IND_INDEX, 0);
 212         return r;
 213 }
 214
 215 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 216 {
 217         WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
 218         WREG32(MC_IND_DATA, (v));
 219         WREG32(MC_IND_INDEX, 0);
 220 }
 221
 222 #if defined(CONFIG_DEBUG_FS)
 223 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
 224 {
 225         struct drm_info_node *node = (struct drm_info_node *) m->private;
 226         struct drm_device *dev = node->minor->dev;
 227         struct radeon_device *rdev = dev->dev_private;
 228         uint32_t tmp;
 229
 230         tmp = RREG32(GB_PIPE_SELECT);
 231         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 232         tmp = RREG32(SU_REG_DEST);
 233         seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
 234         tmp = RREG32(GB_TILE_CONFIG);
 235         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 236         tmp = RREG32(DST_PIPE_CONFIG);
 237         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 238         return 0;
 239 }
 240
 241 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
 242 {
 243         struct drm_info_node *node = (struct drm_info_node *) m->private;
 244         struct drm_device *dev = node->minor->dev;
 245         struct radeon_device *rdev = dev->dev_private;
 246         uint32_t tmp;
 247
 248         tmp = RREG32(0x2140);
 249         seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
 250         radeon_asic_reset(rdev);
 251         tmp = RREG32(0x425C);
 252         seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
 253         return 0;
 254 }
 255
 256 static struct drm_info_list rv515_pipes_info_list[] = {
 257         {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
 258 };
 259
 260 static struct drm_info_list rv515_ga_info_list[] = {
 261         {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
 262 };
 263 #endif
 264
 265 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
 266 {
 267 #if defined(CONFIG_DEBUG_FS)
 268         return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
 269 #else
 270         return 0;
 271 #endif
 272 }
 273
 274 int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
 275 {
 276 #if defined(CONFIG_DEBUG_FS)
 277         return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
 278 #else
 279         return 0;
 280 #endif
 281 }
 282
 283 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
 284 {
 285         save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL);
 286         save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL);
 287         save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
 288         save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
 289         save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
 290         save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
 291
 292         /* Stop all video */
 293         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
 294         WREG32(R_000300_VGA_RENDER_CONTROL, 0);
 295         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
 296         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
 297         WREG32(R_006080_D1CRTC_CONTROL, 0);
 298         WREG32(R_006880_D2CRTC_CONTROL, 0);
 299         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
 300         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
 301         WREG32(R_000330_D1VGA_CONTROL, 0);
 302         WREG32(R_000338_D2VGA_CONTROL, 0);
 303 }
 304
 305 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
 306 {
 307         WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
 308         WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
 309         WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
 310         WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
 311         WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
 312         /* Unlock host access */
 313         WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
 314         mdelay(1);
 315         /* Restore video state */
 316         WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
 317         WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
 318         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
 319         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
 320         WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
 321         WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
 322         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
 323         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
 324         WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
 325 }
 326
 327 void rv515_mc_program(struct radeon_device *rdev)
 328 {
 329         struct rv515_mc_save save;
 330
 331         /* Stops all mc clients */
 332         rv515_mc_stop(rdev, &save);
 333
 334         /* Wait for mc idle */
 335         if (rv515_mc_wait_for_idle(rdev))
 336                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 337         /* Write VRAM size in case we are limiting it */
 338         WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
 339         /* Program MC, should be a 32bits limited address space */
 340         WREG32_MC(R_000001_MC_FB_LOCATION,
 341                         S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
 342                         S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
 343         WREG32(R_000134_HDP_FB_LOCATION,
 344                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 345         if (rdev->flags & RADEON_IS_AGP) {
 346                 WREG32_MC(R_000002_MC_AGP_LOCATION,
 347                         S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
 348                         S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
 349                 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
 350                 WREG32_MC(R_000004_MC_AGP_BASE_2,
 351                         S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
 352         } else {
 353                 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
 354                 WREG32_MC(R_000003_MC_AGP_BASE, 0);
 355                 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
 356         }
 357
 358         rv515_mc_resume(rdev, &save);
 359 }
 360
 361 void rv515_clock_startup(struct radeon_device *rdev)
 362 {
 363         if (radeon_dynclks != -1 && radeon_dynclks)
 364                 radeon_atom_set_clock_gating(rdev, 1);
 365         /* We need to force on some of the block */
 366         WREG32_PLL(R_00000F_CP_DYN_CNTL,
 367                 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
 368         WREG32_PLL(R_000011_E2_DYN_CNTL,
 369                 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
 370         WREG32_PLL(R_000013_IDCT_DYN_CNTL,
 371                 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
 372 }
 373
 374 static int rv515_startup(struct radeon_device *rdev)
 375 {
 376         int r;
 377
 378         rv515_mc_program(rdev);
 379         /* Resume clock */
 380         rv515_clock_startup(rdev);
 381         /* Initialize GPU configuration (# pipes, ...) */
 382         rv515_gpu_init(rdev);
 383         /* Initialize GART (initialize after TTM so we can allocate
 384          * memory through TTM but finalize after TTM) */
 385         if (rdev->flags & RADEON_IS_PCIE) {
 386                 r = rv370_pcie_gart_enable(rdev);
 387                 if (r)
 388                         return r;
 389         }
 390
 391         /* allocate wb buffer */
 392         r = radeon_wb_init(rdev);
 393         if (r)
 394                 return r;
 395
 396         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
 397         if (r) {
 398                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
 399                 return r;
 400         }
 401
 402         /* Enable IRQ */
 403         rs600_irq_set(rdev);
 404         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 405         /* 1M ring buffer */
 406         r = r100_cp_init(rdev, 1024 * 1024);
 407         if (r) {
 408                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
 409                 return r;
 410         }
 411
 412         r = radeon_ib_pool_start(rdev);
 413         if (r)
 414                 return r;
 415
 416         r = r100_ib_test(rdev);
 417         if (r) {
 418                 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
 419                 rdev->accel_working = false;
 420                 return r;
 421         }
 422         return 0;
 423 }
 424
 425 int rv515_resume(struct radeon_device *rdev)
 426 {
 427         /* Make sur GART are not working */
 428         if (rdev->flags & RADEON_IS_PCIE)
 429                 rv370_pcie_gart_disable(rdev);
 430         /* Resume clock before doing reset */
 431         rv515_clock_startup(rdev);
 432         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 433         if (radeon_asic_reset(rdev)) {
 434                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 435                         RREG32(R_000E40_RBBM_STATUS),
 436                         RREG32(R_0007C0_CP_STAT));
 437         }
 438         /* post */
 439         atom_asic_init(rdev->mode_info.atom_context);
 440         /* Resume clock after posting */
 441         rv515_clock_startup(rdev);
 442         /* Initialize surface registers */
 443         radeon_surface_init(rdev);
 444
 445         rdev->accel_working = true;
 446         return rv515_startup(rdev);
 447 }
 448
 449 int rv515_suspend(struct radeon_device *rdev)
 450 {
 451         r100_cp_disable(rdev);
 452         radeon_wb_disable(rdev);
 453         rs600_irq_disable(rdev);
 454         if (rdev->flags & RADEON_IS_PCIE)
 455                 rv370_pcie_gart_disable(rdev);
 456         return 0;
 457 }
 458
 459 void rv515_set_safe_registers(struct radeon_device *rdev)
 460 {
 461         rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
 462         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
 463 }
 464
 465 void rv515_fini(struct radeon_device *rdev)
 466 {
 467         r100_cp_fini(rdev);
 468         radeon_wb_fini(rdev);
 469         r100_ib_fini(rdev);
 470         radeon_gem_fini(rdev);
 471         rv370_pcie_gart_fini(rdev);
 472         radeon_agp_fini(rdev);
 473         radeon_irq_kms_fini(rdev);
 474         radeon_fence_driver_fini(rdev);
 475         radeon_bo_fini(rdev);
 476         radeon_atombios_fini(rdev);
 477         kfree(rdev->bios);
 478         rdev->bios = NULL;
 479 }
 480
 481 int rv515_init(struct radeon_device *rdev)
 482 {
 483         int r;
 484
 485         /* Initialize scratch registers */
 486         radeon_scratch_init(rdev);
 487         /* Initialize surface registers */
 488         radeon_surface_init(rdev);
 489         /* TODO: disable VGA need to use VGA request */
 490         /* restore some register to sane defaults */
 491         r100_restore_sanity(rdev);
 492         /* BIOS*/
 493         if (!radeon_get_bios(rdev)) {
 494                 if (ASIC_IS_AVIVO(rdev))
 495                         return -EINVAL;
 496         }
 497         if (rdev->is_atom_bios) {
 498                 r = radeon_atombios_init(rdev);
 499                 if (r)
 500                         return r;
 501         } else {
 502                 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
 503                 return -EINVAL;
 504         }
 505         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 506         if (radeon_asic_reset(rdev)) {
 507                 dev_warn(rdev->dev,
 508                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 509                         RREG32(R_000E40_RBBM_STATUS),
 510                         RREG32(R_0007C0_CP_STAT));
 511         }
 512         /* check if cards are posted or not */
 513         if (radeon_boot_test_post_card(rdev) == false)
 514                 return -EINVAL;
 515         /* Initialize clocks */
 516         radeon_get_clock_info(rdev->ddev);
 517         /* initialize AGP */
 518         if (rdev->flags & RADEON_IS_AGP) {
 519                 r = radeon_agp_init(rdev);
 520                 if (r) {
 521                         radeon_agp_disable(rdev);
 522                 }
 523         }
 524         /* initialize memory controller */
 525         rv515_mc_init(rdev);
 526         rv515_debugfs(rdev);
 527         /* Fence driver */
 528         r = radeon_fence_driver_init(rdev);
 529         if (r)
 530                 return r;
 531         r = radeon_irq_kms_init(rdev);
 532         if (r)
 533                 return r;
 534         /* Memory manager */
 535         r = radeon_bo_init(rdev);
 536         if (r)
 537                 return r;
 538         r = rv370_pcie_gart_init(rdev);
 539         if (r)
 540                 return r;
 541         rv515_set_safe_registers(rdev);
 542
 543         r = radeon_ib_pool_init(rdev);
 544         rdev->accel_working = true;
 545         if (r) {
 546                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
 547                 rdev->accel_working = false;
 548         }
 549
 550         r = rv515_startup(rdev);
 551         if (r) {
 552                 /* Somethings want wront with the accel init stop accel */
 553                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 554                 r100_cp_fini(rdev);
 555                 radeon_wb_fini(rdev);
 556                 r100_ib_fini(rdev);
 557                 radeon_irq_kms_fini(rdev);
 558                 rv370_pcie_gart_fini(rdev);
 559                 radeon_agp_fini(rdev);
 560                 rdev->accel_working = false;
 561         }
 562         return 0;
 563 }
 564
 565 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
 566 {
 567         int index_reg = 0x6578 + crtc->crtc_offset;
 568         int data_reg = 0x657c + crtc->crtc_offset;
 569
 570         WREG32(0x659C + crtc->crtc_offset, 0x0);
 571         WREG32(0x6594 + crtc->crtc_offset, 0x705);
 572         WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
 573         WREG32(0x65D8 + crtc->crtc_offset, 0x0);
 574         WREG32(0x65B0 + crtc->crtc_offset, 0x0);
 575         WREG32(0x65C0 + crtc->crtc_offset, 0x0);
 576         WREG32(0x65D4 + crtc->crtc_offset, 0x0);
 577         WREG32(index_reg, 0x0);
 578         WREG32(data_reg, 0x841880A8);
 579         WREG32(index_reg, 0x1);
 580         WREG32(data_reg, 0x84208680);
 581         WREG32(index_reg, 0x2);
 582         WREG32(data_reg, 0xBFF880B0);
 583         WREG32(index_reg, 0x100);
 584         WREG32(data_reg, 0x83D88088);
 585         WREG32(index_reg, 0x101);
 586         WREG32(data_reg, 0x84608680);
 587         WREG32(index_reg, 0x102);
 588         WREG32(data_reg, 0xBFF080D0);
 589         WREG32(index_reg, 0x200);
 590         WREG32(data_reg, 0x83988068);
 591         WREG32(index_reg, 0x201);
 592         WREG32(data_reg, 0x84A08680);
 593         WREG32(index_reg, 0x202);
 594         WREG32(data_reg, 0xBFF080F8);
 595         WREG32(index_reg, 0x300);
 596         WREG32(data_reg, 0x83588058);
 597         WREG32(index_reg, 0x301);
 598         WREG32(data_reg, 0x84E08660);
 599         WREG32(index_reg, 0x302);
 600         WREG32(data_reg, 0xBFF88120);
 601         WREG32(index_reg, 0x400);
 602         WREG32(data_reg, 0x83188040);
 603         WREG32(index_reg, 0x401);
 604         WREG32(data_reg, 0x85008660);
 605         WREG32(index_reg, 0x402);
 606         WREG32(data_reg, 0xBFF88150);
 607         WREG32(index_reg, 0x500);
 608         WREG32(data_reg, 0x82D88030);
 609         WREG32(index_reg, 0x501);
 610         WREG32(data_reg, 0x85408640);
 611         WREG32(index_reg, 0x502);
 612         WREG32(data_reg, 0xBFF88180);
 613         WREG32(index_reg, 0x600);
 614         WREG32(data_reg, 0x82A08018);
 615         WREG32(index_reg, 0x601);
 616         WREG32(data_reg, 0x85808620);
 617         WREG32(index_reg, 0x602);
 618         WREG32(data_reg, 0xBFF081B8);
 619         WREG32(index_reg, 0x700);
 620         WREG32(data_reg, 0x82608010);
 621         WREG32(index_reg, 0x701);
 622         WREG32(data_reg, 0x85A08600);
 623         WREG32(index_reg, 0x702);
 624         WREG32(data_reg, 0x800081F0);
 625         WREG32(index_reg, 0x800);
 626         WREG32(data_reg, 0x8228BFF8);
 627         WREG32(index_reg, 0x801);
 628         WREG32(data_reg, 0x85E085E0);
 629         WREG32(index_reg, 0x802);
 630         WREG32(data_reg, 0xBFF88228);
 631         WREG32(index_reg, 0x10000);
 632         WREG32(data_reg, 0x82A8BF00);
 633         WREG32(index_reg, 0x10001);
 634         WREG32(data_reg, 0x82A08CC0);
 635         WREG32(index_reg, 0x10002);
 636         WREG32(data_reg, 0x8008BEF8);
 637         WREG32(index_reg, 0x10100);
 638         WREG32(data_reg, 0x81F0BF28);
 639         WREG32(index_reg, 0x10101);
 640         WREG32(data_reg, 0x83608CA0);
 641         WREG32(index_reg, 0x10102);
 642         WREG32(data_reg, 0x8018BED0);
 643         WREG32(index_reg, 0x10200);
 644         WREG32(data_reg, 0x8148BF38);
 645         WREG32(index_reg, 0x10201);
 646         WREG32(data_reg, 0x84408C80);
 647         WREG32(index_reg, 0x10202);
 648         WREG32(data_reg, 0x8008BEB8);
 649         WREG32(index_reg, 0x10300);
 650         WREG32(data_reg, 0x80B0BF78);
 651         WREG32(index_reg, 0x10301);
 652         WREG32(data_reg, 0x85008C20);
 653         WREG32(index_reg, 0x10302);
 654         WREG32(data_reg, 0x8020BEA0);
 655         WREG32(index_reg, 0x10400);
 656         WREG32(data_reg, 0x8028BF90);
 657         WREG32(index_reg, 0x10401);
 658         WREG32(data_reg, 0x85E08BC0);
 659         WREG32(index_reg, 0x10402);
 660         WREG32(data_reg, 0x8018BE90);
 661         WREG32(index_reg, 0x10500);
 662         WREG32(data_reg, 0xBFB8BFB0);
 663         WREG32(index_reg, 0x10501);
 664         WREG32(data_reg, 0x86C08B40);
 665         WREG32(index_reg, 0x10502);
 666         WREG32(data_reg, 0x8010BE90);
 667         WREG32(index_reg, 0x10600);
 668         WREG32(data_reg, 0xBF58BFC8);
 669         WREG32(index_reg, 0x10601);
 670         WREG32(data_reg, 0x87A08AA0);
 671         WREG32(index_reg, 0x10602);
 672         WREG32(data_reg, 0x8010BE98);
 673         WREG32(index_reg, 0x10700);
 674         WREG32(data_reg, 0xBF10BFF0);
 675         WREG32(index_reg, 0x10701);
 676         WREG32(data_reg, 0x886089E0);
 677         WREG32(index_reg, 0x10702);
 678         WREG32(data_reg, 0x8018BEB0);
 679         WREG32(index_reg, 0x10800);
 680         WREG32(data_reg, 0xBED8BFE8);
 681         WREG32(index_reg, 0x10801);
 682         WREG32(data_reg, 0x89408940);
 683         WREG32(index_reg, 0x10802);
 684         WREG32(data_reg, 0xBFE8BED8);
 685         WREG32(index_reg, 0x20000);
 686         WREG32(data_reg, 0x80008000);
 687         WREG32(index_reg, 0x20001);
 688         WREG32(data_reg, 0x90008000);
 689         WREG32(index_reg, 0x20002);
 690         WREG32(data_reg, 0x80008000);
 691         WREG32(index_reg, 0x20003);
 692         WREG32(data_reg, 0x80008000);
 693         WREG32(index_reg, 0x20100);
 694         WREG32(data_reg, 0x80108000);
 695         WREG32(index_reg, 0x20101);
 696         WREG32(data_reg, 0x8FE0BF70);
 697         WREG32(index_reg, 0x20102);
 698         WREG32(data_reg, 0xBFE880C0);
 699         WREG32(index_reg, 0x20103);
 700         WREG32(data_reg, 0x80008000);
 701         WREG32(index_reg, 0x20200);
 702         WREG32(data_reg, 0x8018BFF8);
 703         WREG32(index_reg, 0x20201);
 704         WREG32(data_reg, 0x8F80BF08);
 705         WREG32(index_reg, 0x20202);
 706         WREG32(data_reg, 0xBFD081A0);
 707         WREG32(index_reg, 0x20203);
 708         WREG32(data_reg, 0xBFF88000);
 709         WREG32(index_reg, 0x20300);
 710         WREG32(data_reg, 0x80188000);
 711         WREG32(index_reg, 0x20301);
 712         WREG32(data_reg, 0x8EE0BEC0);
 713         WREG32(index_reg, 0x20302);
 714         WREG32(data_reg, 0xBFB082A0);
 715         WREG32(index_reg, 0x20303);
 716         WREG32(data_reg, 0x80008000);
 717         WREG32(index_reg, 0x20400);
 718         WREG32(data_reg, 0x80188000);
 719         WREG32(index_reg, 0x20401);
 720         WREG32(data_reg, 0x8E00BEA0);
 721         WREG32(index_reg, 0x20402);
 722         WREG32(data_reg, 0xBF8883C0);
 723         WREG32(index_reg, 0x20403);
 724         WREG32(data_reg, 0x80008000);
 725         WREG32(index_reg, 0x20500);
 726         WREG32(data_reg, 0x80188000);
 727         WREG32(index_reg, 0x20501);
 728         WREG32(data_reg, 0x8D00BE90);
 729         WREG32(index_reg, 0x20502);
 730         WREG32(data_reg, 0xBF588500);
 731         WREG32(index_reg, 0x20503);
 732         WREG32(data_reg, 0x80008008);
 733         WREG32(index_reg, 0x20600);
 734         WREG32(data_reg, 0x80188000);
 735         WREG32(index_reg, 0x20601);
 736         WREG32(data_reg, 0x8BC0BE98);
 737         WREG32(index_reg, 0x20602);
 738         WREG32(data_reg, 0xBF308660);
 739         WREG32(index_reg, 0x20603);
 740         WREG32(data_reg, 0x80008008);
 741         WREG32(index_reg, 0x20700);
 742         WREG32(data_reg, 0x80108000);
 743         WREG32(index_reg, 0x20701);
 744         WREG32(data_reg, 0x8A80BEB0);
 745         WREG32(index_reg, 0x20702);
 746         WREG32(data_reg, 0xBF0087C0);
 747         WREG32(index_reg, 0x20703);
 748         WREG32(data_reg, 0x80008008);
 749         WREG32(index_reg, 0x20800);
 750         WREG32(data_reg, 0x80108000);
 751         WREG32(index_reg, 0x20801);
 752         WREG32(data_reg, 0x8920BED0);
 753         WREG32(index_reg, 0x20802);
 754         WREG32(data_reg, 0xBED08920);
 755         WREG32(index_reg, 0x20803);
 756         WREG32(data_reg, 0x80008010);
 757         WREG32(index_reg, 0x30000);
 758         WREG32(data_reg, 0x90008000);
 759         WREG32(index_reg, 0x30001);
 760         WREG32(data_reg, 0x80008000);
 761         WREG32(index_reg, 0x30100);
 762         WREG32(data_reg, 0x8FE0BF90);
 763         WREG32(index_reg, 0x30101);
 764         WREG32(data_reg, 0xBFF880A0);
 765         WREG32(index_reg, 0x30200);
 766         WREG32(data_reg, 0x8F60BF40);
 767         WREG32(index_reg, 0x30201);
 768         WREG32(data_reg, 0xBFE88180);
 769         WREG32(index_reg, 0x30300);
 770         WREG32(data_reg, 0x8EC0BF00);
 771         WREG32(index_reg, 0x30301);
 772         WREG32(data_reg, 0xBFC88280);
 773         WREG32(index_reg, 0x30400);
 774         WREG32(data_reg, 0x8DE0BEE0);
 775         WREG32(index_reg, 0x30401);
 776         WREG32(data_reg, 0xBFA083A0);
 777         WREG32(index_reg, 0x30500);
 778         WREG32(data_reg, 0x8CE0BED0);
 779         WREG32(index_reg, 0x30501);
 780         WREG32(data_reg, 0xBF7884E0);
 781         WREG32(index_reg, 0x30600);
 782         WREG32(data_reg, 0x8BA0BED8);
 783         WREG32(index_reg, 0x30601);
 784         WREG32(data_reg, 0xBF508640);
 785         WREG32(index_reg, 0x30700);
 786         WREG32(data_reg, 0x8A60BEE8);
 787         WREG32(index_reg, 0x30701);
 788         WREG32(data_reg, 0xBF2087A0);
 789         WREG32(index_reg, 0x30800);
 790         WREG32(data_reg, 0x8900BF00);
 791         WREG32(index_reg, 0x30801);
 792         WREG32(data_reg, 0xBF008900);
 793 }
 794
 795 struct rv515_watermark {
 796         u32        lb_request_fifo_depth;
 797         fixed20_12 num_line_pair;
 798         fixed20_12 estimated_width;
 799         fixed20_12 worst_case_latency;
 800         fixed20_12 consumption_rate;
 801         fixed20_12 active_time;
 802         fixed20_12 dbpp;
 803         fixed20_12 priority_mark_max;
 804         fixed20_12 priority_mark;
 805         fixed20_12 sclk;
 806 };
 807
 808 void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
 809                                   struct radeon_crtc *crtc,
 810                                   struct rv515_watermark *wm)
 811 {
 812         struct drm_display_mode *mode = &crtc->base.mode;
 813         fixed20_12 a, b, c;
 814         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
 815         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
 816
 817         if (!crtc->base.enabled) {
 818                 /* FIXME: wouldn't it better to set priority mark to maximum */
 819                 wm->lb_request_fifo_depth = 4;
 820                 return;
 821         }
 822
 823         if (crtc->vsc.full > dfixed_const(2))
 824                 wm->num_line_pair.full = dfixed_const(2);
 825         else
 826                 wm->num_line_pair.full = dfixed_const(1);
 827
 828         b.full = dfixed_const(mode->crtc_hdisplay);
 829         c.full = dfixed_const(256);
 830         a.full = dfixed_div(b, c);
 831         request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
 832         request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
 833         if (a.full < dfixed_const(4)) {
 834                 wm->lb_request_fifo_depth = 4;
 835         } else {
 836                 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
 837         }
 838
 839         /* Determine consumption rate
 840          *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
 841          *  vtaps = number of vertical taps,
 842          *  vsc = vertical scaling ratio, defined as source/destination
 843          *  hsc = horizontal scaling ration, defined as source/destination
 844          */
 845         a.full = dfixed_const(mode->clock);
 846         b.full = dfixed_const(1000);
 847         a.full = dfixed_div(a, b);
 848         pclk.full = dfixed_div(b, a);
 849         if (crtc->rmx_type != RMX_OFF) {
 850                 b.full = dfixed_const(2);
 851                 if (crtc->vsc.full > b.full)
 852                         b.full = crtc->vsc.full;
 853                 b.full = dfixed_mul(b, crtc->hsc);
 854                 c.full = dfixed_const(2);
 855                 b.full = dfixed_div(b, c);
 856                 consumption_time.full = dfixed_div(pclk, b);
 857         } else {
 858                 consumption_time.full = pclk.full;
 859         }
 860         a.full = dfixed_const(1);
 861         wm->consumption_rate.full = dfixed_div(a, consumption_time);
 862
 863
 864         /* Determine line time
 865          *  LineTime = total time for one line of displayhtotal
 866          *  LineTime = total number of horizontal pixels
 867          *  pclk = pixel clock period(ns)
 868          */
 869         a.full = dfixed_const(crtc->base.mode.crtc_htotal);
 870         line_time.full = dfixed_mul(a, pclk);
 871
 872         /* Determine active time
 873          *  ActiveTime = time of active region of display within one line,
 874          *  hactive = total number of horizontal active pixels
 875          *  htotal = total number of horizontal pixels
 876          */
 877         a.full = dfixed_const(crtc->base.mode.crtc_htotal);
 878         b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
 879         wm->active_time.full = dfixed_mul(line_time, b);
 880         wm->active_time.full = dfixed_div(wm->active_time, a);
 881
 882         /* Determine chunk time
 883          * ChunkTime = the time it takes the DCP to send one chunk of data
 884          * to the LB which consists of pipeline delay and inter chunk gap
 885          * sclk = system clock(Mhz)
 886          */
 887         a.full = dfixed_const(600 * 1000);
 888         chunk_time.full = dfixed_div(a, rdev->pm.sclk);
 889         read_delay_latency.full = dfixed_const(1000);
 890
 891         /* Determine the worst case latency
 892          * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
 893          * WorstCaseLatency = worst case time from urgent to when the MC starts
 894          *                    to return data
 895          * READ_DELAY_IDLE_MAX = constant of 1us
 896          * ChunkTime = time it takes the DCP to send one chunk of data to the LB
 897          *             which consists of pipeline delay and inter chunk gap
 898          */
 899         if (dfixed_trunc(wm->num_line_pair) > 1) {
 900                 a.full = dfixed_const(3);
 901                 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
 902                 wm->worst_case_latency.full += read_delay_latency.full;
 903         } else {
 904                 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
 905         }
 906
 907         /* Determine the tolerable latency
 908          * TolerableLatency = Any given request has only 1 line time
 909          *                    for the data to be returned
 910          * LBRequestFifoDepth = Number of chunk requests the LB can
 911          *                      put into the request FIFO for a display
 912          *  LineTime = total time for one line of display
 913          *  ChunkTime = the time it takes the DCP to send one chunk
 914          *              of data to the LB which consists of
 915          *  pipeline delay and inter chunk gap
 916          */
 917         if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
 918                 tolerable_latency.full = line_time.full;
 919         } else {
 920                 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
 921                 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
 922                 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
 923                 tolerable_latency.full = line_time.full - tolerable_latency.full;
 924         }
 925         /* We assume worst case 32bits (4 bytes) */
 926         wm->dbpp.full = dfixed_const(2 * 16);
 927
 928         /* Determine the maximum priority mark
 929          *  width = viewport width in pixels
 930          */
 931         a.full = dfixed_const(16);
 932         wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
 933         wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
 934         wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
 935
 936         /* Determine estimated width */
 937         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
 938         estimated_width.full = dfixed_div(estimated_width, consumption_time);
 939         if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
 940                 wm->priority_mark.full = wm->priority_mark_max.full;
 941         } else {
 942                 a.full = dfixed_const(16);
 943                 wm->priority_mark.full = dfixed_div(estimated_width, a);
 944                 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
 945                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
 946         }
 947 }
 948
 949 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
 950 {
 951         struct drm_display_mode *mode0 = NULL;
 952         struct drm_display_mode *mode1 = NULL;
 953         struct rv515_watermark wm0;
 954         struct rv515_watermark wm1;
 955         u32 tmp;
 956         u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
 957         u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
 958         fixed20_12 priority_mark02, priority_mark12, fill_rate;
 959         fixed20_12 a, b;
 960
 961         if (rdev->mode_info.crtcs[0]->base.enabled)
 962                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
 963         if (rdev->mode_info.crtcs[1]->base.enabled)
 964                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 965         rs690_line_buffer_adjust(rdev, mode0, mode1);
 966
 967         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
 968         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
 969
 970         tmp = wm0.lb_request_fifo_depth;
 971         tmp |= wm1.lb_request_fifo_depth << 16;
 972         WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
 973
 974         if (mode0 && mode1) {
 975                 if (dfixed_trunc(wm0.dbpp) > 64)
 976                         a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
 977                 else
 978                         a.full = wm0.num_line_pair.full;
 979                 if (dfixed_trunc(wm1.dbpp) > 64)
 980                         b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
 981                 else
 982                         b.full = wm1.num_line_pair.full;
 983                 a.full += b.full;
 984                 fill_rate.full = dfixed_div(wm0.sclk, a);
 985                 if (wm0.consumption_rate.full > fill_rate.full) {
 986                         b.full = wm0.consumption_rate.full - fill_rate.full;
 987                         b.full = dfixed_mul(b, wm0.active_time);
 988                         a.full = dfixed_const(16);
 989                         b.full = dfixed_div(b, a);
 990                         a.full = dfixed_mul(wm0.worst_case_latency,
 991                                                 wm0.consumption_rate);
 992                         priority_mark02.full = a.full + b.full;
 993                 } else {
 994                         a.full = dfixed_mul(wm0.worst_case_latency,
 995                                                 wm0.consumption_rate);
 996                         b.full = dfixed_const(16 * 1000);
 997                         priority_mark02.full = dfixed_div(a, b);
 998                 }
 999                 if (wm1.consumption_rate.full > fill_rate.full) {
1000                         b.full = wm1.consumption_rate.full - fill_rate.full;
1001                         b.full = dfixed_mul(b, wm1.active_time);
1002                         a.full = dfixed_const(16);
1003                         b.full = dfixed_div(b, a);
1004                         a.full = dfixed_mul(wm1.worst_case_latency,
1005                                                 wm1.consumption_rate);
1006                         priority_mark12.full = a.full + b.full;
1007                 } else {
1008                         a.full = dfixed_mul(wm1.worst_case_latency,
1009                                                 wm1.consumption_rate);
1010                         b.full = dfixed_const(16 * 1000);
1011                         priority_mark12.full = dfixed_div(a, b);
1012                 }
1013                 if (wm0.priority_mark.full > priority_mark02.full)
1014                         priority_mark02.full = wm0.priority_mark.full;
1015                 if (dfixed_trunc(priority_mark02) < 0)
1016                         priority_mark02.full = 0;
1017                 if (wm0.priority_mark_max.full > priority_mark02.full)
1018                         priority_mark02.full = wm0.priority_mark_max.full;
1019                 if (wm1.priority_mark.full > priority_mark12.full)
1020                         priority_mark12.full = wm1.priority_mark.full;
1021                 if (dfixed_trunc(priority_mark12) < 0)
1022                         priority_mark12.full = 0;
1023                 if (wm1.priority_mark_max.full > priority_mark12.full)
1024                         priority_mark12.full = wm1.priority_mark_max.full;
1025                 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1026                 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1027                 if (rdev->disp_priority == 2) {
1028                         d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1029                         d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1030                 }
1031         } else if (mode0) {
1032                 if (dfixed_trunc(wm0.dbpp) > 64)
1033                         a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
1034                 else
1035                         a.full = wm0.num_line_pair.full;
1036                 fill_rate.full = dfixed_div(wm0.sclk, a);
1037                 if (wm0.consumption_rate.full > fill_rate.full) {
1038                         b.full = wm0.consumption_rate.full - fill_rate.full;
1039                         b.full = dfixed_mul(b, wm0.active_time);
1040                         a.full = dfixed_const(16);
1041                         b.full = dfixed_div(b, a);
1042                         a.full = dfixed_mul(wm0.worst_case_latency,
1043                                                 wm0.consumption_rate);
1044                         priority_mark02.full = a.full + b.full;
1045                 } else {
1046                         a.full = dfixed_mul(wm0.worst_case_latency,
1047                                                 wm0.consumption_rate);
1048                         b.full = dfixed_const(16);
1049                         priority_mark02.full = dfixed_div(a, b);
1050                 }
1051                 if (wm0.priority_mark.full > priority_mark02.full)
1052                         priority_mark02.full = wm0.priority_mark.full;
1053                 if (dfixed_trunc(priority_mark02) < 0)
1054                         priority_mark02.full = 0;
1055                 if (wm0.priority_mark_max.full > priority_mark02.full)
1056                         priority_mark02.full = wm0.priority_mark_max.full;
1057                 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1058                 if (rdev->disp_priority == 2)
1059                         d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1060         } else if (mode1) {
1061                 if (dfixed_trunc(wm1.dbpp) > 64)
1062                         a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
1063                 else
1064                         a.full = wm1.num_line_pair.full;
1065                 fill_rate.full = dfixed_div(wm1.sclk, a);
1066                 if (wm1.consumption_rate.full > fill_rate.full) {
1067                         b.full = wm1.consumption_rate.full - fill_rate.full;
1068                         b.full = dfixed_mul(b, wm1.active_time);
1069                         a.full = dfixed_const(16);
1070                         b.full = dfixed_div(b, a);
1071                         a.full = dfixed_mul(wm1.worst_case_latency,
1072                                                 wm1.consumption_rate);
1073                         priority_mark12.full = a.full + b.full;
1074                 } else {
1075                         a.full = dfixed_mul(wm1.worst_case_latency,
1076                                                 wm1.consumption_rate);
1077                         b.full = dfixed_const(16 * 1000);
1078                         priority_mark12.full = dfixed_div(a, b);
1079                 }
1080                 if (wm1.priority_mark.full > priority_mark12.full)
1081                         priority_mark12.full = wm1.priority_mark.full;
1082                 if (dfixed_trunc(priority_mark12) < 0)
1083                         priority_mark12.full = 0;
1084                 if (wm1.priority_mark_max.full > priority_mark12.full)
1085                         priority_mark12.full = wm1.priority_mark_max.full;
1086                 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1087                 if (rdev->disp_priority == 2)
1088                         d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1089         }
1090
1091         WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1092         WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
1093         WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1094         WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
1095 }
1096
1097 void rv515_bandwidth_update(struct radeon_device *rdev)
1098 {
1099         uint32_t tmp;
1100         struct drm_display_mode *mode0 = NULL;
1101         struct drm_display_mode *mode1 = NULL;
1102
1103         radeon_update_display_priority(rdev);
1104
1105         if (rdev->mode_info.crtcs[0]->base.enabled)
1106                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1107         if (rdev->mode_info.crtcs[1]->base.enabled)
1108                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1109         /*
1110          * Set display0/1 priority up in the memory controller for
1111          * modes if the user specifies HIGH for displaypriority
1112          * option.
1113          */
1114         if ((rdev->disp_priority == 2) &&
1115             (rdev->family == CHIP_RV515)) {
1116                 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1117                 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1118                 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1119                 if (mode1)
1120                         tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1121                 if (mode0)
1122                         tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1123                 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1124         }
1125         rv515_bandwidth_avivo_update(rdev);
1126 }