drivers/gpu/drm/radeon/rv770.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/firmware.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34 #include "radeon_drm.h"
  35 #include "rv770d.h"
  36 #include "atom.h"
  37 #include "avivod.h"
  38
  39 #define R700_PFP_UCODE_SIZE 848
  40 #define R700_PM4_UCODE_SIZE 1360
  41
  42 static void rv770_gpu_init(struct radeon_device *rdev);
  43 void rv770_fini(struct radeon_device *rdev);
  44 static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
  45
  46 u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  47 {
  48         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  49         u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
  50
  51         /* Lock the graphics update lock */
  52         tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
  53         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  54
  55         /* update the scanout addresses */
  56         if (radeon_crtc->crtc_id) {
  57                 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  58                 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  59         } else {
  60                 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  61                 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  62         }
  63         WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  64                (u32)crtc_base);
  65         WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  66                (u32)crtc_base);
  67
  68         /* Wait for update_pending to go high. */
  69         while (!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING));
  70         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
  71
  72         /* Unlock the lock, so double-buffering can take place inside vblank */
  73         tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
  74         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  75
  76         /* Return current update_pending status: */
  77         return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
  78 }
  79
  80 /* get temperature in millidegrees */
  81 int rv770_get_temp(struct radeon_device *rdev)
  82 {
  83         u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
  84                 ASIC_T_SHIFT;
  85         int actual_temp;
  86
  87         if (temp & 0x400)
  88                 actual_temp = -256;
  89         else if (temp & 0x200)
  90                 actual_temp = 255;
  91         else if (temp & 0x100) {
  92                 actual_temp = temp & 0x1ff;
  93                 actual_temp |= ~0x1ff;
  94         } else
  95                 actual_temp = temp & 0xff;
  96
  97         return (actual_temp * 1000) / 2;
  98 }
  99
 100 void rv770_pm_misc(struct radeon_device *rdev)
 101 {
 102         int req_ps_idx = rdev->pm.requested_power_state_index;
 103         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 104         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 105         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 106
 107         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 108                 /* 0xff01 is a flag rather then an actual voltage */
 109                 if (voltage->voltage == 0xff01)
 110                         return;
 111                 if (voltage->voltage != rdev->pm.current_vddc) {
 112                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 113                         rdev->pm.current_vddc = voltage->voltage;
 114                         DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
 115                 }
 116         }
 117 }
 118
 119 /*
 120  * GART
 121  */
 122 int rv770_pcie_gart_enable(struct radeon_device *rdev)
 123 {
 124         u32 tmp;
 125         int r, i;
 126
 127         if (rdev->gart.table.vram.robj == NULL) {
 128                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 129                 return -EINVAL;
 130         }
 131         r = radeon_gart_table_vram_pin(rdev);
 132         if (r)
 133                 return r;
 134         radeon_gart_restore(rdev);
 135         /* Setup L2 cache */
 136         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 137                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 138                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 139         WREG32(VM_L2_CNTL2, 0);
 140         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 141         /* Setup TLB control */
 142         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 143                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 144                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 145                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 146         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 147         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 148         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 149         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 150         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 151         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 152         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 153         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 154         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 155         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 156         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 157                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 158         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 159                         (u32)(rdev->dummy_page.addr >> 12));
 160         for (i = 1; i < 7; i++)
 161                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 162
 163         r600_pcie_gart_tlb_flush(rdev);
 164         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 165                  (unsigned)(rdev->mc.gtt_size >> 20),
 166                  (unsigned long long)rdev->gart.table_addr);
 167         rdev->gart.ready = true;
 168         return 0;
 169 }
 170
 171 void rv770_pcie_gart_disable(struct radeon_device *rdev)
 172 {
 173         u32 tmp;
 174         int i, r;
 175
 176         /* Disable all tables */
 177         for (i = 0; i < 7; i++)
 178                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 179
 180         /* Setup L2 cache */
 181         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 182                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 183         WREG32(VM_L2_CNTL2, 0);
 184         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 185         /* Setup TLB control */
 186         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 187         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 188         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 189         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 190         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 191         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 192         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 193         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 194         if (rdev->gart.table.vram.robj) {
 195                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 196                 if (likely(r == 0)) {
 197                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 198                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 199                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 200                 }
 201         }
 202 }
 203
 204 void rv770_pcie_gart_fini(struct radeon_device *rdev)
 205 {
 206         radeon_gart_fini(rdev);
 207         rv770_pcie_gart_disable(rdev);
 208         radeon_gart_table_vram_free(rdev);
 209 }
 210
 211
 212 void rv770_agp_enable(struct radeon_device *rdev)
 213 {
 214         u32 tmp;
 215         int i;
 216
 217         /* Setup L2 cache */
 218         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 219                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 220                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 221         WREG32(VM_L2_CNTL2, 0);
 222         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 223         /* Setup TLB control */
 224         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 225                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 226                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 227                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 228         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 229         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 230         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 231         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 232         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 233         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 234         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 235         for (i = 0; i < 7; i++)
 236                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 237 }
 238
 239 static void rv770_mc_program(struct radeon_device *rdev)
 240 {
 241         struct rv515_mc_save save;
 242         u32 tmp;
 243         int i, j;
 244
 245         /* Initialize HDP */
 246         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 247                 WREG32((0x2c14 + j), 0x00000000);
 248                 WREG32((0x2c18 + j), 0x00000000);
 249                 WREG32((0x2c1c + j), 0x00000000);
 250                 WREG32((0x2c20 + j), 0x00000000);
 251                 WREG32((0x2c24 + j), 0x00000000);
 252         }
 253         /* r7xx hw bug.  Read from HDP_DEBUG1 rather
 254          * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
 255          */
 256         tmp = RREG32(HDP_DEBUG1);
 257
 258         rv515_mc_stop(rdev, &save);
 259         if (r600_mc_wait_for_idle(rdev)) {
 260                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 261         }
 262         /* Lockout access through VGA aperture*/
 263         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 264         /* Update configuration */
 265         if (rdev->flags & RADEON_IS_AGP) {
 266                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 267                         /* VRAM before AGP */
 268                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 269                                 rdev->mc.vram_start >> 12);
 270                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 271                                 rdev->mc.gtt_end >> 12);
 272                 } else {
 273                         /* VRAM after AGP */
 274                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 275                                 rdev->mc.gtt_start >> 12);
 276                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 277                                 rdev->mc.vram_end >> 12);
 278                 }
 279         } else {
 280                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 281                         rdev->mc.vram_start >> 12);
 282                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 283                         rdev->mc.vram_end >> 12);
 284         }
 285         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 286         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 287         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 288         WREG32(MC_VM_FB_LOCATION, tmp);
 289         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 290         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 291         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 292         if (rdev->flags & RADEON_IS_AGP) {
 293                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
 294                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
 295                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 296         } else {
 297                 WREG32(MC_VM_AGP_BASE, 0);
 298                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 299                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 300         }
 301         if (r600_mc_wait_for_idle(rdev)) {
 302                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 303         }
 304         rv515_mc_resume(rdev, &save);
 305         /* we need to own VRAM, so turn off the VGA renderer here
 306          * to stop it overwriting our objects */
 307         rv515_vga_render_disable(rdev);
 308 }
 309
 310
 311 /*
 312  * CP.
 313  */
 314 void r700_cp_stop(struct radeon_device *rdev)
 315 {
 316         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 317         WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
 318         WREG32(SCRATCH_UMSK, 0);
 319 }
 320
 321 static int rv770_cp_load_microcode(struct radeon_device *rdev)
 322 {
 323         const __be32 *fw_data;
 324         int i;
 325
 326         if (!rdev->me_fw || !rdev->pfp_fw)
 327                 return -EINVAL;
 328
 329         r700_cp_stop(rdev);
 330         WREG32(CP_RB_CNTL,
 331 #ifdef __BIG_ENDIAN
 332                BUF_SWAP_32BIT |
 333 #endif
 334                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
 335
 336         /* Reset cp */
 337         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
 338         RREG32(GRBM_SOFT_RESET);
 339         mdelay(15);
 340         WREG32(GRBM_SOFT_RESET, 0);
 341
 342         fw_data = (const __be32 *)rdev->pfp_fw->data;
 343         WREG32(CP_PFP_UCODE_ADDR, 0);
 344         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
 345                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
 346         WREG32(CP_PFP_UCODE_ADDR, 0);
 347
 348         fw_data = (const __be32 *)rdev->me_fw->data;
 349         WREG32(CP_ME_RAM_WADDR, 0);
 350         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
 351                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
 352
 353         WREG32(CP_PFP_UCODE_ADDR, 0);
 354         WREG32(CP_ME_RAM_WADDR, 0);
 355         WREG32(CP_ME_RAM_RADDR, 0);
 356         return 0;
 357 }
 358
 359 void r700_cp_fini(struct radeon_device *rdev)
 360 {
 361         r700_cp_stop(rdev);
 362         radeon_ring_fini(rdev);
 363 }
 364
 365 /*
 366  * Core functions
 367  */
 368 static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
 369                                              u32 num_tile_pipes,
 370                                              u32 num_backends,
 371                                              u32 backend_disable_mask)
 372 {
 373         u32 backend_map = 0;
 374         u32 enabled_backends_mask;
 375         u32 enabled_backends_count;
 376         u32 cur_pipe;
 377         u32 swizzle_pipe[R7XX_MAX_PIPES];
 378         u32 cur_backend;
 379         u32 i;
 380         bool force_no_swizzle;
 381
 382         if (num_tile_pipes > R7XX_MAX_PIPES)
 383                 num_tile_pipes = R7XX_MAX_PIPES;
 384         if (num_tile_pipes < 1)
 385                 num_tile_pipes = 1;
 386         if (num_backends > R7XX_MAX_BACKENDS)
 387                 num_backends = R7XX_MAX_BACKENDS;
 388         if (num_backends < 1)
 389                 num_backends = 1;
 390
 391         enabled_backends_mask = 0;
 392         enabled_backends_count = 0;
 393         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
 394                 if (((backend_disable_mask >> i) & 1) == 0) {
 395                         enabled_backends_mask |= (1 << i);
 396                         ++enabled_backends_count;
 397                 }
 398                 if (enabled_backends_count == num_backends)
 399                         break;
 400         }
 401
 402         if (enabled_backends_count == 0) {
 403                 enabled_backends_mask = 1;
 404                 enabled_backends_count = 1;
 405         }
 406
 407         if (enabled_backends_count != num_backends)
 408                 num_backends = enabled_backends_count;
 409
 410         switch (rdev->family) {
 411         case CHIP_RV770:
 412         case CHIP_RV730:
 413                 force_no_swizzle = false;
 414                 break;
 415         case CHIP_RV710:
 416         case CHIP_RV740:
 417         default:
 418                 force_no_swizzle = true;
 419                 break;
 420         }
 421
 422         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
 423         switch (num_tile_pipes) {
 424         case 1:
 425                 swizzle_pipe[0] = 0;
 426                 break;
 427         case 2:
 428                 swizzle_pipe[0] = 0;
 429                 swizzle_pipe[1] = 1;
 430                 break;
 431         case 3:
 432                 if (force_no_swizzle) {
 433                         swizzle_pipe[0] = 0;
 434                         swizzle_pipe[1] = 1;
 435                         swizzle_pipe[2] = 2;
 436                 } else {
 437                         swizzle_pipe[0] = 0;
 438                         swizzle_pipe[1] = 2;
 439                         swizzle_pipe[2] = 1;
 440                 }
 441                 break;
 442         case 4:
 443                 if (force_no_swizzle) {
 444                         swizzle_pipe[0] = 0;
 445                         swizzle_pipe[1] = 1;
 446                         swizzle_pipe[2] = 2;
 447                         swizzle_pipe[3] = 3;
 448                 } else {
 449                         swizzle_pipe[0] = 0;
 450                         swizzle_pipe[1] = 2;
 451                         swizzle_pipe[2] = 3;
 452                         swizzle_pipe[3] = 1;
 453                 }
 454                 break;
 455         case 5:
 456                 if (force_no_swizzle) {
 457                         swizzle_pipe[0] = 0;
 458                         swizzle_pipe[1] = 1;
 459                         swizzle_pipe[2] = 2;
 460                         swizzle_pipe[3] = 3;
 461                         swizzle_pipe[4] = 4;
 462                 } else {
 463                         swizzle_pipe[0] = 0;
 464                         swizzle_pipe[1] = 2;
 465                         swizzle_pipe[2] = 4;
 466                         swizzle_pipe[3] = 1;
 467                         swizzle_pipe[4] = 3;
 468                 }
 469                 break;
 470         case 6:
 471                 if (force_no_swizzle) {
 472                         swizzle_pipe[0] = 0;
 473                         swizzle_pipe[1] = 1;
 474                         swizzle_pipe[2] = 2;
 475                         swizzle_pipe[3] = 3;
 476                         swizzle_pipe[4] = 4;
 477                         swizzle_pipe[5] = 5;
 478                 } else {
 479                         swizzle_pipe[0] = 0;
 480                         swizzle_pipe[1] = 2;
 481                         swizzle_pipe[2] = 4;
 482                         swizzle_pipe[3] = 5;
 483                         swizzle_pipe[4] = 3;
 484                         swizzle_pipe[5] = 1;
 485                 }
 486                 break;
 487         case 7:
 488                 if (force_no_swizzle) {
 489                         swizzle_pipe[0] = 0;
 490                         swizzle_pipe[1] = 1;
 491                         swizzle_pipe[2] = 2;
 492                         swizzle_pipe[3] = 3;
 493                         swizzle_pipe[4] = 4;
 494                         swizzle_pipe[5] = 5;
 495                         swizzle_pipe[6] = 6;
 496                 } else {
 497                         swizzle_pipe[0] = 0;
 498                         swizzle_pipe[1] = 2;
 499                         swizzle_pipe[2] = 4;
 500                         swizzle_pipe[3] = 6;
 501                         swizzle_pipe[4] = 3;
 502                         swizzle_pipe[5] = 1;
 503                         swizzle_pipe[6] = 5;
 504                 }
 505                 break;
 506         case 8:
 507                 if (force_no_swizzle) {
 508                         swizzle_pipe[0] = 0;
 509                         swizzle_pipe[1] = 1;
 510                         swizzle_pipe[2] = 2;
 511                         swizzle_pipe[3] = 3;
 512                         swizzle_pipe[4] = 4;
 513                         swizzle_pipe[5] = 5;
 514                         swizzle_pipe[6] = 6;
 515                         swizzle_pipe[7] = 7;
 516                 } else {
 517                         swizzle_pipe[0] = 0;
 518                         swizzle_pipe[1] = 2;
 519                         swizzle_pipe[2] = 4;
 520                         swizzle_pipe[3] = 6;
 521                         swizzle_pipe[4] = 3;
 522                         swizzle_pipe[5] = 1;
 523                         swizzle_pipe[6] = 7;
 524                         swizzle_pipe[7] = 5;
 525                 }
 526                 break;
 527         }
 528
 529         cur_backend = 0;
 530         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 531                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 532                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 533
 534                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 535
 536                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 537         }
 538
 539         return backend_map;
 540 }
 541
 542 static void rv770_gpu_init(struct radeon_device *rdev)
 543 {
 544         int i, j, num_qd_pipes;
 545         u32 ta_aux_cntl;
 546         u32 sx_debug_1;
 547         u32 smx_dc_ctl0;
 548         u32 db_debug3;
 549         u32 num_gs_verts_per_thread;
 550         u32 vgt_gs_per_es;
 551         u32 gs_prim_buffer_depth = 0;
 552         u32 sq_ms_fifo_sizes;
 553         u32 sq_config;
 554         u32 sq_thread_resource_mgmt;
 555         u32 hdp_host_path_cntl;
 556         u32 sq_dyn_gpr_size_simd_ab_0;
 557         u32 backend_map;
 558         u32 gb_tiling_config = 0;
 559         u32 cc_rb_backend_disable = 0;
 560         u32 cc_gc_shader_pipe_config = 0;
 561         u32 mc_arb_ramcfg;
 562         u32 db_debug4;
 563
 564         /* setup chip specs */
 565         switch (rdev->family) {
 566         case CHIP_RV770:
 567                 rdev->config.rv770.max_pipes = 4;
 568                 rdev->config.rv770.max_tile_pipes = 8;
 569                 rdev->config.rv770.max_simds = 10;
 570                 rdev->config.rv770.max_backends = 4;
 571                 rdev->config.rv770.max_gprs = 256;
 572                 rdev->config.rv770.max_threads = 248;
 573                 rdev->config.rv770.max_stack_entries = 512;
 574                 rdev->config.rv770.max_hw_contexts = 8;
 575                 rdev->config.rv770.max_gs_threads = 16 * 2;
 576                 rdev->config.rv770.sx_max_export_size = 128;
 577                 rdev->config.rv770.sx_max_export_pos_size = 16;
 578                 rdev->config.rv770.sx_max_export_smx_size = 112;
 579                 rdev->config.rv770.sq_num_cf_insts = 2;
 580
 581                 rdev->config.rv770.sx_num_of_sets = 7;
 582                 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
 583                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 584                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 585                 break;
 586         case CHIP_RV730:
 587                 rdev->config.rv770.max_pipes = 2;
 588                 rdev->config.rv770.max_tile_pipes = 4;
 589                 rdev->config.rv770.max_simds = 8;
 590                 rdev->config.rv770.max_backends = 2;
 591                 rdev->config.rv770.max_gprs = 128;
 592                 rdev->config.rv770.max_threads = 248;
 593                 rdev->config.rv770.max_stack_entries = 256;
 594                 rdev->config.rv770.max_hw_contexts = 8;
 595                 rdev->config.rv770.max_gs_threads = 16 * 2;
 596                 rdev->config.rv770.sx_max_export_size = 256;
 597                 rdev->config.rv770.sx_max_export_pos_size = 32;
 598                 rdev->config.rv770.sx_max_export_smx_size = 224;
 599                 rdev->config.rv770.sq_num_cf_insts = 2;
 600
 601                 rdev->config.rv770.sx_num_of_sets = 7;
 602                 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
 603                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 604                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 605                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 606                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 607                         rdev->config.rv770.sx_max_export_smx_size += 16;
 608                 }
 609                 break;
 610         case CHIP_RV710:
 611                 rdev->config.rv770.max_pipes = 2;
 612                 rdev->config.rv770.max_tile_pipes = 2;
 613                 rdev->config.rv770.max_simds = 2;
 614                 rdev->config.rv770.max_backends = 1;
 615                 rdev->config.rv770.max_gprs = 256;
 616                 rdev->config.rv770.max_threads = 192;
 617                 rdev->config.rv770.max_stack_entries = 256;
 618                 rdev->config.rv770.max_hw_contexts = 4;
 619                 rdev->config.rv770.max_gs_threads = 8 * 2;
 620                 rdev->config.rv770.sx_max_export_size = 128;
 621                 rdev->config.rv770.sx_max_export_pos_size = 16;
 622                 rdev->config.rv770.sx_max_export_smx_size = 112;
 623                 rdev->config.rv770.sq_num_cf_insts = 1;
 624
 625                 rdev->config.rv770.sx_num_of_sets = 7;
 626                 rdev->config.rv770.sc_prim_fifo_size = 0x40;
 627                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 628                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 629                 break;
 630         case CHIP_RV740:
 631                 rdev->config.rv770.max_pipes = 4;
 632                 rdev->config.rv770.max_tile_pipes = 4;
 633                 rdev->config.rv770.max_simds = 8;
 634                 rdev->config.rv770.max_backends = 4;
 635                 rdev->config.rv770.max_gprs = 256;
 636                 rdev->config.rv770.max_threads = 248;
 637                 rdev->config.rv770.max_stack_entries = 512;
 638                 rdev->config.rv770.max_hw_contexts = 8;
 639                 rdev->config.rv770.max_gs_threads = 16 * 2;
 640                 rdev->config.rv770.sx_max_export_size = 256;
 641                 rdev->config.rv770.sx_max_export_pos_size = 32;
 642                 rdev->config.rv770.sx_max_export_smx_size = 224;
 643                 rdev->config.rv770.sq_num_cf_insts = 2;
 644
 645                 rdev->config.rv770.sx_num_of_sets = 7;
 646                 rdev->config.rv770.sc_prim_fifo_size = 0x100;
 647                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 648                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 649
 650                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 651                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 652                         rdev->config.rv770.sx_max_export_smx_size += 16;
 653                 }
 654                 break;
 655         default:
 656                 break;
 657         }
 658
 659         /* Initialize HDP */
 660         j = 0;
 661         for (i = 0; i < 32; i++) {
 662                 WREG32((0x2c14 + j), 0x00000000);
 663                 WREG32((0x2c18 + j), 0x00000000);
 664                 WREG32((0x2c1c + j), 0x00000000);
 665                 WREG32((0x2c20 + j), 0x00000000);
 666                 WREG32((0x2c24 + j), 0x00000000);
 667                 j += 0x18;
 668         }
 669
 670         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 671
 672         /* setup tiling, simd, pipe config */
 673         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 674
 675         switch (rdev->config.rv770.max_tile_pipes) {
 676         case 1:
 677         default:
 678                 gb_tiling_config |= PIPE_TILING(0);
 679                 break;
 680         case 2:
 681                 gb_tiling_config |= PIPE_TILING(1);
 682                 break;
 683         case 4:
 684                 gb_tiling_config |= PIPE_TILING(2);
 685                 break;
 686         case 8:
 687                 gb_tiling_config |= PIPE_TILING(3);
 688                 break;
 689         }
 690         rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
 691
 692         if (rdev->family == CHIP_RV770)
 693                 gb_tiling_config |= BANK_TILING(1);
 694         else
 695                 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
 696         rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
 697         gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
 698         if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
 699                 rdev->config.rv770.tiling_group_size = 512;
 700         else
 701                 rdev->config.rv770.tiling_group_size = 256;
 702         if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
 703                 gb_tiling_config |= ROW_TILING(3);
 704                 gb_tiling_config |= SAMPLE_SPLIT(3);
 705         } else {
 706                 gb_tiling_config |=
 707                         ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 708                 gb_tiling_config |=
 709                         SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 710         }
 711
 712         gb_tiling_config |= BANK_SWAPS(1);
 713
 714         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
 715         cc_rb_backend_disable |=
 716                 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
 717
 718         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
 719         cc_gc_shader_pipe_config |=
 720                 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
 721         cc_gc_shader_pipe_config |=
 722                 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
 723
 724         if (rdev->family == CHIP_RV740)
 725                 backend_map = 0x28;
 726         else
 727                 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
 728                                                                 rdev->config.rv770.max_tile_pipes,
 729                                                                 (R7XX_MAX_BACKENDS -
 730                                                                  r600_count_pipe_bits((cc_rb_backend_disable &
 731                                                                                        R7XX_MAX_BACKENDS_MASK) >> 16)),
 732                                                                 (cc_rb_backend_disable >> 16));
 733
 734         rdev->config.rv770.tile_config = gb_tiling_config;
 735         rdev->config.rv770.backend_map = backend_map;
 736         gb_tiling_config |= BACKEND_MAP(backend_map);
 737
 738         WREG32(GB_TILING_CONFIG, gb_tiling_config);
 739         WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 740         WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 741
 742         WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
 743         WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
 744         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 745         WREG32(CC_SYS_RB_BACKEND_DISABLE,  cc_rb_backend_disable);
 746
 747         WREG32(CGTS_SYS_TCC_DISABLE, 0);
 748         WREG32(CGTS_TCC_DISABLE, 0);
 749         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
 750         WREG32(CGTS_USER_TCC_DISABLE, 0);
 751
 752         num_qd_pipes =
 753                 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
 754         WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
 755         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
 756
 757         /* set HW defaults for 3D engine */
 758         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
 759                                      ROQ_IB2_START(0x2b)));
 760
 761         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
 762
 763         ta_aux_cntl = RREG32(TA_CNTL_AUX);
 764         WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
 765
 766         sx_debug_1 = RREG32(SX_DEBUG_1);
 767         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
 768         WREG32(SX_DEBUG_1, sx_debug_1);
 769
 770         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
 771         smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
 772         smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
 773         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 774
 775         if (rdev->family != CHIP_RV740)
 776                 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
 777                                        GS_FLUSH_CTL(4) |
 778                                        ACK_FLUSH_CTL(3) |
 779                                        SYNC_FLUSH_CTL));
 780
 781         db_debug3 = RREG32(DB_DEBUG3);
 782         db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
 783         switch (rdev->family) {
 784         case CHIP_RV770:
 785         case CHIP_RV740:
 786                 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
 787                 break;
 788         case CHIP_RV710:
 789         case CHIP_RV730:
 790         default:
 791                 db_debug3 |= DB_CLK_OFF_DELAY(2);
 792                 break;
 793         }
 794         WREG32(DB_DEBUG3, db_debug3);
 795
 796         if (rdev->family != CHIP_RV770) {
 797                 db_debug4 = RREG32(DB_DEBUG4);
 798                 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
 799                 WREG32(DB_DEBUG4, db_debug4);
 800         }
 801
 802         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
 803                                         POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
 804                                         SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
 805
 806         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
 807                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
 808                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
 809
 810         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 811
 812         WREG32(VGT_NUM_INSTANCES, 1);
 813
 814         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
 815
 816         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
 817
 818         WREG32(CP_PERFMON_CNTL, 0);
 819
 820         sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
 821                             DONE_FIFO_HIWATER(0xe0) |
 822                             ALU_UPDATE_FIFO_HIWATER(0x8));
 823         switch (rdev->family) {
 824         case CHIP_RV770:
 825         case CHIP_RV730:
 826         case CHIP_RV710:
 827                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
 828                 break;
 829         case CHIP_RV740:
 830         default:
 831                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
 832                 break;
 833         }
 834         WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
 835
 836         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 837          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 838          */
 839         sq_config = RREG32(SQ_CONFIG);
 840         sq_config &= ~(PS_PRIO(3) |
 841                        VS_PRIO(3) |
 842                        GS_PRIO(3) |
 843                        ES_PRIO(3));
 844         sq_config |= (DX9_CONSTS |
 845                       VC_ENABLE |
 846                       EXPORT_SRC_C |
 847                       PS_PRIO(0) |
 848                       VS_PRIO(1) |
 849                       GS_PRIO(2) |
 850                       ES_PRIO(3));
 851         if (rdev->family == CHIP_RV710)
 852                 /* no vertex cache */
 853                 sq_config &= ~VC_ENABLE;
 854
 855         WREG32(SQ_CONFIG, sq_config);
 856
 857         WREG32(SQ_GPR_RESOURCE_MGMT_1,  (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 858                                          NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 859                                          NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
 860
 861         WREG32(SQ_GPR_RESOURCE_MGMT_2,  (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
 862                                          NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
 863
 864         sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
 865                                    NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
 866                                    NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
 867         if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
 868                 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
 869         else
 870                 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
 871         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 872
 873         WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 874                                                      NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 875
 876         WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 877                                                      NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 878
 879         sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 880                                      SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
 881                                      SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 882                                      SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
 883
 884         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
 885         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
 886         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
 887         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
 888         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
 889         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
 890         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
 891         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
 892
 893         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
 894                                           FORCE_EOV_MAX_REZ_CNT(255)));
 895
 896         if (rdev->family == CHIP_RV710)
 897                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
 898                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 899         else
 900                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
 901                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 902
 903         switch (rdev->family) {
 904         case CHIP_RV770:
 905         case CHIP_RV730:
 906         case CHIP_RV740:
 907                 gs_prim_buffer_depth = 384;
 908                 break;
 909         case CHIP_RV710:
 910                 gs_prim_buffer_depth = 128;
 911                 break;
 912         default:
 913                 break;
 914         }
 915
 916         num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
 917         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
 918         /* Max value for this is 256 */
 919         if (vgt_gs_per_es > 256)
 920                 vgt_gs_per_es = 256;
 921
 922         WREG32(VGT_ES_PER_GS, 128);
 923         WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
 924         WREG32(VGT_GS_PER_VS, 2);
 925
 926         /* more default values. 2D/3D driver should adjust as needed */
 927         WREG32(VGT_GS_VERTEX_REUSE, 16);
 928         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 929         WREG32(VGT_STRMOUT_EN, 0);
 930         WREG32(SX_MISC, 0);
 931         WREG32(PA_SC_MODE_CNTL, 0);
 932         WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
 933         WREG32(PA_SC_AA_CONFIG, 0);
 934         WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
 935         WREG32(PA_SC_LINE_STIPPLE, 0);
 936         WREG32(SPI_INPUT_Z, 0);
 937         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
 938         WREG32(CB_COLOR7_FRAG, 0);
 939
 940         /* clear render buffer base addresses */
 941         WREG32(CB_COLOR0_BASE, 0);
 942         WREG32(CB_COLOR1_BASE, 0);
 943         WREG32(CB_COLOR2_BASE, 0);
 944         WREG32(CB_COLOR3_BASE, 0);
 945         WREG32(CB_COLOR4_BASE, 0);
 946         WREG32(CB_COLOR5_BASE, 0);
 947         WREG32(CB_COLOR6_BASE, 0);
 948         WREG32(CB_COLOR7_BASE, 0);
 949
 950         WREG32(TCP_CNTL, 0);
 951
 952         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
 953         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 954
 955         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 956
 957         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
 958                                           NUM_CLIP_SEQ(3)));
 959
 960 }
 961
 962 static int rv770_vram_scratch_init(struct radeon_device *rdev)
 963 {
 964         int r;
 965         u64 gpu_addr;
 966
 967         if (rdev->vram_scratch.robj == NULL) {
 968                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
 969                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
 970                                      &rdev->vram_scratch.robj);
 971                 if (r) {
 972                         return r;
 973                 }
 974         }
 975
 976         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
 977         if (unlikely(r != 0))
 978                 return r;
 979         r = radeon_bo_pin(rdev->vram_scratch.robj,
 980                           RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
 981         if (r) {
 982                 radeon_bo_unreserve(rdev->vram_scratch.robj);
 983                 return r;
 984         }
 985         r = radeon_bo_kmap(rdev->vram_scratch.robj,
 986                                 (void **)&rdev->vram_scratch.ptr);
 987         if (r)
 988                 radeon_bo_unpin(rdev->vram_scratch.robj);
 989         radeon_bo_unreserve(rdev->vram_scratch.robj);
 990
 991         return r;
 992 }
 993
 994 static void rv770_vram_scratch_fini(struct radeon_device *rdev)
 995 {
 996         int r;
 997
 998         if (rdev->vram_scratch.robj == NULL) {
 999                 return;
1000         }
1001         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1002         if (likely(r == 0)) {
1003                 radeon_bo_kunmap(rdev->vram_scratch.robj);
1004                 radeon_bo_unpin(rdev->vram_scratch.robj);
1005                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1006         }
1007         radeon_bo_unref(&rdev->vram_scratch.robj);
1008 }
1009
1010 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1011 {
1012         u64 size_bf, size_af;
1013
1014         if (mc->mc_vram_size > 0xE0000000) {
1015                 /* leave room for at least 512M GTT */
1016                 dev_warn(rdev->dev, "limiting VRAM\n");
1017                 mc->real_vram_size = 0xE0000000;
1018                 mc->mc_vram_size = 0xE0000000;
1019         }
1020         if (rdev->flags & RADEON_IS_AGP) {
1021                 size_bf = mc->gtt_start;
1022                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1023                 if (size_bf > size_af) {
1024                         if (mc->mc_vram_size > size_bf) {
1025                                 dev_warn(rdev->dev, "limiting VRAM\n");
1026                                 mc->real_vram_size = size_bf;
1027                                 mc->mc_vram_size = size_bf;
1028                         }
1029                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1030                 } else {
1031                         if (mc->mc_vram_size > size_af) {
1032                                 dev_warn(rdev->dev, "limiting VRAM\n");
1033                                 mc->real_vram_size = size_af;
1034                                 mc->mc_vram_size = size_af;
1035                         }
1036                         mc->vram_start = mc->gtt_end;
1037                 }
1038                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1039                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1040                                 mc->mc_vram_size >> 20, mc->vram_start,
1041                                 mc->vram_end, mc->real_vram_size >> 20);
1042         } else {
1043                 radeon_vram_location(rdev, &rdev->mc, 0);
1044                 rdev->mc.gtt_base_align = 0;
1045                 radeon_gtt_location(rdev, mc);
1046         }
1047 }
1048
1049 int rv770_mc_init(struct radeon_device *rdev)
1050 {
1051         u32 tmp;
1052         int chansize, numchan;
1053
1054         /* Get VRAM informations */
1055         rdev->mc.vram_is_ddr = true;
1056         tmp = RREG32(MC_ARB_RAMCFG);
1057         if (tmp & CHANSIZE_OVERRIDE) {
1058                 chansize = 16;
1059         } else if (tmp & CHANSIZE_MASK) {
1060                 chansize = 64;
1061         } else {
1062                 chansize = 32;
1063         }
1064         tmp = RREG32(MC_SHARED_CHMAP);
1065         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1066         case 0:
1067         default:
1068                 numchan = 1;
1069                 break;
1070         case 1:
1071                 numchan = 2;
1072                 break;
1073         case 2:
1074                 numchan = 4;
1075                 break;
1076         case 3:
1077                 numchan = 8;
1078                 break;
1079         }
1080         rdev->mc.vram_width = numchan * chansize;
1081         /* Could aper size report 0 ? */
1082         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1083         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1084         /* Setup GPU memory space */
1085         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1086         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1087         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1088         r700_vram_gtt_location(rdev, &rdev->mc);
1089         radeon_update_bandwidth_info(rdev);
1090
1091         return 0;
1092 }
1093
1094 static int rv770_startup(struct radeon_device *rdev)
1095 {
1096         int r;
1097
1098         /* enable pcie gen2 link */
1099         rv770_pcie_gen2_enable(rdev);
1100
1101         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1102                 r = r600_init_microcode(rdev);
1103                 if (r) {
1104                         DRM_ERROR("Failed to load firmware!\n");
1105                         return r;
1106                 }
1107         }
1108
1109         rv770_mc_program(rdev);
1110         if (rdev->flags & RADEON_IS_AGP) {
1111                 rv770_agp_enable(rdev);
1112         } else {
1113                 r = rv770_pcie_gart_enable(rdev);
1114                 if (r)
1115                         return r;
1116         }
1117         r = rv770_vram_scratch_init(rdev);
1118         if (r)
1119                 return r;
1120         rv770_gpu_init(rdev);
1121         r = r600_blit_init(rdev);
1122         if (r) {
1123                 r600_blit_fini(rdev);
1124                 rdev->asic->copy = NULL;
1125                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1126         }
1127
1128         /* allocate wb buffer */
1129         r = radeon_wb_init(rdev);
1130         if (r)
1131                 return r;
1132
1133         /* Enable IRQ */
1134         r = r600_irq_init(rdev);
1135         if (r) {
1136                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1137                 radeon_irq_kms_fini(rdev);
1138                 return r;
1139         }
1140         r600_irq_set(rdev);
1141
1142         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1143         if (r)
1144                 return r;
1145         r = rv770_cp_load_microcode(rdev);
1146         if (r)
1147                 return r;
1148         r = r600_cp_resume(rdev);
1149         if (r)
1150                 return r;
1151
1152         return 0;
1153 }
1154
1155 int rv770_resume(struct radeon_device *rdev)
1156 {
1157         int r;
1158
1159         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1160          * posting will perform necessary task to bring back GPU into good
1161          * shape.
1162          */
1163         /* post card */
1164         atom_asic_init(rdev->mode_info.atom_context);
1165
1166         r = rv770_startup(rdev);
1167         if (r) {
1168                 DRM_ERROR("r600 startup failed on resume\n");
1169                 return r;
1170         }
1171
1172         r = r600_ib_test(rdev);
1173         if (r) {
1174                 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1175                 return r;
1176         }
1177
1178         r = r600_audio_init(rdev);
1179         if (r) {
1180                 dev_err(rdev->dev, "radeon: audio init failed\n");
1181                 return r;
1182         }
1183
1184         return r;
1185
1186 }
1187
1188 int rv770_suspend(struct radeon_device *rdev)
1189 {
1190         r600_audio_fini(rdev);
1191         /* FIXME: we should wait for ring to be empty */
1192         r700_cp_stop(rdev);
1193         rdev->cp.ready = false;
1194         r600_irq_suspend(rdev);
1195         radeon_wb_disable(rdev);
1196         rv770_pcie_gart_disable(rdev);
1197         r600_blit_suspend(rdev);
1198
1199         return 0;
1200 }
1201
1202 /* Plan is to move initialization in that function and use
1203  * helper function so that radeon_device_init pretty much
1204  * do nothing more than calling asic specific function. This
1205  * should also allow to remove a bunch of callback function
1206  * like vram_info.
1207  */
1208 int rv770_init(struct radeon_device *rdev)
1209 {
1210         int r;
1211
1212         /* This don't do much */
1213         r = radeon_gem_init(rdev);
1214         if (r)
1215                 return r;
1216         /* Read BIOS */
1217         if (!radeon_get_bios(rdev)) {
1218                 if (ASIC_IS_AVIVO(rdev))
1219                         return -EINVAL;
1220         }
1221         /* Must be an ATOMBIOS */
1222         if (!rdev->is_atom_bios) {
1223                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1224                 return -EINVAL;
1225         }
1226         r = radeon_atombios_init(rdev);
1227         if (r)
1228                 return r;
1229         /* Post card if necessary */
1230         if (!radeon_card_posted(rdev)) {
1231                 if (!rdev->bios) {
1232                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1233                         return -EINVAL;
1234                 }
1235                 DRM_INFO("GPU not posted. posting now...\n");
1236                 atom_asic_init(rdev->mode_info.atom_context);
1237         }
1238         /* Initialize scratch registers */
1239         r600_scratch_init(rdev);
1240         /* Initialize surface registers */
1241         radeon_surface_init(rdev);
1242         /* Initialize clocks */
1243         radeon_get_clock_info(rdev->ddev);
1244         /* Fence driver */
1245         r = radeon_fence_driver_init(rdev);
1246         if (r)
1247                 return r;
1248         /* initialize AGP */
1249         if (rdev->flags & RADEON_IS_AGP) {
1250                 r = radeon_agp_init(rdev);
1251                 if (r)
1252                         radeon_agp_disable(rdev);
1253         }
1254         r = rv770_mc_init(rdev);
1255         if (r)
1256                 return r;
1257         /* Memory manager */
1258         r = radeon_bo_init(rdev);
1259         if (r)
1260                 return r;
1261
1262         r = radeon_irq_kms_init(rdev);
1263         if (r)
1264                 return r;
1265
1266         rdev->cp.ring_obj = NULL;
1267         r600_ring_init(rdev, 1024 * 1024);
1268
1269         rdev->ih.ring_obj = NULL;
1270         r600_ih_ring_init(rdev, 64 * 1024);
1271
1272         r = r600_pcie_gart_init(rdev);
1273         if (r)
1274                 return r;
1275
1276         rdev->accel_working = true;
1277         r = rv770_startup(rdev);
1278         if (r) {
1279                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1280                 r700_cp_fini(rdev);
1281                 r600_irq_fini(rdev);
1282                 radeon_wb_fini(rdev);
1283                 radeon_irq_kms_fini(rdev);
1284                 rv770_pcie_gart_fini(rdev);
1285                 rdev->accel_working = false;
1286         }
1287         if (rdev->accel_working) {
1288                 r = radeon_ib_pool_init(rdev);
1289                 if (r) {
1290                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1291                         rdev->accel_working = false;
1292                 } else {
1293                         r = r600_ib_test(rdev);
1294                         if (r) {
1295                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1296                                 rdev->accel_working = false;
1297                         }
1298                 }
1299         }
1300
1301         r = r600_audio_init(rdev);
1302         if (r) {
1303                 dev_err(rdev->dev, "radeon: audio init failed\n");
1304                 return r;
1305         }
1306
1307         return 0;
1308 }
1309
1310 void rv770_fini(struct radeon_device *rdev)
1311 {
1312         r600_blit_fini(rdev);
1313         r700_cp_fini(rdev);
1314         r600_irq_fini(rdev);
1315         radeon_wb_fini(rdev);
1316         radeon_ib_pool_fini(rdev);
1317         radeon_irq_kms_fini(rdev);
1318         rv770_pcie_gart_fini(rdev);
1319         rv770_vram_scratch_fini(rdev);
1320         radeon_gem_fini(rdev);
1321         radeon_fence_driver_fini(rdev);
1322         radeon_agp_fini(rdev);
1323         radeon_bo_fini(rdev);
1324         radeon_atombios_fini(rdev);
1325         kfree(rdev->bios);
1326         rdev->bios = NULL;
1327 }
1328
1329 static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1330 {
1331         u32 link_width_cntl, lanes, speed_cntl, tmp;
1332         u16 link_cntl2;
1333
1334         if (radeon_pcie_gen2 == 0)
1335                 return;
1336
1337         if (rdev->flags & RADEON_IS_IGP)
1338                 return;
1339
1340         if (!(rdev->flags & RADEON_IS_PCIE))
1341                 return;
1342
1343         /* x2 cards have a special sequence */
1344         if (ASIC_IS_X2(rdev))
1345                 return;
1346
1347         /* advertise upconfig capability */
1348         link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1349         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1350         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1351         link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1352         if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
1353                 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1354                 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
1355                                      LC_RECONFIG_ARC_MISSING_ESCAPE);
1356                 link_width_cntl |= lanes | LC_RECONFIG_NOW |
1357                         LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
1358                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1359         } else {
1360                 link_width_cntl |= LC_UPCONFIGURE_DIS;
1361                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1362         }
1363
1364         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1365         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1366             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1367
1368                 tmp = RREG32(0x541c);
1369                 WREG32(0x541c, tmp | 0x8);
1370                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
1371                 link_cntl2 = RREG16(0x4088);
1372                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
1373                 link_cntl2 |= 0x2;
1374                 WREG16(0x4088, link_cntl2);
1375                 WREG32(MM_CFGREGS_CNTL, 0);
1376
1377                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1378                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
1379                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1380
1381                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1382                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1383                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1384
1385                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1386                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1387                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1388
1389                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1390                 speed_cntl |= LC_GEN2_EN_STRAP;
1391                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1392
1393         } else {
1394                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1395                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
1396                 if (1)
1397                         link_width_cntl |= LC_UPCONFIGURE_DIS;
1398                 else
1399                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1400                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1401         }
1402 }