2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
29 #include "radeon_asic.h"
30 #include "radeon_audio.h"
31 #include <drm/radeon_drm.h>
34 #include "si_blit_shaders.h"
35 #include "clearstate_si.h"
36 #include "radeon_ucode.h"
39 MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
40 MODULE_FIRMWARE("radeon/TAHITI_me.bin");
41 MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
42 MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
43 MODULE_FIRMWARE("radeon/TAHITI_mc2.bin");
44 MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
45 MODULE_FIRMWARE("radeon/TAHITI_smc.bin");
47 MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
48 MODULE_FIRMWARE("radeon/tahiti_me.bin");
49 MODULE_FIRMWARE("radeon/tahiti_ce.bin");
50 MODULE_FIRMWARE("radeon/tahiti_mc.bin");
51 MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
52 MODULE_FIRMWARE("radeon/tahiti_smc.bin");
54 MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
55 MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
56 MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
57 MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
58 MODULE_FIRMWARE("radeon/PITCAIRN_mc2.bin");
59 MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
60 MODULE_FIRMWARE("radeon/PITCAIRN_smc.bin");
62 MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
63 MODULE_FIRMWARE("radeon/pitcairn_me.bin");
64 MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
65 MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
66 MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
67 MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
69 MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
70 MODULE_FIRMWARE("radeon/VERDE_me.bin");
71 MODULE_FIRMWARE("radeon/VERDE_ce.bin");
72 MODULE_FIRMWARE("radeon/VERDE_mc.bin");
73 MODULE_FIRMWARE("radeon/VERDE_mc2.bin");
74 MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
75 MODULE_FIRMWARE("radeon/VERDE_smc.bin");
77 MODULE_FIRMWARE("radeon/verde_pfp.bin");
78 MODULE_FIRMWARE("radeon/verde_me.bin");
79 MODULE_FIRMWARE("radeon/verde_ce.bin");
80 MODULE_FIRMWARE("radeon/verde_mc.bin");
81 MODULE_FIRMWARE("radeon/verde_rlc.bin");
82 MODULE_FIRMWARE("radeon/verde_smc.bin");
84 MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
85 MODULE_FIRMWARE("radeon/OLAND_me.bin");
86 MODULE_FIRMWARE("radeon/OLAND_ce.bin");
87 MODULE_FIRMWARE("radeon/OLAND_mc.bin");
88 MODULE_FIRMWARE("radeon/OLAND_mc2.bin");
89 MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
90 MODULE_FIRMWARE("radeon/OLAND_smc.bin");
92 MODULE_FIRMWARE("radeon/oland_pfp.bin");
93 MODULE_FIRMWARE("radeon/oland_me.bin");
94 MODULE_FIRMWARE("radeon/oland_ce.bin");
95 MODULE_FIRMWARE("radeon/oland_mc.bin");
96 MODULE_FIRMWARE("radeon/oland_rlc.bin");
97 MODULE_FIRMWARE("radeon/oland_smc.bin");
99 MODULE_FIRMWARE("radeon/HAINAN_pfp.bin");
100 MODULE_FIRMWARE("radeon/HAINAN_me.bin");
101 MODULE_FIRMWARE("radeon/HAINAN_ce.bin");
102 MODULE_FIRMWARE("radeon/HAINAN_mc.bin");
103 MODULE_FIRMWARE("radeon/HAINAN_mc2.bin");
104 MODULE_FIRMWARE("radeon/HAINAN_rlc.bin");
105 MODULE_FIRMWARE("radeon/HAINAN_smc.bin");
107 MODULE_FIRMWARE("radeon/hainan_pfp.bin");
108 MODULE_FIRMWARE("radeon/hainan_me.bin");
109 MODULE_FIRMWARE("radeon/hainan_ce.bin");
110 MODULE_FIRMWARE("radeon/hainan_mc.bin");
111 MODULE_FIRMWARE("radeon/hainan_rlc.bin");
112 MODULE_FIRMWARE("radeon/hainan_smc.bin");
114 static u32 si_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh);
115 static void si_pcie_gen3_enable(struct radeon_device *rdev);
116 static void si_program_aspm(struct radeon_device *rdev);
117 extern void sumo_rlc_fini(struct radeon_device *rdev);
118 extern int sumo_rlc_init(struct radeon_device *rdev);
119 extern int r600_ih_ring_alloc(struct radeon_device *rdev);
120 extern void r600_ih_ring_fini(struct radeon_device *rdev);
121 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
122 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
123 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
124 extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
125 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
126 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
127 static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
129 static void si_init_pg(struct radeon_device *rdev);
130 static void si_init_cg(struct radeon_device *rdev);
131 static void si_fini_pg(struct radeon_device *rdev);
132 static void si_fini_cg(struct radeon_device *rdev);
133 static void si_rlc_stop(struct radeon_device *rdev);
135 static const u32 verde_rlc_save_restore_register_list[] =
137 (0x8000 << 16) | (0x98f4 >> 2),
139 (0x8040 << 16) | (0x98f4 >> 2),
141 (0x8000 << 16) | (0xe80 >> 2),
143 (0x8040 << 16) | (0xe80 >> 2),
145 (0x8000 << 16) | (0x89bc >> 2),
147 (0x8040 << 16) | (0x89bc >> 2),
149 (0x8000 << 16) | (0x8c1c >> 2),
151 (0x8040 << 16) | (0x8c1c >> 2),
153 (0x9c00 << 16) | (0x98f0 >> 2),
155 (0x9c00 << 16) | (0xe7c >> 2),
157 (0x8000 << 16) | (0x9148 >> 2),
159 (0x8040 << 16) | (0x9148 >> 2),
161 (0x9c00 << 16) | (0x9150 >> 2),
163 (0x9c00 << 16) | (0x897c >> 2),
165 (0x9c00 << 16) | (0x8d8c >> 2),
167 (0x9c00 << 16) | (0xac54 >> 2),
170 (0x9c00 << 16) | (0x98f8 >> 2),
172 (0x9c00 << 16) | (0x9910 >> 2),
174 (0x9c00 << 16) | (0x9914 >> 2),
176 (0x9c00 << 16) | (0x9918 >> 2),
178 (0x9c00 << 16) | (0x991c >> 2),
180 (0x9c00 << 16) | (0x9920 >> 2),
182 (0x9c00 << 16) | (0x9924 >> 2),
184 (0x9c00 << 16) | (0x9928 >> 2),
186 (0x9c00 << 16) | (0x992c >> 2),
188 (0x9c00 << 16) | (0x9930 >> 2),
190 (0x9c00 << 16) | (0x9934 >> 2),
192 (0x9c00 << 16) | (0x9938 >> 2),
194 (0x9c00 << 16) | (0x993c >> 2),
196 (0x9c00 << 16) | (0x9940 >> 2),
198 (0x9c00 << 16) | (0x9944 >> 2),
200 (0x9c00 << 16) | (0x9948 >> 2),
202 (0x9c00 << 16) | (0x994c >> 2),
204 (0x9c00 << 16) | (0x9950 >> 2),
206 (0x9c00 << 16) | (0x9954 >> 2),
208 (0x9c00 << 16) | (0x9958 >> 2),
210 (0x9c00 << 16) | (0x995c >> 2),
212 (0x9c00 << 16) | (0x9960 >> 2),
214 (0x9c00 << 16) | (0x9964 >> 2),
216 (0x9c00 << 16) | (0x9968 >> 2),
218 (0x9c00 << 16) | (0x996c >> 2),
220 (0x9c00 << 16) | (0x9970 >> 2),
222 (0x9c00 << 16) | (0x9974 >> 2),
224 (0x9c00 << 16) | (0x9978 >> 2),
226 (0x9c00 << 16) | (0x997c >> 2),
228 (0x9c00 << 16) | (0x9980 >> 2),
230 (0x9c00 << 16) | (0x9984 >> 2),
232 (0x9c00 << 16) | (0x9988 >> 2),
234 (0x9c00 << 16) | (0x998c >> 2),
236 (0x9c00 << 16) | (0x8c00 >> 2),
238 (0x9c00 << 16) | (0x8c14 >> 2),
240 (0x9c00 << 16) | (0x8c04 >> 2),
242 (0x9c00 << 16) | (0x8c08 >> 2),
244 (0x8000 << 16) | (0x9b7c >> 2),
246 (0x8040 << 16) | (0x9b7c >> 2),
248 (0x8000 << 16) | (0xe84 >> 2),
250 (0x8040 << 16) | (0xe84 >> 2),
252 (0x8000 << 16) | (0x89c0 >> 2),
254 (0x8040 << 16) | (0x89c0 >> 2),
256 (0x8000 << 16) | (0x914c >> 2),
258 (0x8040 << 16) | (0x914c >> 2),
260 (0x8000 << 16) | (0x8c20 >> 2),
262 (0x8040 << 16) | (0x8c20 >> 2),
264 (0x8000 << 16) | (0x9354 >> 2),
266 (0x8040 << 16) | (0x9354 >> 2),
268 (0x9c00 << 16) | (0x9060 >> 2),
270 (0x9c00 << 16) | (0x9364 >> 2),
272 (0x9c00 << 16) | (0x9100 >> 2),
274 (0x9c00 << 16) | (0x913c >> 2),
276 (0x8000 << 16) | (0x90e0 >> 2),
278 (0x8000 << 16) | (0x90e4 >> 2),
280 (0x8000 << 16) | (0x90e8 >> 2),
282 (0x8040 << 16) | (0x90e0 >> 2),
284 (0x8040 << 16) | (0x90e4 >> 2),
286 (0x8040 << 16) | (0x90e8 >> 2),
288 (0x9c00 << 16) | (0x8bcc >> 2),
290 (0x9c00 << 16) | (0x8b24 >> 2),
292 (0x9c00 << 16) | (0x88c4 >> 2),
294 (0x9c00 << 16) | (0x8e50 >> 2),
296 (0x9c00 << 16) | (0x8c0c >> 2),
298 (0x9c00 << 16) | (0x8e58 >> 2),
300 (0x9c00 << 16) | (0x8e5c >> 2),
302 (0x9c00 << 16) | (0x9508 >> 2),
304 (0x9c00 << 16) | (0x950c >> 2),
306 (0x9c00 << 16) | (0x9494 >> 2),
308 (0x9c00 << 16) | (0xac0c >> 2),
310 (0x9c00 << 16) | (0xac10 >> 2),
312 (0x9c00 << 16) | (0xac14 >> 2),
314 (0x9c00 << 16) | (0xae00 >> 2),
316 (0x9c00 << 16) | (0xac08 >> 2),
318 (0x9c00 << 16) | (0x88d4 >> 2),
320 (0x9c00 << 16) | (0x88c8 >> 2),
322 (0x9c00 << 16) | (0x88cc >> 2),
324 (0x9c00 << 16) | (0x89b0 >> 2),
326 (0x9c00 << 16) | (0x8b10 >> 2),
328 (0x9c00 << 16) | (0x8a14 >> 2),
330 (0x9c00 << 16) | (0x9830 >> 2),
332 (0x9c00 << 16) | (0x9834 >> 2),
334 (0x9c00 << 16) | (0x9838 >> 2),
336 (0x9c00 << 16) | (0x9a10 >> 2),
338 (0x8000 << 16) | (0x9870 >> 2),
340 (0x8000 << 16) | (0x9874 >> 2),
342 (0x8001 << 16) | (0x9870 >> 2),
344 (0x8001 << 16) | (0x9874 >> 2),
346 (0x8040 << 16) | (0x9870 >> 2),
348 (0x8040 << 16) | (0x9874 >> 2),
350 (0x8041 << 16) | (0x9870 >> 2),
352 (0x8041 << 16) | (0x9874 >> 2),
357 static const u32 tahiti_golden_rlc_registers[] =
359 0xc424, 0xffffffff, 0x00601005,
360 0xc47c, 0xffffffff, 0x10104040,
361 0xc488, 0xffffffff, 0x0100000a,
362 0xc314, 0xffffffff, 0x00000800,
363 0xc30c, 0xffffffff, 0x800000f4,
364 0xf4a8, 0xffffffff, 0x00000000
367 static const u32 tahiti_golden_registers[] =
369 0x9a10, 0x00010000, 0x00018208,
370 0x9830, 0xffffffff, 0x00000000,
371 0x9834, 0xf00fffff, 0x00000400,
372 0x9838, 0x0002021c, 0x00020200,
373 0xc78, 0x00000080, 0x00000000,
374 0xd030, 0x000300c0, 0x00800040,
375 0xd830, 0x000300c0, 0x00800040,
376 0x5bb0, 0x000000f0, 0x00000070,
377 0x5bc0, 0x00200000, 0x50100000,
378 0x7030, 0x31000311, 0x00000011,
379 0x277c, 0x00000003, 0x000007ff,
380 0x240c, 0x000007ff, 0x00000000,
381 0x8a14, 0xf000001f, 0x00000007,
382 0x8b24, 0xffffffff, 0x00ffffff,
383 0x8b10, 0x0000ff0f, 0x00000000,
384 0x28a4c, 0x07ffffff, 0x4e000000,
385 0x28350, 0x3f3f3fff, 0x2a00126a,
386 0x30, 0x000000ff, 0x0040,
387 0x34, 0x00000040, 0x00004040,
388 0x9100, 0x07ffffff, 0x03000000,
389 0x8e88, 0x01ff1f3f, 0x00000000,
390 0x8e84, 0x01ff1f3f, 0x00000000,
391 0x9060, 0x0000007f, 0x00000020,
392 0x9508, 0x00010000, 0x00010000,
393 0xac14, 0x00000200, 0x000002fb,
394 0xac10, 0xffffffff, 0x0000543b,
395 0xac0c, 0xffffffff, 0xa9210876,
396 0x88d0, 0xffffffff, 0x000fff40,
397 0x88d4, 0x0000001f, 0x00000010,
398 0x1410, 0x20000000, 0x20fffed8,
399 0x15c0, 0x000c0fc0, 0x000c0400
402 static const u32 tahiti_golden_registers2[] =
404 0xc64, 0x00000001, 0x00000001
407 static const u32 pitcairn_golden_rlc_registers[] =
409 0xc424, 0xffffffff, 0x00601004,
410 0xc47c, 0xffffffff, 0x10102020,
411 0xc488, 0xffffffff, 0x01000020,
412 0xc314, 0xffffffff, 0x00000800,
413 0xc30c, 0xffffffff, 0x800000a4
416 static const u32 pitcairn_golden_registers[] =
418 0x9a10, 0x00010000, 0x00018208,
419 0x9830, 0xffffffff, 0x00000000,
420 0x9834, 0xf00fffff, 0x00000400,
421 0x9838, 0x0002021c, 0x00020200,
422 0xc78, 0x00000080, 0x00000000,
423 0xd030, 0x000300c0, 0x00800040,
424 0xd830, 0x000300c0, 0x00800040,
425 0x5bb0, 0x000000f0, 0x00000070,
426 0x5bc0, 0x00200000, 0x50100000,
427 0x7030, 0x31000311, 0x00000011,
428 0x2ae4, 0x00073ffe, 0x000022a2,
429 0x240c, 0x000007ff, 0x00000000,
430 0x8a14, 0xf000001f, 0x00000007,
431 0x8b24, 0xffffffff, 0x00ffffff,
432 0x8b10, 0x0000ff0f, 0x00000000,
433 0x28a4c, 0x07ffffff, 0x4e000000,
434 0x28350, 0x3f3f3fff, 0x2a00126a,
435 0x30, 0x000000ff, 0x0040,
436 0x34, 0x00000040, 0x00004040,
437 0x9100, 0x07ffffff, 0x03000000,
438 0x9060, 0x0000007f, 0x00000020,
439 0x9508, 0x00010000, 0x00010000,
440 0xac14, 0x000003ff, 0x000000f7,
441 0xac10, 0xffffffff, 0x00000000,
442 0xac0c, 0xffffffff, 0x32761054,
443 0x88d4, 0x0000001f, 0x00000010,
444 0x15c0, 0x000c0fc0, 0x000c0400
447 static const u32 verde_golden_rlc_registers[] =
449 0xc424, 0xffffffff, 0x033f1005,
450 0xc47c, 0xffffffff, 0x10808020,
451 0xc488, 0xffffffff, 0x00800008,
452 0xc314, 0xffffffff, 0x00001000,
453 0xc30c, 0xffffffff, 0x80010014
456 static const u32 verde_golden_registers[] =
458 0x9a10, 0x00010000, 0x00018208,
459 0x9830, 0xffffffff, 0x00000000,
460 0x9834, 0xf00fffff, 0x00000400,
461 0x9838, 0x0002021c, 0x00020200,
462 0xc78, 0x00000080, 0x00000000,
463 0xd030, 0x000300c0, 0x00800040,
464 0xd030, 0x000300c0, 0x00800040,
465 0xd830, 0x000300c0, 0x00800040,
466 0xd830, 0x000300c0, 0x00800040,
467 0x5bb0, 0x000000f0, 0x00000070,
468 0x5bc0, 0x00200000, 0x50100000,
469 0x7030, 0x31000311, 0x00000011,
470 0x2ae4, 0x00073ffe, 0x000022a2,
471 0x2ae4, 0x00073ffe, 0x000022a2,
472 0x2ae4, 0x00073ffe, 0x000022a2,
473 0x240c, 0x000007ff, 0x00000000,
474 0x240c, 0x000007ff, 0x00000000,
475 0x240c, 0x000007ff, 0x00000000,
476 0x8a14, 0xf000001f, 0x00000007,
477 0x8a14, 0xf000001f, 0x00000007,
478 0x8a14, 0xf000001f, 0x00000007,
479 0x8b24, 0xffffffff, 0x00ffffff,
480 0x8b10, 0x0000ff0f, 0x00000000,
481 0x28a4c, 0x07ffffff, 0x4e000000,
482 0x28350, 0x3f3f3fff, 0x0000124a,
483 0x28350, 0x3f3f3fff, 0x0000124a,
484 0x28350, 0x3f3f3fff, 0x0000124a,
485 0x30, 0x000000ff, 0x0040,
486 0x34, 0x00000040, 0x00004040,
487 0x9100, 0x07ffffff, 0x03000000,
488 0x9100, 0x07ffffff, 0x03000000,
489 0x8e88, 0x01ff1f3f, 0x00000000,
490 0x8e88, 0x01ff1f3f, 0x00000000,
491 0x8e88, 0x01ff1f3f, 0x00000000,
492 0x8e84, 0x01ff1f3f, 0x00000000,
493 0x8e84, 0x01ff1f3f, 0x00000000,
494 0x8e84, 0x01ff1f3f, 0x00000000,
495 0x9060, 0x0000007f, 0x00000020,
496 0x9508, 0x00010000, 0x00010000,
497 0xac14, 0x000003ff, 0x00000003,
498 0xac14, 0x000003ff, 0x00000003,
499 0xac14, 0x000003ff, 0x00000003,
500 0xac10, 0xffffffff, 0x00000000,
501 0xac10, 0xffffffff, 0x00000000,
502 0xac10, 0xffffffff, 0x00000000,
503 0xac0c, 0xffffffff, 0x00001032,
504 0xac0c, 0xffffffff, 0x00001032,
505 0xac0c, 0xffffffff, 0x00001032,
506 0x88d4, 0x0000001f, 0x00000010,
507 0x88d4, 0x0000001f, 0x00000010,
508 0x88d4, 0x0000001f, 0x00000010,
509 0x15c0, 0x000c0fc0, 0x000c0400
512 static const u32 oland_golden_rlc_registers[] =
514 0xc424, 0xffffffff, 0x00601005,
515 0xc47c, 0xffffffff, 0x10104040,
516 0xc488, 0xffffffff, 0x0100000a,
517 0xc314, 0xffffffff, 0x00000800,
518 0xc30c, 0xffffffff, 0x800000f4
521 static const u32 oland_golden_registers[] =
523 0x9a10, 0x00010000, 0x00018208,
524 0x9830, 0xffffffff, 0x00000000,
525 0x9834, 0xf00fffff, 0x00000400,
526 0x9838, 0x0002021c, 0x00020200,
527 0xc78, 0x00000080, 0x00000000,
528 0xd030, 0x000300c0, 0x00800040,
529 0xd830, 0x000300c0, 0x00800040,
530 0x5bb0, 0x000000f0, 0x00000070,
531 0x5bc0, 0x00200000, 0x50100000,
532 0x7030, 0x31000311, 0x00000011,
533 0x2ae4, 0x00073ffe, 0x000022a2,
534 0x240c, 0x000007ff, 0x00000000,
535 0x8a14, 0xf000001f, 0x00000007,
536 0x8b24, 0xffffffff, 0x00ffffff,
537 0x8b10, 0x0000ff0f, 0x00000000,
538 0x28a4c, 0x07ffffff, 0x4e000000,
539 0x28350, 0x3f3f3fff, 0x00000082,
540 0x30, 0x000000ff, 0x0040,
541 0x34, 0x00000040, 0x00004040,
542 0x9100, 0x07ffffff, 0x03000000,
543 0x9060, 0x0000007f, 0x00000020,
544 0x9508, 0x00010000, 0x00010000,
545 0xac14, 0x000003ff, 0x000000f3,
546 0xac10, 0xffffffff, 0x00000000,
547 0xac0c, 0xffffffff, 0x00003210,
548 0x88d4, 0x0000001f, 0x00000010,
549 0x15c0, 0x000c0fc0, 0x000c0400
552 static const u32 hainan_golden_registers[] =
554 0x9a10, 0x00010000, 0x00018208,
555 0x9830, 0xffffffff, 0x00000000,
556 0x9834, 0xf00fffff, 0x00000400,
557 0x9838, 0x0002021c, 0x00020200,
558 0xd0c0, 0xff000fff, 0x00000100,
559 0xd030, 0x000300c0, 0x00800040,
560 0xd8c0, 0xff000fff, 0x00000100,
561 0xd830, 0x000300c0, 0x00800040,
562 0x2ae4, 0x00073ffe, 0x000022a2,
563 0x240c, 0x000007ff, 0x00000000,
564 0x8a14, 0xf000001f, 0x00000007,
565 0x8b24, 0xffffffff, 0x00ffffff,
566 0x8b10, 0x0000ff0f, 0x00000000,
567 0x28a4c, 0x07ffffff, 0x4e000000,
568 0x28350, 0x3f3f3fff, 0x00000000,
569 0x30, 0x000000ff, 0x0040,
570 0x34, 0x00000040, 0x00004040,
571 0x9100, 0x03e00000, 0x03600000,
572 0x9060, 0x0000007f, 0x00000020,
573 0x9508, 0x00010000, 0x00010000,
574 0xac14, 0x000003ff, 0x000000f1,
575 0xac10, 0xffffffff, 0x00000000,
576 0xac0c, 0xffffffff, 0x00003210,
577 0x88d4, 0x0000001f, 0x00000010,
578 0x15c0, 0x000c0fc0, 0x000c0400
581 static const u32 hainan_golden_registers2[] =
583 0x98f8, 0xffffffff, 0x02010001
586 static const u32 tahiti_mgcg_cgcg_init[] =
588 0xc400, 0xffffffff, 0xfffffffc,
589 0x802c, 0xffffffff, 0xe0000000,
590 0x9a60, 0xffffffff, 0x00000100,
591 0x92a4, 0xffffffff, 0x00000100,
592 0xc164, 0xffffffff, 0x00000100,
593 0x9774, 0xffffffff, 0x00000100,
594 0x8984, 0xffffffff, 0x06000100,
595 0x8a18, 0xffffffff, 0x00000100,
596 0x92a0, 0xffffffff, 0x00000100,
597 0xc380, 0xffffffff, 0x00000100,
598 0x8b28, 0xffffffff, 0x00000100,
599 0x9144, 0xffffffff, 0x00000100,
600 0x8d88, 0xffffffff, 0x00000100,
601 0x8d8c, 0xffffffff, 0x00000100,
602 0x9030, 0xffffffff, 0x00000100,
603 0x9034, 0xffffffff, 0x00000100,
604 0x9038, 0xffffffff, 0x00000100,
605 0x903c, 0xffffffff, 0x00000100,
606 0xad80, 0xffffffff, 0x00000100,
607 0xac54, 0xffffffff, 0x00000100,
608 0x897c, 0xffffffff, 0x06000100,
609 0x9868, 0xffffffff, 0x00000100,
610 0x9510, 0xffffffff, 0x00000100,
611 0xaf04, 0xffffffff, 0x00000100,
612 0xae04, 0xffffffff, 0x00000100,
613 0x949c, 0xffffffff, 0x00000100,
614 0x802c, 0xffffffff, 0xe0000000,
615 0x9160, 0xffffffff, 0x00010000,
616 0x9164, 0xffffffff, 0x00030002,
617 0x9168, 0xffffffff, 0x00040007,
618 0x916c, 0xffffffff, 0x00060005,
619 0x9170, 0xffffffff, 0x00090008,
620 0x9174, 0xffffffff, 0x00020001,
621 0x9178, 0xffffffff, 0x00040003,
622 0x917c, 0xffffffff, 0x00000007,
623 0x9180, 0xffffffff, 0x00060005,
624 0x9184, 0xffffffff, 0x00090008,
625 0x9188, 0xffffffff, 0x00030002,
626 0x918c, 0xffffffff, 0x00050004,
627 0x9190, 0xffffffff, 0x00000008,
628 0x9194, 0xffffffff, 0x00070006,
629 0x9198, 0xffffffff, 0x000a0009,
630 0x919c, 0xffffffff, 0x00040003,
631 0x91a0, 0xffffffff, 0x00060005,
632 0x91a4, 0xffffffff, 0x00000009,
633 0x91a8, 0xffffffff, 0x00080007,
634 0x91ac, 0xffffffff, 0x000b000a,
635 0x91b0, 0xffffffff, 0x00050004,
636 0x91b4, 0xffffffff, 0x00070006,
637 0x91b8, 0xffffffff, 0x0008000b,
638 0x91bc, 0xffffffff, 0x000a0009,
639 0x91c0, 0xffffffff, 0x000d000c,
640 0x91c4, 0xffffffff, 0x00060005,
641 0x91c8, 0xffffffff, 0x00080007,
642 0x91cc, 0xffffffff, 0x0000000b,
643 0x91d0, 0xffffffff, 0x000a0009,
644 0x91d4, 0xffffffff, 0x000d000c,
645 0x91d8, 0xffffffff, 0x00070006,
646 0x91dc, 0xffffffff, 0x00090008,
647 0x91e0, 0xffffffff, 0x0000000c,
648 0x91e4, 0xffffffff, 0x000b000a,
649 0x91e8, 0xffffffff, 0x000e000d,
650 0x91ec, 0xffffffff, 0x00080007,
651 0x91f0, 0xffffffff, 0x000a0009,
652 0x91f4, 0xffffffff, 0x0000000d,
653 0x91f8, 0xffffffff, 0x000c000b,
654 0x91fc, 0xffffffff, 0x000f000e,
655 0x9200, 0xffffffff, 0x00090008,
656 0x9204, 0xffffffff, 0x000b000a,
657 0x9208, 0xffffffff, 0x000c000f,
658 0x920c, 0xffffffff, 0x000e000d,
659 0x9210, 0xffffffff, 0x00110010,
660 0x9214, 0xffffffff, 0x000a0009,
661 0x9218, 0xffffffff, 0x000c000b,
662 0x921c, 0xffffffff, 0x0000000f,
663 0x9220, 0xffffffff, 0x000e000d,
664 0x9224, 0xffffffff, 0x00110010,
665 0x9228, 0xffffffff, 0x000b000a,
666 0x922c, 0xffffffff, 0x000d000c,
667 0x9230, 0xffffffff, 0x00000010,
668 0x9234, 0xffffffff, 0x000f000e,
669 0x9238, 0xffffffff, 0x00120011,
670 0x923c, 0xffffffff, 0x000c000b,
671 0x9240, 0xffffffff, 0x000e000d,
672 0x9244, 0xffffffff, 0x00000011,
673 0x9248, 0xffffffff, 0x0010000f,
674 0x924c, 0xffffffff, 0x00130012,
675 0x9250, 0xffffffff, 0x000d000c,
676 0x9254, 0xffffffff, 0x000f000e,
677 0x9258, 0xffffffff, 0x00100013,
678 0x925c, 0xffffffff, 0x00120011,
679 0x9260, 0xffffffff, 0x00150014,
680 0x9264, 0xffffffff, 0x000e000d,
681 0x9268, 0xffffffff, 0x0010000f,
682 0x926c, 0xffffffff, 0x00000013,
683 0x9270, 0xffffffff, 0x00120011,
684 0x9274, 0xffffffff, 0x00150014,
685 0x9278, 0xffffffff, 0x000f000e,
686 0x927c, 0xffffffff, 0x00110010,
687 0x9280, 0xffffffff, 0x00000014,
688 0x9284, 0xffffffff, 0x00130012,
689 0x9288, 0xffffffff, 0x00160015,
690 0x928c, 0xffffffff, 0x0010000f,
691 0x9290, 0xffffffff, 0x00120011,
692 0x9294, 0xffffffff, 0x00000015,
693 0x9298, 0xffffffff, 0x00140013,
694 0x929c, 0xffffffff, 0x00170016,
695 0x9150, 0xffffffff, 0x96940200,
696 0x8708, 0xffffffff, 0x00900100,
697 0xc478, 0xffffffff, 0x00000080,
698 0xc404, 0xffffffff, 0x0020003f,
699 0x30, 0xffffffff, 0x0000001c,
700 0x34, 0x000f0000, 0x000f0000,
701 0x160c, 0xffffffff, 0x00000100,
702 0x1024, 0xffffffff, 0x00000100,
703 0x102c, 0x00000101, 0x00000000,
704 0x20a8, 0xffffffff, 0x00000104,
705 0x264c, 0x000c0000, 0x000c0000,
706 0x2648, 0x000c0000, 0x000c0000,
707 0x55e4, 0xff000fff, 0x00000100,
708 0x55e8, 0x00000001, 0x00000001,
709 0x2f50, 0x00000001, 0x00000001,
710 0x30cc, 0xc0000fff, 0x00000104,
711 0xc1e4, 0x00000001, 0x00000001,
712 0xd0c0, 0xfffffff0, 0x00000100,
713 0xd8c0, 0xfffffff0, 0x00000100
716 static const u32 pitcairn_mgcg_cgcg_init[] =
718 0xc400, 0xffffffff, 0xfffffffc,
719 0x802c, 0xffffffff, 0xe0000000,
720 0x9a60, 0xffffffff, 0x00000100,
721 0x92a4, 0xffffffff, 0x00000100,
722 0xc164, 0xffffffff, 0x00000100,
723 0x9774, 0xffffffff, 0x00000100,
724 0x8984, 0xffffffff, 0x06000100,
725 0x8a18, 0xffffffff, 0x00000100,
726 0x92a0, 0xffffffff, 0x00000100,
727 0xc380, 0xffffffff, 0x00000100,
728 0x8b28, 0xffffffff, 0x00000100,
729 0x9144, 0xffffffff, 0x00000100,
730 0x8d88, 0xffffffff, 0x00000100,
731 0x8d8c, 0xffffffff, 0x00000100,
732 0x9030, 0xffffffff, 0x00000100,
733 0x9034, 0xffffffff, 0x00000100,
734 0x9038, 0xffffffff, 0x00000100,
735 0x903c, 0xffffffff, 0x00000100,
736 0xad80, 0xffffffff, 0x00000100,
737 0xac54, 0xffffffff, 0x00000100,
738 0x897c, 0xffffffff, 0x06000100,
739 0x9868, 0xffffffff, 0x00000100,
740 0x9510, 0xffffffff, 0x00000100,
741 0xaf04, 0xffffffff, 0x00000100,
742 0xae04, 0xffffffff, 0x00000100,
743 0x949c, 0xffffffff, 0x00000100,
744 0x802c, 0xffffffff, 0xe0000000,
745 0x9160, 0xffffffff, 0x00010000,
746 0x9164, 0xffffffff, 0x00030002,
747 0x9168, 0xffffffff, 0x00040007,
748 0x916c, 0xffffffff, 0x00060005,
749 0x9170, 0xffffffff, 0x00090008,
750 0x9174, 0xffffffff, 0x00020001,
751 0x9178, 0xffffffff, 0x00040003,
752 0x917c, 0xffffffff, 0x00000007,
753 0x9180, 0xffffffff, 0x00060005,
754 0x9184, 0xffffffff, 0x00090008,
755 0x9188, 0xffffffff, 0x00030002,
756 0x918c, 0xffffffff, 0x00050004,
757 0x9190, 0xffffffff, 0x00000008,
758 0x9194, 0xffffffff, 0x00070006,
759 0x9198, 0xffffffff, 0x000a0009,
760 0x919c, 0xffffffff, 0x00040003,
761 0x91a0, 0xffffffff, 0x00060005,
762 0x91a4, 0xffffffff, 0x00000009,
763 0x91a8, 0xffffffff, 0x00080007,
764 0x91ac, 0xffffffff, 0x000b000a,
765 0x91b0, 0xffffffff, 0x00050004,
766 0x91b4, 0xffffffff, 0x00070006,
767 0x91b8, 0xffffffff, 0x0008000b,
768 0x91bc, 0xffffffff, 0x000a0009,
769 0x91c0, 0xffffffff, 0x000d000c,
770 0x9200, 0xffffffff, 0x00090008,
771 0x9204, 0xffffffff, 0x000b000a,
772 0x9208, 0xffffffff, 0x000c000f,
773 0x920c, 0xffffffff, 0x000e000d,
774 0x9210, 0xffffffff, 0x00110010,
775 0x9214, 0xffffffff, 0x000a0009,
776 0x9218, 0xffffffff, 0x000c000b,
777 0x921c, 0xffffffff, 0x0000000f,
778 0x9220, 0xffffffff, 0x000e000d,
779 0x9224, 0xffffffff, 0x00110010,
780 0x9228, 0xffffffff, 0x000b000a,
781 0x922c, 0xffffffff, 0x000d000c,
782 0x9230, 0xffffffff, 0x00000010,
783 0x9234, 0xffffffff, 0x000f000e,
784 0x9238, 0xffffffff, 0x00120011,
785 0x923c, 0xffffffff, 0x000c000b,
786 0x9240, 0xffffffff, 0x000e000d,
787 0x9244, 0xffffffff, 0x00000011,
788 0x9248, 0xffffffff, 0x0010000f,
789 0x924c, 0xffffffff, 0x00130012,
790 0x9250, 0xffffffff, 0x000d000c,
791 0x9254, 0xffffffff, 0x000f000e,
792 0x9258, 0xffffffff, 0x00100013,
793 0x925c, 0xffffffff, 0x00120011,
794 0x9260, 0xffffffff, 0x00150014,
795 0x9150, 0xffffffff, 0x96940200,
796 0x8708, 0xffffffff, 0x00900100,
797 0xc478, 0xffffffff, 0x00000080,
798 0xc404, 0xffffffff, 0x0020003f,
799 0x30, 0xffffffff, 0x0000001c,
800 0x34, 0x000f0000, 0x000f0000,
801 0x160c, 0xffffffff, 0x00000100,
802 0x1024, 0xffffffff, 0x00000100,
803 0x102c, 0x00000101, 0x00000000,
804 0x20a8, 0xffffffff, 0x00000104,
805 0x55e4, 0xff000fff, 0x00000100,
806 0x55e8, 0x00000001, 0x00000001,
807 0x2f50, 0x00000001, 0x00000001,
808 0x30cc, 0xc0000fff, 0x00000104,
809 0xc1e4, 0x00000001, 0x00000001,
810 0xd0c0, 0xfffffff0, 0x00000100,
811 0xd8c0, 0xfffffff0, 0x00000100
814 static const u32 verde_mgcg_cgcg_init[] =
816 0xc400, 0xffffffff, 0xfffffffc,
817 0x802c, 0xffffffff, 0xe0000000,
818 0x9a60, 0xffffffff, 0x00000100,
819 0x92a4, 0xffffffff, 0x00000100,
820 0xc164, 0xffffffff, 0x00000100,
821 0x9774, 0xffffffff, 0x00000100,
822 0x8984, 0xffffffff, 0x06000100,
823 0x8a18, 0xffffffff, 0x00000100,
824 0x92a0, 0xffffffff, 0x00000100,
825 0xc380, 0xffffffff, 0x00000100,
826 0x8b28, 0xffffffff, 0x00000100,
827 0x9144, 0xffffffff, 0x00000100,
828 0x8d88, 0xffffffff, 0x00000100,
829 0x8d8c, 0xffffffff, 0x00000100,
830 0x9030, 0xffffffff, 0x00000100,
831 0x9034, 0xffffffff, 0x00000100,
832 0x9038, 0xffffffff, 0x00000100,
833 0x903c, 0xffffffff, 0x00000100,
834 0xad80, 0xffffffff, 0x00000100,
835 0xac54, 0xffffffff, 0x00000100,
836 0x897c, 0xffffffff, 0x06000100,
837 0x9868, 0xffffffff, 0x00000100,
838 0x9510, 0xffffffff, 0x00000100,
839 0xaf04, 0xffffffff, 0x00000100,
840 0xae04, 0xffffffff, 0x00000100,
841 0x949c, 0xffffffff, 0x00000100,
842 0x802c, 0xffffffff, 0xe0000000,
843 0x9160, 0xffffffff, 0x00010000,
844 0x9164, 0xffffffff, 0x00030002,
845 0x9168, 0xffffffff, 0x00040007,
846 0x916c, 0xffffffff, 0x00060005,
847 0x9170, 0xffffffff, 0x00090008,
848 0x9174, 0xffffffff, 0x00020001,
849 0x9178, 0xffffffff, 0x00040003,
850 0x917c, 0xffffffff, 0x00000007,
851 0x9180, 0xffffffff, 0x00060005,
852 0x9184, 0xffffffff, 0x00090008,
853 0x9188, 0xffffffff, 0x00030002,
854 0x918c, 0xffffffff, 0x00050004,
855 0x9190, 0xffffffff, 0x00000008,
856 0x9194, 0xffffffff, 0x00070006,
857 0x9198, 0xffffffff, 0x000a0009,
858 0x919c, 0xffffffff, 0x00040003,
859 0x91a0, 0xffffffff, 0x00060005,
860 0x91a4, 0xffffffff, 0x00000009,
861 0x91a8, 0xffffffff, 0x00080007,
862 0x91ac, 0xffffffff, 0x000b000a,
863 0x91b0, 0xffffffff, 0x00050004,
864 0x91b4, 0xffffffff, 0x00070006,
865 0x91b8, 0xffffffff, 0x0008000b,
866 0x91bc, 0xffffffff, 0x000a0009,
867 0x91c0, 0xffffffff, 0x000d000c,
868 0x9200, 0xffffffff, 0x00090008,
869 0x9204, 0xffffffff, 0x000b000a,
870 0x9208, 0xffffffff, 0x000c000f,
871 0x920c, 0xffffffff, 0x000e000d,
872 0x9210, 0xffffffff, 0x00110010,
873 0x9214, 0xffffffff, 0x000a0009,
874 0x9218, 0xffffffff, 0x000c000b,
875 0x921c, 0xffffffff, 0x0000000f,
876 0x9220, 0xffffffff, 0x000e000d,
877 0x9224, 0xffffffff, 0x00110010,
878 0x9228, 0xffffffff, 0x000b000a,
879 0x922c, 0xffffffff, 0x000d000c,
880 0x9230, 0xffffffff, 0x00000010,
881 0x9234, 0xffffffff, 0x000f000e,
882 0x9238, 0xffffffff, 0x00120011,
883 0x923c, 0xffffffff, 0x000c000b,
884 0x9240, 0xffffffff, 0x000e000d,
885 0x9244, 0xffffffff, 0x00000011,
886 0x9248, 0xffffffff, 0x0010000f,
887 0x924c, 0xffffffff, 0x00130012,
888 0x9250, 0xffffffff, 0x000d000c,
889 0x9254, 0xffffffff, 0x000f000e,
890 0x9258, 0xffffffff, 0x00100013,
891 0x925c, 0xffffffff, 0x00120011,
892 0x9260, 0xffffffff, 0x00150014,
893 0x9150, 0xffffffff, 0x96940200,
894 0x8708, 0xffffffff, 0x00900100,
895 0xc478, 0xffffffff, 0x00000080,
896 0xc404, 0xffffffff, 0x0020003f,
897 0x30, 0xffffffff, 0x0000001c,
898 0x34, 0x000f0000, 0x000f0000,
899 0x160c, 0xffffffff, 0x00000100,
900 0x1024, 0xffffffff, 0x00000100,
901 0x102c, 0x00000101, 0x00000000,
902 0x20a8, 0xffffffff, 0x00000104,
903 0x264c, 0x000c0000, 0x000c0000,
904 0x2648, 0x000c0000, 0x000c0000,
905 0x55e4, 0xff000fff, 0x00000100,
906 0x55e8, 0x00000001, 0x00000001,
907 0x2f50, 0x00000001, 0x00000001,
908 0x30cc, 0xc0000fff, 0x00000104,
909 0xc1e4, 0x00000001, 0x00000001,
910 0xd0c0, 0xfffffff0, 0x00000100,
911 0xd8c0, 0xfffffff0, 0x00000100
914 static const u32 oland_mgcg_cgcg_init[] =
916 0xc400, 0xffffffff, 0xfffffffc,
917 0x802c, 0xffffffff, 0xe0000000,
918 0x9a60, 0xffffffff, 0x00000100,
919 0x92a4, 0xffffffff, 0x00000100,
920 0xc164, 0xffffffff, 0x00000100,
921 0x9774, 0xffffffff, 0x00000100,
922 0x8984, 0xffffffff, 0x06000100,
923 0x8a18, 0xffffffff, 0x00000100,
924 0x92a0, 0xffffffff, 0x00000100,
925 0xc380, 0xffffffff, 0x00000100,
926 0x8b28, 0xffffffff, 0x00000100,
927 0x9144, 0xffffffff, 0x00000100,
928 0x8d88, 0xffffffff, 0x00000100,
929 0x8d8c, 0xffffffff, 0x00000100,
930 0x9030, 0xffffffff, 0x00000100,
931 0x9034, 0xffffffff, 0x00000100,
932 0x9038, 0xffffffff, 0x00000100,
933 0x903c, 0xffffffff, 0x00000100,
934 0xad80, 0xffffffff, 0x00000100,
935 0xac54, 0xffffffff, 0x00000100,
936 0x897c, 0xffffffff, 0x06000100,
937 0x9868, 0xffffffff, 0x00000100,
938 0x9510, 0xffffffff, 0x00000100,
939 0xaf04, 0xffffffff, 0x00000100,
940 0xae04, 0xffffffff, 0x00000100,
941 0x949c, 0xffffffff, 0x00000100,
942 0x802c, 0xffffffff, 0xe0000000,
943 0x9160, 0xffffffff, 0x00010000,
944 0x9164, 0xffffffff, 0x00030002,
945 0x9168, 0xffffffff, 0x00040007,
946 0x916c, 0xffffffff, 0x00060005,
947 0x9170, 0xffffffff, 0x00090008,
948 0x9174, 0xffffffff, 0x00020001,
949 0x9178, 0xffffffff, 0x00040003,
950 0x917c, 0xffffffff, 0x00000007,
951 0x9180, 0xffffffff, 0x00060005,
952 0x9184, 0xffffffff, 0x00090008,
953 0x9188, 0xffffffff, 0x00030002,
954 0x918c, 0xffffffff, 0x00050004,
955 0x9190, 0xffffffff, 0x00000008,
956 0x9194, 0xffffffff, 0x00070006,
957 0x9198, 0xffffffff, 0x000a0009,
958 0x919c, 0xffffffff, 0x00040003,
959 0x91a0, 0xffffffff, 0x00060005,
960 0x91a4, 0xffffffff, 0x00000009,
961 0x91a8, 0xffffffff, 0x00080007,
962 0x91ac, 0xffffffff, 0x000b000a,
963 0x91b0, 0xffffffff, 0x00050004,
964 0x91b4, 0xffffffff, 0x00070006,
965 0x91b8, 0xffffffff, 0x0008000b,
966 0x91bc, 0xffffffff, 0x000a0009,
967 0x91c0, 0xffffffff, 0x000d000c,
968 0x91c4, 0xffffffff, 0x00060005,
969 0x91c8, 0xffffffff, 0x00080007,
970 0x91cc, 0xffffffff, 0x0000000b,
971 0x91d0, 0xffffffff, 0x000a0009,
972 0x91d4, 0xffffffff, 0x000d000c,
973 0x9150, 0xffffffff, 0x96940200,
974 0x8708, 0xffffffff, 0x00900100,
975 0xc478, 0xffffffff, 0x00000080,
976 0xc404, 0xffffffff, 0x0020003f,
977 0x30, 0xffffffff, 0x0000001c,
978 0x34, 0x000f0000, 0x000f0000,
979 0x160c, 0xffffffff, 0x00000100,
980 0x1024, 0xffffffff, 0x00000100,
981 0x102c, 0x00000101, 0x00000000,
982 0x20a8, 0xffffffff, 0x00000104,
983 0x264c, 0x000c0000, 0x000c0000,
984 0x2648, 0x000c0000, 0x000c0000,
985 0x55e4, 0xff000fff, 0x00000100,
986 0x55e8, 0x00000001, 0x00000001,
987 0x2f50, 0x00000001, 0x00000001,
988 0x30cc, 0xc0000fff, 0x00000104,
989 0xc1e4, 0x00000001, 0x00000001,
990 0xd0c0, 0xfffffff0, 0x00000100,
991 0xd8c0, 0xfffffff0, 0x00000100
994 static const u32 hainan_mgcg_cgcg_init[] =
996 0xc400, 0xffffffff, 0xfffffffc,
997 0x802c, 0xffffffff, 0xe0000000,
998 0x9a60, 0xffffffff, 0x00000100,
999 0x92a4, 0xffffffff, 0x00000100,
1000 0xc164, 0xffffffff, 0x00000100,
1001 0x9774, 0xffffffff, 0x00000100,
1002 0x8984, 0xffffffff, 0x06000100,
1003 0x8a18, 0xffffffff, 0x00000100,
1004 0x92a0, 0xffffffff, 0x00000100,
1005 0xc380, 0xffffffff, 0x00000100,
1006 0x8b28, 0xffffffff, 0x00000100,
1007 0x9144, 0xffffffff, 0x00000100,
1008 0x8d88, 0xffffffff, 0x00000100,
1009 0x8d8c, 0xffffffff, 0x00000100,
1010 0x9030, 0xffffffff, 0x00000100,
1011 0x9034, 0xffffffff, 0x00000100,
1012 0x9038, 0xffffffff, 0x00000100,
1013 0x903c, 0xffffffff, 0x00000100,
1014 0xad80, 0xffffffff, 0x00000100,
1015 0xac54, 0xffffffff, 0x00000100,
1016 0x897c, 0xffffffff, 0x06000100,
1017 0x9868, 0xffffffff, 0x00000100,
1018 0x9510, 0xffffffff, 0x00000100,
1019 0xaf04, 0xffffffff, 0x00000100,
1020 0xae04, 0xffffffff, 0x00000100,
1021 0x949c, 0xffffffff, 0x00000100,
1022 0x802c, 0xffffffff, 0xe0000000,
1023 0x9160, 0xffffffff, 0x00010000,
1024 0x9164, 0xffffffff, 0x00030002,
1025 0x9168, 0xffffffff, 0x00040007,
1026 0x916c, 0xffffffff, 0x00060005,
1027 0x9170, 0xffffffff, 0x00090008,
1028 0x9174, 0xffffffff, 0x00020001,
1029 0x9178, 0xffffffff, 0x00040003,
1030 0x917c, 0xffffffff, 0x00000007,
1031 0x9180, 0xffffffff, 0x00060005,
1032 0x9184, 0xffffffff, 0x00090008,
1033 0x9188, 0xffffffff, 0x00030002,
1034 0x918c, 0xffffffff, 0x00050004,
1035 0x9190, 0xffffffff, 0x00000008,
1036 0x9194, 0xffffffff, 0x00070006,
1037 0x9198, 0xffffffff, 0x000a0009,
1038 0x919c, 0xffffffff, 0x00040003,
1039 0x91a0, 0xffffffff, 0x00060005,
1040 0x91a4, 0xffffffff, 0x00000009,
1041 0x91a8, 0xffffffff, 0x00080007,
1042 0x91ac, 0xffffffff, 0x000b000a,
1043 0x91b0, 0xffffffff, 0x00050004,
1044 0x91b4, 0xffffffff, 0x00070006,
1045 0x91b8, 0xffffffff, 0x0008000b,
1046 0x91bc, 0xffffffff, 0x000a0009,
1047 0x91c0, 0xffffffff, 0x000d000c,
1048 0x91c4, 0xffffffff, 0x00060005,
1049 0x91c8, 0xffffffff, 0x00080007,
1050 0x91cc, 0xffffffff, 0x0000000b,
1051 0x91d0, 0xffffffff, 0x000a0009,
1052 0x91d4, 0xffffffff, 0x000d000c,
1053 0x9150, 0xffffffff, 0x96940200,
1054 0x8708, 0xffffffff, 0x00900100,
1055 0xc478, 0xffffffff, 0x00000080,
1056 0xc404, 0xffffffff, 0x0020003f,
1057 0x30, 0xffffffff, 0x0000001c,
1058 0x34, 0x000f0000, 0x000f0000,
1059 0x160c, 0xffffffff, 0x00000100,
1060 0x1024, 0xffffffff, 0x00000100,
1061 0x20a8, 0xffffffff, 0x00000104,
1062 0x264c, 0x000c0000, 0x000c0000,
1063 0x2648, 0x000c0000, 0x000c0000,
1064 0x2f50, 0x00000001, 0x00000001,
1065 0x30cc, 0xc0000fff, 0x00000104,
1066 0xc1e4, 0x00000001, 0x00000001,
1067 0xd0c0, 0xfffffff0, 0x00000100,
1068 0xd8c0, 0xfffffff0, 0x00000100
1071 static u32 verde_pg_init[] =
1073 0x353c, 0xffffffff, 0x40000,
1074 0x3538, 0xffffffff, 0x200010ff,
1075 0x353c, 0xffffffff, 0x0,
1076 0x353c, 0xffffffff, 0x0,
1077 0x353c, 0xffffffff, 0x0,
1078 0x353c, 0xffffffff, 0x0,
1079 0x353c, 0xffffffff, 0x0,
1080 0x353c, 0xffffffff, 0x7007,
1081 0x3538, 0xffffffff, 0x300010ff,
1082 0x353c, 0xffffffff, 0x0,
1083 0x353c, 0xffffffff, 0x0,
1084 0x353c, 0xffffffff, 0x0,
1085 0x353c, 0xffffffff, 0x0,
1086 0x353c, 0xffffffff, 0x0,
1087 0x353c, 0xffffffff, 0x400000,
1088 0x3538, 0xffffffff, 0x100010ff,
1089 0x353c, 0xffffffff, 0x0,
1090 0x353c, 0xffffffff, 0x0,
1091 0x353c, 0xffffffff, 0x0,
1092 0x353c, 0xffffffff, 0x0,
1093 0x353c, 0xffffffff, 0x0,
1094 0x353c, 0xffffffff, 0x120200,
1095 0x3538, 0xffffffff, 0x500010ff,
1096 0x353c, 0xffffffff, 0x0,
1097 0x353c, 0xffffffff, 0x0,
1098 0x353c, 0xffffffff, 0x0,
1099 0x353c, 0xffffffff, 0x0,
1100 0x353c, 0xffffffff, 0x0,
1101 0x353c, 0xffffffff, 0x1e1e16,
1102 0x3538, 0xffffffff, 0x600010ff,
1103 0x353c, 0xffffffff, 0x0,
1104 0x353c, 0xffffffff, 0x0,
1105 0x353c, 0xffffffff, 0x0,
1106 0x353c, 0xffffffff, 0x0,
1107 0x353c, 0xffffffff, 0x0,
1108 0x353c, 0xffffffff, 0x171f1e,
1109 0x3538, 0xffffffff, 0x700010ff,
1110 0x353c, 0xffffffff, 0x0,
1111 0x353c, 0xffffffff, 0x0,
1112 0x353c, 0xffffffff, 0x0,
1113 0x353c, 0xffffffff, 0x0,
1114 0x353c, 0xffffffff, 0x0,
1115 0x353c, 0xffffffff, 0x0,
1116 0x3538, 0xffffffff, 0x9ff,
1117 0x3500, 0xffffffff, 0x0,
1118 0x3504, 0xffffffff, 0x10000800,
1119 0x3504, 0xffffffff, 0xf,
1120 0x3504, 0xffffffff, 0xf,
1121 0x3500, 0xffffffff, 0x4,
1122 0x3504, 0xffffffff, 0x1000051e,
1123 0x3504, 0xffffffff, 0xffff,
1124 0x3504, 0xffffffff, 0xffff,
1125 0x3500, 0xffffffff, 0x8,
1126 0x3504, 0xffffffff, 0x80500,
1127 0x3500, 0xffffffff, 0x12,
1128 0x3504, 0xffffffff, 0x9050c,
1129 0x3500, 0xffffffff, 0x1d,
1130 0x3504, 0xffffffff, 0xb052c,
1131 0x3500, 0xffffffff, 0x2a,
1132 0x3504, 0xffffffff, 0x1053e,
1133 0x3500, 0xffffffff, 0x2d,
1134 0x3504, 0xffffffff, 0x10546,
1135 0x3500, 0xffffffff, 0x30,
1136 0x3504, 0xffffffff, 0xa054e,
1137 0x3500, 0xffffffff, 0x3c,
1138 0x3504, 0xffffffff, 0x1055f,
1139 0x3500, 0xffffffff, 0x3f,
1140 0x3504, 0xffffffff, 0x10567,
1141 0x3500, 0xffffffff, 0x42,
1142 0x3504, 0xffffffff, 0x1056f,
1143 0x3500, 0xffffffff, 0x45,
1144 0x3504, 0xffffffff, 0x10572,
1145 0x3500, 0xffffffff, 0x48,
1146 0x3504, 0xffffffff, 0x20575,
1147 0x3500, 0xffffffff, 0x4c,
1148 0x3504, 0xffffffff, 0x190801,
1149 0x3500, 0xffffffff, 0x67,
1150 0x3504, 0xffffffff, 0x1082a,
1151 0x3500, 0xffffffff, 0x6a,
1152 0x3504, 0xffffffff, 0x1b082d,
1153 0x3500, 0xffffffff, 0x87,
1154 0x3504, 0xffffffff, 0x310851,
1155 0x3500, 0xffffffff, 0xba,
1156 0x3504, 0xffffffff, 0x891,
1157 0x3500, 0xffffffff, 0xbc,
1158 0x3504, 0xffffffff, 0x893,
1159 0x3500, 0xffffffff, 0xbe,
1160 0x3504, 0xffffffff, 0x20895,
1161 0x3500, 0xffffffff, 0xc2,
1162 0x3504, 0xffffffff, 0x20899,
1163 0x3500, 0xffffffff, 0xc6,
1164 0x3504, 0xffffffff, 0x2089d,
1165 0x3500, 0xffffffff, 0xca,
1166 0x3504, 0xffffffff, 0x8a1,
1167 0x3500, 0xffffffff, 0xcc,
1168 0x3504, 0xffffffff, 0x8a3,
1169 0x3500, 0xffffffff, 0xce,
1170 0x3504, 0xffffffff, 0x308a5,
1171 0x3500, 0xffffffff, 0xd3,
1172 0x3504, 0xffffffff, 0x6d08cd,
1173 0x3500, 0xffffffff, 0x142,
1174 0x3504, 0xffffffff, 0x2000095a,
1175 0x3504, 0xffffffff, 0x1,
1176 0x3500, 0xffffffff, 0x144,
1177 0x3504, 0xffffffff, 0x301f095b,
1178 0x3500, 0xffffffff, 0x165,
1179 0x3504, 0xffffffff, 0xc094d,
1180 0x3500, 0xffffffff, 0x173,
1181 0x3504, 0xffffffff, 0xf096d,
1182 0x3500, 0xffffffff, 0x184,
1183 0x3504, 0xffffffff, 0x15097f,
1184 0x3500, 0xffffffff, 0x19b,
1185 0x3504, 0xffffffff, 0xc0998,
1186 0x3500, 0xffffffff, 0x1a9,
1187 0x3504, 0xffffffff, 0x409a7,
1188 0x3500, 0xffffffff, 0x1af,
1189 0x3504, 0xffffffff, 0xcdc,
1190 0x3500, 0xffffffff, 0x1b1,
1191 0x3504, 0xffffffff, 0x800,
1192 0x3508, 0xffffffff, 0x6c9b2000,
1193 0x3510, 0xfc00, 0x2000,
1194 0x3544, 0xffffffff, 0xfc0,
1195 0x28d4, 0x00000100, 0x100
1198 static void si_init_golden_registers(struct radeon_device *rdev)
1200 switch (rdev->family) {
1202 radeon_program_register_sequence(rdev,
1203 tahiti_golden_registers,
1204 (const u32)ARRAY_SIZE(tahiti_golden_registers));
1205 radeon_program_register_sequence(rdev,
1206 tahiti_golden_rlc_registers,
1207 (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
1208 radeon_program_register_sequence(rdev,
1209 tahiti_mgcg_cgcg_init,
1210 (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
1211 radeon_program_register_sequence(rdev,
1212 tahiti_golden_registers2,
1213 (const u32)ARRAY_SIZE(tahiti_golden_registers2));
1216 radeon_program_register_sequence(rdev,
1217 pitcairn_golden_registers,
1218 (const u32)ARRAY_SIZE(pitcairn_golden_registers));
1219 radeon_program_register_sequence(rdev,
1220 pitcairn_golden_rlc_registers,
1221 (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
1222 radeon_program_register_sequence(rdev,
1223 pitcairn_mgcg_cgcg_init,
1224 (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
1227 radeon_program_register_sequence(rdev,
1228 verde_golden_registers,
1229 (const u32)ARRAY_SIZE(verde_golden_registers));
1230 radeon_program_register_sequence(rdev,
1231 verde_golden_rlc_registers,
1232 (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
1233 radeon_program_register_sequence(rdev,
1234 verde_mgcg_cgcg_init,
1235 (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
1236 radeon_program_register_sequence(rdev,
1238 (const u32)ARRAY_SIZE(verde_pg_init));
1241 radeon_program_register_sequence(rdev,
1242 oland_golden_registers,
1243 (const u32)ARRAY_SIZE(oland_golden_registers));
1244 radeon_program_register_sequence(rdev,
1245 oland_golden_rlc_registers,
1246 (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
1247 radeon_program_register_sequence(rdev,
1248 oland_mgcg_cgcg_init,
1249 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
1252 radeon_program_register_sequence(rdev,
1253 hainan_golden_registers,
1254 (const u32)ARRAY_SIZE(hainan_golden_registers));
1255 radeon_program_register_sequence(rdev,
1256 hainan_golden_registers2,
1257 (const u32)ARRAY_SIZE(hainan_golden_registers2));
1258 radeon_program_register_sequence(rdev,
1259 hainan_mgcg_cgcg_init,
1260 (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
1268 * si_get_allowed_info_register - fetch the register for the info ioctl
1270 * @rdev: radeon_device pointer
1271 * @reg: register offset in bytes
1272 * @val: register value
1274 * Returns 0 for success or -EINVAL for an invalid register
1277 int si_get_allowed_info_register(struct radeon_device *rdev,
1283 case GRBM_STATUS_SE0:
1284 case GRBM_STATUS_SE1:
1287 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET):
1288 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET):
1297 #define PCIE_BUS_CLK 10000
1298 #define TCLK (PCIE_BUS_CLK / 10)
1301 * si_get_xclk - get the xclk
1303 * @rdev: radeon_device pointer
1305 * Returns the reference clock used by the gfx engine
1308 u32 si_get_xclk(struct radeon_device *rdev)
1310 u32 reference_clock = rdev->clock.spll.reference_freq;
1313 tmp = RREG32(CG_CLKPIN_CNTL_2);
1314 if (tmp & MUX_TCLK_TO_XCLK)
1317 tmp = RREG32(CG_CLKPIN_CNTL);
1318 if (tmp & XTALIN_DIVIDE)
1319 return reference_clock / 4;
1321 return reference_clock;
1324 /* get temperature in millidegrees */
1325 int si_get_temp(struct radeon_device *rdev)
1328 int actual_temp = 0;
1330 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
1336 actual_temp = temp & 0x1ff;
1338 actual_temp = (actual_temp * 1000);
1343 #define TAHITI_IO_MC_REGS_SIZE 36
1345 static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1346 {0x0000006f, 0x03044000},
1347 {0x00000070, 0x0480c018},
1348 {0x00000071, 0x00000040},
1349 {0x00000072, 0x01000000},
1350 {0x00000074, 0x000000ff},
1351 {0x00000075, 0x00143400},
1352 {0x00000076, 0x08ec0800},
1353 {0x00000077, 0x040000cc},
1354 {0x00000079, 0x00000000},
1355 {0x0000007a, 0x21000409},
1356 {0x0000007c, 0x00000000},
1357 {0x0000007d, 0xe8000000},
1358 {0x0000007e, 0x044408a8},
1359 {0x0000007f, 0x00000003},
1360 {0x00000080, 0x00000000},
1361 {0x00000081, 0x01000000},
1362 {0x00000082, 0x02000000},
1363 {0x00000083, 0x00000000},
1364 {0x00000084, 0xe3f3e4f4},
1365 {0x00000085, 0x00052024},
1366 {0x00000087, 0x00000000},
1367 {0x00000088, 0x66036603},
1368 {0x00000089, 0x01000000},
1369 {0x0000008b, 0x1c0a0000},
1370 {0x0000008c, 0xff010000},
1371 {0x0000008e, 0xffffefff},
1372 {0x0000008f, 0xfff3efff},
1373 {0x00000090, 0xfff3efbf},
1374 {0x00000094, 0x00101101},
1375 {0x00000095, 0x00000fff},
1376 {0x00000096, 0x00116fff},
1377 {0x00000097, 0x60010000},
1378 {0x00000098, 0x10010000},
1379 {0x00000099, 0x00006000},
1380 {0x0000009a, 0x00001000},
1381 {0x0000009f, 0x00a77400}
1384 static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1385 {0x0000006f, 0x03044000},
1386 {0x00000070, 0x0480c018},
1387 {0x00000071, 0x00000040},
1388 {0x00000072, 0x01000000},
1389 {0x00000074, 0x000000ff},
1390 {0x00000075, 0x00143400},
1391 {0x00000076, 0x08ec0800},
1392 {0x00000077, 0x040000cc},
1393 {0x00000079, 0x00000000},
1394 {0x0000007a, 0x21000409},
1395 {0x0000007c, 0x00000000},
1396 {0x0000007d, 0xe8000000},
1397 {0x0000007e, 0x044408a8},
1398 {0x0000007f, 0x00000003},
1399 {0x00000080, 0x00000000},
1400 {0x00000081, 0x01000000},
1401 {0x00000082, 0x02000000},
1402 {0x00000083, 0x00000000},
1403 {0x00000084, 0xe3f3e4f4},
1404 {0x00000085, 0x00052024},
1405 {0x00000087, 0x00000000},
1406 {0x00000088, 0x66036603},
1407 {0x00000089, 0x01000000},
1408 {0x0000008b, 0x1c0a0000},
1409 {0x0000008c, 0xff010000},
1410 {0x0000008e, 0xffffefff},
1411 {0x0000008f, 0xfff3efff},
1412 {0x00000090, 0xfff3efbf},
1413 {0x00000094, 0x00101101},
1414 {0x00000095, 0x00000fff},
1415 {0x00000096, 0x00116fff},
1416 {0x00000097, 0x60010000},
1417 {0x00000098, 0x10010000},
1418 {0x00000099, 0x00006000},
1419 {0x0000009a, 0x00001000},
1420 {0x0000009f, 0x00a47400}
1423 static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1424 {0x0000006f, 0x03044000},
1425 {0x00000070, 0x0480c018},
1426 {0x00000071, 0x00000040},
1427 {0x00000072, 0x01000000},
1428 {0x00000074, 0x000000ff},
1429 {0x00000075, 0x00143400},
1430 {0x00000076, 0x08ec0800},
1431 {0x00000077, 0x040000cc},
1432 {0x00000079, 0x00000000},
1433 {0x0000007a, 0x21000409},
1434 {0x0000007c, 0x00000000},
1435 {0x0000007d, 0xe8000000},
1436 {0x0000007e, 0x044408a8},
1437 {0x0000007f, 0x00000003},
1438 {0x00000080, 0x00000000},
1439 {0x00000081, 0x01000000},
1440 {0x00000082, 0x02000000},
1441 {0x00000083, 0x00000000},
1442 {0x00000084, 0xe3f3e4f4},
1443 {0x00000085, 0x00052024},
1444 {0x00000087, 0x00000000},
1445 {0x00000088, 0x66036603},
1446 {0x00000089, 0x01000000},
1447 {0x0000008b, 0x1c0a0000},
1448 {0x0000008c, 0xff010000},
1449 {0x0000008e, 0xffffefff},
1450 {0x0000008f, 0xfff3efff},
1451 {0x00000090, 0xfff3efbf},
1452 {0x00000094, 0x00101101},
1453 {0x00000095, 0x00000fff},
1454 {0x00000096, 0x00116fff},
1455 {0x00000097, 0x60010000},
1456 {0x00000098, 0x10010000},
1457 {0x00000099, 0x00006000},
1458 {0x0000009a, 0x00001000},
1459 {0x0000009f, 0x00a37400}
1462 static const u32 oland_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1463 {0x0000006f, 0x03044000},
1464 {0x00000070, 0x0480c018},
1465 {0x00000071, 0x00000040},
1466 {0x00000072, 0x01000000},
1467 {0x00000074, 0x000000ff},
1468 {0x00000075, 0x00143400},
1469 {0x00000076, 0x08ec0800},
1470 {0x00000077, 0x040000cc},
1471 {0x00000079, 0x00000000},
1472 {0x0000007a, 0x21000409},
1473 {0x0000007c, 0x00000000},
1474 {0x0000007d, 0xe8000000},
1475 {0x0000007e, 0x044408a8},
1476 {0x0000007f, 0x00000003},
1477 {0x00000080, 0x00000000},
1478 {0x00000081, 0x01000000},
1479 {0x00000082, 0x02000000},
1480 {0x00000083, 0x00000000},
1481 {0x00000084, 0xe3f3e4f4},
1482 {0x00000085, 0x00052024},
1483 {0x00000087, 0x00000000},
1484 {0x00000088, 0x66036603},
1485 {0x00000089, 0x01000000},
1486 {0x0000008b, 0x1c0a0000},
1487 {0x0000008c, 0xff010000},
1488 {0x0000008e, 0xffffefff},
1489 {0x0000008f, 0xfff3efff},
1490 {0x00000090, 0xfff3efbf},
1491 {0x00000094, 0x00101101},
1492 {0x00000095, 0x00000fff},
1493 {0x00000096, 0x00116fff},
1494 {0x00000097, 0x60010000},
1495 {0x00000098, 0x10010000},
1496 {0x00000099, 0x00006000},
1497 {0x0000009a, 0x00001000},
1498 {0x0000009f, 0x00a17730}
1501 static const u32 hainan_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1502 {0x0000006f, 0x03044000},
1503 {0x00000070, 0x0480c018},
1504 {0x00000071, 0x00000040},
1505 {0x00000072, 0x01000000},
1506 {0x00000074, 0x000000ff},
1507 {0x00000075, 0x00143400},
1508 {0x00000076, 0x08ec0800},
1509 {0x00000077, 0x040000cc},
1510 {0x00000079, 0x00000000},
1511 {0x0000007a, 0x21000409},
1512 {0x0000007c, 0x00000000},
1513 {0x0000007d, 0xe8000000},
1514 {0x0000007e, 0x044408a8},
1515 {0x0000007f, 0x00000003},
1516 {0x00000080, 0x00000000},
1517 {0x00000081, 0x01000000},
1518 {0x00000082, 0x02000000},
1519 {0x00000083, 0x00000000},
1520 {0x00000084, 0xe3f3e4f4},
1521 {0x00000085, 0x00052024},
1522 {0x00000087, 0x00000000},
1523 {0x00000088, 0x66036603},
1524 {0x00000089, 0x01000000},
1525 {0x0000008b, 0x1c0a0000},
1526 {0x0000008c, 0xff010000},
1527 {0x0000008e, 0xffffefff},
1528 {0x0000008f, 0xfff3efff},
1529 {0x00000090, 0xfff3efbf},
1530 {0x00000094, 0x00101101},
1531 {0x00000095, 0x00000fff},
1532 {0x00000096, 0x00116fff},
1533 {0x00000097, 0x60010000},
1534 {0x00000098, 0x10010000},
1535 {0x00000099, 0x00006000},
1536 {0x0000009a, 0x00001000},
1537 {0x0000009f, 0x00a07730}
1541 int si_mc_load_microcode(struct radeon_device *rdev)
1543 const __be32 *fw_data = NULL;
1544 const __le32 *new_fw_data = NULL;
1545 u32 running, blackout = 0;
1546 u32 *io_mc_regs = NULL;
1547 const __le32 *new_io_mc_regs = NULL;
1548 int i, regs_size, ucode_size;
1554 const struct mc_firmware_header_v1_0 *hdr =
1555 (const struct mc_firmware_header_v1_0 *)rdev->mc_fw->data;
1557 radeon_ucode_print_mc_hdr(&hdr->header);
1558 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
1559 new_io_mc_regs = (const __le32 *)
1560 (rdev->mc_fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
1561 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1562 new_fw_data = (const __le32 *)
1563 (rdev->mc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1565 ucode_size = rdev->mc_fw->size / 4;
1567 switch (rdev->family) {
1569 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
1570 regs_size = TAHITI_IO_MC_REGS_SIZE;
1573 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
1574 regs_size = TAHITI_IO_MC_REGS_SIZE;
1578 io_mc_regs = (u32 *)&verde_io_mc_regs;
1579 regs_size = TAHITI_IO_MC_REGS_SIZE;
1582 io_mc_regs = (u32 *)&oland_io_mc_regs;
1583 regs_size = TAHITI_IO_MC_REGS_SIZE;
1586 io_mc_regs = (u32 *)&hainan_io_mc_regs;
1587 regs_size = TAHITI_IO_MC_REGS_SIZE;
1590 fw_data = (const __be32 *)rdev->mc_fw->data;
1593 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
1597 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1598 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
1601 /* reset the engine and set to writable */
1602 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1603 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
1605 /* load mc io regs */
1606 for (i = 0; i < regs_size; i++) {
1608 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
1609 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
1611 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
1612 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
1615 /* load the MC ucode */
1616 for (i = 0; i < ucode_size; i++) {
1618 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
1620 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
1623 /* put the engine back into the active state */
1624 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1625 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
1626 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
1628 /* wait for training to complete */
1629 for (i = 0; i < rdev->usec_timeout; i++) {
1630 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
1634 for (i = 0; i < rdev->usec_timeout; i++) {
1635 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
1641 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
1647 static int si_init_microcode(struct radeon_device *rdev)
1649 const char *chip_name;
1650 const char *new_chip_name;
1651 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
1652 size_t smc_req_size, mc2_req_size;
1659 switch (rdev->family) {
1661 chip_name = "TAHITI";
1662 new_chip_name = "tahiti";
1663 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1664 me_req_size = SI_PM4_UCODE_SIZE * 4;
1665 ce_req_size = SI_CE_UCODE_SIZE * 4;
1666 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1667 mc_req_size = SI_MC_UCODE_SIZE * 4;
1668 mc2_req_size = TAHITI_MC_UCODE_SIZE * 4;
1669 smc_req_size = ALIGN(TAHITI_SMC_UCODE_SIZE, 4);
1672 chip_name = "PITCAIRN";
1673 new_chip_name = "pitcairn";
1674 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1675 me_req_size = SI_PM4_UCODE_SIZE * 4;
1676 ce_req_size = SI_CE_UCODE_SIZE * 4;
1677 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1678 mc_req_size = SI_MC_UCODE_SIZE * 4;
1679 mc2_req_size = PITCAIRN_MC_UCODE_SIZE * 4;
1680 smc_req_size = ALIGN(PITCAIRN_SMC_UCODE_SIZE, 4);
1683 chip_name = "VERDE";
1684 new_chip_name = "verde";
1685 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1686 me_req_size = SI_PM4_UCODE_SIZE * 4;
1687 ce_req_size = SI_CE_UCODE_SIZE * 4;
1688 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1689 mc_req_size = SI_MC_UCODE_SIZE * 4;
1690 mc2_req_size = VERDE_MC_UCODE_SIZE * 4;
1691 smc_req_size = ALIGN(VERDE_SMC_UCODE_SIZE, 4);
1694 chip_name = "OLAND";
1695 new_chip_name = "oland";
1696 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1697 me_req_size = SI_PM4_UCODE_SIZE * 4;
1698 ce_req_size = SI_CE_UCODE_SIZE * 4;
1699 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1700 mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
1701 smc_req_size = ALIGN(OLAND_SMC_UCODE_SIZE, 4);
1704 chip_name = "HAINAN";
1705 new_chip_name = "hainan";
1706 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1707 me_req_size = SI_PM4_UCODE_SIZE * 4;
1708 ce_req_size = SI_CE_UCODE_SIZE * 4;
1709 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1710 mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
1711 smc_req_size = ALIGN(HAINAN_SMC_UCODE_SIZE, 4);
1716 DRM_INFO("Loading %s Microcode\n", new_chip_name);
1718 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", new_chip_name);
1719 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
1721 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1722 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
1725 if (rdev->pfp_fw->size != pfp_req_size) {
1727 "si_cp: Bogus length %zu in firmware \"%s\"\n",
1728 rdev->pfp_fw->size, fw_name);
1733 err = radeon_ucode_validate(rdev->pfp_fw);
1736 "si_cp: validation failed for firmware \"%s\"\n",
1744 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", new_chip_name);
1745 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1747 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1748 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1751 if (rdev->me_fw->size != me_req_size) {
1753 "si_cp: Bogus length %zu in firmware \"%s\"\n",
1754 rdev->me_fw->size, fw_name);
1758 err = radeon_ucode_validate(rdev->me_fw);
1761 "si_cp: validation failed for firmware \"%s\"\n",
1769 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", new_chip_name);
1770 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
1772 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
1773 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
1776 if (rdev->ce_fw->size != ce_req_size) {
1778 "si_cp: Bogus length %zu in firmware \"%s\"\n",
1779 rdev->ce_fw->size, fw_name);
1783 err = radeon_ucode_validate(rdev->ce_fw);
1786 "si_cp: validation failed for firmware \"%s\"\n",
1794 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", new_chip_name);
1795 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
1797 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
1798 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
1801 if (rdev->rlc_fw->size != rlc_req_size) {
1803 "si_rlc: Bogus length %zu in firmware \"%s\"\n",
1804 rdev->rlc_fw->size, fw_name);
1808 err = radeon_ucode_validate(rdev->rlc_fw);
1811 "si_cp: validation failed for firmware \"%s\"\n",
1819 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", new_chip_name);
1820 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1822 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc2.bin", chip_name);
1823 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1825 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
1826 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1830 if ((rdev->mc_fw->size != mc_req_size) &&
1831 (rdev->mc_fw->size != mc2_req_size)) {
1833 "si_mc: Bogus length %zu in firmware \"%s\"\n",
1834 rdev->mc_fw->size, fw_name);
1837 DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size);
1839 err = radeon_ucode_validate(rdev->mc_fw);
1842 "si_cp: validation failed for firmware \"%s\"\n",
1850 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", new_chip_name);
1851 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
1853 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
1854 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
1857 "smc: error loading firmware \"%s\"\n",
1859 release_firmware(rdev->smc_fw);
1860 rdev->smc_fw = NULL;
1862 } else if (rdev->smc_fw->size != smc_req_size) {
1864 "si_smc: Bogus length %zu in firmware \"%s\"\n",
1865 rdev->smc_fw->size, fw_name);
1869 err = radeon_ucode_validate(rdev->smc_fw);
1872 "si_cp: validation failed for firmware \"%s\"\n",
1881 rdev->new_fw = false;
1882 } else if (new_fw < 6) {
1883 printk(KERN_ERR "si_fw: mixing new and old firmware!\n");
1886 rdev->new_fw = true;
1892 "si_cp: Failed to load firmware \"%s\"\n",
1894 release_firmware(rdev->pfp_fw);
1895 rdev->pfp_fw = NULL;
1896 release_firmware(rdev->me_fw);
1898 release_firmware(rdev->ce_fw);
1900 release_firmware(rdev->rlc_fw);
1901 rdev->rlc_fw = NULL;
1902 release_firmware(rdev->mc_fw);
1904 release_firmware(rdev->smc_fw);
1905 rdev->smc_fw = NULL;
1910 /* watermark setup */
1911 static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
1912 struct radeon_crtc *radeon_crtc,
1913 struct drm_display_mode *mode,
1914 struct drm_display_mode *other_mode)
1916 u32 tmp, buffer_alloc, i;
1917 u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
1920 * There are 3 line buffers, each one shared by 2 display controllers.
1921 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
1922 * the display controllers. The paritioning is done via one of four
1923 * preset allocations specified in bits 21:20:
1925 * 2 - whole lb, other crtc must be disabled
1927 /* this can get tricky if we have two large displays on a paired group
1928 * of crtcs. Ideally for multiple large displays we'd assign them to
1929 * non-linked crtcs for maximum line buffer allocation.
1931 if (radeon_crtc->base.enabled && mode) {
1936 tmp = 2; /* whole */
1944 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
1945 DC_LB_MEMORY_CONFIG(tmp));
1947 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1948 DMIF_BUFFERS_ALLOCATED(buffer_alloc));
1949 for (i = 0; i < rdev->usec_timeout; i++) {
1950 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
1951 DMIF_BUFFERS_ALLOCATED_COMPLETED)
1956 if (radeon_crtc->base.enabled && mode) {
1966 /* controller not enabled, so no lb used */
1970 static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
1972 u32 tmp = RREG32(MC_SHARED_CHMAP);
1974 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1997 struct dce6_wm_params {
1998 u32 dram_channels; /* number of dram channels */
1999 u32 yclk; /* bandwidth per dram data pin in kHz */
2000 u32 sclk; /* engine clock in kHz */
2001 u32 disp_clk; /* display clock in kHz */
2002 u32 src_width; /* viewport width */
2003 u32 active_time; /* active display time in ns */
2004 u32 blank_time; /* blank time in ns */
2005 bool interlaced; /* mode is interlaced */
2006 fixed20_12 vsc; /* vertical scale ratio */
2007 u32 num_heads; /* number of active crtcs */
2008 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
2009 u32 lb_size; /* line buffer allocated to pipe */
2010 u32 vtaps; /* vertical scaler taps */
2013 static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
2015 /* Calculate raw DRAM Bandwidth */
2016 fixed20_12 dram_efficiency; /* 0.7 */
2017 fixed20_12 yclk, dram_channels, bandwidth;
2020 a.full = dfixed_const(1000);
2021 yclk.full = dfixed_const(wm->yclk);
2022 yclk.full = dfixed_div(yclk, a);
2023 dram_channels.full = dfixed_const(wm->dram_channels * 4);
2024 a.full = dfixed_const(10);
2025 dram_efficiency.full = dfixed_const(7);
2026 dram_efficiency.full = dfixed_div(dram_efficiency, a);
2027 bandwidth.full = dfixed_mul(dram_channels, yclk);
2028 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
2030 return dfixed_trunc(bandwidth);
2033 static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
2035 /* Calculate DRAM Bandwidth and the part allocated to display. */
2036 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
2037 fixed20_12 yclk, dram_channels, bandwidth;
2040 a.full = dfixed_const(1000);
2041 yclk.full = dfixed_const(wm->yclk);
2042 yclk.full = dfixed_div(yclk, a);
2043 dram_channels.full = dfixed_const(wm->dram_channels * 4);
2044 a.full = dfixed_const(10);
2045 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
2046 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
2047 bandwidth.full = dfixed_mul(dram_channels, yclk);
2048 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
2050 return dfixed_trunc(bandwidth);
2053 static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
2055 /* Calculate the display Data return Bandwidth */
2056 fixed20_12 return_efficiency; /* 0.8 */
2057 fixed20_12 sclk, bandwidth;
2060 a.full = dfixed_const(1000);
2061 sclk.full = dfixed_const(wm->sclk);
2062 sclk.full = dfixed_div(sclk, a);
2063 a.full = dfixed_const(10);
2064 return_efficiency.full = dfixed_const(8);
2065 return_efficiency.full = dfixed_div(return_efficiency, a);
2066 a.full = dfixed_const(32);
2067 bandwidth.full = dfixed_mul(a, sclk);
2068 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
2070 return dfixed_trunc(bandwidth);
2073 static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
2078 static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
2080 /* Calculate the DMIF Request Bandwidth */
2081 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
2082 fixed20_12 disp_clk, sclk, bandwidth;
2083 fixed20_12 a, b1, b2;
2086 a.full = dfixed_const(1000);
2087 disp_clk.full = dfixed_const(wm->disp_clk);
2088 disp_clk.full = dfixed_div(disp_clk, a);
2089 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
2090 b1.full = dfixed_mul(a, disp_clk);
2092 a.full = dfixed_const(1000);
2093 sclk.full = dfixed_const(wm->sclk);
2094 sclk.full = dfixed_div(sclk, a);
2095 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
2096 b2.full = dfixed_mul(a, sclk);
2098 a.full = dfixed_const(10);
2099 disp_clk_request_efficiency.full = dfixed_const(8);
2100 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
2102 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
2104 a.full = dfixed_const(min_bandwidth);
2105 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
2107 return dfixed_trunc(bandwidth);
2110 static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
2112 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
2113 u32 dram_bandwidth = dce6_dram_bandwidth(wm);
2114 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
2115 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
2117 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
2120 static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
2122 /* Calculate the display mode Average Bandwidth
2123 * DisplayMode should contain the source and destination dimensions,
2127 fixed20_12 line_time;
2128 fixed20_12 src_width;
2129 fixed20_12 bandwidth;
2132 a.full = dfixed_const(1000);
2133 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
2134 line_time.full = dfixed_div(line_time, a);
2135 bpp.full = dfixed_const(wm->bytes_per_pixel);
2136 src_width.full = dfixed_const(wm->src_width);
2137 bandwidth.full = dfixed_mul(src_width, bpp);
2138 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
2139 bandwidth.full = dfixed_div(bandwidth, line_time);
2141 return dfixed_trunc(bandwidth);
2144 static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
2146 /* First calcualte the latency in ns */
2147 u32 mc_latency = 2000; /* 2000 ns. */
2148 u32 available_bandwidth = dce6_available_bandwidth(wm);
2149 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
2150 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
2151 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
2152 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
2153 (wm->num_heads * cursor_line_pair_return_time);
2154 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
2155 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
2156 u32 tmp, dmif_size = 12288;
2159 if (wm->num_heads == 0)
2162 a.full = dfixed_const(2);
2163 b.full = dfixed_const(1);
2164 if ((wm->vsc.full > a.full) ||
2165 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
2167 ((wm->vsc.full >= a.full) && wm->interlaced))
2168 max_src_lines_per_dst_line = 4;
2170 max_src_lines_per_dst_line = 2;
2172 a.full = dfixed_const(available_bandwidth);
2173 b.full = dfixed_const(wm->num_heads);
2174 a.full = dfixed_div(a, b);
2176 b.full = dfixed_const(mc_latency + 512);
2177 c.full = dfixed_const(wm->disp_clk);
2178 b.full = dfixed_div(b, c);
2180 c.full = dfixed_const(dmif_size);
2181 b.full = dfixed_div(c, b);
2183 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
2185 b.full = dfixed_const(1000);
2186 c.full = dfixed_const(wm->disp_clk);
2187 b.full = dfixed_div(c, b);
2188 c.full = dfixed_const(wm->bytes_per_pixel);
2189 b.full = dfixed_mul(b, c);
2191 lb_fill_bw = min(tmp, dfixed_trunc(b));
2193 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
2194 b.full = dfixed_const(1000);
2195 c.full = dfixed_const(lb_fill_bw);
2196 b.full = dfixed_div(c, b);
2197 a.full = dfixed_div(a, b);
2198 line_fill_time = dfixed_trunc(a);
2200 if (line_fill_time < wm->active_time)
2203 return latency + (line_fill_time - wm->active_time);
2207 static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
2209 if (dce6_average_bandwidth(wm) <=
2210 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
2216 static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
2218 if (dce6_average_bandwidth(wm) <=
2219 (dce6_available_bandwidth(wm) / wm->num_heads))
2225 static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
2227 u32 lb_partitions = wm->lb_size / wm->src_width;
2228 u32 line_time = wm->active_time + wm->blank_time;
2229 u32 latency_tolerant_lines;
2233 a.full = dfixed_const(1);
2234 if (wm->vsc.full > a.full)
2235 latency_tolerant_lines = 1;
2237 if (lb_partitions <= (wm->vtaps + 1))
2238 latency_tolerant_lines = 1;
2240 latency_tolerant_lines = 2;
2243 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
2245 if (dce6_latency_watermark(wm) <= latency_hiding)
2251 static void dce6_program_watermarks(struct radeon_device *rdev,
2252 struct radeon_crtc *radeon_crtc,
2253 u32 lb_size, u32 num_heads)
2255 struct drm_display_mode *mode = &radeon_crtc->base.mode;
2256 struct dce6_wm_params wm_low, wm_high;
2260 u32 latency_watermark_a = 0, latency_watermark_b = 0;
2261 u32 priority_a_mark = 0, priority_b_mark = 0;
2262 u32 priority_a_cnt = PRIORITY_OFF;
2263 u32 priority_b_cnt = PRIORITY_OFF;
2264 u32 tmp, arb_control3;
2267 if (radeon_crtc->base.enabled && num_heads && mode) {
2268 pixel_period = 1000000 / (u32)mode->clock;
2269 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
2273 if (rdev->family == CHIP_ARUBA)
2274 dram_channels = evergreen_get_number_of_dram_channels(rdev);
2276 dram_channels = si_get_number_of_dram_channels(rdev);
2278 /* watermark for high clocks */
2279 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2281 radeon_dpm_get_mclk(rdev, false) * 10;
2283 radeon_dpm_get_sclk(rdev, false) * 10;
2285 wm_high.yclk = rdev->pm.current_mclk * 10;
2286 wm_high.sclk = rdev->pm.current_sclk * 10;
2289 wm_high.disp_clk = mode->clock;
2290 wm_high.src_width = mode->crtc_hdisplay;
2291 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
2292 wm_high.blank_time = line_time - wm_high.active_time;
2293 wm_high.interlaced = false;
2294 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2295 wm_high.interlaced = true;
2296 wm_high.vsc = radeon_crtc->vsc;
2298 if (radeon_crtc->rmx_type != RMX_OFF)
2300 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
2301 wm_high.lb_size = lb_size;
2302 wm_high.dram_channels = dram_channels;
2303 wm_high.num_heads = num_heads;
2305 /* watermark for low clocks */
2306 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2308 radeon_dpm_get_mclk(rdev, true) * 10;
2310 radeon_dpm_get_sclk(rdev, true) * 10;
2312 wm_low.yclk = rdev->pm.current_mclk * 10;
2313 wm_low.sclk = rdev->pm.current_sclk * 10;
2316 wm_low.disp_clk = mode->clock;
2317 wm_low.src_width = mode->crtc_hdisplay;
2318 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
2319 wm_low.blank_time = line_time - wm_low.active_time;
2320 wm_low.interlaced = false;
2321 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2322 wm_low.interlaced = true;
2323 wm_low.vsc = radeon_crtc->vsc;
2325 if (radeon_crtc->rmx_type != RMX_OFF)
2327 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
2328 wm_low.lb_size = lb_size;
2329 wm_low.dram_channels = dram_channels;
2330 wm_low.num_heads = num_heads;
2332 /* set for high clocks */
2333 latency_watermark_a = min(dce6_latency_watermark(&wm_high), (u32)65535);
2334 /* set for low clocks */
2335 latency_watermark_b = min(dce6_latency_watermark(&wm_low), (u32)65535);
2337 /* possibly force display priority to high */
2338 /* should really do this at mode validation time... */
2339 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
2340 !dce6_average_bandwidth_vs_available_bandwidth(&wm_high) ||
2341 !dce6_check_latency_hiding(&wm_high) ||
2342 (rdev->disp_priority == 2)) {
2343 DRM_DEBUG_KMS("force priority to high\n");
2344 priority_a_cnt |= PRIORITY_ALWAYS_ON;
2345 priority_b_cnt |= PRIORITY_ALWAYS_ON;
2347 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
2348 !dce6_average_bandwidth_vs_available_bandwidth(&wm_low) ||
2349 !dce6_check_latency_hiding(&wm_low) ||
2350 (rdev->disp_priority == 2)) {
2351 DRM_DEBUG_KMS("force priority to high\n");
2352 priority_a_cnt |= PRIORITY_ALWAYS_ON;
2353 priority_b_cnt |= PRIORITY_ALWAYS_ON;
2356 a.full = dfixed_const(1000);
2357 b.full = dfixed_const(mode->clock);
2358 b.full = dfixed_div(b, a);
2359 c.full = dfixed_const(latency_watermark_a);
2360 c.full = dfixed_mul(c, b);
2361 c.full = dfixed_mul(c, radeon_crtc->hsc);
2362 c.full = dfixed_div(c, a);
2363 a.full = dfixed_const(16);
2364 c.full = dfixed_div(c, a);
2365 priority_a_mark = dfixed_trunc(c);
2366 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
2368 a.full = dfixed_const(1000);
2369 b.full = dfixed_const(mode->clock);
2370 b.full = dfixed_div(b, a);
2371 c.full = dfixed_const(latency_watermark_b);
2372 c.full = dfixed_mul(c, b);
2373 c.full = dfixed_mul(c, radeon_crtc->hsc);
2374 c.full = dfixed_div(c, a);
2375 a.full = dfixed_const(16);
2376 c.full = dfixed_div(c, a);
2377 priority_b_mark = dfixed_trunc(c);
2378 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
2380 /* Save number of lines the linebuffer leads before the scanout */
2381 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
2385 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
2387 tmp &= ~LATENCY_WATERMARK_MASK(3);
2388 tmp |= LATENCY_WATERMARK_MASK(1);
2389 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
2390 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
2391 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
2392 LATENCY_HIGH_WATERMARK(line_time)));
2394 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
2395 tmp &= ~LATENCY_WATERMARK_MASK(3);
2396 tmp |= LATENCY_WATERMARK_MASK(2);
2397 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
2398 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
2399 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
2400 LATENCY_HIGH_WATERMARK(line_time)));
2401 /* restore original selection */
2402 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
2404 /* write the priority marks */
2405 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
2406 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
2408 /* save values for DPM */
2409 radeon_crtc->line_time = line_time;
2410 radeon_crtc->wm_high = latency_watermark_a;
2411 radeon_crtc->wm_low = latency_watermark_b;
2414 void dce6_bandwidth_update(struct radeon_device *rdev)
2416 struct drm_display_mode *mode0 = NULL;
2417 struct drm_display_mode *mode1 = NULL;
2418 u32 num_heads = 0, lb_size;
2421 if (!rdev->mode_info.mode_config_initialized)
2424 radeon_update_display_priority(rdev);
2426 for (i = 0; i < rdev->num_crtc; i++) {
2427 if (rdev->mode_info.crtcs[i]->base.enabled)
2430 for (i = 0; i < rdev->num_crtc; i += 2) {
2431 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
2432 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
2433 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
2434 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
2435 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
2436 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
2443 static void si_tiling_mode_table_init(struct radeon_device *rdev)
2445 u32 *tile = rdev->config.si.tile_mode_array;
2446 const u32 num_tile_mode_states =
2447 ARRAY_SIZE(rdev->config.si.tile_mode_array);
2448 u32 reg_offset, split_equal_to_row_size;
2450 switch (rdev->config.si.mem_row_size_in_kb) {
2452 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
2456 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
2459 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
2463 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2464 tile[reg_offset] = 0;
2466 switch(rdev->family) {
2469 /* non-AA compressed depth or any compressed stencil */
2470 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2471 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2472 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2473 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2474 NUM_BANKS(ADDR_SURF_16_BANK) |
2475 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2476 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2477 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2478 /* 2xAA/4xAA compressed depth only */
2479 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2480 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2481 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2482 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2483 NUM_BANKS(ADDR_SURF_16_BANK) |
2484 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2485 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2486 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2487 /* 8xAA compressed depth only */
2488 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2489 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2490 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2491 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2492 NUM_BANKS(ADDR_SURF_16_BANK) |
2493 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2495 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2496 /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
2497 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2498 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2499 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2500 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2501 NUM_BANKS(ADDR_SURF_16_BANK) |
2502 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2503 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2504 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2505 /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
2506 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2507 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2508 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2509 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2510 NUM_BANKS(ADDR_SURF_16_BANK) |
2511 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2512 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2513 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2514 /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
2515 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2516 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2517 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2518 TILE_SPLIT(split_equal_to_row_size) |
2519 NUM_BANKS(ADDR_SURF_16_BANK) |
2520 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2521 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2522 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2523 /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
2524 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2525 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2526 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2527 TILE_SPLIT(split_equal_to_row_size) |
2528 NUM_BANKS(ADDR_SURF_16_BANK) |
2529 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2532 /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
2533 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2534 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2535 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2536 TILE_SPLIT(split_equal_to_row_size) |
2537 NUM_BANKS(ADDR_SURF_16_BANK) |
2538 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2539 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2540 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2541 /* 1D and 1D Array Surfaces */
2542 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2543 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2544 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2545 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2546 NUM_BANKS(ADDR_SURF_16_BANK) |
2547 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2548 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2549 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2550 /* Displayable maps. */
2551 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2552 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2553 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2554 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2555 NUM_BANKS(ADDR_SURF_16_BANK) |
2556 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2557 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2558 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2560 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2561 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2562 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2563 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2564 NUM_BANKS(ADDR_SURF_16_BANK) |
2565 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2566 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2567 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2568 /* Display 16bpp. */
2569 tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2570 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2571 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2572 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2573 NUM_BANKS(ADDR_SURF_16_BANK) |
2574 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2575 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2576 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2577 /* Display 32bpp. */
2578 tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2579 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2580 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2581 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2582 NUM_BANKS(ADDR_SURF_16_BANK) |
2583 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2584 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2585 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2587 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2588 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2589 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2590 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2591 NUM_BANKS(ADDR_SURF_16_BANK) |
2592 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2593 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2594 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2596 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2597 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2598 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2599 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2600 NUM_BANKS(ADDR_SURF_16_BANK) |
2601 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2602 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2603 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2605 tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2606 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2607 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2608 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2609 NUM_BANKS(ADDR_SURF_16_BANK) |
2610 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2611 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2612 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2614 tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2615 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2616 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2617 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2618 NUM_BANKS(ADDR_SURF_16_BANK) |
2619 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2620 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2621 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2623 tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2624 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2625 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2626 TILE_SPLIT(split_equal_to_row_size) |
2627 NUM_BANKS(ADDR_SURF_16_BANK) |
2628 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2629 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2630 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2632 tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2633 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2634 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2635 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2636 NUM_BANKS(ADDR_SURF_16_BANK) |
2637 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2638 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2639 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2641 tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2642 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2643 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2644 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2645 NUM_BANKS(ADDR_SURF_16_BANK) |
2646 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2647 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2648 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2650 tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2651 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2652 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2653 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2654 NUM_BANKS(ADDR_SURF_16_BANK) |
2655 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2656 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2657 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2659 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2660 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2661 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2662 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2663 NUM_BANKS(ADDR_SURF_16_BANK) |
2664 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2665 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2666 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2668 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2669 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2670 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2671 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2672 NUM_BANKS(ADDR_SURF_8_BANK) |
2673 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2674 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2675 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2677 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2678 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2684 /* non-AA compressed depth or any compressed stencil */
2685 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2686 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2687 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2688 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2689 NUM_BANKS(ADDR_SURF_16_BANK) |
2690 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2691 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2692 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2693 /* 2xAA/4xAA compressed depth only */
2694 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2695 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2696 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2697 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2698 NUM_BANKS(ADDR_SURF_16_BANK) |
2699 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2700 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2701 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2702 /* 8xAA compressed depth only */
2703 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2704 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2705 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2706 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2707 NUM_BANKS(ADDR_SURF_16_BANK) |
2708 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2709 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2710 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2711 /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
2712 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2713 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2714 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2715 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2716 NUM_BANKS(ADDR_SURF_16_BANK) |
2717 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2718 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2719 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2720 /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
2721 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2722 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2723 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2724 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2725 NUM_BANKS(ADDR_SURF_16_BANK) |
2726 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2727 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2728 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2729 /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
2730 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2731 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2732 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2733 TILE_SPLIT(split_equal_to_row_size) |
2734 NUM_BANKS(ADDR_SURF_16_BANK) |
2735 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2736 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2737 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2738 /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
2739 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2740 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2741 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2742 TILE_SPLIT(split_equal_to_row_size) |
2743 NUM_BANKS(ADDR_SURF_16_BANK) |
2744 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2745 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2746 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2747 /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
2748 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2749 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2750 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2751 TILE_SPLIT(split_equal_to_row_size) |
2752 NUM_BANKS(ADDR_SURF_16_BANK) |
2753 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2754 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2755 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2756 /* 1D and 1D Array Surfaces */
2757 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2758 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2759 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2760 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2761 NUM_BANKS(ADDR_SURF_16_BANK) |
2762 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2763 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2764 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2765 /* Displayable maps. */
2766 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2767 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2768 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2769 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2770 NUM_BANKS(ADDR_SURF_16_BANK) |
2771 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2772 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2773 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2775 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2776 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2777 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2778 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2779 NUM_BANKS(ADDR_SURF_16_BANK) |
2780 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2781 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2782 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2783 /* Display 16bpp. */
2784 tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2785 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2786 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2787 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2788 NUM_BANKS(ADDR_SURF_16_BANK) |
2789 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2790 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2791 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2792 /* Display 32bpp. */
2793 tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2794 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2795 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2796 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2797 NUM_BANKS(ADDR_SURF_16_BANK) |
2798 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2799 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2800 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2802 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2803 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2804 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2805 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2806 NUM_BANKS(ADDR_SURF_16_BANK) |
2807 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2808 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2809 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2811 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2812 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2813 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2814 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2815 NUM_BANKS(ADDR_SURF_16_BANK) |
2816 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2817 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2818 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2820 tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2821 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2822 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2823 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2824 NUM_BANKS(ADDR_SURF_16_BANK) |
2825 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2826 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2827 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2829 tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2830 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2831 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2832 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2833 NUM_BANKS(ADDR_SURF_16_BANK) |
2834 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2835 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2836 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2838 tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2839 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2840 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2841 TILE_SPLIT(split_equal_to_row_size) |
2842 NUM_BANKS(ADDR_SURF_16_BANK) |
2843 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2844 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2845 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2847 tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2848 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2849 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2850 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2851 NUM_BANKS(ADDR_SURF_16_BANK) |
2852 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2853 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2854 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2856 tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2857 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2858 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2859 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2860 NUM_BANKS(ADDR_SURF_16_BANK) |
2861 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2862 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2863 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2865 tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2866 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2867 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2868 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2869 NUM_BANKS(ADDR_SURF_16_BANK) |
2870 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2871 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2872 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2874 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2875 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2876 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2877 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2878 NUM_BANKS(ADDR_SURF_16_BANK) |
2879 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2880 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2881 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2883 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2884 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2885 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2886 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2887 NUM_BANKS(ADDR_SURF_8_BANK) |
2888 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2889 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2890 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2892 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2893 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2897 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
2901 static void si_select_se_sh(struct radeon_device *rdev,
2902 u32 se_num, u32 sh_num)
2904 u32 data = INSTANCE_BROADCAST_WRITES;
2906 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
2907 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
2908 else if (se_num == 0xffffffff)
2909 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
2910 else if (sh_num == 0xffffffff)
2911 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
2913 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
2914 WREG32(GRBM_GFX_INDEX, data);
2917 static u32 si_create_bitmask(u32 bit_width)
2921 for (i = 0; i < bit_width; i++) {
2928 static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
2932 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
2934 data &= INACTIVE_CUS_MASK;
2937 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
2939 data >>= INACTIVE_CUS_SHIFT;
2941 mask = si_create_bitmask(cu_per_sh);
2943 return ~data & mask;
2946 static void si_setup_spi(struct radeon_device *rdev,
2947 u32 se_num, u32 sh_per_se,
2951 u32 data, mask, active_cu;
2953 for (i = 0; i < se_num; i++) {
2954 for (j = 0; j < sh_per_se; j++) {
2955 si_select_se_sh(rdev, i, j);
2956 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
2957 active_cu = si_get_cu_enabled(rdev, cu_per_sh);
2960 for (k = 0; k < 16; k++) {
2962 if (active_cu & mask) {
2964 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
2970 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
2973 static u32 si_get_rb_disabled(struct radeon_device *rdev,
2974 u32 max_rb_num_per_se,
2979 data = RREG32(CC_RB_BACKEND_DISABLE);
2981 data &= BACKEND_DISABLE_MASK;
2984 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
2986 data >>= BACKEND_DISABLE_SHIFT;
2988 mask = si_create_bitmask(max_rb_num_per_se / sh_per_se);
2993 static void si_setup_rb(struct radeon_device *rdev,
2994 u32 se_num, u32 sh_per_se,
2995 u32 max_rb_num_per_se)
2999 u32 disabled_rbs = 0;
3000 u32 enabled_rbs = 0;
3002 for (i = 0; i < se_num; i++) {
3003 for (j = 0; j < sh_per_se; j++) {
3004 si_select_se_sh(rdev, i, j);
3005 data = si_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
3006 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
3009 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3012 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
3013 if (!(disabled_rbs & mask))
3014 enabled_rbs |= mask;
3018 rdev->config.si.backend_enable_mask = enabled_rbs;
3020 for (i = 0; i < se_num; i++) {
3021 si_select_se_sh(rdev, i, 0xffffffff);
3023 for (j = 0; j < sh_per_se; j++) {
3024 switch (enabled_rbs & 3) {
3026 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
3029 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
3033 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
3038 WREG32(PA_SC_RASTER_CONFIG, data);
3040 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3043 static void si_gpu_init(struct radeon_device *rdev)
3045 u32 gb_addr_config = 0;
3046 u32 mc_shared_chmap, mc_arb_ramcfg;
3048 u32 hdp_host_path_cntl;
3052 switch (rdev->family) {
3054 rdev->config.si.max_shader_engines = 2;
3055 rdev->config.si.max_tile_pipes = 12;
3056 rdev->config.si.max_cu_per_sh = 8;
3057 rdev->config.si.max_sh_per_se = 2;
3058 rdev->config.si.max_backends_per_se = 4;
3059 rdev->config.si.max_texture_channel_caches = 12;
3060 rdev->config.si.max_gprs = 256;
3061 rdev->config.si.max_gs_threads = 32;
3062 rdev->config.si.max_hw_contexts = 8;
3064 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3065 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
3066 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3067 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3068 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
3071 rdev->config.si.max_shader_engines = 2;
3072 rdev->config.si.max_tile_pipes = 8;
3073 rdev->config.si.max_cu_per_sh = 5;
3074 rdev->config.si.max_sh_per_se = 2;
3075 rdev->config.si.max_backends_per_se = 4;
3076 rdev->config.si.max_texture_channel_caches = 8;
3077 rdev->config.si.max_gprs = 256;
3078 rdev->config.si.max_gs_threads = 32;
3079 rdev->config.si.max_hw_contexts = 8;
3081 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3082 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
3083 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3084 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3085 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
3089 rdev->config.si.max_shader_engines = 1;
3090 rdev->config.si.max_tile_pipes = 4;
3091 rdev->config.si.max_cu_per_sh = 5;
3092 rdev->config.si.max_sh_per_se = 2;
3093 rdev->config.si.max_backends_per_se = 4;
3094 rdev->config.si.max_texture_channel_caches = 4;
3095 rdev->config.si.max_gprs = 256;
3096 rdev->config.si.max_gs_threads = 32;
3097 rdev->config.si.max_hw_contexts = 8;
3099 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3100 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
3101 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3102 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3103 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
3106 rdev->config.si.max_shader_engines = 1;
3107 rdev->config.si.max_tile_pipes = 4;
3108 rdev->config.si.max_cu_per_sh = 6;
3109 rdev->config.si.max_sh_per_se = 1;
3110 rdev->config.si.max_backends_per_se = 2;
3111 rdev->config.si.max_texture_channel_caches = 4;
3112 rdev->config.si.max_gprs = 256;
3113 rdev->config.si.max_gs_threads = 16;
3114 rdev->config.si.max_hw_contexts = 8;
3116 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3117 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
3118 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3119 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3120 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
3123 rdev->config.si.max_shader_engines = 1;
3124 rdev->config.si.max_tile_pipes = 4;
3125 rdev->config.si.max_cu_per_sh = 5;
3126 rdev->config.si.max_sh_per_se = 1;
3127 rdev->config.si.max_backends_per_se = 1;
3128 rdev->config.si.max_texture_channel_caches = 2;
3129 rdev->config.si.max_gprs = 256;
3130 rdev->config.si.max_gs_threads = 16;
3131 rdev->config.si.max_hw_contexts = 8;
3133 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3134 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
3135 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3136 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3137 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
3141 /* Initialize HDP */
3142 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
3143 WREG32((0x2c14 + j), 0x00000000);
3144 WREG32((0x2c18 + j), 0x00000000);
3145 WREG32((0x2c1c + j), 0x00000000);
3146 WREG32((0x2c20 + j), 0x00000000);
3147 WREG32((0x2c24 + j), 0x00000000);
3150 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
3151 WREG32(SRBM_INT_CNTL, 1);
3152 WREG32(SRBM_INT_ACK, 1);
3154 evergreen_fix_pci_max_read_req_size(rdev);
3156 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
3158 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
3159 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
3161 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
3162 rdev->config.si.mem_max_burst_length_bytes = 256;
3163 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
3164 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
3165 if (rdev->config.si.mem_row_size_in_kb > 4)
3166 rdev->config.si.mem_row_size_in_kb = 4;
3167 /* XXX use MC settings? */
3168 rdev->config.si.shader_engine_tile_size = 32;
3169 rdev->config.si.num_gpus = 1;
3170 rdev->config.si.multi_gpu_tile_size = 64;
3172 /* fix up row size */
3173 gb_addr_config &= ~ROW_SIZE_MASK;
3174 switch (rdev->config.si.mem_row_size_in_kb) {
3177 gb_addr_config |= ROW_SIZE(0);
3180 gb_addr_config |= ROW_SIZE(1);
3183 gb_addr_config |= ROW_SIZE(2);
3187 /* setup tiling info dword. gb_addr_config is not adequate since it does
3188 * not have bank info, so create a custom tiling dword.
3189 * bits 3:0 num_pipes
3190 * bits 7:4 num_banks
3191 * bits 11:8 group_size
3192 * bits 15:12 row_size
3194 rdev->config.si.tile_config = 0;
3195 switch (rdev->config.si.num_tile_pipes) {
3197 rdev->config.si.tile_config |= (0 << 0);
3200 rdev->config.si.tile_config |= (1 << 0);
3203 rdev->config.si.tile_config |= (2 << 0);
3207 /* XXX what about 12? */
3208 rdev->config.si.tile_config |= (3 << 0);
3211 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
3212 case 0: /* four banks */
3213 rdev->config.si.tile_config |= 0 << 4;
3215 case 1: /* eight banks */
3216 rdev->config.si.tile_config |= 1 << 4;
3218 case 2: /* sixteen banks */
3220 rdev->config.si.tile_config |= 2 << 4;
3223 rdev->config.si.tile_config |=
3224 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
3225 rdev->config.si.tile_config |=
3226 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
3228 WREG32(GB_ADDR_CONFIG, gb_addr_config);
3229 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
3230 WREG32(DMIF_ADDR_CALC, gb_addr_config);
3231 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
3232 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
3233 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
3234 if (rdev->has_uvd) {
3235 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
3236 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
3237 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
3240 si_tiling_mode_table_init(rdev);
3242 si_setup_rb(rdev, rdev->config.si.max_shader_engines,
3243 rdev->config.si.max_sh_per_se,
3244 rdev->config.si.max_backends_per_se);
3246 si_setup_spi(rdev, rdev->config.si.max_shader_engines,
3247 rdev->config.si.max_sh_per_se,
3248 rdev->config.si.max_cu_per_sh);
3250 rdev->config.si.active_cus = 0;
3251 for (i = 0; i < rdev->config.si.max_shader_engines; i++) {
3252 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) {
3253 rdev->config.si.active_cus +=
3254 hweight32(si_get_cu_active_bitmap(rdev, i, j));
3258 /* set HW defaults for 3D engine */
3259 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
3260 ROQ_IB2_START(0x2b)));
3261 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
3263 sx_debug_1 = RREG32(SX_DEBUG_1);
3264 WREG32(SX_DEBUG_1, sx_debug_1);
3266 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
3268 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
3269 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
3270 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
3271 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
3273 WREG32(VGT_NUM_INSTANCES, 1);
3275 WREG32(CP_PERFMON_CNTL, 0);
3277 WREG32(SQ_CONFIG, 0);
3279 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
3280 FORCE_EOV_MAX_REZ_CNT(255)));
3282 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
3283 AUTO_INVLD_EN(ES_AND_GS_AUTO));
3285 WREG32(VGT_GS_VERTEX_REUSE, 16);
3286 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
3288 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
3289 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
3290 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
3291 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
3292 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
3293 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
3294 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
3295 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
3297 tmp = RREG32(HDP_MISC_CNTL);
3298 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
3299 WREG32(HDP_MISC_CNTL, tmp);
3301 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
3302 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
3304 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
3310 * GPU scratch registers helpers function.
3312 static void si_scratch_init(struct radeon_device *rdev)
3316 rdev->scratch.num_reg = 7;
3317 rdev->scratch.reg_base = SCRATCH_REG0;
3318 for (i = 0; i < rdev->scratch.num_reg; i++) {
3319 rdev->scratch.free[i] = true;
3320 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3324 void si_fence_ring_emit(struct radeon_device *rdev,
3325 struct radeon_fence *fence)
3327 struct radeon_ring *ring = &rdev->ring[fence->ring];
3328 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3330 /* flush read cache over gart */
3331 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3332 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3333 radeon_ring_write(ring, 0);
3334 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3335 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3336 PACKET3_TC_ACTION_ENA |
3337 PACKET3_SH_KCACHE_ACTION_ENA |
3338 PACKET3_SH_ICACHE_ACTION_ENA);
3339 radeon_ring_write(ring, 0xFFFFFFFF);
3340 radeon_ring_write(ring, 0);
3341 radeon_ring_write(ring, 10); /* poll interval */
3342 /* EVENT_WRITE_EOP - flush caches, send int */
3343 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3344 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
3345 radeon_ring_write(ring, lower_32_bits(addr));
3346 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
3347 radeon_ring_write(ring, fence->seq);
3348 radeon_ring_write(ring, 0);
3354 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3356 struct radeon_ring *ring = &rdev->ring[ib->ring];
3357 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
3360 if (ib->is_const_ib) {
3361 /* set switch buffer packet before const IB */
3362 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3363 radeon_ring_write(ring, 0);
3365 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3368 if (ring->rptr_save_reg) {
3369 next_rptr = ring->wptr + 3 + 4 + 8;
3370 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3371 radeon_ring_write(ring, ((ring->rptr_save_reg -
3372 PACKET3_SET_CONFIG_REG_START) >> 2));
3373 radeon_ring_write(ring, next_rptr);
3374 } else if (rdev->wb.enabled) {
3375 next_rptr = ring->wptr + 5 + 4 + 8;
3376 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3377 radeon_ring_write(ring, (1 << 8));
3378 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3379 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
3380 radeon_ring_write(ring, next_rptr);
3383 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3386 radeon_ring_write(ring, header);
3387 radeon_ring_write(ring,
3391 (ib->gpu_addr & 0xFFFFFFFC));
3392 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3393 radeon_ring_write(ring, ib->length_dw | (vm_id << 24));
3395 if (!ib->is_const_ib) {
3396 /* flush read cache over gart for this vmid */
3397 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3398 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3399 radeon_ring_write(ring, vm_id);
3400 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3401 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3402 PACKET3_TC_ACTION_ENA |
3403 PACKET3_SH_KCACHE_ACTION_ENA |
3404 PACKET3_SH_ICACHE_ACTION_ENA);
3405 radeon_ring_write(ring, 0xFFFFFFFF);
3406 radeon_ring_write(ring, 0);
3407 radeon_ring_write(ring, 10); /* poll interval */
3414 static void si_cp_enable(struct radeon_device *rdev, bool enable)
3417 WREG32(CP_ME_CNTL, 0);
3419 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
3420 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3421 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
3422 WREG32(SCRATCH_UMSK, 0);
3423 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3424 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3425 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3430 static int si_cp_load_microcode(struct radeon_device *rdev)
3434 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw)
3437 si_cp_enable(rdev, false);
3440 const struct gfx_firmware_header_v1_0 *pfp_hdr =
3441 (const struct gfx_firmware_header_v1_0 *)rdev->pfp_fw->data;
3442 const struct gfx_firmware_header_v1_0 *ce_hdr =
3443 (const struct gfx_firmware_header_v1_0 *)rdev->ce_fw->data;
3444 const struct gfx_firmware_header_v1_0 *me_hdr =
3445 (const struct gfx_firmware_header_v1_0 *)rdev->me_fw->data;
3446 const __le32 *fw_data;
3449 radeon_ucode_print_gfx_hdr(&pfp_hdr->header);
3450 radeon_ucode_print_gfx_hdr(&ce_hdr->header);
3451 radeon_ucode_print_gfx_hdr(&me_hdr->header);
3454 fw_data = (const __le32 *)
3455 (rdev->pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
3456 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
3457 WREG32(CP_PFP_UCODE_ADDR, 0);
3458 for (i = 0; i < fw_size; i++)
3459 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
3460 WREG32(CP_PFP_UCODE_ADDR, 0);
3463 fw_data = (const __le32 *)
3464 (rdev->ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
3465 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
3466 WREG32(CP_CE_UCODE_ADDR, 0);
3467 for (i = 0; i < fw_size; i++)
3468 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
3469 WREG32(CP_CE_UCODE_ADDR, 0);
3472 fw_data = (const __be32 *)
3473 (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
3474 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
3475 WREG32(CP_ME_RAM_WADDR, 0);
3476 for (i = 0; i < fw_size; i++)
3477 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
3478 WREG32(CP_ME_RAM_WADDR, 0);
3480 const __be32 *fw_data;
3483 fw_data = (const __be32 *)rdev->pfp_fw->data;
3484 WREG32(CP_PFP_UCODE_ADDR, 0);
3485 for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
3486 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
3487 WREG32(CP_PFP_UCODE_ADDR, 0);
3490 fw_data = (const __be32 *)rdev->ce_fw->data;
3491 WREG32(CP_CE_UCODE_ADDR, 0);
3492 for (i = 0; i < SI_CE_UCODE_SIZE; i++)
3493 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
3494 WREG32(CP_CE_UCODE_ADDR, 0);
3497 fw_data = (const __be32 *)rdev->me_fw->data;
3498 WREG32(CP_ME_RAM_WADDR, 0);
3499 for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
3500 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
3501 WREG32(CP_ME_RAM_WADDR, 0);
3504 WREG32(CP_PFP_UCODE_ADDR, 0);
3505 WREG32(CP_CE_UCODE_ADDR, 0);
3506 WREG32(CP_ME_RAM_WADDR, 0);
3507 WREG32(CP_ME_RAM_RADDR, 0);
3511 static int si_cp_start(struct radeon_device *rdev)
3513 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3516 r = radeon_ring_lock(rdev, ring, 7 + 4);
3518 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3522 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
3523 radeon_ring_write(ring, 0x1);
3524 radeon_ring_write(ring, 0x0);
3525 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
3526 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
3527 radeon_ring_write(ring, 0);
3528 radeon_ring_write(ring, 0);
3530 /* init the CE partitions */
3531 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
3532 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3533 radeon_ring_write(ring, 0xc000);
3534 radeon_ring_write(ring, 0xe000);
3535 radeon_ring_unlock_commit(rdev, ring, false);
3537 si_cp_enable(rdev, true);
3539 r = radeon_ring_lock(rdev, ring, si_default_size + 10);
3541 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3545 /* setup clear context state */
3546 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3547 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3549 for (i = 0; i < si_default_size; i++)
3550 radeon_ring_write(ring, si_default_state[i]);
3552 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3553 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3555 /* set clear context state */
3556 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3557 radeon_ring_write(ring, 0);
3559 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
3560 radeon_ring_write(ring, 0x00000316);
3561 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
3562 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
3564 radeon_ring_unlock_commit(rdev, ring, false);
3566 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
3567 ring = &rdev->ring[i];
3568 r = radeon_ring_lock(rdev, ring, 2);
3570 /* clear the compute context state */
3571 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
3572 radeon_ring_write(ring, 0);
3574 radeon_ring_unlock_commit(rdev, ring, false);
3580 static void si_cp_fini(struct radeon_device *rdev)
3582 struct radeon_ring *ring;
3583 si_cp_enable(rdev, false);
3585 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3586 radeon_ring_fini(rdev, ring);
3587 radeon_scratch_free(rdev, ring->rptr_save_reg);
3589 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3590 radeon_ring_fini(rdev, ring);
3591 radeon_scratch_free(rdev, ring->rptr_save_reg);
3593 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3594 radeon_ring_fini(rdev, ring);
3595 radeon_scratch_free(rdev, ring->rptr_save_reg);
3598 static int si_cp_resume(struct radeon_device *rdev)
3600 struct radeon_ring *ring;
3605 si_enable_gui_idle_interrupt(rdev, false);
3607 WREG32(CP_SEM_WAIT_TIMER, 0x0);
3608 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
3610 /* Set the write pointer delay */
3611 WREG32(CP_RB_WPTR_DELAY, 0);
3613 WREG32(CP_DEBUG, 0);
3614 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
3616 /* ring 0 - compute and gfx */
3617 /* Set ring buffer size */
3618 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3619 rb_bufsz = order_base_2(ring->ring_size / 8);
3620 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3622 tmp |= BUF_SWAP_32BIT;
3624 WREG32(CP_RB0_CNTL, tmp);
3626 /* Initialize the ring buffer's read and write pointers */
3627 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
3629 WREG32(CP_RB0_WPTR, ring->wptr);
3631 /* set the wb address whether it's enabled or not */
3632 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
3633 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
3635 if (rdev->wb.enabled)
3636 WREG32(SCRATCH_UMSK, 0xff);
3638 tmp |= RB_NO_UPDATE;
3639 WREG32(SCRATCH_UMSK, 0);
3643 WREG32(CP_RB0_CNTL, tmp);
3645 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
3647 /* ring1 - compute only */
3648 /* Set ring buffer size */
3649 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3650 rb_bufsz = order_base_2(ring->ring_size / 8);
3651 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3653 tmp |= BUF_SWAP_32BIT;
3655 WREG32(CP_RB1_CNTL, tmp);
3657 /* Initialize the ring buffer's read and write pointers */
3658 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
3660 WREG32(CP_RB1_WPTR, ring->wptr);
3662 /* set the wb address whether it's enabled or not */
3663 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
3664 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
3667 WREG32(CP_RB1_CNTL, tmp);
3669 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
3671 /* ring2 - compute only */
3672 /* Set ring buffer size */
3673 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3674 rb_bufsz = order_base_2(ring->ring_size / 8);
3675 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3677 tmp |= BUF_SWAP_32BIT;
3679 WREG32(CP_RB2_CNTL, tmp);
3681 /* Initialize the ring buffer's read and write pointers */
3682 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
3684 WREG32(CP_RB2_WPTR, ring->wptr);
3686 /* set the wb address whether it's enabled or not */
3687 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
3688 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
3691 WREG32(CP_RB2_CNTL, tmp);
3693 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
3695 /* start the rings */
3697 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
3698 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
3699 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
3700 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
3702 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3703 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3704 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3707 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
3709 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3711 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
3713 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3716 si_enable_gui_idle_interrupt(rdev, true);
3718 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
3719 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
3724 u32 si_gpu_check_soft_reset(struct radeon_device *rdev)
3730 tmp = RREG32(GRBM_STATUS);
3731 if (tmp & (PA_BUSY | SC_BUSY |
3732 BCI_BUSY | SX_BUSY |
3733 TA_BUSY | VGT_BUSY |
3735 GDS_BUSY | SPI_BUSY |
3736 IA_BUSY | IA_BUSY_NO_DMA))
3737 reset_mask |= RADEON_RESET_GFX;
3739 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
3740 CP_BUSY | CP_COHERENCY_BUSY))
3741 reset_mask |= RADEON_RESET_CP;
3743 if (tmp & GRBM_EE_BUSY)
3744 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
3747 tmp = RREG32(GRBM_STATUS2);
3748 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
3749 reset_mask |= RADEON_RESET_RLC;
3751 /* DMA_STATUS_REG 0 */
3752 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
3753 if (!(tmp & DMA_IDLE))
3754 reset_mask |= RADEON_RESET_DMA;
3756 /* DMA_STATUS_REG 1 */
3757 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
3758 if (!(tmp & DMA_IDLE))
3759 reset_mask |= RADEON_RESET_DMA1;
3762 tmp = RREG32(SRBM_STATUS2);
3764 reset_mask |= RADEON_RESET_DMA;
3766 if (tmp & DMA1_BUSY)
3767 reset_mask |= RADEON_RESET_DMA1;
3770 tmp = RREG32(SRBM_STATUS);
3773 reset_mask |= RADEON_RESET_IH;
3776 reset_mask |= RADEON_RESET_SEM;
3778 if (tmp & GRBM_RQ_PENDING)
3779 reset_mask |= RADEON_RESET_GRBM;
3782 reset_mask |= RADEON_RESET_VMC;
3784 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
3785 MCC_BUSY | MCD_BUSY))
3786 reset_mask |= RADEON_RESET_MC;
3788 if (evergreen_is_display_hung(rdev))
3789 reset_mask |= RADEON_RESET_DISPLAY;
3792 tmp = RREG32(VM_L2_STATUS);
3794 reset_mask |= RADEON_RESET_VMC;
3796 /* Skip MC reset as it's mostly likely not hung, just busy */
3797 if (reset_mask & RADEON_RESET_MC) {
3798 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
3799 reset_mask &= ~RADEON_RESET_MC;
3805 static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
3807 struct evergreen_mc_save save;
3808 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
3811 if (reset_mask == 0)
3814 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
3816 evergreen_print_gpu_status_regs(rdev);
3817 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
3818 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
3819 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3820 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
3829 /* Disable CP parsing/prefetching */
3830 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
3832 if (reset_mask & RADEON_RESET_DMA) {
3834 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
3835 tmp &= ~DMA_RB_ENABLE;
3836 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
3838 if (reset_mask & RADEON_RESET_DMA1) {
3840 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
3841 tmp &= ~DMA_RB_ENABLE;
3842 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
3847 evergreen_mc_stop(rdev, &save);
3848 if (evergreen_mc_wait_for_idle(rdev)) {
3849 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3852 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {
3853 grbm_soft_reset = SOFT_RESET_CB |
3867 if (reset_mask & RADEON_RESET_CP) {
3868 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
3870 srbm_soft_reset |= SOFT_RESET_GRBM;
3873 if (reset_mask & RADEON_RESET_DMA)
3874 srbm_soft_reset |= SOFT_RESET_DMA;
3876 if (reset_mask & RADEON_RESET_DMA1)
3877 srbm_soft_reset |= SOFT_RESET_DMA1;
3879 if (reset_mask & RADEON_RESET_DISPLAY)
3880 srbm_soft_reset |= SOFT_RESET_DC;
3882 if (reset_mask & RADEON_RESET_RLC)
3883 grbm_soft_reset |= SOFT_RESET_RLC;
3885 if (reset_mask & RADEON_RESET_SEM)
3886 srbm_soft_reset |= SOFT_RESET_SEM;
3888 if (reset_mask & RADEON_RESET_IH)
3889 srbm_soft_reset |= SOFT_RESET_IH;
3891 if (reset_mask & RADEON_RESET_GRBM)
3892 srbm_soft_reset |= SOFT_RESET_GRBM;
3894 if (reset_mask & RADEON_RESET_VMC)
3895 srbm_soft_reset |= SOFT_RESET_VMC;
3897 if (reset_mask & RADEON_RESET_MC)
3898 srbm_soft_reset |= SOFT_RESET_MC;
3900 if (grbm_soft_reset) {
3901 tmp = RREG32(GRBM_SOFT_RESET);
3902 tmp |= grbm_soft_reset;
3903 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3904 WREG32(GRBM_SOFT_RESET, tmp);
3905 tmp = RREG32(GRBM_SOFT_RESET);
3909 tmp &= ~grbm_soft_reset;
3910 WREG32(GRBM_SOFT_RESET, tmp);
3911 tmp = RREG32(GRBM_SOFT_RESET);
3914 if (srbm_soft_reset) {
3915 tmp = RREG32(SRBM_SOFT_RESET);
3916 tmp |= srbm_soft_reset;
3917 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3918 WREG32(SRBM_SOFT_RESET, tmp);
3919 tmp = RREG32(SRBM_SOFT_RESET);
3923 tmp &= ~srbm_soft_reset;
3924 WREG32(SRBM_SOFT_RESET, tmp);
3925 tmp = RREG32(SRBM_SOFT_RESET);
3928 /* Wait a little for things to settle down */
3931 evergreen_mc_resume(rdev, &save);
3934 evergreen_print_gpu_status_regs(rdev);
3937 static void si_set_clk_bypass_mode(struct radeon_device *rdev)
3941 tmp = RREG32(CG_SPLL_FUNC_CNTL);
3942 tmp |= SPLL_BYPASS_EN;
3943 WREG32(CG_SPLL_FUNC_CNTL, tmp);
3945 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
3946 tmp |= SPLL_CTLREQ_CHG;
3947 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
3949 for (i = 0; i < rdev->usec_timeout; i++) {
3950 if (RREG32(SPLL_STATUS) & SPLL_CHG_STATUS)
3955 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
3956 tmp &= ~(SPLL_CTLREQ_CHG | SCLK_MUX_UPDATE);
3957 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
3959 tmp = RREG32(MPLL_CNTL_MODE);
3960 tmp &= ~MPLL_MCLK_SEL;
3961 WREG32(MPLL_CNTL_MODE, tmp);
3964 static void si_spll_powerdown(struct radeon_device *rdev)
3968 tmp = RREG32(SPLL_CNTL_MODE);
3969 tmp |= SPLL_SW_DIR_CONTROL;
3970 WREG32(SPLL_CNTL_MODE, tmp);
3972 tmp = RREG32(CG_SPLL_FUNC_CNTL);
3974 WREG32(CG_SPLL_FUNC_CNTL, tmp);
3976 tmp = RREG32(CG_SPLL_FUNC_CNTL);
3978 WREG32(CG_SPLL_FUNC_CNTL, tmp);
3980 tmp = RREG32(SPLL_CNTL_MODE);
3981 tmp &= ~SPLL_SW_DIR_CONTROL;
3982 WREG32(SPLL_CNTL_MODE, tmp);
3985 static void si_gpu_pci_config_reset(struct radeon_device *rdev)
3987 struct evergreen_mc_save save;
3990 dev_info(rdev->dev, "GPU pci config reset\n");
3998 /* Disable CP parsing/prefetching */
3999 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
4001 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
4002 tmp &= ~DMA_RB_ENABLE;
4003 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
4005 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
4006 tmp &= ~DMA_RB_ENABLE;
4007 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
4008 /* XXX other engines? */
4010 /* halt the rlc, disable cp internal ints */
4015 /* disable mem access */
4016 evergreen_mc_stop(rdev, &save);
4017 if (evergreen_mc_wait_for_idle(rdev)) {
4018 dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
4021 /* set mclk/sclk to bypass */
4022 si_set_clk_bypass_mode(rdev);
4023 /* powerdown spll */
4024 si_spll_powerdown(rdev);
4026 pci_clear_master(rdev->pdev);
4028 radeon_pci_config_reset(rdev);
4029 /* wait for asic to come out of reset */
4030 for (i = 0; i < rdev->usec_timeout; i++) {
4031 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
4037 int si_asic_reset(struct radeon_device *rdev)
4041 reset_mask = si_gpu_check_soft_reset(rdev);
4044 r600_set_bios_scratch_engine_hung(rdev, true);
4046 /* try soft reset */
4047 si_gpu_soft_reset(rdev, reset_mask);
4049 reset_mask = si_gpu_check_soft_reset(rdev);
4051 /* try pci config reset */
4052 if (reset_mask && radeon_hard_reset)
4053 si_gpu_pci_config_reset(rdev);
4055 reset_mask = si_gpu_check_soft_reset(rdev);
4058 r600_set_bios_scratch_engine_hung(rdev, false);
4064 * si_gfx_is_lockup - Check if the GFX engine is locked up
4066 * @rdev: radeon_device pointer
4067 * @ring: radeon_ring structure holding ring information
4069 * Check if the GFX engine is locked up.
4070 * Returns true if the engine appears to be locked up, false if not.
4072 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
4074 u32 reset_mask = si_gpu_check_soft_reset(rdev);
4076 if (!(reset_mask & (RADEON_RESET_GFX |
4077 RADEON_RESET_COMPUTE |
4078 RADEON_RESET_CP))) {
4079 radeon_ring_lockup_update(rdev, ring);
4082 return radeon_ring_test_lockup(rdev, ring);
4086 static void si_mc_program(struct radeon_device *rdev)
4088 struct evergreen_mc_save save;
4092 /* Initialize HDP */
4093 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
4094 WREG32((0x2c14 + j), 0x00000000);
4095 WREG32((0x2c18 + j), 0x00000000);
4096 WREG32((0x2c1c + j), 0x00000000);
4097 WREG32((0x2c20 + j), 0x00000000);
4098 WREG32((0x2c24 + j), 0x00000000);
4100 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
4102 evergreen_mc_stop(rdev, &save);
4103 if (radeon_mc_wait_for_idle(rdev)) {
4104 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
4106 if (!ASIC_IS_NODCE(rdev))
4107 /* Lockout access through VGA aperture*/
4108 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
4109 /* Update configuration */
4110 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
4111 rdev->mc.vram_start >> 12);
4112 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
4113 rdev->mc.vram_end >> 12);
4114 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
4115 rdev->vram_scratch.gpu_addr >> 12);
4116 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
4117 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
4118 WREG32(MC_VM_FB_LOCATION, tmp);
4119 /* XXX double check these! */
4120 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
4121 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
4122 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
4123 WREG32(MC_VM_AGP_BASE, 0);
4124 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
4125 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
4126 if (radeon_mc_wait_for_idle(rdev)) {
4127 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
4129 evergreen_mc_resume(rdev, &save);
4130 if (!ASIC_IS_NODCE(rdev)) {
4131 /* we need to own VRAM, so turn off the VGA renderer here
4132 * to stop it overwriting our objects */
4133 rv515_vga_render_disable(rdev);
4137 void si_vram_gtt_location(struct radeon_device *rdev,
4138 struct radeon_mc *mc)
4140 if (mc->mc_vram_size > 0xFFC0000000ULL) {
4141 /* leave room for at least 1024M GTT */
4142 dev_warn(rdev->dev, "limiting VRAM\n");
4143 mc->real_vram_size = 0xFFC0000000ULL;
4144 mc->mc_vram_size = 0xFFC0000000ULL;
4146 radeon_vram_location(rdev, &rdev->mc, 0);
4147 rdev->mc.gtt_base_align = 0;
4148 radeon_gtt_location(rdev, mc);
4151 static int si_mc_init(struct radeon_device *rdev)
4154 int chansize, numchan;
4156 /* Get VRAM informations */
4157 rdev->mc.vram_is_ddr = true;
4158 tmp = RREG32(MC_ARB_RAMCFG);
4159 if (tmp & CHANSIZE_OVERRIDE) {
4161 } else if (tmp & CHANSIZE_MASK) {
4166 tmp = RREG32(MC_SHARED_CHMAP);
4167 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
4197 rdev->mc.vram_width = numchan * chansize;
4198 /* Could aper size report 0 ? */
4199 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
4200 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
4201 /* size in MB on si */
4202 tmp = RREG32(CONFIG_MEMSIZE);
4203 /* some boards may have garbage in the upper 16 bits */
4204 if (tmp & 0xffff0000) {
4205 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
4209 rdev->mc.mc_vram_size = tmp * 1024ULL * 1024ULL;
4210 rdev->mc.real_vram_size = rdev->mc.mc_vram_size;
4211 rdev->mc.visible_vram_size = rdev->mc.aper_size;
4212 si_vram_gtt_location(rdev, &rdev->mc);
4213 radeon_update_bandwidth_info(rdev);
4221 void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
4223 /* flush hdp cache */
4224 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4226 /* bits 0-15 are the VM contexts0-15 */
4227 WREG32(VM_INVALIDATE_REQUEST, 1);
4230 static int si_pcie_gart_enable(struct radeon_device *rdev)
4234 if (rdev->gart.robj == NULL) {
4235 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
4238 r = radeon_gart_table_vram_pin(rdev);
4241 /* Setup TLB control */
4242 WREG32(MC_VM_MX_L1_TLB_CNTL,
4245 ENABLE_L1_FRAGMENT_PROCESSING |
4246 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
4247 ENABLE_ADVANCED_DRIVER_MODEL |
4248 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
4249 /* Setup L2 cache */
4250 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
4251 ENABLE_L2_FRAGMENT_PROCESSING |
4252 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
4253 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
4254 EFFECTIVE_L2_QUEUE_SIZE(7) |
4255 CONTEXT1_IDENTITY_ACCESS_MODE(1));
4256 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
4257 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
4259 L2_CACHE_BIGK_FRAGMENT_SIZE(4));
4260 /* setup context0 */
4261 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
4262 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
4263 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
4264 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
4265 (u32)(rdev->dummy_page.addr >> 12));
4266 WREG32(VM_CONTEXT0_CNTL2, 0);
4267 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
4268 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
4274 /* empty context1-15 */
4275 /* set vm size, must be a multiple of 4 */
4276 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
4277 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1);
4278 /* Assign the pt base to something valid for now; the pts used for
4279 * the VMs are determined by the application and setup and assigned
4280 * on the fly in the vm part of radeon_gart.c
4282 for (i = 1; i < 16; i++) {
4284 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
4285 rdev->vm_manager.saved_table_addr[i]);
4287 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
4288 rdev->vm_manager.saved_table_addr[i]);
4291 /* enable context1-15 */
4292 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
4293 (u32)(rdev->dummy_page.addr >> 12));
4294 WREG32(VM_CONTEXT1_CNTL2, 4);
4295 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
4296 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |
4297 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
4298 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
4299 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
4300 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
4301 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
4302 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
4303 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
4304 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
4305 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
4306 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
4307 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
4308 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
4310 si_pcie_gart_tlb_flush(rdev);
4311 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
4312 (unsigned)(rdev->mc.gtt_size >> 20),
4313 (unsigned long long)rdev->gart.table_addr);
4314 rdev->gart.ready = true;
4318 static void si_pcie_gart_disable(struct radeon_device *rdev)
4322 for (i = 1; i < 16; ++i) {
4325 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2);
4327 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2);
4328 rdev->vm_manager.saved_table_addr[i] = RREG32(reg);
4331 /* Disable all tables */
4332 WREG32(VM_CONTEXT0_CNTL, 0);
4333 WREG32(VM_CONTEXT1_CNTL, 0);
4334 /* Setup TLB control */
4335 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
4336 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
4337 /* Setup L2 cache */
4338 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
4339 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
4340 EFFECTIVE_L2_QUEUE_SIZE(7) |
4341 CONTEXT1_IDENTITY_ACCESS_MODE(1));
4342 WREG32(VM_L2_CNTL2, 0);
4343 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
4344 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
4345 radeon_gart_table_vram_unpin(rdev);
4348 static void si_pcie_gart_fini(struct radeon_device *rdev)
4350 si_pcie_gart_disable(rdev);
4351 radeon_gart_table_vram_free(rdev);
4352 radeon_gart_fini(rdev);
4356 static bool si_vm_reg_valid(u32 reg)
4358 /* context regs are fine */
4362 /* check config regs */
4364 case GRBM_GFX_INDEX:
4365 case CP_STRMOUT_CNTL:
4366 case VGT_VTX_VECT_EJECT_REG:
4367 case VGT_CACHE_INVALIDATION:
4368 case VGT_ESGS_RING_SIZE:
4369 case VGT_GSVS_RING_SIZE:
4370 case VGT_GS_VERTEX_REUSE:
4371 case VGT_PRIMITIVE_TYPE:
4372 case VGT_INDEX_TYPE:
4373 case VGT_NUM_INDICES:
4374 case VGT_NUM_INSTANCES:
4375 case VGT_TF_RING_SIZE:
4376 case VGT_HS_OFFCHIP_PARAM:
4377 case VGT_TF_MEMORY_BASE:
4379 case PA_SU_LINE_STIPPLE_VALUE:
4380 case PA_SC_LINE_STIPPLE_STATE:
4383 case SPI_STATIC_THREAD_MGMT_1:
4384 case SPI_STATIC_THREAD_MGMT_2:
4385 case SPI_STATIC_THREAD_MGMT_3:
4386 case SPI_PS_MAX_WAVE_ID:
4387 case SPI_CONFIG_CNTL:
4388 case SPI_CONFIG_CNTL_1:
4392 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
4397 static int si_vm_packet3_ce_check(struct radeon_device *rdev,
4398 u32 *ib, struct radeon_cs_packet *pkt)
4400 switch (pkt->opcode) {
4402 case PACKET3_SET_BASE:
4403 case PACKET3_SET_CE_DE_COUNTERS:
4404 case PACKET3_LOAD_CONST_RAM:
4405 case PACKET3_WRITE_CONST_RAM:
4406 case PACKET3_WRITE_CONST_RAM_OFFSET:
4407 case PACKET3_DUMP_CONST_RAM:
4408 case PACKET3_INCREMENT_CE_COUNTER:
4409 case PACKET3_WAIT_ON_DE_COUNTER:
4410 case PACKET3_CE_WRITE:
4413 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
4419 static int si_vm_packet3_cp_dma_check(u32 *ib, u32 idx)
4421 u32 start_reg, reg, i;
4422 u32 command = ib[idx + 4];
4423 u32 info = ib[idx + 1];
4424 u32 idx_value = ib[idx];
4425 if (command & PACKET3_CP_DMA_CMD_SAS) {
4426 /* src address space is register */
4427 if (((info & 0x60000000) >> 29) == 0) {
4428 start_reg = idx_value << 2;
4429 if (command & PACKET3_CP_DMA_CMD_SAIC) {
4431 if (!si_vm_reg_valid(reg)) {
4432 DRM_ERROR("CP DMA Bad SRC register\n");
4436 for (i = 0; i < (command & 0x1fffff); i++) {
4437 reg = start_reg + (4 * i);
4438 if (!si_vm_reg_valid(reg)) {
4439 DRM_ERROR("CP DMA Bad SRC register\n");
4446 if (command & PACKET3_CP_DMA_CMD_DAS) {
4447 /* dst address space is register */
4448 if (((info & 0x00300000) >> 20) == 0) {
4449 start_reg = ib[idx + 2];
4450 if (command & PACKET3_CP_DMA_CMD_DAIC) {
4452 if (!si_vm_reg_valid(reg)) {
4453 DRM_ERROR("CP DMA Bad DST register\n");
4457 for (i = 0; i < (command & 0x1fffff); i++) {
4458 reg = start_reg + (4 * i);
4459 if (!si_vm_reg_valid(reg)) {
4460 DRM_ERROR("CP DMA Bad DST register\n");
4470 static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
4471 u32 *ib, struct radeon_cs_packet *pkt)
4474 u32 idx = pkt->idx + 1;
4475 u32 idx_value = ib[idx];
4476 u32 start_reg, end_reg, reg, i;
4478 switch (pkt->opcode) {
4480 case PACKET3_SET_BASE:
4481 case PACKET3_CLEAR_STATE:
4482 case PACKET3_INDEX_BUFFER_SIZE:
4483 case PACKET3_DISPATCH_DIRECT:
4484 case PACKET3_DISPATCH_INDIRECT:
4485 case PACKET3_ALLOC_GDS:
4486 case PACKET3_WRITE_GDS_RAM:
4487 case PACKET3_ATOMIC_GDS:
4488 case PACKET3_ATOMIC:
4489 case PACKET3_OCCLUSION_QUERY:
4490 case PACKET3_SET_PREDICATION:
4491 case PACKET3_COND_EXEC:
4492 case PACKET3_PRED_EXEC:
4493 case PACKET3_DRAW_INDIRECT:
4494 case PACKET3_DRAW_INDEX_INDIRECT:
4495 case PACKET3_INDEX_BASE:
4496 case PACKET3_DRAW_INDEX_2:
4497 case PACKET3_CONTEXT_CONTROL:
4498 case PACKET3_INDEX_TYPE:
4499 case PACKET3_DRAW_INDIRECT_MULTI:
4500 case PACKET3_DRAW_INDEX_AUTO:
4501 case PACKET3_DRAW_INDEX_IMMD:
4502 case PACKET3_NUM_INSTANCES:
4503 case PACKET3_DRAW_INDEX_MULTI_AUTO:
4504 case PACKET3_STRMOUT_BUFFER_UPDATE:
4505 case PACKET3_DRAW_INDEX_OFFSET_2:
4506 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
4507 case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
4508 case PACKET3_MPEG_INDEX:
4509 case PACKET3_WAIT_REG_MEM:
4510 case PACKET3_MEM_WRITE:
4511 case PACKET3_PFP_SYNC_ME:
4512 case PACKET3_SURFACE_SYNC:
4513 case PACKET3_EVENT_WRITE:
4514 case PACKET3_EVENT_WRITE_EOP:
4515 case PACKET3_EVENT_WRITE_EOS:
4516 case PACKET3_SET_CONTEXT_REG:
4517 case PACKET3_SET_CONTEXT_REG_INDIRECT:
4518 case PACKET3_SET_SH_REG:
4519 case PACKET3_SET_SH_REG_OFFSET:
4520 case PACKET3_INCREMENT_DE_COUNTER:
4521 case PACKET3_WAIT_ON_CE_COUNTER:
4522 case PACKET3_WAIT_ON_AVAIL_BUFFER:
4523 case PACKET3_ME_WRITE:
4525 case PACKET3_COPY_DATA:
4526 if ((idx_value & 0xf00) == 0) {
4527 reg = ib[idx + 3] * 4;
4528 if (!si_vm_reg_valid(reg))
4532 case PACKET3_WRITE_DATA:
4533 if ((idx_value & 0xf00) == 0) {
4534 start_reg = ib[idx + 1] * 4;
4535 if (idx_value & 0x10000) {
4536 if (!si_vm_reg_valid(start_reg))
4539 for (i = 0; i < (pkt->count - 2); i++) {
4540 reg = start_reg + (4 * i);
4541 if (!si_vm_reg_valid(reg))
4547 case PACKET3_COND_WRITE:
4548 if (idx_value & 0x100) {
4549 reg = ib[idx + 5] * 4;
4550 if (!si_vm_reg_valid(reg))
4554 case PACKET3_COPY_DW:
4555 if (idx_value & 0x2) {
4556 reg = ib[idx + 3] * 4;
4557 if (!si_vm_reg_valid(reg))
4561 case PACKET3_SET_CONFIG_REG:
4562 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
4563 end_reg = 4 * pkt->count + start_reg - 4;
4564 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
4565 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
4566 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
4567 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
4570 for (i = 0; i < pkt->count; i++) {
4571 reg = start_reg + (4 * i);
4572 if (!si_vm_reg_valid(reg))
4576 case PACKET3_CP_DMA:
4577 r = si_vm_packet3_cp_dma_check(ib, idx);
4582 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
4588 static int si_vm_packet3_compute_check(struct radeon_device *rdev,
4589 u32 *ib, struct radeon_cs_packet *pkt)
4592 u32 idx = pkt->idx + 1;
4593 u32 idx_value = ib[idx];
4594 u32 start_reg, reg, i;
4596 switch (pkt->opcode) {
4598 case PACKET3_SET_BASE:
4599 case PACKET3_CLEAR_STATE:
4600 case PACKET3_DISPATCH_DIRECT:
4601 case PACKET3_DISPATCH_INDIRECT:
4602 case PACKET3_ALLOC_GDS:
4603 case PACKET3_WRITE_GDS_RAM:
4604 case PACKET3_ATOMIC_GDS:
4605 case PACKET3_ATOMIC:
4606 case PACKET3_OCCLUSION_QUERY:
4607 case PACKET3_SET_PREDICATION:
4608 case PACKET3_COND_EXEC:
4609 case PACKET3_PRED_EXEC:
4610 case PACKET3_CONTEXT_CONTROL:
4611 case PACKET3_STRMOUT_BUFFER_UPDATE:
4612 case PACKET3_WAIT_REG_MEM:
4613 case PACKET3_MEM_WRITE:
4614 case PACKET3_PFP_SYNC_ME:
4615 case PACKET3_SURFACE_SYNC:
4616 case PACKET3_EVENT_WRITE:
4617 case PACKET3_EVENT_WRITE_EOP:
4618 case PACKET3_EVENT_WRITE_EOS:
4619 case PACKET3_SET_CONTEXT_REG:
4620 case PACKET3_SET_CONTEXT_REG_INDIRECT:
4621 case PACKET3_SET_SH_REG:
4622 case PACKET3_SET_SH_REG_OFFSET:
4623 case PACKET3_INCREMENT_DE_COUNTER:
4624 case PACKET3_WAIT_ON_CE_COUNTER:
4625 case PACKET3_WAIT_ON_AVAIL_BUFFER:
4626 case PACKET3_ME_WRITE:
4628 case PACKET3_COPY_DATA:
4629 if ((idx_value & 0xf00) == 0) {
4630 reg = ib[idx + 3] * 4;
4631 if (!si_vm_reg_valid(reg))
4635 case PACKET3_WRITE_DATA:
4636 if ((idx_value & 0xf00) == 0) {
4637 start_reg = ib[idx + 1] * 4;
4638 if (idx_value & 0x10000) {
4639 if (!si_vm_reg_valid(start_reg))
4642 for (i = 0; i < (pkt->count - 2); i++) {
4643 reg = start_reg + (4 * i);
4644 if (!si_vm_reg_valid(reg))
4650 case PACKET3_COND_WRITE:
4651 if (idx_value & 0x100) {
4652 reg = ib[idx + 5] * 4;
4653 if (!si_vm_reg_valid(reg))
4657 case PACKET3_COPY_DW:
4658 if (idx_value & 0x2) {
4659 reg = ib[idx + 3] * 4;
4660 if (!si_vm_reg_valid(reg))
4664 case PACKET3_CP_DMA:
4665 r = si_vm_packet3_cp_dma_check(ib, idx);
4670 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
4676 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
4680 struct radeon_cs_packet pkt;
4684 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
4685 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
4688 case RADEON_PACKET_TYPE0:
4689 dev_err(rdev->dev, "Packet0 not allowed!\n");
4692 case RADEON_PACKET_TYPE2:
4695 case RADEON_PACKET_TYPE3:
4696 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
4697 if (ib->is_const_ib)
4698 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
4701 case RADEON_RING_TYPE_GFX_INDEX:
4702 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
4704 case CAYMAN_RING_TYPE_CP1_INDEX:
4705 case CAYMAN_RING_TYPE_CP2_INDEX:
4706 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
4709 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring);
4714 idx += pkt.count + 2;
4717 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
4722 for (i = 0; i < ib->length_dw; i++) {
4724 printk("\t0x%08x <---\n", ib->ptr[i]);
4726 printk("\t0x%08x\n", ib->ptr[i]);
4730 } while (idx < ib->length_dw);
4738 int si_vm_init(struct radeon_device *rdev)
4741 rdev->vm_manager.nvm = 16;
4742 /* base offset of vram pages */
4743 rdev->vm_manager.vram_base_offset = 0;
4748 void si_vm_fini(struct radeon_device *rdev)
4753 * si_vm_decode_fault - print human readable fault info
4755 * @rdev: radeon_device pointer
4756 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
4757 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
4759 * Print human readable fault information (SI).
4761 static void si_vm_decode_fault(struct radeon_device *rdev,
4762 u32 status, u32 addr)
4764 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
4765 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
4766 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
4769 if (rdev->family == CHIP_TAHITI) {
5010 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
5011 protections, vmid, addr,
5012 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
5016 void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
5017 unsigned vm_id, uint64_t pd_addr)
5019 /* write new base address */
5020 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5021 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5022 WRITE_DATA_DST_SEL(0)));
5025 radeon_ring_write(ring,
5026 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);
5028 radeon_ring_write(ring,
5029 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);
5031 radeon_ring_write(ring, 0);
5032 radeon_ring_write(ring, pd_addr >> 12);
5034 /* flush hdp cache */
5035 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5036 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5037 WRITE_DATA_DST_SEL(0)));
5038 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
5039 radeon_ring_write(ring, 0);
5040 radeon_ring_write(ring, 0x1);
5042 /* bits 0-15 are the VM contexts0-15 */
5043 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5044 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5045 WRITE_DATA_DST_SEL(0)));
5046 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
5047 radeon_ring_write(ring, 0);
5048 radeon_ring_write(ring, 1 << vm_id);
5050 /* wait for the invalidate to complete */
5051 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
5052 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
5053 WAIT_REG_MEM_ENGINE(0))); /* me */
5054 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
5055 radeon_ring_write(ring, 0);
5056 radeon_ring_write(ring, 0); /* ref */
5057 radeon_ring_write(ring, 0); /* mask */
5058 radeon_ring_write(ring, 0x20); /* poll interval */
5060 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5061 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5062 radeon_ring_write(ring, 0x0);
5066 * Power and clock gating
5068 static void si_wait_for_rlc_serdes(struct radeon_device *rdev)
5072 for (i = 0; i < rdev->usec_timeout; i++) {
5073 if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0)
5078 for (i = 0; i < rdev->usec_timeout; i++) {
5079 if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0)
5085 static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
5088 u32 tmp = RREG32(CP_INT_CNTL_RING0);
5093 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5095 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5096 WREG32(CP_INT_CNTL_RING0, tmp);
5099 /* read a gfx register */
5100 tmp = RREG32(DB_DEPTH_INFO);
5102 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
5103 for (i = 0; i < rdev->usec_timeout; i++) {
5104 if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
5111 static void si_set_uvd_dcm(struct radeon_device *rdev,
5116 tmp = RREG32(UVD_CGC_CTRL);
5117 tmp &= ~(CLK_OD_MASK | CG_DT_MASK);
5118 tmp |= DCM | CG_DT(1) | CLK_OD(4);
5122 tmp2 = DYN_OR_EN | DYN_RR_EN | G_DIV_ID(7);
5128 WREG32(UVD_CGC_CTRL, tmp);
5129 WREG32_UVD_CTX(UVD_CGC_CTRL2, tmp2);
5132 void si_init_uvd_internal_cg(struct radeon_device *rdev)
5134 bool hw_mode = true;
5137 si_set_uvd_dcm(rdev, false);
5139 u32 tmp = RREG32(UVD_CGC_CTRL);
5141 WREG32(UVD_CGC_CTRL, tmp);
5145 static u32 si_halt_rlc(struct radeon_device *rdev)
5149 orig = data = RREG32(RLC_CNTL);
5151 if (data & RLC_ENABLE) {
5152 data &= ~RLC_ENABLE;
5153 WREG32(RLC_CNTL, data);
5155 si_wait_for_rlc_serdes(rdev);
5161 static void si_update_rlc(struct radeon_device *rdev, u32 rlc)
5165 tmp = RREG32(RLC_CNTL);
5167 WREG32(RLC_CNTL, rlc);
5170 static void si_enable_dma_pg(struct radeon_device *rdev, bool enable)
5174 orig = data = RREG32(DMA_PG);
5175 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA))
5176 data |= PG_CNTL_ENABLE;
5178 data &= ~PG_CNTL_ENABLE;
5180 WREG32(DMA_PG, data);
5183 static void si_init_dma_pg(struct radeon_device *rdev)
5187 WREG32(DMA_PGFSM_WRITE, 0x00002000);
5188 WREG32(DMA_PGFSM_CONFIG, 0x100010ff);
5190 for (tmp = 0; tmp < 5; tmp++)
5191 WREG32(DMA_PGFSM_WRITE, 0);
5194 static void si_enable_gfx_cgpg(struct radeon_device *rdev,
5199 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
5200 tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
5201 WREG32(RLC_TTOP_D, tmp);
5203 tmp = RREG32(RLC_PG_CNTL);
5204 tmp |= GFX_PG_ENABLE;
5205 WREG32(RLC_PG_CNTL, tmp);
5207 tmp = RREG32(RLC_AUTO_PG_CTRL);
5209 WREG32(RLC_AUTO_PG_CTRL, tmp);
5211 tmp = RREG32(RLC_AUTO_PG_CTRL);
5213 WREG32(RLC_AUTO_PG_CTRL, tmp);
5215 tmp = RREG32(DB_RENDER_CONTROL);
5219 static void si_init_gfx_cgpg(struct radeon_device *rdev)
5223 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
5225 tmp = RREG32(RLC_PG_CNTL);
5227 WREG32(RLC_PG_CNTL, tmp);
5229 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5231 tmp = RREG32(RLC_AUTO_PG_CTRL);
5233 tmp &= ~GRBM_REG_SGIT_MASK;
5234 tmp |= GRBM_REG_SGIT(0x700);
5235 tmp &= ~PG_AFTER_GRBM_REG_ST_MASK;
5236 WREG32(RLC_AUTO_PG_CTRL, tmp);
5239 static u32 si_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh)
5241 u32 mask = 0, tmp, tmp1;
5244 si_select_se_sh(rdev, se, sh);
5245 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
5246 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
5247 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5254 for (i = 0; i < rdev->config.si.max_cu_per_sh; i ++) {
5259 return (~tmp) & mask;
5262 static void si_init_ao_cu_mask(struct radeon_device *rdev)
5264 u32 i, j, k, active_cu_number = 0;
5265 u32 mask, counter, cu_bitmap;
5268 for (i = 0; i < rdev->config.si.max_shader_engines; i++) {
5269 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) {
5273 for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) {
5274 if (si_get_cu_active_bitmap(rdev, i, j) & mask) {
5282 active_cu_number += counter;
5283 tmp |= (cu_bitmap << (i * 16 + j * 8));
5287 WREG32(RLC_PG_AO_CU_MASK, tmp);
5289 tmp = RREG32(RLC_MAX_PG_CU);
5290 tmp &= ~MAX_PU_CU_MASK;
5291 tmp |= MAX_PU_CU(active_cu_number);
5292 WREG32(RLC_MAX_PG_CU, tmp);
5295 static void si_enable_cgcg(struct radeon_device *rdev,
5298 u32 data, orig, tmp;
5300 orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
5302 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {
5303 si_enable_gui_idle_interrupt(rdev, true);
5305 WREG32(RLC_GCPM_GENERAL_3, 0x00000080);
5307 tmp = si_halt_rlc(rdev);
5309 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
5310 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
5311 WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
5313 si_wait_for_rlc_serdes(rdev);
5315 si_update_rlc(rdev, tmp);
5317 WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
5319 data |= CGCG_EN | CGLS_EN;
5321 si_enable_gui_idle_interrupt(rdev, false);
5323 RREG32(CB_CGTT_SCLK_CTRL);
5324 RREG32(CB_CGTT_SCLK_CTRL);
5325 RREG32(CB_CGTT_SCLK_CTRL);
5326 RREG32(CB_CGTT_SCLK_CTRL);
5328 data &= ~(CGCG_EN | CGLS_EN);
5332 WREG32(RLC_CGCG_CGLS_CTRL, data);
5335 static void si_enable_mgcg(struct radeon_device *rdev,
5338 u32 data, orig, tmp = 0;
5340 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)) {
5341 orig = data = RREG32(CGTS_SM_CTRL_REG);
5344 WREG32(CGTS_SM_CTRL_REG, data);
5346 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CP_LS) {
5347 orig = data = RREG32(CP_MEM_SLP_CNTL);
5348 data |= CP_MEM_LS_EN;
5350 WREG32(CP_MEM_SLP_CNTL, data);
5353 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
5356 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
5358 tmp = si_halt_rlc(rdev);
5360 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
5361 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
5362 WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff);
5364 si_update_rlc(rdev, tmp);
5366 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
5369 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
5371 data = RREG32(CP_MEM_SLP_CNTL);
5372 if (data & CP_MEM_LS_EN) {
5373 data &= ~CP_MEM_LS_EN;
5374 WREG32(CP_MEM_SLP_CNTL, data);
5376 orig = data = RREG32(CGTS_SM_CTRL_REG);
5377 data |= LS_OVERRIDE | OVERRIDE;
5379 WREG32(CGTS_SM_CTRL_REG, data);
5381 tmp = si_halt_rlc(rdev);
5383 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
5384 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
5385 WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff);
5387 si_update_rlc(rdev, tmp);
5391 static void si_enable_uvd_mgcg(struct radeon_device *rdev,
5394 u32 orig, data, tmp;
5396 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)) {
5397 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
5399 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp);
5401 orig = data = RREG32(UVD_CGC_CTRL);
5404 WREG32(UVD_CGC_CTRL, data);
5406 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0);
5407 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0);
5409 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
5411 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp);
5413 orig = data = RREG32(UVD_CGC_CTRL);
5416 WREG32(UVD_CGC_CTRL, data);
5418 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff);
5419 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff);
5423 static const u32 mc_cg_registers[] =
5436 static void si_enable_mc_ls(struct radeon_device *rdev,
5442 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
5443 orig = data = RREG32(mc_cg_registers[i]);
5444 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))
5445 data |= MC_LS_ENABLE;
5447 data &= ~MC_LS_ENABLE;
5449 WREG32(mc_cg_registers[i], data);
5453 static void si_enable_mc_mgcg(struct radeon_device *rdev,
5459 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
5460 orig = data = RREG32(mc_cg_registers[i]);
5461 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_MGCG))
5462 data |= MC_CG_ENABLE;
5464 data &= ~MC_CG_ENABLE;
5466 WREG32(mc_cg_registers[i], data);
5470 static void si_enable_dma_mgcg(struct radeon_device *rdev,
5473 u32 orig, data, offset;
5476 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_MGCG)) {
5477 for (i = 0; i < 2; i++) {
5479 offset = DMA0_REGISTER_OFFSET;
5481 offset = DMA1_REGISTER_OFFSET;
5482 orig = data = RREG32(DMA_POWER_CNTL + offset);
5483 data &= ~MEM_POWER_OVERRIDE;
5485 WREG32(DMA_POWER_CNTL + offset, data);
5486 WREG32(DMA_CLK_CTRL + offset, 0x00000100);
5489 for (i = 0; i < 2; i++) {
5491 offset = DMA0_REGISTER_OFFSET;
5493 offset = DMA1_REGISTER_OFFSET;
5494 orig = data = RREG32(DMA_POWER_CNTL + offset);
5495 data |= MEM_POWER_OVERRIDE;
5497 WREG32(DMA_POWER_CNTL + offset, data);
5499 orig = data = RREG32(DMA_CLK_CTRL + offset);
5502 WREG32(DMA_CLK_CTRL + offset, data);
5507 static void si_enable_bif_mgls(struct radeon_device *rdev,
5512 orig = data = RREG32_PCIE(PCIE_CNTL2);
5514 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_BIF_LS))
5515 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN |
5516 REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN;
5518 data &= ~(SLV_MEM_LS_EN | MST_MEM_LS_EN |
5519 REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN);
5522 WREG32_PCIE(PCIE_CNTL2, data);
5525 static void si_enable_hdp_mgcg(struct radeon_device *rdev,
5530 orig = data = RREG32(HDP_HOST_PATH_CNTL);
5532 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_MGCG))
5533 data &= ~CLOCK_GATING_DIS;
5535 data |= CLOCK_GATING_DIS;
5538 WREG32(HDP_HOST_PATH_CNTL, data);
5541 static void si_enable_hdp_ls(struct radeon_device *rdev,
5546 orig = data = RREG32(HDP_MEM_POWER_LS);
5548 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_LS))
5549 data |= HDP_LS_ENABLE;
5551 data &= ~HDP_LS_ENABLE;
5554 WREG32(HDP_MEM_POWER_LS, data);
5557 static void si_update_cg(struct radeon_device *rdev,
5558 u32 block, bool enable)
5560 if (block & RADEON_CG_BLOCK_GFX) {
5561 si_enable_gui_idle_interrupt(rdev, false);
5562 /* order matters! */
5564 si_enable_mgcg(rdev, true);
5565 si_enable_cgcg(rdev, true);
5567 si_enable_cgcg(rdev, false);
5568 si_enable_mgcg(rdev, false);
5570 si_enable_gui_idle_interrupt(rdev, true);
5573 if (block & RADEON_CG_BLOCK_MC) {
5574 si_enable_mc_mgcg(rdev, enable);
5575 si_enable_mc_ls(rdev, enable);
5578 if (block & RADEON_CG_BLOCK_SDMA) {
5579 si_enable_dma_mgcg(rdev, enable);
5582 if (block & RADEON_CG_BLOCK_BIF) {
5583 si_enable_bif_mgls(rdev, enable);
5586 if (block & RADEON_CG_BLOCK_UVD) {
5587 if (rdev->has_uvd) {
5588 si_enable_uvd_mgcg(rdev, enable);
5592 if (block & RADEON_CG_BLOCK_HDP) {
5593 si_enable_hdp_mgcg(rdev, enable);
5594 si_enable_hdp_ls(rdev, enable);
5598 static void si_init_cg(struct radeon_device *rdev)
5600 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
5601 RADEON_CG_BLOCK_MC |
5602 RADEON_CG_BLOCK_SDMA |
5603 RADEON_CG_BLOCK_BIF |
5604 RADEON_CG_BLOCK_HDP), true);
5605 if (rdev->has_uvd) {
5606 si_update_cg(rdev, RADEON_CG_BLOCK_UVD, true);
5607 si_init_uvd_internal_cg(rdev);
5611 static void si_fini_cg(struct radeon_device *rdev)
5613 if (rdev->has_uvd) {
5614 si_update_cg(rdev, RADEON_CG_BLOCK_UVD, false);
5616 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
5617 RADEON_CG_BLOCK_MC |
5618 RADEON_CG_BLOCK_SDMA |
5619 RADEON_CG_BLOCK_BIF |
5620 RADEON_CG_BLOCK_HDP), false);
5623 u32 si_get_csb_size(struct radeon_device *rdev)
5626 const struct cs_section_def *sect = NULL;
5627 const struct cs_extent_def *ext = NULL;
5629 if (rdev->rlc.cs_data == NULL)
5632 /* begin clear state */
5634 /* context control state */
5637 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
5638 for (ext = sect->section; ext->extent != NULL; ++ext) {
5639 if (sect->id == SECT_CONTEXT)
5640 count += 2 + ext->reg_count;
5645 /* pa_sc_raster_config */
5647 /* end clear state */
5655 void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
5658 const struct cs_section_def *sect = NULL;
5659 const struct cs_extent_def *ext = NULL;
5661 if (rdev->rlc.cs_data == NULL)
5666 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5667 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5669 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5670 buffer[count++] = cpu_to_le32(0x80000000);
5671 buffer[count++] = cpu_to_le32(0x80000000);
5673 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
5674 for (ext = sect->section; ext->extent != NULL; ++ext) {
5675 if (sect->id == SECT_CONTEXT) {
5677 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
5678 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
5679 for (i = 0; i < ext->reg_count; i++)
5680 buffer[count++] = cpu_to_le32(ext->extent[i]);
5687 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5688 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
5689 switch (rdev->family) {
5692 buffer[count++] = cpu_to_le32(0x2a00126a);
5695 buffer[count++] = cpu_to_le32(0x0000124a);
5698 buffer[count++] = cpu_to_le32(0x00000082);
5701 buffer[count++] = cpu_to_le32(0x00000000);
5704 buffer[count++] = cpu_to_le32(0x00000000);
5708 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5709 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
5711 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
5712 buffer[count++] = cpu_to_le32(0);
5715 static void si_init_pg(struct radeon_device *rdev)
5717 if (rdev->pg_flags) {
5718 if (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA) {
5719 si_init_dma_pg(rdev);
5721 si_init_ao_cu_mask(rdev);
5722 if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
5723 si_init_gfx_cgpg(rdev);
5725 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
5726 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5728 si_enable_dma_pg(rdev, true);
5729 si_enable_gfx_cgpg(rdev, true);
5731 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
5732 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5736 static void si_fini_pg(struct radeon_device *rdev)
5738 if (rdev->pg_flags) {
5739 si_enable_dma_pg(rdev, false);
5740 si_enable_gfx_cgpg(rdev, false);
5747 void si_rlc_reset(struct radeon_device *rdev)
5749 u32 tmp = RREG32(GRBM_SOFT_RESET);
5751 tmp |= SOFT_RESET_RLC;
5752 WREG32(GRBM_SOFT_RESET, tmp);
5754 tmp &= ~SOFT_RESET_RLC;
5755 WREG32(GRBM_SOFT_RESET, tmp);
5759 static void si_rlc_stop(struct radeon_device *rdev)
5761 WREG32(RLC_CNTL, 0);
5763 si_enable_gui_idle_interrupt(rdev, false);
5765 si_wait_for_rlc_serdes(rdev);
5768 static void si_rlc_start(struct radeon_device *rdev)
5770 WREG32(RLC_CNTL, RLC_ENABLE);
5772 si_enable_gui_idle_interrupt(rdev, true);
5777 static bool si_lbpw_supported(struct radeon_device *rdev)
5781 /* Enable LBPW only for DDR3 */
5782 tmp = RREG32(MC_SEQ_MISC0);
5783 if ((tmp & 0xF0000000) == 0xB0000000)
5788 static void si_enable_lbpw(struct radeon_device *rdev, bool enable)
5792 tmp = RREG32(RLC_LB_CNTL);
5794 tmp |= LOAD_BALANCE_ENABLE;
5796 tmp &= ~LOAD_BALANCE_ENABLE;
5797 WREG32(RLC_LB_CNTL, tmp);
5800 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5801 WREG32(SPI_LB_CU_MASK, 0x00ff);
5805 static int si_rlc_resume(struct radeon_device *rdev)
5820 WREG32(RLC_RL_BASE, 0);
5821 WREG32(RLC_RL_SIZE, 0);
5822 WREG32(RLC_LB_CNTL, 0);
5823 WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
5824 WREG32(RLC_LB_CNTR_INIT, 0);
5825 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
5827 WREG32(RLC_MC_CNTL, 0);
5828 WREG32(RLC_UCODE_CNTL, 0);
5831 const struct rlc_firmware_header_v1_0 *hdr =
5832 (const struct rlc_firmware_header_v1_0 *)rdev->rlc_fw->data;
5833 u32 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5834 const __le32 *fw_data = (const __le32 *)
5835 (rdev->rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5837 radeon_ucode_print_rlc_hdr(&hdr->header);
5839 for (i = 0; i < fw_size; i++) {
5840 WREG32(RLC_UCODE_ADDR, i);
5841 WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++));
5844 const __be32 *fw_data =
5845 (const __be32 *)rdev->rlc_fw->data;
5846 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
5847 WREG32(RLC_UCODE_ADDR, i);
5848 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
5851 WREG32(RLC_UCODE_ADDR, 0);
5853 si_enable_lbpw(rdev, si_lbpw_supported(rdev));
5860 static void si_enable_interrupts(struct radeon_device *rdev)
5862 u32 ih_cntl = RREG32(IH_CNTL);
5863 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
5865 ih_cntl |= ENABLE_INTR;
5866 ih_rb_cntl |= IH_RB_ENABLE;
5867 WREG32(IH_CNTL, ih_cntl);
5868 WREG32(IH_RB_CNTL, ih_rb_cntl);
5869 rdev->ih.enabled = true;
5872 static void si_disable_interrupts(struct radeon_device *rdev)
5874 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
5875 u32 ih_cntl = RREG32(IH_CNTL);
5877 ih_rb_cntl &= ~IH_RB_ENABLE;
5878 ih_cntl &= ~ENABLE_INTR;
5879 WREG32(IH_RB_CNTL, ih_rb_cntl);
5880 WREG32(IH_CNTL, ih_cntl);
5881 /* set rptr, wptr to 0 */
5882 WREG32(IH_RB_RPTR, 0);
5883 WREG32(IH_RB_WPTR, 0);
5884 rdev->ih.enabled = false;
5888 static void si_disable_interrupt_state(struct radeon_device *rdev)
5892 tmp = RREG32(CP_INT_CNTL_RING0) &
5893 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5894 WREG32(CP_INT_CNTL_RING0, tmp);
5895 WREG32(CP_INT_CNTL_RING1, 0);
5896 WREG32(CP_INT_CNTL_RING2, 0);
5897 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
5898 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
5899 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
5900 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
5901 WREG32(GRBM_INT_CNTL, 0);
5902 WREG32(SRBM_INT_CNTL, 0);
5903 if (rdev->num_crtc >= 2) {
5904 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
5905 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
5907 if (rdev->num_crtc >= 4) {
5908 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
5909 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
5911 if (rdev->num_crtc >= 6) {
5912 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
5913 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
5916 if (rdev->num_crtc >= 2) {
5917 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
5918 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
5920 if (rdev->num_crtc >= 4) {
5921 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
5922 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
5924 if (rdev->num_crtc >= 6) {
5925 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
5926 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
5929 if (!ASIC_IS_NODCE(rdev)) {
5930 WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
5932 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5933 WREG32(DC_HPD1_INT_CONTROL, tmp);
5934 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5935 WREG32(DC_HPD2_INT_CONTROL, tmp);
5936 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5937 WREG32(DC_HPD3_INT_CONTROL, tmp);
5938 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5939 WREG32(DC_HPD4_INT_CONTROL, tmp);
5940 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5941 WREG32(DC_HPD5_INT_CONTROL, tmp);
5942 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5943 WREG32(DC_HPD6_INT_CONTROL, tmp);
5947 static int si_irq_init(struct radeon_device *rdev)
5951 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
5954 ret = r600_ih_ring_alloc(rdev);
5959 si_disable_interrupts(rdev);
5962 ret = si_rlc_resume(rdev);
5964 r600_ih_ring_fini(rdev);
5968 /* setup interrupt control */
5969 /* set dummy read address to ring address */
5970 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
5971 interrupt_cntl = RREG32(INTERRUPT_CNTL);
5972 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
5973 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
5975 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
5976 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
5977 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
5978 WREG32(INTERRUPT_CNTL, interrupt_cntl);
5980 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
5981 rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
5983 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
5984 IH_WPTR_OVERFLOW_CLEAR |
5987 if (rdev->wb.enabled)
5988 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
5990 /* set the writeback address whether it's enabled or not */
5991 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
5992 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
5994 WREG32(IH_RB_CNTL, ih_rb_cntl);
5996 /* set rptr, wptr to 0 */
5997 WREG32(IH_RB_RPTR, 0);
5998 WREG32(IH_RB_WPTR, 0);
6000 /* Default settings for IH_CNTL (disabled at first) */
6001 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
6002 /* RPTR_REARM only works if msi's are enabled */
6003 if (rdev->msi_enabled)
6004 ih_cntl |= RPTR_REARM;
6005 WREG32(IH_CNTL, ih_cntl);
6007 /* force the active interrupt state to all disabled */
6008 si_disable_interrupt_state(rdev);
6010 pci_set_master(rdev->pdev);
6013 si_enable_interrupts(rdev);
6018 int si_irq_set(struct radeon_device *rdev)
6021 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
6022 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
6023 u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0;
6024 u32 grbm_int_cntl = 0;
6025 u32 dma_cntl, dma_cntl1;
6026 u32 thermal_int = 0;
6028 if (!rdev->irq.installed) {
6029 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
6032 /* don't enable anything if the ih is disabled */
6033 if (!rdev->ih.enabled) {
6034 si_disable_interrupts(rdev);
6035 /* force the active interrupt state to all disabled */
6036 si_disable_interrupt_state(rdev);
6040 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
6041 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
6043 if (!ASIC_IS_NODCE(rdev)) {
6044 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6045 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6046 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6047 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6048 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6049 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6052 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
6053 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
6055 thermal_int = RREG32(CG_THERMAL_INT) &
6056 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6058 /* enable CP interrupts on all rings */
6059 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
6060 DRM_DEBUG("si_irq_set: sw int gfx\n");
6061 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
6063 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
6064 DRM_DEBUG("si_irq_set: sw int cp1\n");
6065 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
6067 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
6068 DRM_DEBUG("si_irq_set: sw int cp2\n");
6069 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
6071 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
6072 DRM_DEBUG("si_irq_set: sw int dma\n");
6073 dma_cntl |= TRAP_ENABLE;
6076 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
6077 DRM_DEBUG("si_irq_set: sw int dma1\n");
6078 dma_cntl1 |= TRAP_ENABLE;
6080 if (rdev->irq.crtc_vblank_int[0] ||
6081 atomic_read(&rdev->irq.pflip[0])) {
6082 DRM_DEBUG("si_irq_set: vblank 0\n");
6083 crtc1 |= VBLANK_INT_MASK;
6085 if (rdev->irq.crtc_vblank_int[1] ||
6086 atomic_read(&rdev->irq.pflip[1])) {
6087 DRM_DEBUG("si_irq_set: vblank 1\n");
6088 crtc2 |= VBLANK_INT_MASK;
6090 if (rdev->irq.crtc_vblank_int[2] ||
6091 atomic_read(&rdev->irq.pflip[2])) {
6092 DRM_DEBUG("si_irq_set: vblank 2\n");
6093 crtc3 |= VBLANK_INT_MASK;
6095 if (rdev->irq.crtc_vblank_int[3] ||
6096 atomic_read(&rdev->irq.pflip[3])) {
6097 DRM_DEBUG("si_irq_set: vblank 3\n");
6098 crtc4 |= VBLANK_INT_MASK;
6100 if (rdev->irq.crtc_vblank_int[4] ||
6101 atomic_read(&rdev->irq.pflip[4])) {
6102 DRM_DEBUG("si_irq_set: vblank 4\n");
6103 crtc5 |= VBLANK_INT_MASK;
6105 if (rdev->irq.crtc_vblank_int[5] ||
6106 atomic_read(&rdev->irq.pflip[5])) {
6107 DRM_DEBUG("si_irq_set: vblank 5\n");
6108 crtc6 |= VBLANK_INT_MASK;
6110 if (rdev->irq.hpd[0]) {
6111 DRM_DEBUG("si_irq_set: hpd 1\n");
6112 hpd1 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6114 if (rdev->irq.hpd[1]) {
6115 DRM_DEBUG("si_irq_set: hpd 2\n");
6116 hpd2 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6118 if (rdev->irq.hpd[2]) {
6119 DRM_DEBUG("si_irq_set: hpd 3\n");
6120 hpd3 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6122 if (rdev->irq.hpd[3]) {
6123 DRM_DEBUG("si_irq_set: hpd 4\n");
6124 hpd4 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6126 if (rdev->irq.hpd[4]) {
6127 DRM_DEBUG("si_irq_set: hpd 5\n");
6128 hpd5 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6130 if (rdev->irq.hpd[5]) {
6131 DRM_DEBUG("si_irq_set: hpd 6\n");
6132 hpd6 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6135 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
6136 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
6137 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
6139 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);
6140 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);
6142 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
6144 if (rdev->irq.dpm_thermal) {
6145 DRM_DEBUG("dpm thermal\n");
6146 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6149 if (rdev->num_crtc >= 2) {
6150 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
6151 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
6153 if (rdev->num_crtc >= 4) {
6154 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
6155 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
6157 if (rdev->num_crtc >= 6) {
6158 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
6159 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
6162 if (rdev->num_crtc >= 2) {
6163 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
6164 GRPH_PFLIP_INT_MASK);
6165 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
6166 GRPH_PFLIP_INT_MASK);
6168 if (rdev->num_crtc >= 4) {
6169 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
6170 GRPH_PFLIP_INT_MASK);
6171 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
6172 GRPH_PFLIP_INT_MASK);
6174 if (rdev->num_crtc >= 6) {
6175 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
6176 GRPH_PFLIP_INT_MASK);
6177 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
6178 GRPH_PFLIP_INT_MASK);
6181 if (!ASIC_IS_NODCE(rdev)) {
6182 WREG32(DC_HPD1_INT_CONTROL, hpd1);
6183 WREG32(DC_HPD2_INT_CONTROL, hpd2);
6184 WREG32(DC_HPD3_INT_CONTROL, hpd3);
6185 WREG32(DC_HPD4_INT_CONTROL, hpd4);
6186 WREG32(DC_HPD5_INT_CONTROL, hpd5);
6187 WREG32(DC_HPD6_INT_CONTROL, hpd6);
6190 WREG32(CG_THERMAL_INT, thermal_int);
6193 RREG32(SRBM_STATUS);
6198 static inline void si_irq_ack(struct radeon_device *rdev)
6202 if (ASIC_IS_NODCE(rdev))
6205 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
6206 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
6207 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
6208 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
6209 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
6210 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
6211 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
6212 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
6213 if (rdev->num_crtc >= 4) {
6214 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
6215 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
6217 if (rdev->num_crtc >= 6) {
6218 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
6219 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
6222 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
6223 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6224 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
6225 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6226 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
6227 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
6228 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
6229 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
6230 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
6231 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
6232 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
6233 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
6235 if (rdev->num_crtc >= 4) {
6236 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
6237 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6238 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
6239 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6240 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
6241 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
6242 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
6243 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
6244 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
6245 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
6246 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
6247 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
6250 if (rdev->num_crtc >= 6) {
6251 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
6252 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6253 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
6254 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6255 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
6256 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
6257 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
6258 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
6259 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
6260 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
6261 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
6262 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
6265 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
6266 tmp = RREG32(DC_HPD1_INT_CONTROL);
6267 tmp |= DC_HPDx_INT_ACK;
6268 WREG32(DC_HPD1_INT_CONTROL, tmp);
6270 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
6271 tmp = RREG32(DC_HPD2_INT_CONTROL);
6272 tmp |= DC_HPDx_INT_ACK;
6273 WREG32(DC_HPD2_INT_CONTROL, tmp);
6275 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
6276 tmp = RREG32(DC_HPD3_INT_CONTROL);
6277 tmp |= DC_HPDx_INT_ACK;
6278 WREG32(DC_HPD3_INT_CONTROL, tmp);
6280 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
6281 tmp = RREG32(DC_HPD4_INT_CONTROL);
6282 tmp |= DC_HPDx_INT_ACK;
6283 WREG32(DC_HPD4_INT_CONTROL, tmp);
6285 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
6286 tmp = RREG32(DC_HPD5_INT_CONTROL);
6287 tmp |= DC_HPDx_INT_ACK;
6288 WREG32(DC_HPD5_INT_CONTROL, tmp);
6290 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
6291 tmp = RREG32(DC_HPD5_INT_CONTROL);
6292 tmp |= DC_HPDx_INT_ACK;
6293 WREG32(DC_HPD6_INT_CONTROL, tmp);
6296 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT) {
6297 tmp = RREG32(DC_HPD1_INT_CONTROL);
6298 tmp |= DC_HPDx_RX_INT_ACK;
6299 WREG32(DC_HPD1_INT_CONTROL, tmp);
6301 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT) {
6302 tmp = RREG32(DC_HPD2_INT_CONTROL);
6303 tmp |= DC_HPDx_RX_INT_ACK;
6304 WREG32(DC_HPD2_INT_CONTROL, tmp);
6306 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) {
6307 tmp = RREG32(DC_HPD3_INT_CONTROL);
6308 tmp |= DC_HPDx_RX_INT_ACK;
6309 WREG32(DC_HPD3_INT_CONTROL, tmp);
6311 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) {
6312 tmp = RREG32(DC_HPD4_INT_CONTROL);
6313 tmp |= DC_HPDx_RX_INT_ACK;
6314 WREG32(DC_HPD4_INT_CONTROL, tmp);
6316 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) {
6317 tmp = RREG32(DC_HPD5_INT_CONTROL);
6318 tmp |= DC_HPDx_RX_INT_ACK;
6319 WREG32(DC_HPD5_INT_CONTROL, tmp);
6321 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {
6322 tmp = RREG32(DC_HPD5_INT_CONTROL);
6323 tmp |= DC_HPDx_RX_INT_ACK;
6324 WREG32(DC_HPD6_INT_CONTROL, tmp);
6328 static void si_irq_disable(struct radeon_device *rdev)
6330 si_disable_interrupts(rdev);
6331 /* Wait and acknowledge irq */
6334 si_disable_interrupt_state(rdev);
6337 static void si_irq_suspend(struct radeon_device *rdev)
6339 si_irq_disable(rdev);
6343 static void si_irq_fini(struct radeon_device *rdev)
6345 si_irq_suspend(rdev);
6346 r600_ih_ring_fini(rdev);
6349 static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
6353 if (rdev->wb.enabled)
6354 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
6356 wptr = RREG32(IH_RB_WPTR);
6358 if (wptr & RB_OVERFLOW) {
6359 wptr &= ~RB_OVERFLOW;
6360 /* When a ring buffer overflow happen start parsing interrupt
6361 * from the last not overwritten vector (wptr + 16). Hopefully
6362 * this should allow us to catchup.
6364 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
6365 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
6366 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
6367 tmp = RREG32(IH_RB_CNTL);
6368 tmp |= IH_WPTR_OVERFLOW_CLEAR;
6369 WREG32(IH_RB_CNTL, tmp);
6371 return (wptr & rdev->ih.ptr_mask);
6375 * Each IV ring entry is 128 bits:
6376 * [7:0] - interrupt source id
6378 * [59:32] - interrupt source data
6379 * [63:60] - reserved
6382 * [127:80] - reserved
6384 int si_irq_process(struct radeon_device *rdev)
6388 u32 src_id, src_data, ring_id;
6390 bool queue_hotplug = false;
6391 bool queue_dp = false;
6392 bool queue_thermal = false;
6395 if (!rdev->ih.enabled || rdev->shutdown)
6398 wptr = si_get_ih_wptr(rdev);
6401 /* is somebody else already processing irqs? */
6402 if (atomic_xchg(&rdev->ih.lock, 1))
6405 rptr = rdev->ih.rptr;
6406 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
6408 /* Order reading of wptr vs. reading of IH ring data */
6411 /* display interrupts */
6414 while (rptr != wptr) {
6415 /* wptr/rptr are in bytes! */
6416 ring_index = rptr / 4;
6417 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
6418 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
6419 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
6422 case 1: /* D1 vblank/vline */
6424 case 0: /* D1 vblank */
6425 if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT))
6426 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6428 if (rdev->irq.crtc_vblank_int[0]) {
6429 drm_handle_vblank(rdev->ddev, 0);
6430 rdev->pm.vblank_sync = true;
6431 wake_up(&rdev->irq.vblank_queue);
6433 if (atomic_read(&rdev->irq.pflip[0]))
6434 radeon_crtc_handle_vblank(rdev, 0);
6435 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
6436 DRM_DEBUG("IH: D1 vblank\n");
6439 case 1: /* D1 vline */
6440 if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT))
6441 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6443 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
6444 DRM_DEBUG("IH: D1 vline\n");
6448 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6452 case 2: /* D2 vblank/vline */
6454 case 0: /* D2 vblank */
6455 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT))
6456 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6458 if (rdev->irq.crtc_vblank_int[1]) {
6459 drm_handle_vblank(rdev->ddev, 1);
6460 rdev->pm.vblank_sync = true;
6461 wake_up(&rdev->irq.vblank_queue);
6463 if (atomic_read(&rdev->irq.pflip[1]))
6464 radeon_crtc_handle_vblank(rdev, 1);
6465 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
6466 DRM_DEBUG("IH: D2 vblank\n");
6469 case 1: /* D2 vline */
6470 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT))
6471 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6473 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
6474 DRM_DEBUG("IH: D2 vline\n");
6478 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6482 case 3: /* D3 vblank/vline */
6484 case 0: /* D3 vblank */
6485 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT))
6486 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6488 if (rdev->irq.crtc_vblank_int[2]) {
6489 drm_handle_vblank(rdev->ddev, 2);
6490 rdev->pm.vblank_sync = true;
6491 wake_up(&rdev->irq.vblank_queue);
6493 if (atomic_read(&rdev->irq.pflip[2]))
6494 radeon_crtc_handle_vblank(rdev, 2);
6495 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
6496 DRM_DEBUG("IH: D3 vblank\n");
6499 case 1: /* D3 vline */
6500 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT))
6501 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6503 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
6504 DRM_DEBUG("IH: D3 vline\n");
6508 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6512 case 4: /* D4 vblank/vline */
6514 case 0: /* D4 vblank */
6515 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT))
6516 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6518 if (rdev->irq.crtc_vblank_int[3]) {
6519 drm_handle_vblank(rdev->ddev, 3);
6520 rdev->pm.vblank_sync = true;
6521 wake_up(&rdev->irq.vblank_queue);
6523 if (atomic_read(&rdev->irq.pflip[3]))
6524 radeon_crtc_handle_vblank(rdev, 3);
6525 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
6526 DRM_DEBUG("IH: D4 vblank\n");
6529 case 1: /* D4 vline */
6530 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT))
6531 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6533 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
6534 DRM_DEBUG("IH: D4 vline\n");
6538 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6542 case 5: /* D5 vblank/vline */
6544 case 0: /* D5 vblank */
6545 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT))
6546 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6548 if (rdev->irq.crtc_vblank_int[4]) {
6549 drm_handle_vblank(rdev->ddev, 4);
6550 rdev->pm.vblank_sync = true;
6551 wake_up(&rdev->irq.vblank_queue);
6553 if (atomic_read(&rdev->irq.pflip[4]))
6554 radeon_crtc_handle_vblank(rdev, 4);
6555 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
6556 DRM_DEBUG("IH: D5 vblank\n");
6559 case 1: /* D5 vline */
6560 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT))
6561 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6563 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
6564 DRM_DEBUG("IH: D5 vline\n");
6568 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6572 case 6: /* D6 vblank/vline */
6574 case 0: /* D6 vblank */
6575 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT))
6576 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6578 if (rdev->irq.crtc_vblank_int[5]) {
6579 drm_handle_vblank(rdev->ddev, 5);
6580 rdev->pm.vblank_sync = true;
6581 wake_up(&rdev->irq.vblank_queue);
6583 if (atomic_read(&rdev->irq.pflip[5]))
6584 radeon_crtc_handle_vblank(rdev, 5);
6585 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
6586 DRM_DEBUG("IH: D6 vblank\n");
6589 case 1: /* D6 vline */
6590 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT))
6591 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6593 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
6594 DRM_DEBUG("IH: D6 vline\n");
6598 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6602 case 8: /* D1 page flip */
6603 case 10: /* D2 page flip */
6604 case 12: /* D3 page flip */
6605 case 14: /* D4 page flip */
6606 case 16: /* D5 page flip */
6607 case 18: /* D6 page flip */
6608 DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
6609 if (radeon_use_pflipirq > 0)
6610 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
6612 case 42: /* HPD hotplug */
6615 if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT))
6616 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6618 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
6619 queue_hotplug = true;
6620 DRM_DEBUG("IH: HPD1\n");
6624 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT))
6625 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6627 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
6628 queue_hotplug = true;
6629 DRM_DEBUG("IH: HPD2\n");
6633 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT))
6634 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6636 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
6637 queue_hotplug = true;
6638 DRM_DEBUG("IH: HPD3\n");
6642 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT))
6643 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6645 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
6646 queue_hotplug = true;
6647 DRM_DEBUG("IH: HPD4\n");
6651 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT))
6652 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6654 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
6655 queue_hotplug = true;
6656 DRM_DEBUG("IH: HPD5\n");
6660 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT))
6661 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6663 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
6664 queue_hotplug = true;
6665 DRM_DEBUG("IH: HPD6\n");
6669 if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT))
6670 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6672 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT;
6674 DRM_DEBUG("IH: HPD_RX 1\n");
6678 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT))
6679 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6681 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT;
6683 DRM_DEBUG("IH: HPD_RX 2\n");
6687 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT))
6688 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6690 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT;
6692 DRM_DEBUG("IH: HPD_RX 3\n");
6696 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT))
6697 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6699 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT;
6701 DRM_DEBUG("IH: HPD_RX 4\n");
6705 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT))
6706 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6708 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT;
6710 DRM_DEBUG("IH: HPD_RX 5\n");
6714 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT))
6715 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6717 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT;
6719 DRM_DEBUG("IH: HPD_RX 6\n");
6723 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6728 DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
6729 WREG32(SRBM_INT_ACK, 0x1);
6732 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
6733 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
6737 addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
6738 status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
6739 /* reset addr and status */
6740 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
6741 if (addr == 0x0 && status == 0x0)
6743 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
6744 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
6746 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
6748 si_vm_decode_fault(rdev, status, addr);
6750 case 176: /* RINGID0 CP_INT */
6751 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
6753 case 177: /* RINGID1 CP_INT */
6754 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
6756 case 178: /* RINGID2 CP_INT */
6757 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
6759 case 181: /* CP EOP event */
6760 DRM_DEBUG("IH: CP EOP\n");
6763 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
6766 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
6769 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
6773 case 224: /* DMA trap event */
6774 DRM_DEBUG("IH: DMA trap\n");
6775 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
6777 case 230: /* thermal low to high */
6778 DRM_DEBUG("IH: thermal low to high\n");
6779 rdev->pm.dpm.thermal.high_to_low = false;
6780 queue_thermal = true;
6782 case 231: /* thermal high to low */
6783 DRM_DEBUG("IH: thermal high to low\n");
6784 rdev->pm.dpm.thermal.high_to_low = true;
6785 queue_thermal = true;
6787 case 233: /* GUI IDLE */
6788 DRM_DEBUG("IH: GUI idle\n");
6790 case 244: /* DMA trap event */
6791 DRM_DEBUG("IH: DMA1 trap\n");
6792 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
6795 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6799 /* wptr/rptr are in bytes! */
6801 rptr &= rdev->ih.ptr_mask;
6802 WREG32(IH_RB_RPTR, rptr);
6805 schedule_work(&rdev->dp_work);
6807 schedule_delayed_work(&rdev->hotplug_work, 0);
6808 if (queue_thermal && rdev->pm.dpm_enabled)
6809 schedule_work(&rdev->pm.dpm.thermal.work);
6810 rdev->ih.rptr = rptr;
6811 atomic_set(&rdev->ih.lock, 0);
6813 /* make sure wptr hasn't changed while processing */
6814 wptr = si_get_ih_wptr(rdev);
6822 * startup/shutdown callbacks
6824 static int si_startup(struct radeon_device *rdev)
6826 struct radeon_ring *ring;
6829 /* enable pcie gen2/3 link */
6830 si_pcie_gen3_enable(rdev);
6832 si_program_aspm(rdev);
6834 /* scratch needs to be initialized before MC */
6835 r = r600_vram_scratch_init(rdev);
6839 si_mc_program(rdev);
6841 if (!rdev->pm.dpm_enabled) {
6842 r = si_mc_load_microcode(rdev);
6844 DRM_ERROR("Failed to load MC firmware!\n");
6849 r = si_pcie_gart_enable(rdev);
6854 /* allocate rlc buffers */
6855 if (rdev->family == CHIP_VERDE) {
6856 rdev->rlc.reg_list = verde_rlc_save_restore_register_list;
6857 rdev->rlc.reg_list_size =
6858 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
6860 rdev->rlc.cs_data = si_cs_data;
6861 r = sumo_rlc_init(rdev);
6863 DRM_ERROR("Failed to init rlc BOs!\n");
6867 /* allocate wb buffer */
6868 r = radeon_wb_init(rdev);
6872 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
6874 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
6878 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
6880 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
6884 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
6886 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
6890 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
6892 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
6896 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
6898 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
6902 if (rdev->has_uvd) {
6903 r = uvd_v2_2_resume(rdev);
6905 r = radeon_fence_driver_start_ring(rdev,
6906 R600_RING_TYPE_UVD_INDEX);
6908 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
6911 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
6914 r = radeon_vce_resume(rdev);
6916 r = vce_v1_0_resume(rdev);
6918 r = radeon_fence_driver_start_ring(rdev,
6919 TN_RING_TYPE_VCE1_INDEX);
6921 r = radeon_fence_driver_start_ring(rdev,
6922 TN_RING_TYPE_VCE2_INDEX);
6925 dev_err(rdev->dev, "VCE init error (%d).\n", r);
6926 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;
6927 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;
6931 if (!rdev->irq.installed) {
6932 r = radeon_irq_kms_init(rdev);
6937 r = si_irq_init(rdev);
6939 DRM_ERROR("radeon: IH init failed (%d).\n", r);
6940 radeon_irq_kms_fini(rdev);
6945 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
6946 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
6951 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
6952 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
6957 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
6958 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
6963 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
6964 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
6965 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
6969 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
6970 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
6971 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
6975 r = si_cp_load_microcode(rdev);
6978 r = si_cp_resume(rdev);
6982 r = cayman_dma_resume(rdev);
6986 if (rdev->has_uvd) {
6987 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
6988 if (ring->ring_size) {
6989 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
6992 r = uvd_v1_0_init(rdev);
6994 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
7000 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
7001 if (ring->ring_size)
7002 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
7005 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
7006 if (ring->ring_size)
7007 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
7011 r = vce_v1_0_init(rdev);
7012 else if (r != -ENOENT)
7013 DRM_ERROR("radeon: failed initializing VCE (%d).\n", r);
7015 r = radeon_ib_pool_init(rdev);
7017 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
7021 r = radeon_vm_manager_init(rdev);
7023 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
7027 r = radeon_audio_init(rdev);
7034 int si_resume(struct radeon_device *rdev)
7038 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
7039 * posting will perform necessary task to bring back GPU into good
7043 atom_asic_init(rdev->mode_info.atom_context);
7045 /* init golden registers */
7046 si_init_golden_registers(rdev);
7048 if (rdev->pm.pm_method == PM_METHOD_DPM)
7049 radeon_pm_resume(rdev);
7051 rdev->accel_working = true;
7052 r = si_startup(rdev);
7054 DRM_ERROR("si startup failed on resume\n");
7055 rdev->accel_working = false;
7063 int si_suspend(struct radeon_device *rdev)
7065 radeon_pm_suspend(rdev);
7066 radeon_audio_fini(rdev);
7067 radeon_vm_manager_fini(rdev);
7068 si_cp_enable(rdev, false);
7069 cayman_dma_stop(rdev);
7070 if (rdev->has_uvd) {
7071 uvd_v1_0_fini(rdev);
7072 radeon_uvd_suspend(rdev);
7073 radeon_vce_suspend(rdev);
7077 si_irq_suspend(rdev);
7078 radeon_wb_disable(rdev);
7079 si_pcie_gart_disable(rdev);
7083 /* Plan is to move initialization in that function and use
7084 * helper function so that radeon_device_init pretty much
7085 * do nothing more than calling asic specific function. This
7086 * should also allow to remove a bunch of callback function
7089 int si_init(struct radeon_device *rdev)
7091 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7095 if (!radeon_get_bios(rdev)) {
7096 if (ASIC_IS_AVIVO(rdev))
7099 /* Must be an ATOMBIOS */
7100 if (!rdev->is_atom_bios) {
7101 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
7104 r = radeon_atombios_init(rdev);
7108 /* Post card if necessary */
7109 if (!radeon_card_posted(rdev)) {
7111 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
7114 DRM_INFO("GPU not posted. posting now...\n");
7115 atom_asic_init(rdev->mode_info.atom_context);
7117 /* init golden registers */
7118 si_init_golden_registers(rdev);
7119 /* Initialize scratch registers */
7120 si_scratch_init(rdev);
7121 /* Initialize surface registers */
7122 radeon_surface_init(rdev);
7123 /* Initialize clocks */
7124 radeon_get_clock_info(rdev->ddev);
7127 r = radeon_fence_driver_init(rdev);
7131 /* initialize memory controller */
7132 r = si_mc_init(rdev);
7135 /* Memory manager */
7136 r = radeon_bo_init(rdev);
7140 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
7141 !rdev->rlc_fw || !rdev->mc_fw) {
7142 r = si_init_microcode(rdev);
7144 DRM_ERROR("Failed to load firmware!\n");
7149 /* Initialize power management */
7150 radeon_pm_init(rdev);
7152 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7153 ring->ring_obj = NULL;
7154 r600_ring_init(rdev, ring, 1024 * 1024);
7156 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
7157 ring->ring_obj = NULL;
7158 r600_ring_init(rdev, ring, 1024 * 1024);
7160 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
7161 ring->ring_obj = NULL;
7162 r600_ring_init(rdev, ring, 1024 * 1024);
7164 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
7165 ring->ring_obj = NULL;
7166 r600_ring_init(rdev, ring, 64 * 1024);
7168 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
7169 ring->ring_obj = NULL;
7170 r600_ring_init(rdev, ring, 64 * 1024);
7172 if (rdev->has_uvd) {
7173 r = radeon_uvd_init(rdev);
7175 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
7176 ring->ring_obj = NULL;
7177 r600_ring_init(rdev, ring, 4096);
7181 r = radeon_vce_init(rdev);
7183 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
7184 ring->ring_obj = NULL;
7185 r600_ring_init(rdev, ring, 4096);
7187 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
7188 ring->ring_obj = NULL;
7189 r600_ring_init(rdev, ring, 4096);
7192 rdev->ih.ring_obj = NULL;
7193 r600_ih_ring_init(rdev, 64 * 1024);
7195 r = r600_pcie_gart_init(rdev);
7199 rdev->accel_working = true;
7200 r = si_startup(rdev);
7202 dev_err(rdev->dev, "disabling GPU acceleration\n");
7204 cayman_dma_fini(rdev);
7206 sumo_rlc_fini(rdev);
7207 radeon_wb_fini(rdev);
7208 radeon_ib_pool_fini(rdev);
7209 radeon_vm_manager_fini(rdev);
7210 radeon_irq_kms_fini(rdev);
7211 si_pcie_gart_fini(rdev);
7212 rdev->accel_working = false;
7215 /* Don't start up if the MC ucode is missing.
7216 * The default clocks and voltages before the MC ucode
7217 * is loaded are not suffient for advanced operations.
7220 DRM_ERROR("radeon: MC ucode required for NI+.\n");
7227 void si_fini(struct radeon_device *rdev)
7229 radeon_pm_fini(rdev);
7231 cayman_dma_fini(rdev);
7235 sumo_rlc_fini(rdev);
7236 radeon_wb_fini(rdev);
7237 radeon_vm_manager_fini(rdev);
7238 radeon_ib_pool_fini(rdev);
7239 radeon_irq_kms_fini(rdev);
7240 if (rdev->has_uvd) {
7241 uvd_v1_0_fini(rdev);
7242 radeon_uvd_fini(rdev);
7243 radeon_vce_fini(rdev);
7245 si_pcie_gart_fini(rdev);
7246 r600_vram_scratch_fini(rdev);
7247 radeon_gem_fini(rdev);
7248 radeon_fence_driver_fini(rdev);
7249 radeon_bo_fini(rdev);
7250 radeon_atombios_fini(rdev);
7256 * si_get_gpu_clock_counter - return GPU clock counter snapshot
7258 * @rdev: radeon_device pointer
7260 * Fetches a GPU clock counter snapshot (SI).
7261 * Returns the 64 bit clock counter snapshot.
7263 uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev)
7267 mutex_lock(&rdev->gpu_clock_mutex);
7268 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
7269 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
7270 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
7271 mutex_unlock(&rdev->gpu_clock_mutex);
7275 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
7277 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
7280 /* bypass vclk and dclk with bclk */
7281 WREG32_P(CG_UPLL_FUNC_CNTL_2,
7282 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
7283 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
7285 /* put PLL in bypass mode */
7286 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
7288 if (!vclk || !dclk) {
7289 /* keep the Bypass mode */
7293 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
7294 16384, 0x03FFFFFF, 0, 128, 5,
7295 &fb_div, &vclk_div, &dclk_div);
7299 /* set RESET_ANTI_MUX to 0 */
7300 WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
7302 /* set VCO_MODE to 1 */
7303 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
7305 /* disable sleep mode */
7306 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
7308 /* deassert UPLL_RESET */
7309 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
7313 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
7317 /* assert UPLL_RESET again */
7318 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
7320 /* disable spread spectrum. */
7321 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
7323 /* set feedback divider */
7324 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
7326 /* set ref divider to 0 */
7327 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
7329 if (fb_div < 307200)
7330 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
7332 WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
7334 /* set PDIV_A and PDIV_B */
7335 WREG32_P(CG_UPLL_FUNC_CNTL_2,
7336 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
7337 ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
7339 /* give the PLL some time to settle */
7342 /* deassert PLL_RESET */
7343 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
7347 /* switch from bypass mode to normal mode */
7348 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
7350 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
7354 /* switch VCLK and DCLK selection */
7355 WREG32_P(CG_UPLL_FUNC_CNTL_2,
7356 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
7357 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
7364 static void si_pcie_gen3_enable(struct radeon_device *rdev)
7366 struct pci_dev *root = rdev->pdev->bus->self;
7367 int bridge_pos, gpu_pos;
7368 u32 speed_cntl, mask, current_data_rate;
7372 if (pci_is_root_bus(rdev->pdev->bus))
7375 if (radeon_pcie_gen2 == 0)
7378 if (rdev->flags & RADEON_IS_IGP)
7381 if (!(rdev->flags & RADEON_IS_PCIE))
7384 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
7388 if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
7391 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
7392 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
7393 LC_CURRENT_DATA_RATE_SHIFT;
7394 if (mask & DRM_PCIE_SPEED_80) {
7395 if (current_data_rate == 2) {
7396 DRM_INFO("PCIE gen 3 link speeds already enabled\n");
7399 DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n");
7400 } else if (mask & DRM_PCIE_SPEED_50) {
7401 if (current_data_rate == 1) {
7402 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
7405 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
7408 bridge_pos = pci_pcie_cap(root);
7412 gpu_pos = pci_pcie_cap(rdev->pdev);
7416 if (mask & DRM_PCIE_SPEED_80) {
7417 /* re-try equalization if gen3 is not already enabled */
7418 if (current_data_rate != 2) {
7419 u16 bridge_cfg, gpu_cfg;
7420 u16 bridge_cfg2, gpu_cfg2;
7421 u32 max_lw, current_lw, tmp;
7423 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
7424 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
7426 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
7427 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
7429 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
7430 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
7432 tmp = RREG32_PCIE(PCIE_LC_STATUS1);
7433 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
7434 current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
7436 if (current_lw < max_lw) {
7437 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
7438 if (tmp & LC_RENEGOTIATION_SUPPORT) {
7439 tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
7440 tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
7441 tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
7442 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
7446 for (i = 0; i < 10; i++) {
7448 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
7449 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
7452 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
7453 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
7455 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
7456 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
7458 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
7459 tmp |= LC_SET_QUIESCE;
7460 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
7462 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
7464 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
7469 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
7470 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
7471 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
7472 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
7474 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
7475 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
7476 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
7477 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
7480 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
7481 tmp16 &= ~((1 << 4) | (7 << 9));
7482 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
7483 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
7485 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
7486 tmp16 &= ~((1 << 4) | (7 << 9));
7487 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
7488 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
7490 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
7491 tmp &= ~LC_SET_QUIESCE;
7492 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
7497 /* set the link speed */
7498 speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
7499 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
7500 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
7502 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
7504 if (mask & DRM_PCIE_SPEED_80)
7505 tmp16 |= 3; /* gen3 */
7506 else if (mask & DRM_PCIE_SPEED_50)
7507 tmp16 |= 2; /* gen2 */
7509 tmp16 |= 1; /* gen1 */
7510 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
7512 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
7513 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
7514 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
7516 for (i = 0; i < rdev->usec_timeout; i++) {
7517 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
7518 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
7524 static void si_program_aspm(struct radeon_device *rdev)
7527 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
7528 bool disable_clkreq = false;
7530 if (radeon_aspm == 0)
7533 if (!(rdev->flags & RADEON_IS_PCIE))
7536 orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
7537 data &= ~LC_XMIT_N_FTS_MASK;
7538 data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
7540 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
7542 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
7543 data |= LC_GO_TO_RECOVERY;
7545 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
7547 orig = data = RREG32_PCIE(PCIE_P_CNTL);
7548 data |= P_IGNORE_EDB_ERR;
7550 WREG32_PCIE(PCIE_P_CNTL, data);
7552 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
7553 data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
7554 data |= LC_PMI_TO_L1_DIS;
7556 data |= LC_L0S_INACTIVITY(7);
7559 data |= LC_L1_INACTIVITY(7);
7560 data &= ~LC_PMI_TO_L1_DIS;
7562 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
7564 if (!disable_plloff_in_l1) {
7565 bool clk_req_support;
7567 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0);
7568 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
7569 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
7571 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0, data);
7573 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1);
7574 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
7575 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
7577 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1, data);
7579 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0);
7580 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
7581 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
7583 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0, data);
7585 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1);
7586 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
7587 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
7589 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1, data);
7591 if ((rdev->family != CHIP_OLAND) && (rdev->family != CHIP_HAINAN)) {
7592 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0);
7593 data &= ~PLL_RAMP_UP_TIME_0_MASK;
7595 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0, data);
7597 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1);
7598 data &= ~PLL_RAMP_UP_TIME_1_MASK;
7600 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1, data);
7602 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_2);
7603 data &= ~PLL_RAMP_UP_TIME_2_MASK;
7605 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_2, data);
7607 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_3);
7608 data &= ~PLL_RAMP_UP_TIME_3_MASK;
7610 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_3, data);
7612 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0);
7613 data &= ~PLL_RAMP_UP_TIME_0_MASK;
7615 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0, data);
7617 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1);
7618 data &= ~PLL_RAMP_UP_TIME_1_MASK;
7620 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1, data);
7622 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_2);
7623 data &= ~PLL_RAMP_UP_TIME_2_MASK;
7625 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_2, data);
7627 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_3);
7628 data &= ~PLL_RAMP_UP_TIME_3_MASK;
7630 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_3, data);
7632 orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
7633 data &= ~LC_DYN_LANES_PWR_STATE_MASK;
7634 data |= LC_DYN_LANES_PWR_STATE(3);
7636 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
7638 orig = data = RREG32_PIF_PHY0(PB0_PIF_CNTL);
7639 data &= ~LS2_EXIT_TIME_MASK;
7640 if ((rdev->family == CHIP_OLAND) || (rdev->family == CHIP_HAINAN))
7641 data |= LS2_EXIT_TIME(5);
7643 WREG32_PIF_PHY0(PB0_PIF_CNTL, data);
7645 orig = data = RREG32_PIF_PHY1(PB1_PIF_CNTL);
7646 data &= ~LS2_EXIT_TIME_MASK;
7647 if ((rdev->family == CHIP_OLAND) || (rdev->family == CHIP_HAINAN))
7648 data |= LS2_EXIT_TIME(5);
7650 WREG32_PIF_PHY1(PB1_PIF_CNTL, data);
7652 if (!disable_clkreq &&
7653 !pci_is_root_bus(rdev->pdev->bus)) {
7654 struct pci_dev *root = rdev->pdev->bus->self;
7657 clk_req_support = false;
7658 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
7659 if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
7660 clk_req_support = true;
7662 clk_req_support = false;
7665 if (clk_req_support) {
7666 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
7667 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
7669 WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
7671 orig = data = RREG32(THM_CLK_CNTL);
7672 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
7673 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
7675 WREG32(THM_CLK_CNTL, data);
7677 orig = data = RREG32(MISC_CLK_CNTL);
7678 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
7679 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
7681 WREG32(MISC_CLK_CNTL, data);
7683 orig = data = RREG32(CG_CLKPIN_CNTL);
7684 data &= ~BCLK_AS_XCLK;
7686 WREG32(CG_CLKPIN_CNTL, data);
7688 orig = data = RREG32(CG_CLKPIN_CNTL_2);
7689 data &= ~FORCE_BIF_REFCLK_EN;
7691 WREG32(CG_CLKPIN_CNTL_2, data);
7693 orig = data = RREG32(MPLL_BYPASSCLK_SEL);
7694 data &= ~MPLL_CLKOUT_SEL_MASK;
7695 data |= MPLL_CLKOUT_SEL(4);
7697 WREG32(MPLL_BYPASSCLK_SEL, data);
7699 orig = data = RREG32(SPLL_CNTL_MODE);
7700 data &= ~SPLL_REFCLK_SEL_MASK;
7702 WREG32(SPLL_CNTL_MODE, data);
7707 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
7710 orig = data = RREG32_PCIE(PCIE_CNTL2);
7711 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
7713 WREG32_PCIE(PCIE_CNTL2, data);
7716 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
7717 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
7718 data = RREG32_PCIE(PCIE_LC_STATUS1);
7719 if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
7720 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
7721 data &= ~LC_L0S_INACTIVITY_MASK;
7723 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
7729 int si_vce_send_vcepll_ctlreq(struct radeon_device *rdev)
7733 /* make sure VCEPLL_CTLREQ is deasserted */
7734 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
7738 /* assert UPLL_CTLREQ */
7739 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
7741 /* wait for CTLACK and CTLACK2 to get asserted */
7742 for (i = 0; i < 100; ++i) {
7743 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
7744 if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask)
7749 /* deassert UPLL_CTLREQ */
7750 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
7753 DRM_ERROR("Timeout setting UVD clocks!\n");
7760 int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
7762 unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0;
7765 /* bypass evclk and ecclk with bclk */
7766 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
7767 EVCLK_SRC_SEL(1) | ECCLK_SRC_SEL(1),
7768 ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK));
7770 /* put PLL in bypass mode */
7771 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK,
7772 ~VCEPLL_BYPASS_EN_MASK);
7774 if (!evclk || !ecclk) {
7775 /* keep the Bypass mode, put PLL to sleep */
7776 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,
7777 ~VCEPLL_SLEEP_MASK);
7781 r = radeon_uvd_calc_upll_dividers(rdev, evclk, ecclk, 125000, 250000,
7782 16384, 0x03FFFFFF, 0, 128, 5,
7783 &fb_div, &evclk_div, &ecclk_div);
7787 /* set RESET_ANTI_MUX to 0 */
7788 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
7790 /* set VCO_MODE to 1 */
7791 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK,
7792 ~VCEPLL_VCO_MODE_MASK);
7794 /* toggle VCEPLL_SLEEP to 1 then back to 0 */
7795 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,
7796 ~VCEPLL_SLEEP_MASK);
7797 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK);
7799 /* deassert VCEPLL_RESET */
7800 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);
7804 r = si_vce_send_vcepll_ctlreq(rdev);
7808 /* assert VCEPLL_RESET again */
7809 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK);
7811 /* disable spread spectrum. */
7812 WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
7814 /* set feedback divider */
7815 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, VCEPLL_FB_DIV(fb_div), ~VCEPLL_FB_DIV_MASK);
7817 /* set ref divider to 0 */
7818 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK);
7820 /* set PDIV_A and PDIV_B */
7821 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
7822 VCEPLL_PDIV_A(evclk_div) | VCEPLL_PDIV_B(ecclk_div),
7823 ~(VCEPLL_PDIV_A_MASK | VCEPLL_PDIV_B_MASK));
7825 /* give the PLL some time to settle */
7828 /* deassert PLL_RESET */
7829 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);
7833 /* switch from bypass mode to normal mode */
7834 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK);
7836 r = si_vce_send_vcepll_ctlreq(rdev);
7840 /* switch VCLK and DCLK selection */
7841 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
7842 EVCLK_SRC_SEL(16) | ECCLK_SRC_SEL(16),
7843 ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK));
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