drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/component.h>
  30
  31 #include <linux/reset.h>
  32 #include <linux/delay.h>
  33
  34 #include "rockchip_drm_drv.h"
  35 #include "rockchip_drm_gem.h"
  36 #include "rockchip_drm_fb.h"
  37 #include "rockchip_drm_vop.h"
  38
  39 #define __REG_SET_RELAXED(x, off, mask, shift, v) \
  40                 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
  41 #define __REG_SET_NORMAL(x, off, mask, shift, v) \
  42                 vop_mask_write(x, off, (mask) << shift, (v) << shift)
  43
  44 #define REG_SET(x, base, reg, v, mode) \
  45                 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
  46 #define REG_SET_MASK(x, base, reg, mask, v, mode) \
  47                 __REG_SET_##mode(x, base + reg.offset, mask, reg.shift, v)
  48
  49 #define VOP_WIN_SET(x, win, name, v) \
  50                 REG_SET(x, win->base, win->phy->name, v, RELAXED)
  51 #define VOP_SCL_SET(x, win, name, v) \
  52                 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
  53 #define VOP_SCL_SET_EXT(x, win, name, v) \
  54                 REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
  55 #define VOP_CTRL_SET(x, name, v) \
  56                 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
  57
  58 #define VOP_INTR_GET(vop, name) \
  59                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  60
  61 #define VOP_INTR_SET(vop, name, mask, v) \
  62                 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
  63 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  64         do { \
  65                 int i, reg = 0, mask = 0; \
  66                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  67                         if (vop->data->intr->intrs[i] & type) { \
  68                                 reg |= (v) << i; \
  69                                 mask |= 1 << i; \
  70                         } \
  71                 } \
  72                 VOP_INTR_SET(vop, name, mask, reg); \
  73         } while (0)
  74 #define VOP_INTR_GET_TYPE(vop, name, type) \
  75                 vop_get_intr_type(vop, &vop->data->intr->name, type)
  76
  77 #define VOP_WIN_GET(x, win, name) \
  78                 vop_read_reg(x, win->base, &win->phy->name)
  79
  80 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  81                 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
  82
  83 #define to_vop(x) container_of(x, struct vop, crtc)
  84 #define to_vop_win(x) container_of(x, struct vop_win, base)
  85 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
  86
  87 struct vop_plane_state {
  88         struct drm_plane_state base;
  89         int format;
  90         struct drm_rect src;
  91         struct drm_rect dest;
  92         dma_addr_t yrgb_mst;
  93         bool enable;
  94 };
  95
  96 struct vop_win {
  97         struct drm_plane base;
  98         const struct vop_win_data *data;
  99         struct vop *vop;
 100
 101         struct vop_plane_state state;
 102 };
 103
 104 struct vop {
 105         struct drm_crtc crtc;
 106         struct device *dev;
 107         struct drm_device *drm_dev;
 108         bool is_enabled;
 109
 110         /* mutex vsync_ work */
 111         struct mutex vsync_mutex;
 112         bool vsync_work_pending;
 113         struct completion dsp_hold_completion;
 114         struct completion wait_update_complete;
 115         struct drm_pending_vblank_event *event;
 116
 117         const struct vop_data *data;
 118
 119         uint32_t *regsbak;
 120         void __iomem *regs;
 121
 122         /* physical map length of vop register */
 123         uint32_t len;
 124
 125         /* one time only one process allowed to config the register */
 126         spinlock_t reg_lock;
 127         /* lock vop irq reg */
 128         spinlock_t irq_lock;
 129
 130         unsigned int irq;
 131
 132         /* vop AHP clk */
 133         struct clk *hclk;
 134         /* vop dclk */
 135         struct clk *dclk;
 136         /* vop share memory frequency */
 137         struct clk *aclk;
 138
 139         /* vop dclk reset */
 140         struct reset_control *dclk_rst;
 141
 142         struct vop_win win[];
 143 };
 144
 145 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 146 {
 147         writel(v, vop->regs + offset);
 148         vop->regsbak[offset >> 2] = v;
 149 }
 150
 151 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 152 {
 153         return readl(vop->regs + offset);
 154 }
 155
 156 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 157                                     const struct vop_reg *reg)
 158 {
 159         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 160 }
 161
 162 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 163                                   uint32_t mask, uint32_t v)
 164 {
 165         if (mask) {
 166                 uint32_t cached_val = vop->regsbak[offset >> 2];
 167
 168                 cached_val = (cached_val & ~mask) | v;
 169                 writel(cached_val, vop->regs + offset);
 170                 vop->regsbak[offset >> 2] = cached_val;
 171         }
 172 }
 173
 174 static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset,
 175                                           uint32_t mask, uint32_t v)
 176 {
 177         if (mask) {
 178                 uint32_t cached_val = vop->regsbak[offset >> 2];
 179
 180                 cached_val = (cached_val & ~mask) | v;
 181                 writel_relaxed(cached_val, vop->regs + offset);
 182                 vop->regsbak[offset >> 2] = cached_val;
 183         }
 184 }
 185
 186 static inline uint32_t vop_get_intr_type(struct vop *vop,
 187                                          const struct vop_reg *reg, int type)
 188 {
 189         uint32_t i, ret = 0;
 190         uint32_t regs = vop_read_reg(vop, 0, reg);
 191
 192         for (i = 0; i < vop->data->intr->nintrs; i++) {
 193                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 194                         ret |= vop->data->intr->intrs[i];
 195         }
 196
 197         return ret;
 198 }
 199
 200 static inline void vop_cfg_done(struct vop *vop)
 201 {
 202         VOP_CTRL_SET(vop, cfg_done, 1);
 203 }
 204
 205 static bool has_rb_swapped(uint32_t format)
 206 {
 207         switch (format) {
 208         case DRM_FORMAT_XBGR8888:
 209         case DRM_FORMAT_ABGR8888:
 210         case DRM_FORMAT_BGR888:
 211         case DRM_FORMAT_BGR565:
 212                 return true;
 213         default:
 214                 return false;
 215         }
 216 }
 217
 218 static enum vop_data_format vop_convert_format(uint32_t format)
 219 {
 220         switch (format) {
 221         case DRM_FORMAT_XRGB8888:
 222         case DRM_FORMAT_ARGB8888:
 223         case DRM_FORMAT_XBGR8888:
 224         case DRM_FORMAT_ABGR8888:
 225                 return VOP_FMT_ARGB8888;
 226         case DRM_FORMAT_RGB888:
 227         case DRM_FORMAT_BGR888:
 228                 return VOP_FMT_RGB888;
 229         case DRM_FORMAT_RGB565:
 230         case DRM_FORMAT_BGR565:
 231                 return VOP_FMT_RGB565;
 232         case DRM_FORMAT_NV12:
 233                 return VOP_FMT_YUV420SP;
 234         case DRM_FORMAT_NV16:
 235                 return VOP_FMT_YUV422SP;
 236         case DRM_FORMAT_NV24:
 237                 return VOP_FMT_YUV444SP;
 238         default:
 239                 DRM_ERROR("unsupport format[%08x]\n", format);
 240                 return -EINVAL;
 241         }
 242 }
 243
 244 static bool is_yuv_support(uint32_t format)
 245 {
 246         switch (format) {
 247         case DRM_FORMAT_NV12:
 248         case DRM_FORMAT_NV16:
 249         case DRM_FORMAT_NV24:
 250                 return true;
 251         default:
 252                 return false;
 253         }
 254 }
 255
 256 static bool is_alpha_support(uint32_t format)
 257 {
 258         switch (format) {
 259         case DRM_FORMAT_ARGB8888:
 260         case DRM_FORMAT_ABGR8888:
 261                 return true;
 262         default:
 263                 return false;
 264         }
 265 }
 266
 267 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 268                                   uint32_t dst, bool is_horizontal,
 269                                   int vsu_mode, int *vskiplines)
 270 {
 271         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 272
 273         if (is_horizontal) {
 274                 if (mode == SCALE_UP)
 275                         val = GET_SCL_FT_BIC(src, dst);
 276                 else if (mode == SCALE_DOWN)
 277                         val = GET_SCL_FT_BILI_DN(src, dst);
 278         } else {
 279                 if (mode == SCALE_UP) {
 280                         if (vsu_mode == SCALE_UP_BIL)
 281                                 val = GET_SCL_FT_BILI_UP(src, dst);
 282                         else
 283                                 val = GET_SCL_FT_BIC(src, dst);
 284                 } else if (mode == SCALE_DOWN) {
 285                         if (vskiplines) {
 286                                 *vskiplines = scl_get_vskiplines(src, dst);
 287                                 val = scl_get_bili_dn_vskip(src, dst,
 288                                                             *vskiplines);
 289                         } else {
 290                                 val = GET_SCL_FT_BILI_DN(src, dst);
 291                         }
 292                 }
 293         }
 294
 295         return val;
 296 }
 297
 298 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
 299                              uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 300                              uint32_t dst_h, uint32_t pixel_format)
 301 {
 302         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 303         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 304         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 305         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 306         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 307         bool is_yuv = is_yuv_support(pixel_format);
 308         uint16_t cbcr_src_w = src_w / hsub;
 309         uint16_t cbcr_src_h = src_h / vsub;
 310         uint16_t vsu_mode;
 311         uint16_t lb_mode;
 312         uint32_t val;
 313         int vskiplines = 0;
 314
 315         if (dst_w > 3840) {
 316                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 317                 return;
 318         }
 319
 320         if (!win->phy->scl->ext) {
 321                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 322                             scl_cal_scale2(src_w, dst_w));
 323                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 324                             scl_cal_scale2(src_h, dst_h));
 325                 if (is_yuv) {
 326                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 327                                     scl_cal_scale2(src_w, dst_w));
 328                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 329                                     scl_cal_scale2(src_h, dst_h));
 330                 }
 331                 return;
 332         }
 333
 334         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 335         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 336
 337         if (is_yuv) {
 338                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 339                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 340                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 341                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 342                 else
 343                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 344         } else {
 345                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 346                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 347                 else
 348                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 349         }
 350
 351         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 352         if (lb_mode == LB_RGB_3840X2) {
 353                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 354                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 355                         return;
 356                 }
 357                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 358                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 359                         return;
 360                 }
 361                 vsu_mode = SCALE_UP_BIL;
 362         } else if (lb_mode == LB_RGB_2560X4) {
 363                 vsu_mode = SCALE_UP_BIL;
 364         } else {
 365                 vsu_mode = SCALE_UP_BIC;
 366         }
 367
 368         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 369                                 true, 0, NULL);
 370         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 371         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 372                                 false, vsu_mode, &vskiplines);
 373         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 374
 375         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 376         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 377
 378         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 379         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 380         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 381         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 382         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 383         if (is_yuv) {
 384                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 385                                         dst_w, true, 0, NULL);
 386                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 387                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 388                                         dst_h, false, vsu_mode, &vskiplines);
 389                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 390
 391                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 392                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 393                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 394                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 395                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 396                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 397                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 398         }
 399 }
 400
 401 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 402 {
 403         unsigned long flags;
 404
 405         if (WARN_ON(!vop->is_enabled))
 406                 return;
 407
 408         spin_lock_irqsave(&vop->irq_lock, flags);
 409
 410         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 411
 412         spin_unlock_irqrestore(&vop->irq_lock, flags);
 413 }
 414
 415 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 416 {
 417         unsigned long flags;
 418
 419         if (WARN_ON(!vop->is_enabled))
 420                 return;
 421
 422         spin_lock_irqsave(&vop->irq_lock, flags);
 423
 424         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 425
 426         spin_unlock_irqrestore(&vop->irq_lock, flags);
 427 }
 428
 429 static void vop_enable(struct drm_crtc *crtc)
 430 {
 431         struct vop *vop = to_vop(crtc);
 432         int ret;
 433
 434         if (vop->is_enabled)
 435                 return;
 436
 437         ret = pm_runtime_get_sync(vop->dev);
 438         if (ret < 0) {
 439                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 440                 return;
 441         }
 442
 443         ret = clk_enable(vop->hclk);
 444         if (ret < 0) {
 445                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 446                 return;
 447         }
 448
 449         ret = clk_enable(vop->dclk);
 450         if (ret < 0) {
 451                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 452                 goto err_disable_hclk;
 453         }
 454
 455         ret = clk_enable(vop->aclk);
 456         if (ret < 0) {
 457                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 458                 goto err_disable_dclk;
 459         }
 460
 461         /*
 462          * Slave iommu shares power, irq and clock with vop.  It was associated
 463          * automatically with this master device via common driver code.
 464          * Now that we have enabled the clock we attach it to the shared drm
 465          * mapping.
 466          */
 467         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 468         if (ret) {
 469                 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
 470                 goto err_disable_aclk;
 471         }
 472
 473         memcpy(vop->regs, vop->regsbak, vop->len);
 474         /*
 475          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 476          */
 477         vop->is_enabled = true;
 478
 479         spin_lock(&vop->reg_lock);
 480
 481         VOP_CTRL_SET(vop, standby, 0);
 482
 483         spin_unlock(&vop->reg_lock);
 484
 485         enable_irq(vop->irq);
 486
 487         drm_crtc_vblank_on(crtc);
 488
 489         return;
 490
 491 err_disable_aclk:
 492         clk_disable(vop->aclk);
 493 err_disable_dclk:
 494         clk_disable(vop->dclk);
 495 err_disable_hclk:
 496         clk_disable(vop->hclk);
 497 }
 498
 499 static void vop_crtc_disable(struct drm_crtc *crtc)
 500 {
 501         struct vop *vop = to_vop(crtc);
 502         int i;
 503
 504         if (!vop->is_enabled)
 505                 return;
 506
 507         /*
 508          * We need to make sure that all windows are disabled before we
 509          * disable that crtc. Otherwise we might try to scan from a destroyed
 510          * buffer later.
 511          */
 512         for (i = 0; i < vop->data->win_size; i++) {
 513                 struct vop_win *vop_win = &vop->win[i];
 514                 const struct vop_win_data *win = vop_win->data;
 515
 516                 spin_lock(&vop->reg_lock);
 517                 VOP_WIN_SET(vop, win, enable, 0);
 518                 spin_unlock(&vop->reg_lock);
 519         }
 520
 521         drm_crtc_vblank_off(crtc);
 522
 523         /*
 524          * Vop standby will take effect at end of current frame,
 525          * if dsp hold valid irq happen, it means standby complete.
 526          *
 527          * we must wait standby complete when we want to disable aclk,
 528          * if not, memory bus maybe dead.
 529          */
 530         reinit_completion(&vop->dsp_hold_completion);
 531         vop_dsp_hold_valid_irq_enable(vop);
 532
 533         spin_lock(&vop->reg_lock);
 534
 535         VOP_CTRL_SET(vop, standby, 1);
 536
 537         spin_unlock(&vop->reg_lock);
 538
 539         wait_for_completion(&vop->dsp_hold_completion);
 540
 541         vop_dsp_hold_valid_irq_disable(vop);
 542
 543         disable_irq(vop->irq);
 544
 545         vop->is_enabled = false;
 546
 547         /*
 548          * vop standby complete, so iommu detach is safe.
 549          */
 550         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 551
 552         clk_disable(vop->dclk);
 553         clk_disable(vop->aclk);
 554         clk_disable(vop->hclk);
 555         pm_runtime_put(vop->dev);
 556 }
 557
 558 static void vop_plane_destroy(struct drm_plane *plane)
 559 {
 560         drm_plane_cleanup(plane);
 561 }
 562
 563 static int vop_plane_prepare_fb(struct drm_plane *plane,
 564                                 const struct drm_plane_state *new_state)
 565 {
 566         if (plane->state->fb)
 567                 drm_framebuffer_reference(plane->state->fb);
 568
 569         return 0;
 570 }
 571
 572 static void vop_plane_cleanup_fb(struct drm_plane *plane,
 573                                  const struct drm_plane_state *old_state)
 574 {
 575         if (old_state->fb)
 576                 drm_framebuffer_unreference(old_state->fb);
 577 }
 578
 579 static int vop_plane_atomic_check(struct drm_plane *plane,
 580                            struct drm_plane_state *state)
 581 {
 582         struct drm_crtc *crtc = state->crtc;
 583         struct drm_crtc_state *crtc_state;
 584         struct drm_framebuffer *fb = state->fb;
 585         struct vop_win *vop_win = to_vop_win(plane);
 586         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 587         const struct vop_win_data *win = vop_win->data;
 588         bool visible;
 589         int ret;
 590         struct drm_rect *dest = &vop_plane_state->dest;
 591         struct drm_rect *src = &vop_plane_state->src;
 592         struct drm_rect clip;
 593         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 594                                         DRM_PLANE_HELPER_NO_SCALING;
 595         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 596                                         DRM_PLANE_HELPER_NO_SCALING;
 597
 598         if (!crtc || !fb)
 599                 goto out_disable;
 600
 601         crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
 602         if (WARN_ON(!crtc_state))
 603                 return -EINVAL;
 604
 605         src->x1 = state->src_x;
 606         src->y1 = state->src_y;
 607         src->x2 = state->src_x + state->src_w;
 608         src->y2 = state->src_y + state->src_h;
 609         dest->x1 = state->crtc_x;
 610         dest->y1 = state->crtc_y;
 611         dest->x2 = state->crtc_x + state->crtc_w;
 612         dest->y2 = state->crtc_y + state->crtc_h;
 613
 614         clip.x1 = 0;
 615         clip.y1 = 0;
 616         clip.x2 = crtc_state->adjusted_mode.hdisplay;
 617         clip.y2 = crtc_state->adjusted_mode.vdisplay;
 618
 619         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 620                                             src, dest, &clip,
 621                                             min_scale,
 622                                             max_scale,
 623                                             true, true, &visible);
 624         if (ret)
 625                 return ret;
 626
 627         if (!visible)
 628                 goto out_disable;
 629
 630         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 631         if (vop_plane_state->format < 0)
 632                 return vop_plane_state->format;
 633
 634         /*
 635          * Src.x1 can be odd when do clip, but yuv plane start point
 636          * need align with 2 pixel.
 637          */
 638         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 639                 return -EINVAL;
 640
 641         vop_plane_state->enable = true;
 642
 643         return 0;
 644
 645 out_disable:
 646         vop_plane_state->enable = false;
 647         return 0;
 648 }
 649
 650 static void vop_plane_atomic_disable(struct drm_plane *plane,
 651                                      struct drm_plane_state *old_state)
 652 {
 653         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
 654         struct vop_win *vop_win = to_vop_win(plane);
 655         const struct vop_win_data *win = vop_win->data;
 656         struct vop *vop = to_vop(old_state->crtc);
 657
 658         if (!old_state->crtc)
 659                 return;
 660
 661         spin_lock(&vop->reg_lock);
 662
 663         VOP_WIN_SET(vop, win, enable, 0);
 664
 665         spin_unlock(&vop->reg_lock);
 666
 667         vop_plane_state->enable = false;
 668 }
 669
 670 static void vop_plane_atomic_update(struct drm_plane *plane,
 671                 struct drm_plane_state *old_state)
 672 {
 673         struct drm_plane_state *state = plane->state;
 674         struct drm_crtc *crtc = state->crtc;
 675         struct vop_win *vop_win = to_vop_win(plane);
 676         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 677         const struct vop_win_data *win = vop_win->data;
 678         struct vop *vop = to_vop(state->crtc);
 679         struct drm_framebuffer *fb = state->fb;
 680         unsigned int actual_w, actual_h;
 681         unsigned int dsp_stx, dsp_sty;
 682         uint32_t act_info, dsp_info, dsp_st;
 683         struct drm_rect *src = &vop_plane_state->src;
 684         struct drm_rect *dest = &vop_plane_state->dest;
 685         struct drm_gem_object *obj, *uv_obj;
 686         struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 687         unsigned long offset;
 688         dma_addr_t dma_addr;
 689         uint32_t val;
 690         bool rb_swap;
 691
 692         /*
 693          * can't update plane when vop is disabled.
 694          */
 695         if (!crtc)
 696                 return;
 697
 698         if (WARN_ON(!vop->is_enabled))
 699                 return;
 700
 701         if (!vop_plane_state->enable) {
 702                 vop_plane_atomic_disable(plane, old_state);
 703                 return;
 704         }
 705
 706         obj = rockchip_fb_get_gem_obj(fb, 0);
 707         rk_obj = to_rockchip_obj(obj);
 708
 709         actual_w = drm_rect_width(src) >> 16;
 710         actual_h = drm_rect_height(src) >> 16;
 711         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 712
 713         dsp_info = (drm_rect_height(dest) - 1) << 16;
 714         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 715
 716         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 717         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 718         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 719
 720         offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 721         offset += (src->y1 >> 16) * fb->pitches[0];
 722         vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
 723
 724         spin_lock(&vop->reg_lock);
 725
 726         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
 727         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
 728         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
 729         if (is_yuv_support(fb->pixel_format)) {
 730                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 731                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 732                 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
 733
 734                 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
 735                 rk_uv_obj = to_rockchip_obj(uv_obj);
 736
 737                 offset = (src->x1 >> 16) * bpp / hsub;
 738                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 739
 740                 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 741                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
 742                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 743         }
 744
 745         if (win->phy->scl)
 746                 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 747                                     drm_rect_width(dest), drm_rect_height(dest),
 748                                     fb->pixel_format);
 749
 750         VOP_WIN_SET(vop, win, act_info, act_info);
 751         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 752         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 753
 754         rb_swap = has_rb_swapped(fb->pixel_format);
 755         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 756
 757         if (is_alpha_support(fb->pixel_format)) {
 758                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 759                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 760                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 761                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 762                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 763                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 764                         SRC_FACTOR_M0(ALPHA_ONE);
 765                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 766         } else {
 767                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 768         }
 769
 770         VOP_WIN_SET(vop, win, enable, 1);
 771         spin_unlock(&vop->reg_lock);
 772 }
 773
 774 static const struct drm_plane_helper_funcs plane_helper_funcs = {
 775         .prepare_fb = vop_plane_prepare_fb,
 776         .cleanup_fb = vop_plane_cleanup_fb,
 777         .atomic_check = vop_plane_atomic_check,
 778         .atomic_update = vop_plane_atomic_update,
 779         .atomic_disable = vop_plane_atomic_disable,
 780 };
 781
 782 void vop_atomic_plane_reset(struct drm_plane *plane)
 783 {
 784         struct vop_plane_state *vop_plane_state =
 785                                         to_vop_plane_state(plane->state);
 786
 787         if (plane->state && plane->state->fb)
 788                 drm_framebuffer_unreference(plane->state->fb);
 789
 790         kfree(vop_plane_state);
 791         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
 792         if (!vop_plane_state)
 793                 return;
 794
 795         plane->state = &vop_plane_state->base;
 796         plane->state->plane = plane;
 797 }
 798
 799 struct drm_plane_state *
 800 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
 801 {
 802         struct vop_plane_state *old_vop_plane_state;
 803         struct vop_plane_state *vop_plane_state;
 804
 805         if (WARN_ON(!plane->state))
 806                 return NULL;
 807
 808         old_vop_plane_state = to_vop_plane_state(plane->state);
 809         vop_plane_state = kmemdup(old_vop_plane_state,
 810                                   sizeof(*vop_plane_state), GFP_KERNEL);
 811         if (!vop_plane_state)
 812                 return NULL;
 813
 814         __drm_atomic_helper_plane_duplicate_state(plane,
 815                                                   &vop_plane_state->base);
 816
 817         return &vop_plane_state->base;
 818 }
 819
 820 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
 821                                            struct drm_plane_state *state)
 822 {
 823         struct vop_plane_state *vop_state = to_vop_plane_state(state);
 824
 825         __drm_atomic_helper_plane_destroy_state(state);
 826
 827         kfree(vop_state);
 828 }
 829
 830 static const struct drm_plane_funcs vop_plane_funcs = {
 831         .update_plane   = drm_atomic_helper_update_plane,
 832         .disable_plane  = drm_atomic_helper_disable_plane,
 833         .destroy = vop_plane_destroy,
 834         .reset = vop_atomic_plane_reset,
 835         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
 836         .atomic_destroy_state = vop_atomic_plane_destroy_state,
 837 };
 838
 839 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 840 {
 841         struct vop *vop = to_vop(crtc);
 842         unsigned long flags;
 843
 844         if (WARN_ON(!vop->is_enabled))
 845                 return -EPERM;
 846
 847         spin_lock_irqsave(&vop->irq_lock, flags);
 848
 849         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
 850
 851         spin_unlock_irqrestore(&vop->irq_lock, flags);
 852
 853         return 0;
 854 }
 855
 856 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 857 {
 858         struct vop *vop = to_vop(crtc);
 859         unsigned long flags;
 860
 861         if (WARN_ON(!vop->is_enabled))
 862                 return;
 863
 864         spin_lock_irqsave(&vop->irq_lock, flags);
 865
 866         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
 867
 868         spin_unlock_irqrestore(&vop->irq_lock, flags);
 869 }
 870
 871 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
 872 {
 873         struct vop *vop = to_vop(crtc);
 874
 875         reinit_completion(&vop->wait_update_complete);
 876         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
 877 }
 878
 879 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
 880                                            struct drm_file *file_priv)
 881 {
 882         struct drm_device *drm = crtc->dev;
 883         struct vop *vop = to_vop(crtc);
 884         struct drm_pending_vblank_event *e;
 885         unsigned long flags;
 886
 887         spin_lock_irqsave(&drm->event_lock, flags);
 888         e = vop->event;
 889         if (e && e->base.file_priv == file_priv) {
 890                 vop->event = NULL;
 891
 892                 e->base.destroy(&e->base);
 893                 file_priv->event_space += sizeof(e->event);
 894         }
 895         spin_unlock_irqrestore(&drm->event_lock, flags);
 896 }
 897
 898 static const struct rockchip_crtc_funcs private_crtc_funcs = {
 899         .enable_vblank = vop_crtc_enable_vblank,
 900         .disable_vblank = vop_crtc_disable_vblank,
 901         .wait_for_update = vop_crtc_wait_for_update,
 902         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
 903 };
 904
 905 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
 906                                 const struct drm_display_mode *mode,
 907                                 struct drm_display_mode *adjusted_mode)
 908 {
 909         struct vop *vop = to_vop(crtc);
 910
 911         adjusted_mode->clock =
 912                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
 913
 914         return true;
 915 }
 916
 917 static void vop_crtc_enable(struct drm_crtc *crtc)
 918 {
 919         struct vop *vop = to_vop(crtc);
 920         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
 921         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
 922         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
 923         u16 hdisplay = adjusted_mode->hdisplay;
 924         u16 htotal = adjusted_mode->htotal;
 925         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
 926         u16 hact_end = hact_st + hdisplay;
 927         u16 vdisplay = adjusted_mode->vdisplay;
 928         u16 vtotal = adjusted_mode->vtotal;
 929         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
 930         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
 931         u16 vact_end = vact_st + vdisplay;
 932         uint32_t val;
 933
 934         vop_enable(crtc);
 935         /*
 936          * If dclk rate is zero, mean that scanout is stop,
 937          * we don't need wait any more.
 938          */
 939         if (clk_get_rate(vop->dclk)) {
 940                 /*
 941                  * Rk3288 vop timing register is immediately, when configure
 942                  * display timing on display time, may cause tearing.
 943                  *
 944                  * Vop standby will take effect at end of current frame,
 945                  * if dsp hold valid irq happen, it means standby complete.
 946                  *
 947                  * mode set:
 948                  *    standby and wait complete --> |----
 949                  *                                  | display time
 950                  *                                  |----
 951                  *                                  |---> dsp hold irq
 952                  *     configure display timing --> |
 953                  *         standby exit             |
 954                  *                                  | new frame start.
 955                  */
 956
 957                 reinit_completion(&vop->dsp_hold_completion);
 958                 vop_dsp_hold_valid_irq_enable(vop);
 959
 960                 spin_lock(&vop->reg_lock);
 961
 962                 VOP_CTRL_SET(vop, standby, 1);
 963
 964                 spin_unlock(&vop->reg_lock);
 965
 966                 wait_for_completion(&vop->dsp_hold_completion);
 967
 968                 vop_dsp_hold_valid_irq_disable(vop);
 969         }
 970
 971         val = 0x8;
 972         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
 973         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
 974         VOP_CTRL_SET(vop, pin_pol, val);
 975         switch (s->output_type) {
 976         case DRM_MODE_CONNECTOR_LVDS:
 977                 VOP_CTRL_SET(vop, rgb_en, 1);
 978                 break;
 979         case DRM_MODE_CONNECTOR_eDP:
 980                 VOP_CTRL_SET(vop, edp_en, 1);
 981                 break;
 982         case DRM_MODE_CONNECTOR_HDMIA:
 983                 VOP_CTRL_SET(vop, hdmi_en, 1);
 984                 break;
 985         case DRM_MODE_CONNECTOR_DSI:
 986                 VOP_CTRL_SET(vop, mipi_en, 1);
 987                 break;
 988         default:
 989                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
 990         }
 991         VOP_CTRL_SET(vop, out_mode, s->output_mode);
 992
 993         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
 994         val = hact_st << 16;
 995         val |= hact_end;
 996         VOP_CTRL_SET(vop, hact_st_end, val);
 997         VOP_CTRL_SET(vop, hpost_st_end, val);
 998
 999         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1000         val = vact_st << 16;
1001         val |= vact_end;
1002         VOP_CTRL_SET(vop, vact_st_end, val);
1003         VOP_CTRL_SET(vop, vpost_st_end, val);
1004
1005         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1006
1007         VOP_CTRL_SET(vop, standby, 0);
1008 }
1009
1010 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1011                                   struct drm_crtc_state *old_crtc_state)
1012 {
1013         struct vop *vop = to_vop(crtc);
1014
1015         if (WARN_ON(!vop->is_enabled))
1016                 return;
1017
1018         spin_lock(&vop->reg_lock);
1019
1020         vop_cfg_done(vop);
1021
1022         spin_unlock(&vop->reg_lock);
1023 }
1024
1025 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1026                                   struct drm_crtc_state *old_crtc_state)
1027 {
1028         struct vop *vop = to_vop(crtc);
1029
1030         if (crtc->state->event) {
1031                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1032
1033                 vop->event = crtc->state->event;
1034                 crtc->state->event = NULL;
1035         }
1036 }
1037
1038 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1039         .enable = vop_crtc_enable,
1040         .disable = vop_crtc_disable,
1041         .mode_fixup = vop_crtc_mode_fixup,
1042         .atomic_flush = vop_crtc_atomic_flush,
1043         .atomic_begin = vop_crtc_atomic_begin,
1044 };
1045
1046 static void vop_crtc_destroy(struct drm_crtc *crtc)
1047 {
1048         drm_crtc_cleanup(crtc);
1049 }
1050
1051 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1052 {
1053         struct rockchip_crtc_state *rockchip_state;
1054
1055         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1056         if (!rockchip_state)
1057                 return NULL;
1058
1059         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1060         return &rockchip_state->base;
1061 }
1062
1063 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1064                                    struct drm_crtc_state *state)
1065 {
1066         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1067
1068         __drm_atomic_helper_crtc_destroy_state(&s->base);
1069         kfree(s);
1070 }
1071
1072 static const struct drm_crtc_funcs vop_crtc_funcs = {
1073         .set_config = drm_atomic_helper_set_config,
1074         .page_flip = drm_atomic_helper_page_flip,
1075         .destroy = vop_crtc_destroy,
1076         .reset = drm_atomic_helper_crtc_reset,
1077         .atomic_duplicate_state = vop_crtc_duplicate_state,
1078         .atomic_destroy_state = vop_crtc_destroy_state,
1079 };
1080
1081 static bool vop_win_pending_is_complete(struct vop_win *vop_win)
1082 {
1083         struct drm_plane *plane = &vop_win->base;
1084         struct vop_plane_state *state = to_vop_plane_state(plane->state);
1085         dma_addr_t yrgb_mst;
1086
1087         if (!state->enable)
1088                 return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0;
1089
1090         yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
1091
1092         return yrgb_mst == state->yrgb_mst;
1093 }
1094
1095 static void vop_handle_vblank(struct vop *vop)
1096 {
1097         struct drm_device *drm = vop->drm_dev;
1098         struct drm_crtc *crtc = &vop->crtc;
1099         unsigned long flags;
1100         int i;
1101
1102         for (i = 0; i < vop->data->win_size; i++) {
1103                 if (!vop_win_pending_is_complete(&vop->win[i]))
1104                         return;
1105         }
1106
1107         if (vop->event) {
1108                 spin_lock_irqsave(&drm->event_lock, flags);
1109
1110                 drm_crtc_send_vblank_event(crtc, vop->event);
1111                 drm_crtc_vblank_put(crtc);
1112                 vop->event = NULL;
1113
1114                 spin_unlock_irqrestore(&drm->event_lock, flags);
1115         }
1116         if (!completion_done(&vop->wait_update_complete))
1117                 complete(&vop->wait_update_complete);
1118 }
1119
1120 static irqreturn_t vop_isr(int irq, void *data)
1121 {
1122         struct vop *vop = data;
1123         struct drm_crtc *crtc = &vop->crtc;
1124         uint32_t active_irqs;
1125         unsigned long flags;
1126         int ret = IRQ_NONE;
1127
1128         /*
1129          * interrupt register has interrupt status, enable and clear bits, we
1130          * must hold irq_lock to avoid a race with enable/disable_vblank().
1131         */
1132         spin_lock_irqsave(&vop->irq_lock, flags);
1133
1134         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1135         /* Clear all active interrupt sources */
1136         if (active_irqs)
1137                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1138
1139         spin_unlock_irqrestore(&vop->irq_lock, flags);
1140
1141         /* This is expected for vop iommu irqs, since the irq is shared */
1142         if (!active_irqs)
1143                 return IRQ_NONE;
1144
1145         if (active_irqs & DSP_HOLD_VALID_INTR) {
1146                 complete(&vop->dsp_hold_completion);
1147                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1148                 ret = IRQ_HANDLED;
1149         }
1150
1151         if (active_irqs & FS_INTR) {
1152                 drm_crtc_handle_vblank(crtc);
1153                 vop_handle_vblank(vop);
1154                 active_irqs &= ~FS_INTR;
1155                 ret = IRQ_HANDLED;
1156         }
1157
1158         /* Unhandled irqs are spurious. */
1159         if (active_irqs)
1160                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1161
1162         return ret;
1163 }
1164
1165 static int vop_create_crtc(struct vop *vop)
1166 {
1167         const struct vop_data *vop_data = vop->data;
1168         struct device *dev = vop->dev;
1169         struct drm_device *drm_dev = vop->drm_dev;
1170         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1171         struct drm_crtc *crtc = &vop->crtc;
1172         struct device_node *port;
1173         int ret;
1174         int i;
1175
1176         /*
1177          * Create drm_plane for primary and cursor planes first, since we need
1178          * to pass them to drm_crtc_init_with_planes, which sets the
1179          * "possible_crtcs" to the newly initialized crtc.
1180          */
1181         for (i = 0; i < vop_data->win_size; i++) {
1182                 struct vop_win *vop_win = &vop->win[i];
1183                 const struct vop_win_data *win_data = vop_win->data;
1184
1185                 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1186                     win_data->type != DRM_PLANE_TYPE_CURSOR)
1187                         continue;
1188
1189                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1190                                                0, &vop_plane_funcs,
1191                                                win_data->phy->data_formats,
1192                                                win_data->phy->nformats,
1193                                                win_data->type, NULL);
1194                 if (ret) {
1195                         DRM_ERROR("failed to initialize plane\n");
1196                         goto err_cleanup_planes;
1197                 }
1198
1199                 plane = &vop_win->base;
1200                 drm_plane_helper_add(plane, &plane_helper_funcs);
1201                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1202                         primary = plane;
1203                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1204                         cursor = plane;
1205         }
1206
1207         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1208                                         &vop_crtc_funcs, NULL);
1209         if (ret)
1210                 goto err_cleanup_planes;
1211
1212         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1213
1214         /*
1215          * Create drm_planes for overlay windows with possible_crtcs restricted
1216          * to the newly created crtc.
1217          */
1218         for (i = 0; i < vop_data->win_size; i++) {
1219                 struct vop_win *vop_win = &vop->win[i];
1220                 const struct vop_win_data *win_data = vop_win->data;
1221                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1222
1223                 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1224                         continue;
1225
1226                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1227                                                possible_crtcs,
1228                                                &vop_plane_funcs,
1229                                                win_data->phy->data_formats,
1230                                                win_data->phy->nformats,
1231                                                win_data->type, NULL);
1232                 if (ret) {
1233                         DRM_ERROR("failed to initialize overlay plane\n");
1234                         goto err_cleanup_crtc;
1235                 }
1236                 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1237         }
1238
1239         port = of_get_child_by_name(dev->of_node, "port");
1240         if (!port) {
1241                 DRM_ERROR("no port node found in %s\n",
1242                           dev->of_node->full_name);
1243                 ret = -ENOENT;
1244                 goto err_cleanup_crtc;
1245         }
1246
1247         init_completion(&vop->dsp_hold_completion);
1248         init_completion(&vop->wait_update_complete);
1249         crtc->port = port;
1250         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1251
1252         return 0;
1253
1254 err_cleanup_crtc:
1255         drm_crtc_cleanup(crtc);
1256 err_cleanup_planes:
1257         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1258                                  head)
1259                 drm_plane_cleanup(plane);
1260         return ret;
1261 }
1262
1263 static void vop_destroy_crtc(struct vop *vop)
1264 {
1265         struct drm_crtc *crtc = &vop->crtc;
1266         struct drm_device *drm_dev = vop->drm_dev;
1267         struct drm_plane *plane, *tmp;
1268
1269         rockchip_unregister_crtc_funcs(crtc);
1270         of_node_put(crtc->port);
1271
1272         /*
1273          * We need to cleanup the planes now.  Why?
1274          *
1275          * The planes are "&vop->win[i].base".  That means the memory is
1276          * all part of the big "struct vop" chunk of memory.  That memory
1277          * was devm allocated and associated with this component.  We need to
1278          * free it ourselves before vop_unbind() finishes.
1279          */
1280         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1281                                  head)
1282                 vop_plane_destroy(plane);
1283
1284         /*
1285          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1286          * references the CRTC.
1287          */
1288         drm_crtc_cleanup(crtc);
1289 }
1290
1291 static int vop_initial(struct vop *vop)
1292 {
1293         const struct vop_data *vop_data = vop->data;
1294         const struct vop_reg_data *init_table = vop_data->init_table;
1295         struct reset_control *ahb_rst;
1296         int i, ret;
1297
1298         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1299         if (IS_ERR(vop->hclk)) {
1300                 dev_err(vop->dev, "failed to get hclk source\n");
1301                 return PTR_ERR(vop->hclk);
1302         }
1303         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1304         if (IS_ERR(vop->aclk)) {
1305                 dev_err(vop->dev, "failed to get aclk source\n");
1306                 return PTR_ERR(vop->aclk);
1307         }
1308         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1309         if (IS_ERR(vop->dclk)) {
1310                 dev_err(vop->dev, "failed to get dclk source\n");
1311                 return PTR_ERR(vop->dclk);
1312         }
1313
1314         ret = clk_prepare(vop->dclk);
1315         if (ret < 0) {
1316                 dev_err(vop->dev, "failed to prepare dclk\n");
1317                 return ret;
1318         }
1319
1320         /* Enable both the hclk and aclk to setup the vop */
1321         ret = clk_prepare_enable(vop->hclk);
1322         if (ret < 0) {
1323                 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1324                 goto err_unprepare_dclk;
1325         }
1326
1327         ret = clk_prepare_enable(vop->aclk);
1328         if (ret < 0) {
1329                 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1330                 goto err_disable_hclk;
1331         }
1332
1333         /*
1334          * do hclk_reset, reset all vop registers.
1335          */
1336         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1337         if (IS_ERR(ahb_rst)) {
1338                 dev_err(vop->dev, "failed to get ahb reset\n");
1339                 ret = PTR_ERR(ahb_rst);
1340                 goto err_disable_aclk;
1341         }
1342         reset_control_assert(ahb_rst);
1343         usleep_range(10, 20);
1344         reset_control_deassert(ahb_rst);
1345
1346         memcpy(vop->regsbak, vop->regs, vop->len);
1347
1348         for (i = 0; i < vop_data->table_size; i++)
1349                 vop_writel(vop, init_table[i].offset, init_table[i].value);
1350
1351         for (i = 0; i < vop_data->win_size; i++) {
1352                 const struct vop_win_data *win = &vop_data->win[i];
1353
1354                 VOP_WIN_SET(vop, win, enable, 0);
1355         }
1356
1357         vop_cfg_done(vop);
1358
1359         /*
1360          * do dclk_reset, let all config take affect.
1361          */
1362         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1363         if (IS_ERR(vop->dclk_rst)) {
1364                 dev_err(vop->dev, "failed to get dclk reset\n");
1365                 ret = PTR_ERR(vop->dclk_rst);
1366                 goto err_disable_aclk;
1367         }
1368         reset_control_assert(vop->dclk_rst);
1369         usleep_range(10, 20);
1370         reset_control_deassert(vop->dclk_rst);
1371
1372         clk_disable(vop->hclk);
1373         clk_disable(vop->aclk);
1374
1375         vop->is_enabled = false;
1376
1377         return 0;
1378
1379 err_disable_aclk:
1380         clk_disable_unprepare(vop->aclk);
1381 err_disable_hclk:
1382         clk_disable_unprepare(vop->hclk);
1383 err_unprepare_dclk:
1384         clk_unprepare(vop->dclk);
1385         return ret;
1386 }
1387
1388 /*
1389  * Initialize the vop->win array elements.
1390  */
1391 static void vop_win_init(struct vop *vop)
1392 {
1393         const struct vop_data *vop_data = vop->data;
1394         unsigned int i;
1395
1396         for (i = 0; i < vop_data->win_size; i++) {
1397                 struct vop_win *vop_win = &vop->win[i];
1398                 const struct vop_win_data *win_data = &vop_data->win[i];
1399
1400                 vop_win->data = win_data;
1401                 vop_win->vop = vop;
1402         }
1403 }
1404
1405 static int vop_bind(struct device *dev, struct device *master, void *data)
1406 {
1407         struct platform_device *pdev = to_platform_device(dev);
1408         const struct vop_data *vop_data;
1409         struct drm_device *drm_dev = data;
1410         struct vop *vop;
1411         struct resource *res;
1412         size_t alloc_size;
1413         int ret, irq;
1414
1415         vop_data = of_device_get_match_data(dev);
1416         if (!vop_data)
1417                 return -ENODEV;
1418
1419         /* Allocate vop struct and its vop_win array */
1420         alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1421         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1422         if (!vop)
1423                 return -ENOMEM;
1424
1425         vop->dev = dev;
1426         vop->data = vop_data;
1427         vop->drm_dev = drm_dev;
1428         dev_set_drvdata(dev, vop);
1429
1430         vop_win_init(vop);
1431
1432         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1433         vop->len = resource_size(res);
1434         vop->regs = devm_ioremap_resource(dev, res);
1435         if (IS_ERR(vop->regs))
1436                 return PTR_ERR(vop->regs);
1437
1438         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1439         if (!vop->regsbak)
1440                 return -ENOMEM;
1441
1442         ret = vop_initial(vop);
1443         if (ret < 0) {
1444                 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1445                 return ret;
1446         }
1447
1448         irq = platform_get_irq(pdev, 0);
1449         if (irq < 0) {
1450                 dev_err(dev, "cannot find irq for vop\n");
1451                 return irq;
1452         }
1453         vop->irq = (unsigned int)irq;
1454
1455         spin_lock_init(&vop->reg_lock);
1456         spin_lock_init(&vop->irq_lock);
1457
1458         mutex_init(&vop->vsync_mutex);
1459
1460         ret = devm_request_irq(dev, vop->irq, vop_isr,
1461                                IRQF_SHARED, dev_name(dev), vop);
1462         if (ret)
1463                 return ret;
1464
1465         /* IRQ is initially disabled; it gets enabled in power_on */
1466         disable_irq(vop->irq);
1467
1468         ret = vop_create_crtc(vop);
1469         if (ret)
1470                 return ret;
1471
1472         pm_runtime_enable(&pdev->dev);
1473         return 0;
1474 }
1475
1476 static void vop_unbind(struct device *dev, struct device *master, void *data)
1477 {
1478         struct vop *vop = dev_get_drvdata(dev);
1479
1480         pm_runtime_disable(dev);
1481         vop_destroy_crtc(vop);
1482 }
1483
1484 const struct component_ops vop_component_ops = {
1485         .bind = vop_bind,
1486         .unbind = vop_unbind,
1487 };
1488 EXPORT_SYMBOL_GPL(vop_component_ops);