drivers/gpu/drm/tegra/dc.c

   1 /*
   2  * Copyright (C) 2012 Avionic Design GmbH
   3  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/debugfs.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/platform_device.h>
  15
  16 #include <mach/clk.h>
  17
  18 #include "drm.h"
  19 #include "dc.h"
  20
  21 struct tegra_plane {
  22         struct drm_plane base;
  23         unsigned int index;
  24 };
  25
  26 static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
  27 {
  28         return container_of(plane, struct tegra_plane, base);
  29 }
  30
  31 static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
  32                               struct drm_framebuffer *fb, int crtc_x,
  33                               int crtc_y, unsigned int crtc_w,
  34                               unsigned int crtc_h, uint32_t src_x,
  35                               uint32_t src_y, uint32_t src_w, uint32_t src_h)
  36 {
  37         struct tegra_plane *p = to_tegra_plane(plane);
  38         struct tegra_dc *dc = to_tegra_dc(crtc);
  39         struct tegra_dc_window window;
  40         unsigned int i;
  41
  42         memset(&window, 0, sizeof(window));
  43         window.src.x = src_x >> 16;
  44         window.src.y = src_y >> 16;
  45         window.src.w = src_w >> 16;
  46         window.src.h = src_h >> 16;
  47         window.dst.x = crtc_x;
  48         window.dst.y = crtc_y;
  49         window.dst.w = crtc_w;
  50         window.dst.h = crtc_h;
  51         window.format = tegra_dc_format(fb->pixel_format);
  52         window.bits_per_pixel = fb->bits_per_pixel;
  53
  54         for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
  55                 struct drm_gem_cma_object *gem = drm_fb_cma_get_gem_obj(fb, i);
  56
  57                 window.base[i] = gem->paddr + fb->offsets[i];
  58
  59                 /*
  60                  * Tegra doesn't support different strides for U and V planes
  61                  * so we display a warning if the user tries to display a
  62                  * framebuffer with such a configuration.
  63                  */
  64                 if (i >= 2) {
  65                         if (fb->pitches[i] != window.stride[1])
  66                                 DRM_ERROR("unsupported UV-plane configuration\n");
  67                 } else {
  68                         window.stride[i] = fb->pitches[i];
  69                 }
  70         }
  71
  72         return tegra_dc_setup_window(dc, p->index, &window);
  73 }
  74
  75 static int tegra_plane_disable(struct drm_plane *plane)
  76 {
  77         struct tegra_dc *dc = to_tegra_dc(plane->crtc);
  78         struct tegra_plane *p = to_tegra_plane(plane);
  79         unsigned long value;
  80
  81         value = WINDOW_A_SELECT << p->index;
  82         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
  83
  84         value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
  85         value &= ~WIN_ENABLE;
  86         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
  87
  88         tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL);
  89         tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL);
  90
  91         return 0;
  92 }
  93
  94 static void tegra_plane_destroy(struct drm_plane *plane)
  95 {
  96         tegra_plane_disable(plane);
  97         drm_plane_cleanup(plane);
  98 }
  99
 100 static const struct drm_plane_funcs tegra_plane_funcs = {
 101         .update_plane = tegra_plane_update,
 102         .disable_plane = tegra_plane_disable,
 103         .destroy = tegra_plane_destroy,
 104 };
 105
 106 static const uint32_t plane_formats[] = {
 107         DRM_FORMAT_XRGB8888,
 108         DRM_FORMAT_UYVY,
 109         DRM_FORMAT_YUV420,
 110         DRM_FORMAT_YUV422,
 111 };
 112
 113 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
 114 {
 115         unsigned int i;
 116         int err = 0;
 117
 118         for (i = 0; i < 2; i++) {
 119                 struct tegra_plane *plane;
 120
 121                 plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
 122                 if (!plane)
 123                         return -ENOMEM;
 124
 125                 plane->index = 1 + i;
 126
 127                 err = drm_plane_init(drm, &plane->base, 1 << dc->pipe,
 128                                      &tegra_plane_funcs, plane_formats,
 129                                      ARRAY_SIZE(plane_formats), false);
 130                 if (err < 0)
 131                         return err;
 132         }
 133
 134         return 0;
 135 }
 136
 137 static const struct drm_crtc_funcs tegra_crtc_funcs = {
 138         .set_config = drm_crtc_helper_set_config,
 139         .destroy = drm_crtc_cleanup,
 140 };
 141
 142 static void tegra_crtc_disable(struct drm_crtc *crtc)
 143 {
 144         struct drm_device *drm = crtc->dev;
 145         struct drm_plane *plane;
 146
 147         list_for_each_entry(plane, &drm->mode_config.plane_list, head) {
 148                 if (plane->crtc == crtc) {
 149                         tegra_plane_disable(plane);
 150                         plane->crtc = NULL;
 151
 152                         if (plane->fb) {
 153                                 drm_framebuffer_unreference(plane->fb);
 154                                 plane->fb = NULL;
 155                         }
 156                 }
 157         }
 158 }
 159
 160 static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
 161                                   const struct drm_display_mode *mode,
 162                                   struct drm_display_mode *adjusted)
 163 {
 164         return true;
 165 }
 166
 167 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
 168                                   unsigned int bpp)
 169 {
 170         fixed20_12 outf = dfixed_init(out);
 171         fixed20_12 inf = dfixed_init(in);
 172         u32 dda_inc;
 173         int max;
 174
 175         if (v)
 176                 max = 15;
 177         else {
 178                 switch (bpp) {
 179                 case 2:
 180                         max = 8;
 181                         break;
 182
 183                 default:
 184                         WARN_ON_ONCE(1);
 185                         /* fallthrough */
 186                 case 4:
 187                         max = 4;
 188                         break;
 189                 }
 190         }
 191
 192         outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
 193         inf.full -= dfixed_const(1);
 194
 195         dda_inc = dfixed_div(inf, outf);
 196         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
 197
 198         return dda_inc;
 199 }
 200
 201 static inline u32 compute_initial_dda(unsigned int in)
 202 {
 203         fixed20_12 inf = dfixed_init(in);
 204         return dfixed_frac(inf);
 205 }
 206
 207 static int tegra_dc_set_timings(struct tegra_dc *dc,
 208                                 struct drm_display_mode *mode)
 209 {
 210         /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */
 211         unsigned int h_ref_to_sync = 0;
 212         unsigned int v_ref_to_sync = 0;
 213         unsigned long value;
 214
 215         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
 216
 217         value = (v_ref_to_sync << 16) | h_ref_to_sync;
 218         tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
 219
 220         value = ((mode->vsync_end - mode->vsync_start) << 16) |
 221                 ((mode->hsync_end - mode->hsync_start) <<  0);
 222         tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
 223
 224         value = ((mode->vtotal - mode->vsync_end) << 16) |
 225                 ((mode->htotal - mode->hsync_end) <<  0);
 226         tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
 227
 228         value = ((mode->vsync_start - mode->vdisplay) << 16) |
 229                 ((mode->hsync_start - mode->hdisplay) <<  0);
 230         tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
 231
 232         value = (mode->vdisplay << 16) | mode->hdisplay;
 233         tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
 234
 235         return 0;
 236 }
 237
 238 static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
 239                                 struct drm_display_mode *mode,
 240                                 unsigned long *div)
 241 {
 242         unsigned long pclk = mode->clock * 1000, rate;
 243         struct tegra_dc *dc = to_tegra_dc(crtc);
 244         struct tegra_output *output = NULL;
 245         struct drm_encoder *encoder;
 246         long err;
 247
 248         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
 249                 if (encoder->crtc == crtc) {
 250                         output = encoder_to_output(encoder);
 251                         break;
 252                 }
 253
 254         if (!output)
 255                 return -ENODEV;
 256
 257         /*
 258          * This assumes that the display controller will divide its parent
 259          * clock by 2 to generate the pixel clock.
 260          */
 261         err = tegra_output_setup_clock(output, dc->clk, pclk * 2);
 262         if (err < 0) {
 263                 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
 264                 return err;
 265         }
 266
 267         rate = clk_get_rate(dc->clk);
 268         *div = (rate * 2 / pclk) - 2;
 269
 270         DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate, *div);
 271
 272         return 0;
 273 }
 274
 275 static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
 276 {
 277         switch (format) {
 278         case WIN_COLOR_DEPTH_YCbCr422:
 279         case WIN_COLOR_DEPTH_YUV422:
 280                 if (planar)
 281                         *planar = false;
 282
 283                 return true;
 284
 285         case WIN_COLOR_DEPTH_YCbCr420P:
 286         case WIN_COLOR_DEPTH_YUV420P:
 287         case WIN_COLOR_DEPTH_YCbCr422P:
 288         case WIN_COLOR_DEPTH_YUV422P:
 289         case WIN_COLOR_DEPTH_YCbCr422R:
 290         case WIN_COLOR_DEPTH_YUV422R:
 291         case WIN_COLOR_DEPTH_YCbCr422RA:
 292         case WIN_COLOR_DEPTH_YUV422RA:
 293                 if (planar)
 294                         *planar = true;
 295
 296                 return true;
 297         }
 298
 299         return false;
 300 }
 301
 302 int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
 303                           const struct tegra_dc_window *window)
 304 {
 305         unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
 306         unsigned long value;
 307         bool yuv, planar;
 308
 309         /*
 310          * For YUV planar modes, the number of bytes per pixel takes into
 311          * account only the luma component and therefore is 1.
 312          */
 313         yuv = tegra_dc_format_is_yuv(window->format, &planar);
 314         if (!yuv)
 315                 bpp = window->bits_per_pixel / 8;
 316         else
 317                 bpp = planar ? 1 : 2;
 318
 319         value = WINDOW_A_SELECT << index;
 320         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 321
 322         tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
 323         tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
 324
 325         value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
 326         tegra_dc_writel(dc, value, DC_WIN_POSITION);
 327
 328         value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
 329         tegra_dc_writel(dc, value, DC_WIN_SIZE);
 330
 331         h_offset = window->src.x * bpp;
 332         v_offset = window->src.y;
 333         h_size = window->src.w * bpp;
 334         v_size = window->src.h;
 335
 336         value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
 337         tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
 338
 339         /*
 340          * For DDA computations the number of bytes per pixel for YUV planar
 341          * modes needs to take into account all Y, U and V components.
 342          */
 343         if (yuv && planar)
 344                 bpp = 2;
 345
 346         h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
 347         v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
 348
 349         value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
 350         tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
 351
 352         h_dda = compute_initial_dda(window->src.x);
 353         v_dda = compute_initial_dda(window->src.y);
 354
 355         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
 356         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
 357
 358         tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
 359         tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
 360
 361         tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
 362
 363         if (yuv && planar) {
 364                 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
 365                 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
 366                 value = window->stride[1] << 16 | window->stride[0];
 367                 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
 368         } else {
 369                 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
 370         }
 371
 372         tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
 373         tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
 374
 375         value = WIN_ENABLE;
 376
 377         if (yuv) {
 378                 /* setup default colorspace conversion coefficients */
 379                 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
 380                 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
 381                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
 382                 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
 383                 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
 384                 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
 385                 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
 386                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
 387
 388                 value |= CSC_ENABLE;
 389         } else if (bpp < 24) {
 390                 value |= COLOR_EXPAND;
 391         }
 392
 393         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
 394
 395         /*
 396          * Disable blending and assume Window A is the bottom-most window,
 397          * Window C is the top-most window and Window B is in the middle.
 398          */
 399         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
 400         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
 401
 402         switch (index) {
 403         case 0:
 404                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
 405                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
 406                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
 407                 break;
 408
 409         case 1:
 410                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
 411                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
 412                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
 413                 break;
 414
 415         case 2:
 416                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
 417                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
 418                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
 419                 break;
 420         }
 421
 422         tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL);
 423         tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL);
 424
 425         return 0;
 426 }
 427
 428 unsigned int tegra_dc_format(uint32_t format)
 429 {
 430         switch (format) {
 431         case DRM_FORMAT_XRGB8888:
 432                 return WIN_COLOR_DEPTH_B8G8R8A8;
 433
 434         case DRM_FORMAT_RGB565:
 435                 return WIN_COLOR_DEPTH_B5G6R5;
 436
 437         case DRM_FORMAT_UYVY:
 438                 return WIN_COLOR_DEPTH_YCbCr422;
 439
 440         case DRM_FORMAT_YUV420:
 441                 return WIN_COLOR_DEPTH_YCbCr420P;
 442
 443         case DRM_FORMAT_YUV422:
 444                 return WIN_COLOR_DEPTH_YCbCr422P;
 445
 446         default:
 447                 break;
 448         }
 449
 450         WARN(1, "unsupported pixel format %u, using default\n", format);
 451         return WIN_COLOR_DEPTH_B8G8R8A8;
 452 }
 453
 454 static int tegra_crtc_mode_set(struct drm_crtc *crtc,
 455                                struct drm_display_mode *mode,
 456                                struct drm_display_mode *adjusted,
 457                                int x, int y, struct drm_framebuffer *old_fb)
 458 {
 459         struct drm_gem_cma_object *gem = drm_fb_cma_get_gem_obj(crtc->fb, 0);
 460         struct tegra_dc *dc = to_tegra_dc(crtc);
 461         struct tegra_dc_window window;
 462         unsigned long div, value;
 463         int err;
 464
 465         err = tegra_crtc_setup_clk(crtc, mode, &div);
 466         if (err) {
 467                 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
 468                 return err;
 469         }
 470
 471         /* program display mode */
 472         tegra_dc_set_timings(dc, mode);
 473
 474         value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
 475         tegra_dc_writel(dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
 476
 477         value = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY(1));
 478         value &= ~LVS_OUTPUT_POLARITY_LOW;
 479         value &= ~LHS_OUTPUT_POLARITY_LOW;
 480         tegra_dc_writel(dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
 481
 482         value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
 483                 DISP_ORDER_RED_BLUE;
 484         tegra_dc_writel(dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
 485
 486         tegra_dc_writel(dc, 0x00010001, DC_DISP_SHIFT_CLOCK_OPTIONS);
 487
 488         value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
 489         tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
 490
 491         /* setup window parameters */
 492         memset(&window, 0, sizeof(window));
 493         window.src.x = 0;
 494         window.src.y = 0;
 495         window.src.w = mode->hdisplay;
 496         window.src.h = mode->vdisplay;
 497         window.dst.x = 0;
 498         window.dst.y = 0;
 499         window.dst.w = mode->hdisplay;
 500         window.dst.h = mode->vdisplay;
 501         window.format = tegra_dc_format(crtc->fb->pixel_format);
 502         window.bits_per_pixel = crtc->fb->bits_per_pixel;
 503         window.stride[0] = crtc->fb->pitches[0];
 504         window.base[0] = gem->paddr;
 505
 506         err = tegra_dc_setup_window(dc, 0, &window);
 507         if (err < 0)
 508                 dev_err(dc->dev, "failed to enable root plane\n");
 509
 510         return 0;
 511 }
 512
 513 static void tegra_crtc_prepare(struct drm_crtc *crtc)
 514 {
 515         struct tegra_dc *dc = to_tegra_dc(crtc);
 516         unsigned int syncpt;
 517         unsigned long value;
 518
 519         /* hardware initialization */
 520         tegra_periph_reset_deassert(dc->clk);
 521         usleep_range(10000, 20000);
 522
 523         if (dc->pipe)
 524                 syncpt = SYNCPT_VBLANK1;
 525         else
 526                 syncpt = SYNCPT_VBLANK0;
 527
 528         /* initialize display controller */
 529         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
 530         tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
 531
 532         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
 533         tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
 534
 535         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
 536                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
 537         tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
 538
 539         value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
 540                 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
 541         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
 542
 543         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
 544         value |= DISP_CTRL_MODE_C_DISPLAY;
 545         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
 546
 547         /* initialize timer */
 548         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
 549                 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
 550         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
 551
 552         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
 553                 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
 554         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
 555
 556         value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
 557         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 558
 559         value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
 560         tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
 561 }
 562
 563 static void tegra_crtc_commit(struct drm_crtc *crtc)
 564 {
 565         struct tegra_dc *dc = to_tegra_dc(crtc);
 566         unsigned long update_mask;
 567         unsigned long value;
 568
 569         update_mask = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
 570
 571         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
 572
 573         value = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
 574         value |= FRAME_END_INT;
 575         tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
 576
 577         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
 578         value |= FRAME_END_INT;
 579         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 580
 581         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
 582 }
 583
 584 static void tegra_crtc_load_lut(struct drm_crtc *crtc)
 585 {
 586 }
 587
 588 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
 589         .disable = tegra_crtc_disable,
 590         .mode_fixup = tegra_crtc_mode_fixup,
 591         .mode_set = tegra_crtc_mode_set,
 592         .prepare = tegra_crtc_prepare,
 593         .commit = tegra_crtc_commit,
 594         .load_lut = tegra_crtc_load_lut,
 595 };
 596
 597 static irqreturn_t tegra_drm_irq(int irq, void *data)
 598 {
 599         struct tegra_dc *dc = data;
 600         unsigned long status;
 601
 602         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
 603         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
 604
 605         if (status & FRAME_END_INT) {
 606                 /*
 607                 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
 608                 */
 609         }
 610
 611         if (status & VBLANK_INT) {
 612                 /*
 613                 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
 614                 */
 615                 drm_handle_vblank(dc->base.dev, dc->pipe);
 616         }
 617
 618         if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
 619                 /*
 620                 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
 621                 */
 622         }
 623
 624         return IRQ_HANDLED;
 625 }
 626
 627 static int tegra_dc_show_regs(struct seq_file *s, void *data)
 628 {
 629         struct drm_info_node *node = s->private;
 630         struct tegra_dc *dc = node->info_ent->data;
 631
 632 #define DUMP_REG(name)                                          \
 633         seq_printf(s, "%-40s %#05x %08lx\n", #name, name,       \
 634                    tegra_dc_readl(dc, name))
 635
 636         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
 637         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
 638         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
 639         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
 640         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
 641         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
 642         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
 643         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
 644         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
 645         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
 646         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
 647         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
 648         DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
 649         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
 650         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
 651         DUMP_REG(DC_CMD_SIGNAL_RAISE);
 652         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
 653         DUMP_REG(DC_CMD_INT_STATUS);
 654         DUMP_REG(DC_CMD_INT_MASK);
 655         DUMP_REG(DC_CMD_INT_ENABLE);
 656         DUMP_REG(DC_CMD_INT_TYPE);
 657         DUMP_REG(DC_CMD_INT_POLARITY);
 658         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
 659         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
 660         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
 661         DUMP_REG(DC_CMD_STATE_ACCESS);
 662         DUMP_REG(DC_CMD_STATE_CONTROL);
 663         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
 664         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
 665         DUMP_REG(DC_COM_CRC_CONTROL);
 666         DUMP_REG(DC_COM_CRC_CHECKSUM);
 667         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
 668         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
 669         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
 670         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
 671         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
 672         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
 673         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
 674         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
 675         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
 676         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
 677         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
 678         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
 679         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
 680         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
 681         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
 682         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
 683         DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
 684         DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
 685         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
 686         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
 687         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
 688         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
 689         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
 690         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
 691         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
 692         DUMP_REG(DC_COM_PIN_MISC_CONTROL);
 693         DUMP_REG(DC_COM_PIN_PM0_CONTROL);
 694         DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
 695         DUMP_REG(DC_COM_PIN_PM1_CONTROL);
 696         DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
 697         DUMP_REG(DC_COM_SPI_CONTROL);
 698         DUMP_REG(DC_COM_SPI_START_BYTE);
 699         DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
 700         DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
 701         DUMP_REG(DC_COM_HSPI_CS_DC);
 702         DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
 703         DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
 704         DUMP_REG(DC_COM_GPIO_CTRL);
 705         DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
 706         DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
 707         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
 708         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
 709         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
 710         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
 711         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
 712         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
 713         DUMP_REG(DC_DISP_REF_TO_SYNC);
 714         DUMP_REG(DC_DISP_SYNC_WIDTH);
 715         DUMP_REG(DC_DISP_BACK_PORCH);
 716         DUMP_REG(DC_DISP_ACTIVE);
 717         DUMP_REG(DC_DISP_FRONT_PORCH);
 718         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
 719         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
 720         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
 721         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
 722         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
 723         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
 724         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
 725         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
 726         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
 727         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
 728         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
 729         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
 730         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
 731         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
 732         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
 733         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
 734         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
 735         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
 736         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
 737         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
 738         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
 739         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
 740         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
 741         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
 742         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
 743         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
 744         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
 745         DUMP_REG(DC_DISP_M0_CONTROL);
 746         DUMP_REG(DC_DISP_M1_CONTROL);
 747         DUMP_REG(DC_DISP_DI_CONTROL);
 748         DUMP_REG(DC_DISP_PP_CONTROL);
 749         DUMP_REG(DC_DISP_PP_SELECT_A);
 750         DUMP_REG(DC_DISP_PP_SELECT_B);
 751         DUMP_REG(DC_DISP_PP_SELECT_C);
 752         DUMP_REG(DC_DISP_PP_SELECT_D);
 753         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
 754         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
 755         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
 756         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
 757         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
 758         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
 759         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
 760         DUMP_REG(DC_DISP_BORDER_COLOR);
 761         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
 762         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
 763         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
 764         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
 765         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
 766         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
 767         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
 768         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
 769         DUMP_REG(DC_DISP_CURSOR_POSITION);
 770         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
 771         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
 772         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
 773         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
 774         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
 775         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
 776         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
 777         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
 778         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
 779         DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
 780         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
 781         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
 782         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
 783         DUMP_REG(DC_DISP_SD_CONTROL);
 784         DUMP_REG(DC_DISP_SD_CSC_COEFF);
 785         DUMP_REG(DC_DISP_SD_LUT(0));
 786         DUMP_REG(DC_DISP_SD_LUT(1));
 787         DUMP_REG(DC_DISP_SD_LUT(2));
 788         DUMP_REG(DC_DISP_SD_LUT(3));
 789         DUMP_REG(DC_DISP_SD_LUT(4));
 790         DUMP_REG(DC_DISP_SD_LUT(5));
 791         DUMP_REG(DC_DISP_SD_LUT(6));
 792         DUMP_REG(DC_DISP_SD_LUT(7));
 793         DUMP_REG(DC_DISP_SD_LUT(8));
 794         DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
 795         DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
 796         DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
 797         DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
 798         DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
 799         DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
 800         DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
 801         DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
 802         DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
 803         DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
 804         DUMP_REG(DC_DISP_SD_BL_TF(0));
 805         DUMP_REG(DC_DISP_SD_BL_TF(1));
 806         DUMP_REG(DC_DISP_SD_BL_TF(2));
 807         DUMP_REG(DC_DISP_SD_BL_TF(3));
 808         DUMP_REG(DC_DISP_SD_BL_CONTROL);
 809         DUMP_REG(DC_DISP_SD_HW_K_VALUES);
 810         DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
 811         DUMP_REG(DC_WIN_WIN_OPTIONS);
 812         DUMP_REG(DC_WIN_BYTE_SWAP);
 813         DUMP_REG(DC_WIN_BUFFER_CONTROL);
 814         DUMP_REG(DC_WIN_COLOR_DEPTH);
 815         DUMP_REG(DC_WIN_POSITION);
 816         DUMP_REG(DC_WIN_SIZE);
 817         DUMP_REG(DC_WIN_PRESCALED_SIZE);
 818         DUMP_REG(DC_WIN_H_INITIAL_DDA);
 819         DUMP_REG(DC_WIN_V_INITIAL_DDA);
 820         DUMP_REG(DC_WIN_DDA_INC);
 821         DUMP_REG(DC_WIN_LINE_STRIDE);
 822         DUMP_REG(DC_WIN_BUF_STRIDE);
 823         DUMP_REG(DC_WIN_UV_BUF_STRIDE);
 824         DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
 825         DUMP_REG(DC_WIN_DV_CONTROL);
 826         DUMP_REG(DC_WIN_BLEND_NOKEY);
 827         DUMP_REG(DC_WIN_BLEND_1WIN);
 828         DUMP_REG(DC_WIN_BLEND_2WIN_X);
 829         DUMP_REG(DC_WIN_BLEND_2WIN_Y);
 830         DUMP_REG(DC_WIN_BLEND_3WIN_XY);
 831         DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
 832         DUMP_REG(DC_WINBUF_START_ADDR);
 833         DUMP_REG(DC_WINBUF_START_ADDR_NS);
 834         DUMP_REG(DC_WINBUF_START_ADDR_U);
 835         DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
 836         DUMP_REG(DC_WINBUF_START_ADDR_V);
 837         DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
 838         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
 839         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
 840         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
 841         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
 842         DUMP_REG(DC_WINBUF_UFLOW_STATUS);
 843         DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
 844         DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
 845         DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
 846
 847 #undef DUMP_REG
 848
 849         return 0;
 850 }
 851
 852 static struct drm_info_list debugfs_files[] = {
 853         { "regs", tegra_dc_show_regs, 0, NULL },
 854 };
 855
 856 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
 857 {
 858         unsigned int i;
 859         char *name;
 860         int err;
 861
 862         name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
 863         dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
 864         kfree(name);
 865
 866         if (!dc->debugfs)
 867                 return -ENOMEM;
 868
 869         dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
 870                                     GFP_KERNEL);
 871         if (!dc->debugfs_files) {
 872                 err = -ENOMEM;
 873                 goto remove;
 874         }
 875
 876         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
 877                 dc->debugfs_files[i].data = dc;
 878
 879         err = drm_debugfs_create_files(dc->debugfs_files,
 880                                        ARRAY_SIZE(debugfs_files),
 881                                        dc->debugfs, minor);
 882         if (err < 0)
 883                 goto free;
 884
 885         dc->minor = minor;
 886
 887         return 0;
 888
 889 free:
 890         kfree(dc->debugfs_files);
 891         dc->debugfs_files = NULL;
 892 remove:
 893         debugfs_remove(dc->debugfs);
 894         dc->debugfs = NULL;
 895
 896         return err;
 897 }
 898
 899 static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
 900 {
 901         drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
 902                                  dc->minor);
 903         dc->minor = NULL;
 904
 905         kfree(dc->debugfs_files);
 906         dc->debugfs_files = NULL;
 907
 908         debugfs_remove(dc->debugfs);
 909         dc->debugfs = NULL;
 910
 911         return 0;
 912 }
 913
 914 static int tegra_dc_drm_init(struct host1x_client *client,
 915                              struct drm_device *drm)
 916 {
 917         struct tegra_dc *dc = host1x_client_to_dc(client);
 918         int err;
 919
 920         dc->pipe = drm->mode_config.num_crtc;
 921
 922         drm_crtc_init(drm, &dc->base, &tegra_crtc_funcs);
 923         drm_mode_crtc_set_gamma_size(&dc->base, 256);
 924         drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
 925
 926         err = tegra_dc_rgb_init(drm, dc);
 927         if (err < 0 && err != -ENODEV) {
 928                 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
 929                 return err;
 930         }
 931
 932         err = tegra_dc_add_planes(drm, dc);
 933         if (err < 0)
 934                 return err;
 935
 936         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
 937                 err = tegra_dc_debugfs_init(dc, drm->primary);
 938                 if (err < 0)
 939                         dev_err(dc->dev, "debugfs setup failed: %d\n", err);
 940         }
 941
 942         err = devm_request_irq(dc->dev, dc->irq, tegra_drm_irq, 0,
 943                                dev_name(dc->dev), dc);
 944         if (err < 0) {
 945                 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
 946                         err);
 947                 return err;
 948         }
 949
 950         return 0;
 951 }
 952
 953 static int tegra_dc_drm_exit(struct host1x_client *client)
 954 {
 955         struct tegra_dc *dc = host1x_client_to_dc(client);
 956         int err;
 957
 958         devm_free_irq(dc->dev, dc->irq, dc);
 959
 960         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
 961                 err = tegra_dc_debugfs_exit(dc);
 962                 if (err < 0)
 963                         dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
 964         }
 965
 966         err = tegra_dc_rgb_exit(dc);
 967         if (err) {
 968                 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
 969                 return err;
 970         }
 971
 972         return 0;
 973 }
 974
 975 static const struct host1x_client_ops dc_client_ops = {
 976         .drm_init = tegra_dc_drm_init,
 977         .drm_exit = tegra_dc_drm_exit,
 978 };
 979
 980 static int tegra_dc_probe(struct platform_device *pdev)
 981 {
 982         struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
 983         struct resource *regs;
 984         struct tegra_dc *dc;
 985         int err;
 986
 987         dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
 988         if (!dc)
 989                 return -ENOMEM;
 990
 991         INIT_LIST_HEAD(&dc->list);
 992         dc->dev = &pdev->dev;
 993
 994         dc->clk = devm_clk_get(&pdev->dev, NULL);
 995         if (IS_ERR(dc->clk)) {
 996                 dev_err(&pdev->dev, "failed to get clock\n");
 997                 return PTR_ERR(dc->clk);
 998         }
 999
1000         err = clk_prepare_enable(dc->clk);
1001         if (err < 0)
1002                 return err;
1003
1004         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1005         if (!regs) {
1006                 dev_err(&pdev->dev, "failed to get registers\n");
1007                 return -ENXIO;
1008         }
1009
1010         dc->regs = devm_request_and_ioremap(&pdev->dev, regs);
1011         if (!dc->regs) {
1012                 dev_err(&pdev->dev, "failed to remap registers\n");
1013                 return -ENXIO;
1014         }
1015
1016         dc->irq = platform_get_irq(pdev, 0);
1017         if (dc->irq < 0) {
1018                 dev_err(&pdev->dev, "failed to get IRQ\n");
1019                 return -ENXIO;
1020         }
1021
1022         INIT_LIST_HEAD(&dc->client.list);
1023         dc->client.ops = &dc_client_ops;
1024         dc->client.dev = &pdev->dev;
1025
1026         err = tegra_dc_rgb_probe(dc);
1027         if (err < 0 && err != -ENODEV) {
1028                 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1029                 return err;
1030         }
1031
1032         err = host1x_register_client(host1x, &dc->client);
1033         if (err < 0) {
1034                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1035                         err);
1036                 return err;
1037         }
1038
1039         platform_set_drvdata(pdev, dc);
1040
1041         return 0;
1042 }
1043
1044 static int tegra_dc_remove(struct platform_device *pdev)
1045 {
1046         struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
1047         struct tegra_dc *dc = platform_get_drvdata(pdev);
1048         int err;
1049
1050         err = host1x_unregister_client(host1x, &dc->client);
1051         if (err < 0) {
1052                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1053                         err);
1054                 return err;
1055         }
1056
1057         clk_disable_unprepare(dc->clk);
1058
1059         return 0;
1060 }
1061
1062 static struct of_device_id tegra_dc_of_match[] = {
1063         { .compatible = "nvidia,tegra30-dc", },
1064         { .compatible = "nvidia,tegra20-dc", },
1065         { },
1066 };
1067
1068 struct platform_driver tegra_dc_driver = {
1069         .driver = {
1070                 .name = "tegra-dc",
1071                 .owner = THIS_MODULE,
1072                 .of_match_table = tegra_dc_of_match,
1073         },
1074         .probe = tegra_dc_probe,
1075         .remove = tegra_dc_remove,
1076 };