drivers/gpu/drm/tegra/sor.c

   1 /*
   2  * Copyright (C) 2013 NVIDIA Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/debugfs.h>
  11 #include <linux/gpio.h>
  12 #include <linux/io.h>
  13 #include <linux/of_device.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/regulator/consumer.h>
  16 #include <linux/reset.h>
  17
  18 #include <soc/tegra/pmc.h>
  19
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_dp_helper.h>
  22 #include <drm/drm_panel.h>
  23
  24 #include "dc.h"
  25 #include "drm.h"
  26 #include "sor.h"
  27
  28 #define SOR_REKEY 0x38
  29
  30 struct tegra_sor_hdmi_settings {
  31         unsigned long frequency;
  32
  33         u8 vcocap;
  34         u8 ichpmp;
  35         u8 loadadj;
  36         u8 termadj;
  37         u8 tx_pu;
  38         u8 bg_vref;
  39
  40         u8 drive_current[4];
  41         u8 preemphasis[4];
  42 };
  43
  44 #if 1
  45 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
  46         {
  47                 .frequency = 54000000,
  48                 .vcocap = 0x0,
  49                 .ichpmp = 0x1,
  50                 .loadadj = 0x3,
  51                 .termadj = 0x9,
  52                 .tx_pu = 0x10,
  53                 .bg_vref = 0x8,
  54                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  55                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  56         }, {
  57                 .frequency = 75000000,
  58                 .vcocap = 0x3,
  59                 .ichpmp = 0x1,
  60                 .loadadj = 0x3,
  61                 .termadj = 0x9,
  62                 .tx_pu = 0x40,
  63                 .bg_vref = 0x8,
  64                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  65                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  66         }, {
  67                 .frequency = 150000000,
  68                 .vcocap = 0x3,
  69                 .ichpmp = 0x1,
  70                 .loadadj = 0x3,
  71                 .termadj = 0x9,
  72                 .tx_pu = 0x66,
  73                 .bg_vref = 0x8,
  74                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  75                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  76         }, {
  77                 .frequency = 300000000,
  78                 .vcocap = 0x3,
  79                 .ichpmp = 0x1,
  80                 .loadadj = 0x3,
  81                 .termadj = 0x9,
  82                 .tx_pu = 0x66,
  83                 .bg_vref = 0xa,
  84                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
  85                 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
  86         }, {
  87                 .frequency = 600000000,
  88                 .vcocap = 0x3,
  89                 .ichpmp = 0x1,
  90                 .loadadj = 0x3,
  91                 .termadj = 0x9,
  92                 .tx_pu = 0x66,
  93                 .bg_vref = 0x8,
  94                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
  95                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  96         },
  97 };
  98 #else
  99 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
 100         {
 101                 .frequency = 75000000,
 102                 .vcocap = 0x3,
 103                 .ichpmp = 0x1,
 104                 .loadadj = 0x3,
 105                 .termadj = 0x9,
 106                 .tx_pu = 0x40,
 107                 .bg_vref = 0x8,
 108                 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
 109                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 110         }, {
 111                 .frequency = 150000000,
 112                 .vcocap = 0x3,
 113                 .ichpmp = 0x1,
 114                 .loadadj = 0x3,
 115                 .termadj = 0x9,
 116                 .tx_pu = 0x66,
 117                 .bg_vref = 0x8,
 118                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 119                 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
 120         }, {
 121                 .frequency = 300000000,
 122                 .vcocap = 0x3,
 123                 .ichpmp = 0x6,
 124                 .loadadj = 0x3,
 125                 .termadj = 0x9,
 126                 .tx_pu = 0x66,
 127                 .bg_vref = 0xf,
 128                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 129                 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
 130         }, {
 131                 .frequency = 600000000,
 132                 .vcocap = 0x3,
 133                 .ichpmp = 0xa,
 134                 .loadadj = 0x3,
 135                 .termadj = 0xb,
 136                 .tx_pu = 0x66,
 137                 .bg_vref = 0xe,
 138                 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
 139                 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
 140         },
 141 };
 142 #endif
 143
 144 struct tegra_sor_soc {
 145         bool supports_edp;
 146         bool supports_lvds;
 147         bool supports_hdmi;
 148         bool supports_dp;
 149
 150         const struct tegra_sor_hdmi_settings *settings;
 151         unsigned int num_settings;
 152 };
 153
 154 struct tegra_sor;
 155
 156 struct tegra_sor_ops {
 157         const char *name;
 158         int (*probe)(struct tegra_sor *sor);
 159         int (*remove)(struct tegra_sor *sor);
 160 };
 161
 162 struct tegra_sor {
 163         struct host1x_client client;
 164         struct tegra_output output;
 165         struct device *dev;
 166
 167         const struct tegra_sor_soc *soc;
 168         void __iomem *regs;
 169
 170         struct reset_control *rst;
 171         struct clk *clk_parent;
 172         struct clk *clk_safe;
 173         struct clk *clk_dp;
 174         struct clk *clk;
 175
 176         struct drm_dp_aux *aux;
 177
 178         struct drm_info_list *debugfs_files;
 179         struct drm_minor *minor;
 180         struct dentry *debugfs;
 181
 182         const struct tegra_sor_ops *ops;
 183
 184         /* for HDMI 2.0 */
 185         struct tegra_sor_hdmi_settings *settings;
 186         unsigned int num_settings;
 187
 188         struct regulator *avdd_io_supply;
 189         struct regulator *vdd_pll_supply;
 190         struct regulator *hdmi_supply;
 191 };
 192
 193 struct tegra_sor_config {
 194         u32 bits_per_pixel;
 195
 196         u32 active_polarity;
 197         u32 active_count;
 198         u32 tu_size;
 199         u32 active_frac;
 200         u32 watermark;
 201
 202         u32 hblank_symbols;
 203         u32 vblank_symbols;
 204 };
 205
 206 static inline struct tegra_sor *
 207 host1x_client_to_sor(struct host1x_client *client)
 208 {
 209         return container_of(client, struct tegra_sor, client);
 210 }
 211
 212 static inline struct tegra_sor *to_sor(struct tegra_output *output)
 213 {
 214         return container_of(output, struct tegra_sor, output);
 215 }
 216
 217 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned long offset)
 218 {
 219         return readl(sor->regs + (offset << 2));
 220 }
 221
 222 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
 223                                     unsigned long offset)
 224 {
 225         writel(value, sor->regs + (offset << 2));
 226 }
 227
 228 static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
 229                                    struct drm_dp_link *link)
 230 {
 231         unsigned int i;
 232         u8 pattern;
 233         u32 value;
 234         int err;
 235
 236         /* setup lane parameters */
 237         value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
 238                 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
 239                 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
 240                 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
 241         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
 242
 243         value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
 244                 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
 245                 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
 246                 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
 247         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
 248
 249         value = SOR_LANE_POSTCURSOR_LANE3(0x00) |
 250                 SOR_LANE_POSTCURSOR_LANE2(0x00) |
 251                 SOR_LANE_POSTCURSOR_LANE1(0x00) |
 252                 SOR_LANE_POSTCURSOR_LANE0(0x00);
 253         tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0);
 254
 255         /* disable LVDS mode */
 256         tegra_sor_writel(sor, 0, SOR_LVDS);
 257
 258         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
 259         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
 260         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
 261         value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
 262         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
 263
 264         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
 265         value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 266                  SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
 267         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
 268
 269         usleep_range(10, 100);
 270
 271         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
 272         value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 273                    SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
 274         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
 275
 276         err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B);
 277         if (err < 0)
 278                 return err;
 279
 280         for (i = 0, value = 0; i < link->num_lanes; i++) {
 281                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 282                                      SOR_DP_TPG_SCRAMBLER_NONE |
 283                                      SOR_DP_TPG_PATTERN_TRAIN1;
 284                 value = (value << 8) | lane;
 285         }
 286
 287         tegra_sor_writel(sor, value, SOR_DP_TPG);
 288
 289         pattern = DP_TRAINING_PATTERN_1;
 290
 291         err = drm_dp_aux_train(sor->aux, link, pattern);
 292         if (err < 0)
 293                 return err;
 294
 295         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
 296         value |= SOR_DP_SPARE_SEQ_ENABLE;
 297         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
 298         value |= SOR_DP_SPARE_MACRO_SOR_CLK;
 299         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
 300
 301         for (i = 0, value = 0; i < link->num_lanes; i++) {
 302                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 303                                      SOR_DP_TPG_SCRAMBLER_NONE |
 304                                      SOR_DP_TPG_PATTERN_TRAIN2;
 305                 value = (value << 8) | lane;
 306         }
 307
 308         tegra_sor_writel(sor, value, SOR_DP_TPG);
 309
 310         pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
 311
 312         err = drm_dp_aux_train(sor->aux, link, pattern);
 313         if (err < 0)
 314                 return err;
 315
 316         for (i = 0, value = 0; i < link->num_lanes; i++) {
 317                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 318                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
 319                                      SOR_DP_TPG_PATTERN_NONE;
 320                 value = (value << 8) | lane;
 321         }
 322
 323         tegra_sor_writel(sor, value, SOR_DP_TPG);
 324
 325         pattern = DP_TRAINING_PATTERN_DISABLE;
 326
 327         err = drm_dp_aux_train(sor->aux, link, pattern);
 328         if (err < 0)
 329                 return err;
 330
 331         return 0;
 332 }
 333
 334 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
 335 {
 336         u32 mask = 0x08, adj = 0, value;
 337
 338         /* enable pad calibration logic */
 339         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
 340         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
 341         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
 342
 343         value = tegra_sor_readl(sor, SOR_PLL1);
 344         value |= SOR_PLL1_TMDS_TERM;
 345         tegra_sor_writel(sor, value, SOR_PLL1);
 346
 347         while (mask) {
 348                 adj |= mask;
 349
 350                 value = tegra_sor_readl(sor, SOR_PLL1);
 351                 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 352                 value |= SOR_PLL1_TMDS_TERMADJ(adj);
 353                 tegra_sor_writel(sor, value, SOR_PLL1);
 354
 355                 usleep_range(100, 200);
 356
 357                 value = tegra_sor_readl(sor, SOR_PLL1);
 358                 if (value & SOR_PLL1_TERM_COMPOUT)
 359                         adj &= ~mask;
 360
 361                 mask >>= 1;
 362         }
 363
 364         value = tegra_sor_readl(sor, SOR_PLL1);
 365         value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 366         value |= SOR_PLL1_TMDS_TERMADJ(adj);
 367         tegra_sor_writel(sor, value, SOR_PLL1);
 368
 369         /* disable pad calibration logic */
 370         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
 371         value |= SOR_DP_PADCTL_PAD_CAL_PD;
 372         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
 373 }
 374
 375 static void tegra_sor_super_update(struct tegra_sor *sor)
 376 {
 377         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 378         tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
 379         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 380 }
 381
 382 static void tegra_sor_update(struct tegra_sor *sor)
 383 {
 384         tegra_sor_writel(sor, 0, SOR_STATE0);
 385         tegra_sor_writel(sor, 1, SOR_STATE0);
 386         tegra_sor_writel(sor, 0, SOR_STATE0);
 387 }
 388
 389 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
 390 {
 391         u32 value;
 392
 393         value = tegra_sor_readl(sor, SOR_PWM_DIV);
 394         value &= ~SOR_PWM_DIV_MASK;
 395         value |= 0x400; /* period */
 396         tegra_sor_writel(sor, value, SOR_PWM_DIV);
 397
 398         value = tegra_sor_readl(sor, SOR_PWM_CTL);
 399         value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
 400         value |= 0x400; /* duty cycle */
 401         value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
 402         value |= SOR_PWM_CTL_TRIGGER;
 403         tegra_sor_writel(sor, value, SOR_PWM_CTL);
 404
 405         timeout = jiffies + msecs_to_jiffies(timeout);
 406
 407         while (time_before(jiffies, timeout)) {
 408                 value = tegra_sor_readl(sor, SOR_PWM_CTL);
 409                 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
 410                         return 0;
 411
 412                 usleep_range(25, 100);
 413         }
 414
 415         return -ETIMEDOUT;
 416 }
 417
 418 static int tegra_sor_attach(struct tegra_sor *sor)
 419 {
 420         unsigned long value, timeout;
 421
 422         /* wake up in normal mode */
 423         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 424         value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
 425         value |= SOR_SUPER_STATE_MODE_NORMAL;
 426         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 427         tegra_sor_super_update(sor);
 428
 429         /* attach */
 430         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 431         value |= SOR_SUPER_STATE_ATTACHED;
 432         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 433         tegra_sor_super_update(sor);
 434
 435         timeout = jiffies + msecs_to_jiffies(250);
 436
 437         while (time_before(jiffies, timeout)) {
 438                 value = tegra_sor_readl(sor, SOR_TEST);
 439                 if ((value & SOR_TEST_ATTACHED) != 0)
 440                         return 0;
 441
 442                 usleep_range(25, 100);
 443         }
 444
 445         return -ETIMEDOUT;
 446 }
 447
 448 static int tegra_sor_wakeup(struct tegra_sor *sor)
 449 {
 450         unsigned long value, timeout;
 451
 452         timeout = jiffies + msecs_to_jiffies(250);
 453
 454         /* wait for head to wake up */
 455         while (time_before(jiffies, timeout)) {
 456                 value = tegra_sor_readl(sor, SOR_TEST);
 457                 value &= SOR_TEST_HEAD_MODE_MASK;
 458
 459                 if (value == SOR_TEST_HEAD_MODE_AWAKE)
 460                         return 0;
 461
 462                 usleep_range(25, 100);
 463         }
 464
 465         return -ETIMEDOUT;
 466 }
 467
 468 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
 469 {
 470         u32 value;
 471
 472         value = tegra_sor_readl(sor, SOR_PWR);
 473         value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
 474         tegra_sor_writel(sor, value, SOR_PWR);
 475
 476         timeout = jiffies + msecs_to_jiffies(timeout);
 477
 478         while (time_before(jiffies, timeout)) {
 479                 value = tegra_sor_readl(sor, SOR_PWR);
 480                 if ((value & SOR_PWR_TRIGGER) == 0)
 481                         return 0;
 482
 483                 usleep_range(25, 100);
 484         }
 485
 486         return -ETIMEDOUT;
 487 }
 488
 489 struct tegra_sor_params {
 490         /* number of link clocks per line */
 491         unsigned int num_clocks;
 492         /* ratio between input and output */
 493         u64 ratio;
 494         /* precision factor */
 495         u64 precision;
 496
 497         unsigned int active_polarity;
 498         unsigned int active_count;
 499         unsigned int active_frac;
 500         unsigned int tu_size;
 501         unsigned int error;
 502 };
 503
 504 static int tegra_sor_compute_params(struct tegra_sor *sor,
 505                                     struct tegra_sor_params *params,
 506                                     unsigned int tu_size)
 507 {
 508         u64 active_sym, active_count, frac, approx;
 509         u32 active_polarity, active_frac = 0;
 510         const u64 f = params->precision;
 511         s64 error;
 512
 513         active_sym = params->ratio * tu_size;
 514         active_count = div_u64(active_sym, f) * f;
 515         frac = active_sym - active_count;
 516
 517         /* fraction < 0.5 */
 518         if (frac >= (f / 2)) {
 519                 active_polarity = 1;
 520                 frac = f - frac;
 521         } else {
 522                 active_polarity = 0;
 523         }
 524
 525         if (frac != 0) {
 526                 frac = div_u64(f * f,  frac); /* 1/fraction */
 527                 if (frac <= (15 * f)) {
 528                         active_frac = div_u64(frac, f);
 529
 530                         /* round up */
 531                         if (active_polarity)
 532                                 active_frac++;
 533                 } else {
 534                         active_frac = active_polarity ? 1 : 15;
 535                 }
 536         }
 537
 538         if (active_frac == 1)
 539                 active_polarity = 0;
 540
 541         if (active_polarity == 1) {
 542                 if (active_frac) {
 543                         approx = active_count + (active_frac * (f - 1)) * f;
 544                         approx = div_u64(approx, active_frac * f);
 545                 } else {
 546                         approx = active_count + f;
 547                 }
 548         } else {
 549                 if (active_frac)
 550                         approx = active_count + div_u64(f, active_frac);
 551                 else
 552                         approx = active_count;
 553         }
 554
 555         error = div_s64(active_sym - approx, tu_size);
 556         error *= params->num_clocks;
 557
 558         if (error <= 0 && abs(error) < params->error) {
 559                 params->active_count = div_u64(active_count, f);
 560                 params->active_polarity = active_polarity;
 561                 params->active_frac = active_frac;
 562                 params->error = abs(error);
 563                 params->tu_size = tu_size;
 564
 565                 if (error == 0)
 566                         return true;
 567         }
 568
 569         return false;
 570 }
 571
 572 static int tegra_sor_calc_config(struct tegra_sor *sor,
 573                                  const struct drm_display_mode *mode,
 574                                  struct tegra_sor_config *config,
 575                                  struct drm_dp_link *link)
 576 {
 577         const u64 f = 100000, link_rate = link->rate * 1000;
 578         const u64 pclk = mode->clock * 1000;
 579         u64 input, output, watermark, num;
 580         struct tegra_sor_params params;
 581         u32 num_syms_per_line;
 582         unsigned int i;
 583
 584         if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
 585                 return -EINVAL;
 586
 587         output = link_rate * 8 * link->num_lanes;
 588         input = pclk * config->bits_per_pixel;
 589
 590         if (input >= output)
 591                 return -ERANGE;
 592
 593         memset(&params, 0, sizeof(params));
 594         params.ratio = div64_u64(input * f, output);
 595         params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
 596         params.precision = f;
 597         params.error = 64 * f;
 598         params.tu_size = 64;
 599
 600         for (i = params.tu_size; i >= 32; i--)
 601                 if (tegra_sor_compute_params(sor, &params, i))
 602                         break;
 603
 604         if (params.active_frac == 0) {
 605                 config->active_polarity = 0;
 606                 config->active_count = params.active_count;
 607
 608                 if (!params.active_polarity)
 609                         config->active_count--;
 610
 611                 config->tu_size = params.tu_size;
 612                 config->active_frac = 1;
 613         } else {
 614                 config->active_polarity = params.active_polarity;
 615                 config->active_count = params.active_count;
 616                 config->active_frac = params.active_frac;
 617                 config->tu_size = params.tu_size;
 618         }
 619
 620         dev_dbg(sor->dev,
 621                 "polarity: %d active count: %d tu size: %d active frac: %d\n",
 622                 config->active_polarity, config->active_count,
 623                 config->tu_size, config->active_frac);
 624
 625         watermark = params.ratio * config->tu_size * (f - params.ratio);
 626         watermark = div_u64(watermark, f);
 627
 628         watermark = div_u64(watermark + params.error, f);
 629         config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
 630         num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
 631                             (link->num_lanes * 8);
 632
 633         if (config->watermark > 30) {
 634                 config->watermark = 30;
 635                 dev_err(sor->dev,
 636                         "unable to compute TU size, forcing watermark to %u\n",
 637                         config->watermark);
 638         } else if (config->watermark > num_syms_per_line) {
 639                 config->watermark = num_syms_per_line;
 640                 dev_err(sor->dev, "watermark too high, forcing to %u\n",
 641                         config->watermark);
 642         }
 643
 644         /* compute the number of symbols per horizontal blanking interval */
 645         num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
 646         config->hblank_symbols = div_u64(num, pclk);
 647
 648         if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
 649                 config->hblank_symbols -= 3;
 650
 651         config->hblank_symbols -= 12 / link->num_lanes;
 652
 653         /* compute the number of symbols per vertical blanking interval */
 654         num = (mode->hdisplay - 25) * link_rate;
 655         config->vblank_symbols = div_u64(num, pclk);
 656         config->vblank_symbols -= 36 / link->num_lanes + 4;
 657
 658         dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
 659                 config->vblank_symbols);
 660
 661         return 0;
 662 }
 663
 664 static int tegra_sor_detach(struct tegra_sor *sor)
 665 {
 666         unsigned long value, timeout;
 667
 668         /* switch to safe mode */
 669         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 670         value &= ~SOR_SUPER_STATE_MODE_NORMAL;
 671         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 672         tegra_sor_super_update(sor);
 673
 674         timeout = jiffies + msecs_to_jiffies(250);
 675
 676         while (time_before(jiffies, timeout)) {
 677                 value = tegra_sor_readl(sor, SOR_PWR);
 678                 if (value & SOR_PWR_MODE_SAFE)
 679                         break;
 680         }
 681
 682         if ((value & SOR_PWR_MODE_SAFE) == 0)
 683                 return -ETIMEDOUT;
 684
 685         /* go to sleep */
 686         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 687         value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
 688         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 689         tegra_sor_super_update(sor);
 690
 691         /* detach */
 692         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 693         value &= ~SOR_SUPER_STATE_ATTACHED;
 694         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 695         tegra_sor_super_update(sor);
 696
 697         timeout = jiffies + msecs_to_jiffies(250);
 698
 699         while (time_before(jiffies, timeout)) {
 700                 value = tegra_sor_readl(sor, SOR_TEST);
 701                 if ((value & SOR_TEST_ATTACHED) == 0)
 702                         break;
 703
 704                 usleep_range(25, 100);
 705         }
 706
 707         if ((value & SOR_TEST_ATTACHED) != 0)
 708                 return -ETIMEDOUT;
 709
 710         return 0;
 711 }
 712
 713 static int tegra_sor_power_down(struct tegra_sor *sor)
 714 {
 715         unsigned long value, timeout;
 716         int err;
 717
 718         value = tegra_sor_readl(sor, SOR_PWR);
 719         value &= ~SOR_PWR_NORMAL_STATE_PU;
 720         value |= SOR_PWR_TRIGGER;
 721         tegra_sor_writel(sor, value, SOR_PWR);
 722
 723         timeout = jiffies + msecs_to_jiffies(250);
 724
 725         while (time_before(jiffies, timeout)) {
 726                 value = tegra_sor_readl(sor, SOR_PWR);
 727                 if ((value & SOR_PWR_TRIGGER) == 0)
 728                         return 0;
 729
 730                 usleep_range(25, 100);
 731         }
 732
 733         if ((value & SOR_PWR_TRIGGER) != 0)
 734                 return -ETIMEDOUT;
 735
 736         err = clk_set_parent(sor->clk, sor->clk_safe);
 737         if (err < 0)
 738                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
 739
 740         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
 741         value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
 742                    SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
 743         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
 744
 745         /* stop lane sequencer */
 746         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
 747                 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
 748         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 749
 750         timeout = jiffies + msecs_to_jiffies(250);
 751
 752         while (time_before(jiffies, timeout)) {
 753                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 754                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 755                         break;
 756
 757                 usleep_range(25, 100);
 758         }
 759
 760         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
 761                 return -ETIMEDOUT;
 762
 763         value = tegra_sor_readl(sor, SOR_PLL2);
 764         value |= SOR_PLL2_PORT_POWERDOWN;
 765         tegra_sor_writel(sor, value, SOR_PLL2);
 766
 767         usleep_range(20, 100);
 768
 769         value = tegra_sor_readl(sor, SOR_PLL0);
 770         value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
 771         tegra_sor_writel(sor, value, SOR_PLL0);
 772
 773         value = tegra_sor_readl(sor, SOR_PLL2);
 774         value |= SOR_PLL2_SEQ_PLLCAPPD;
 775         value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
 776         tegra_sor_writel(sor, value, SOR_PLL2);
 777
 778         usleep_range(20, 100);
 779
 780         return 0;
 781 }
 782
 783 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
 784 {
 785         u32 value;
 786
 787         timeout = jiffies + msecs_to_jiffies(timeout);
 788
 789         while (time_before(jiffies, timeout)) {
 790                 value = tegra_sor_readl(sor, SOR_CRCA);
 791                 if (value & SOR_CRCA_VALID)
 792                         return 0;
 793
 794                 usleep_range(100, 200);
 795         }
 796
 797         return -ETIMEDOUT;
 798 }
 799
 800 static int tegra_sor_show_crc(struct seq_file *s, void *data)
 801 {
 802         struct drm_info_node *node = s->private;
 803         struct tegra_sor *sor = node->info_ent->data;
 804         struct drm_crtc *crtc = sor->output.encoder.crtc;
 805         struct drm_device *drm = node->minor->dev;
 806         int err = 0;
 807         u32 value;
 808
 809         drm_modeset_lock_all(drm);
 810
 811         if (!crtc || !crtc->state->active) {
 812                 err = -EBUSY;
 813                 goto unlock;
 814         }
 815
 816         value = tegra_sor_readl(sor, SOR_STATE1);
 817         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
 818         tegra_sor_writel(sor, value, SOR_STATE1);
 819
 820         value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
 821         value |= SOR_CRC_CNTRL_ENABLE;
 822         tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
 823
 824         value = tegra_sor_readl(sor, SOR_TEST);
 825         value &= ~SOR_TEST_CRC_POST_SERIALIZE;
 826         tegra_sor_writel(sor, value, SOR_TEST);
 827
 828         err = tegra_sor_crc_wait(sor, 100);
 829         if (err < 0)
 830                 goto unlock;
 831
 832         tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
 833         value = tegra_sor_readl(sor, SOR_CRCB);
 834
 835         seq_printf(s, "%08x\n", value);
 836
 837 unlock:
 838         drm_modeset_unlock_all(drm);
 839         return err;
 840 }
 841
 842 static int tegra_sor_show_regs(struct seq_file *s, void *data)
 843 {
 844         struct drm_info_node *node = s->private;
 845         struct tegra_sor *sor = node->info_ent->data;
 846         struct drm_crtc *crtc = sor->output.encoder.crtc;
 847         struct drm_device *drm = node->minor->dev;
 848         int err = 0;
 849
 850         drm_modeset_lock_all(drm);
 851
 852         if (!crtc || !crtc->state->active) {
 853                 err = -EBUSY;
 854                 goto unlock;
 855         }
 856
 857 #define DUMP_REG(name)                                          \
 858         seq_printf(s, "%-38s %#05x %08x\n", #name, name,        \
 859                    tegra_sor_readl(sor, name))
 860
 861         DUMP_REG(SOR_CTXSW);
 862         DUMP_REG(SOR_SUPER_STATE0);
 863         DUMP_REG(SOR_SUPER_STATE1);
 864         DUMP_REG(SOR_STATE0);
 865         DUMP_REG(SOR_STATE1);
 866         DUMP_REG(SOR_HEAD_STATE0(0));
 867         DUMP_REG(SOR_HEAD_STATE0(1));
 868         DUMP_REG(SOR_HEAD_STATE1(0));
 869         DUMP_REG(SOR_HEAD_STATE1(1));
 870         DUMP_REG(SOR_HEAD_STATE2(0));
 871         DUMP_REG(SOR_HEAD_STATE2(1));
 872         DUMP_REG(SOR_HEAD_STATE3(0));
 873         DUMP_REG(SOR_HEAD_STATE3(1));
 874         DUMP_REG(SOR_HEAD_STATE4(0));
 875         DUMP_REG(SOR_HEAD_STATE4(1));
 876         DUMP_REG(SOR_HEAD_STATE5(0));
 877         DUMP_REG(SOR_HEAD_STATE5(1));
 878         DUMP_REG(SOR_CRC_CNTRL);
 879         DUMP_REG(SOR_DP_DEBUG_MVID);
 880         DUMP_REG(SOR_CLK_CNTRL);
 881         DUMP_REG(SOR_CAP);
 882         DUMP_REG(SOR_PWR);
 883         DUMP_REG(SOR_TEST);
 884         DUMP_REG(SOR_PLL0);
 885         DUMP_REG(SOR_PLL1);
 886         DUMP_REG(SOR_PLL2);
 887         DUMP_REG(SOR_PLL3);
 888         DUMP_REG(SOR_CSTM);
 889         DUMP_REG(SOR_LVDS);
 890         DUMP_REG(SOR_CRCA);
 891         DUMP_REG(SOR_CRCB);
 892         DUMP_REG(SOR_BLANK);
 893         DUMP_REG(SOR_SEQ_CTL);
 894         DUMP_REG(SOR_LANE_SEQ_CTL);
 895         DUMP_REG(SOR_SEQ_INST(0));
 896         DUMP_REG(SOR_SEQ_INST(1));
 897         DUMP_REG(SOR_SEQ_INST(2));
 898         DUMP_REG(SOR_SEQ_INST(3));
 899         DUMP_REG(SOR_SEQ_INST(4));
 900         DUMP_REG(SOR_SEQ_INST(5));
 901         DUMP_REG(SOR_SEQ_INST(6));
 902         DUMP_REG(SOR_SEQ_INST(7));
 903         DUMP_REG(SOR_SEQ_INST(8));
 904         DUMP_REG(SOR_SEQ_INST(9));
 905         DUMP_REG(SOR_SEQ_INST(10));
 906         DUMP_REG(SOR_SEQ_INST(11));
 907         DUMP_REG(SOR_SEQ_INST(12));
 908         DUMP_REG(SOR_SEQ_INST(13));
 909         DUMP_REG(SOR_SEQ_INST(14));
 910         DUMP_REG(SOR_SEQ_INST(15));
 911         DUMP_REG(SOR_PWM_DIV);
 912         DUMP_REG(SOR_PWM_CTL);
 913         DUMP_REG(SOR_VCRC_A0);
 914         DUMP_REG(SOR_VCRC_A1);
 915         DUMP_REG(SOR_VCRC_B0);
 916         DUMP_REG(SOR_VCRC_B1);
 917         DUMP_REG(SOR_CCRC_A0);
 918         DUMP_REG(SOR_CCRC_A1);
 919         DUMP_REG(SOR_CCRC_B0);
 920         DUMP_REG(SOR_CCRC_B1);
 921         DUMP_REG(SOR_EDATA_A0);
 922         DUMP_REG(SOR_EDATA_A1);
 923         DUMP_REG(SOR_EDATA_B0);
 924         DUMP_REG(SOR_EDATA_B1);
 925         DUMP_REG(SOR_COUNT_A0);
 926         DUMP_REG(SOR_COUNT_A1);
 927         DUMP_REG(SOR_COUNT_B0);
 928         DUMP_REG(SOR_COUNT_B1);
 929         DUMP_REG(SOR_DEBUG_A0);
 930         DUMP_REG(SOR_DEBUG_A1);
 931         DUMP_REG(SOR_DEBUG_B0);
 932         DUMP_REG(SOR_DEBUG_B1);
 933         DUMP_REG(SOR_TRIG);
 934         DUMP_REG(SOR_MSCHECK);
 935         DUMP_REG(SOR_XBAR_CTRL);
 936         DUMP_REG(SOR_XBAR_POL);
 937         DUMP_REG(SOR_DP_LINKCTL0);
 938         DUMP_REG(SOR_DP_LINKCTL1);
 939         DUMP_REG(SOR_LANE_DRIVE_CURRENT0);
 940         DUMP_REG(SOR_LANE_DRIVE_CURRENT1);
 941         DUMP_REG(SOR_LANE4_DRIVE_CURRENT0);
 942         DUMP_REG(SOR_LANE4_DRIVE_CURRENT1);
 943         DUMP_REG(SOR_LANE_PREEMPHASIS0);
 944         DUMP_REG(SOR_LANE_PREEMPHASIS1);
 945         DUMP_REG(SOR_LANE4_PREEMPHASIS0);
 946         DUMP_REG(SOR_LANE4_PREEMPHASIS1);
 947         DUMP_REG(SOR_LANE_POSTCURSOR0);
 948         DUMP_REG(SOR_LANE_POSTCURSOR1);
 949         DUMP_REG(SOR_DP_CONFIG0);
 950         DUMP_REG(SOR_DP_CONFIG1);
 951         DUMP_REG(SOR_DP_MN0);
 952         DUMP_REG(SOR_DP_MN1);
 953         DUMP_REG(SOR_DP_PADCTL0);
 954         DUMP_REG(SOR_DP_PADCTL1);
 955         DUMP_REG(SOR_DP_DEBUG0);
 956         DUMP_REG(SOR_DP_DEBUG1);
 957         DUMP_REG(SOR_DP_SPARE0);
 958         DUMP_REG(SOR_DP_SPARE1);
 959         DUMP_REG(SOR_DP_AUDIO_CTRL);
 960         DUMP_REG(SOR_DP_AUDIO_HBLANK_SYMBOLS);
 961         DUMP_REG(SOR_DP_AUDIO_VBLANK_SYMBOLS);
 962         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_HEADER);
 963         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK0);
 964         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK1);
 965         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK2);
 966         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK3);
 967         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK4);
 968         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK5);
 969         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK6);
 970         DUMP_REG(SOR_DP_TPG);
 971         DUMP_REG(SOR_DP_TPG_CONFIG);
 972         DUMP_REG(SOR_DP_LQ_CSTM0);
 973         DUMP_REG(SOR_DP_LQ_CSTM1);
 974         DUMP_REG(SOR_DP_LQ_CSTM2);
 975
 976 #undef DUMP_REG
 977
 978 unlock:
 979         drm_modeset_unlock_all(drm);
 980         return err;
 981 }
 982
 983 static const struct drm_info_list debugfs_files[] = {
 984         { "crc", tegra_sor_show_crc, 0, NULL },
 985         { "regs", tegra_sor_show_regs, 0, NULL },
 986 };
 987
 988 static int tegra_sor_debugfs_init(struct tegra_sor *sor,
 989                                   struct drm_minor *minor)
 990 {
 991         const char *name = sor->soc->supports_dp ? "sor1" : "sor";
 992         unsigned int i;
 993         int err;
 994
 995         sor->debugfs = debugfs_create_dir(name, minor->debugfs_root);
 996         if (!sor->debugfs)
 997                 return -ENOMEM;
 998
 999         sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1000                                      GFP_KERNEL);
1001         if (!sor->debugfs_files) {
1002                 err = -ENOMEM;
1003                 goto remove;
1004         }
1005
1006         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1007                 sor->debugfs_files[i].data = sor;
1008
1009         err = drm_debugfs_create_files(sor->debugfs_files,
1010                                        ARRAY_SIZE(debugfs_files),
1011                                        sor->debugfs, minor);
1012         if (err < 0)
1013                 goto free;
1014
1015         sor->minor = minor;
1016
1017         return 0;
1018
1019 free:
1020         kfree(sor->debugfs_files);
1021         sor->debugfs_files = NULL;
1022 remove:
1023         debugfs_remove_recursive(sor->debugfs);
1024         sor->debugfs = NULL;
1025         return err;
1026 }
1027
1028 static void tegra_sor_debugfs_exit(struct tegra_sor *sor)
1029 {
1030         drm_debugfs_remove_files(sor->debugfs_files, ARRAY_SIZE(debugfs_files),
1031                                  sor->minor);
1032         sor->minor = NULL;
1033
1034         kfree(sor->debugfs_files);
1035         sor->debugfs_files = NULL;
1036
1037         debugfs_remove_recursive(sor->debugfs);
1038         sor->debugfs = NULL;
1039 }
1040
1041 static enum drm_connector_status
1042 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1043 {
1044         struct tegra_output *output = connector_to_output(connector);
1045         struct tegra_sor *sor = to_sor(output);
1046
1047         if (sor->aux)
1048                 return drm_dp_aux_detect(sor->aux);
1049
1050         return tegra_output_connector_detect(connector, force);
1051 }
1052
1053 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1054         .dpms = drm_atomic_helper_connector_dpms,
1055         .reset = drm_atomic_helper_connector_reset,
1056         .detect = tegra_sor_connector_detect,
1057         .fill_modes = drm_helper_probe_single_connector_modes,
1058         .destroy = tegra_output_connector_destroy,
1059         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1060         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1061 };
1062
1063 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1064 {
1065         struct tegra_output *output = connector_to_output(connector);
1066         struct tegra_sor *sor = to_sor(output);
1067         int err;
1068
1069         if (sor->aux)
1070                 drm_dp_aux_enable(sor->aux);
1071
1072         err = tegra_output_connector_get_modes(connector);
1073
1074         if (sor->aux)
1075                 drm_dp_aux_disable(sor->aux);
1076
1077         return err;
1078 }
1079
1080 static enum drm_mode_status
1081 tegra_sor_connector_mode_valid(struct drm_connector *connector,
1082                                struct drm_display_mode *mode)
1083 {
1084         return MODE_OK;
1085 }
1086
1087 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1088         .get_modes = tegra_sor_connector_get_modes,
1089         .mode_valid = tegra_sor_connector_mode_valid,
1090         .best_encoder = tegra_output_connector_best_encoder,
1091 };
1092
1093 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
1094         .destroy = tegra_output_encoder_destroy,
1095 };
1096
1097 static void tegra_sor_edp_disable(struct drm_encoder *encoder)
1098 {
1099         struct tegra_output *output = encoder_to_output(encoder);
1100         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1101         struct tegra_sor *sor = to_sor(output);
1102         u32 value;
1103         int err;
1104
1105         if (output->panel)
1106                 drm_panel_disable(output->panel);
1107
1108         err = tegra_sor_detach(sor);
1109         if (err < 0)
1110                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1111
1112         tegra_sor_writel(sor, 0, SOR_STATE1);
1113         tegra_sor_update(sor);
1114
1115         /*
1116          * The following accesses registers of the display controller, so make
1117          * sure it's only executed when the output is attached to one.
1118          */
1119         if (dc) {
1120                 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1121                 value &= ~SOR_ENABLE;
1122                 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1123
1124                 tegra_dc_commit(dc);
1125         }
1126
1127         err = tegra_sor_power_down(sor);
1128         if (err < 0)
1129                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1130
1131         if (sor->aux) {
1132                 err = drm_dp_aux_disable(sor->aux);
1133                 if (err < 0)
1134                         dev_err(sor->dev, "failed to disable DP: %d\n", err);
1135         }
1136
1137         err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS);
1138         if (err < 0)
1139                 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err);
1140
1141         if (output->panel)
1142                 drm_panel_unprepare(output->panel);
1143
1144         reset_control_assert(sor->rst);
1145         clk_disable_unprepare(sor->clk);
1146 }
1147
1148 #if 0
1149 static int calc_h_ref_to_sync(const struct drm_display_mode *mode,
1150                               unsigned int *value)
1151 {
1152         unsigned int hfp, hsw, hbp, a = 0, b;
1153
1154         hfp = mode->hsync_start - mode->hdisplay;
1155         hsw = mode->hsync_end - mode->hsync_start;
1156         hbp = mode->htotal - mode->hsync_end;
1157
1158         pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp);
1159
1160         b = hfp - 1;
1161
1162         pr_info("a: %u, b: %u\n", a, b);
1163         pr_info("a + hsw + hbp = %u\n", a + hsw + hbp);
1164
1165         if (a + hsw + hbp <= 11) {
1166                 a = 1 + 11 - hsw - hbp;
1167                 pr_info("a: %u\n", a);
1168         }
1169
1170         if (a > b)
1171                 return -EINVAL;
1172
1173         if (hsw < 1)
1174                 return -EINVAL;
1175
1176         if (mode->hdisplay < 16)
1177                 return -EINVAL;
1178
1179         if (value) {
1180                 if (b > a && a % 2)
1181                         *value = a + 1;
1182                 else
1183                         *value = a;
1184         }
1185
1186         return 0;
1187 }
1188 #endif
1189
1190 static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1191 {
1192         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1193         struct tegra_output *output = encoder_to_output(encoder);
1194         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1195         unsigned int vbe, vse, hbe, hse, vbs, hbs, i;
1196         struct tegra_sor *sor = to_sor(output);
1197         struct tegra_sor_config config;
1198         struct drm_dp_link link;
1199         u8 rate, lanes;
1200         int err = 0;
1201         u32 value;
1202
1203         err = clk_prepare_enable(sor->clk);
1204         if (err < 0)
1205                 dev_err(sor->dev, "failed to enable clock: %d\n", err);
1206
1207         reset_control_deassert(sor->rst);
1208
1209         if (output->panel)
1210                 drm_panel_prepare(output->panel);
1211
1212         err = drm_dp_aux_enable(sor->aux);
1213         if (err < 0)
1214                 dev_err(sor->dev, "failed to enable DP: %d\n", err);
1215
1216         err = drm_dp_link_probe(sor->aux, &link);
1217         if (err < 0) {
1218                 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1219                 return;
1220         }
1221
1222         err = clk_set_parent(sor->clk, sor->clk_safe);
1223         if (err < 0)
1224                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1225
1226         memset(&config, 0, sizeof(config));
1227         config.bits_per_pixel = output->connector.display_info.bpc * 3;
1228
1229         err = tegra_sor_calc_config(sor, mode, &config, &link);
1230         if (err < 0)
1231                 dev_err(sor->dev, "failed to compute link configuration: %d\n",
1232                         err);
1233
1234         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1235         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1236         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1237         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1238
1239         value = tegra_sor_readl(sor, SOR_PLL2);
1240         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1241         tegra_sor_writel(sor, value, SOR_PLL2);
1242         usleep_range(20, 100);
1243
1244         value = tegra_sor_readl(sor, SOR_PLL3);
1245         value |= SOR_PLL3_PLL_VDD_MODE_3V3;
1246         tegra_sor_writel(sor, value, SOR_PLL3);
1247
1248         value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST |
1249                 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT;
1250         tegra_sor_writel(sor, value, SOR_PLL0);
1251
1252         value = tegra_sor_readl(sor, SOR_PLL2);
1253         value |= SOR_PLL2_SEQ_PLLCAPPD;
1254         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1255         value |= SOR_PLL2_LVDS_ENABLE;
1256         tegra_sor_writel(sor, value, SOR_PLL2);
1257
1258         value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM;
1259         tegra_sor_writel(sor, value, SOR_PLL1);
1260
1261         while (true) {
1262                 value = tegra_sor_readl(sor, SOR_PLL2);
1263                 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0)
1264                         break;
1265
1266                 usleep_range(250, 1000);
1267         }
1268
1269         value = tegra_sor_readl(sor, SOR_PLL2);
1270         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1271         value &= ~SOR_PLL2_PORT_POWERDOWN;
1272         tegra_sor_writel(sor, value, SOR_PLL2);
1273
1274         /*
1275          * power up
1276          */
1277
1278         /* set safe link bandwidth (1.62 Gbps) */
1279         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1280         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1281         value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62;
1282         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1283
1284         /* step 1 */
1285         value = tegra_sor_readl(sor, SOR_PLL2);
1286         value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN |
1287                  SOR_PLL2_BANDGAP_POWERDOWN;
1288         tegra_sor_writel(sor, value, SOR_PLL2);
1289
1290         value = tegra_sor_readl(sor, SOR_PLL0);
1291         value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1292         tegra_sor_writel(sor, value, SOR_PLL0);
1293
1294         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1295         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
1296         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1297
1298         /* step 2 */
1299         err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS);
1300         if (err < 0)
1301                 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err);
1302
1303         usleep_range(5, 100);
1304
1305         /* step 3 */
1306         value = tegra_sor_readl(sor, SOR_PLL2);
1307         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1308         tegra_sor_writel(sor, value, SOR_PLL2);
1309
1310         usleep_range(20, 100);
1311
1312         /* step 4 */
1313         value = tegra_sor_readl(sor, SOR_PLL0);
1314         value &= ~SOR_PLL0_VCOPD;
1315         value &= ~SOR_PLL0_PWR;
1316         tegra_sor_writel(sor, value, SOR_PLL0);
1317
1318         value = tegra_sor_readl(sor, SOR_PLL2);
1319         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1320         tegra_sor_writel(sor, value, SOR_PLL2);
1321
1322         usleep_range(200, 1000);
1323
1324         /* step 5 */
1325         value = tegra_sor_readl(sor, SOR_PLL2);
1326         value &= ~SOR_PLL2_PORT_POWERDOWN;
1327         tegra_sor_writel(sor, value, SOR_PLL2);
1328
1329         /* switch to DP clock */
1330         err = clk_set_parent(sor->clk, sor->clk_dp);
1331         if (err < 0)
1332                 dev_err(sor->dev, "failed to set DP parent clock: %d\n", err);
1333
1334         /* power DP lanes */
1335         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1336
1337         if (link.num_lanes <= 2)
1338                 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
1339         else
1340                 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
1341
1342         if (link.num_lanes <= 1)
1343                 value &= ~SOR_DP_PADCTL_PD_TXD_1;
1344         else
1345                 value |= SOR_DP_PADCTL_PD_TXD_1;
1346
1347         if (link.num_lanes == 0)
1348                 value &= ~SOR_DP_PADCTL_PD_TXD_0;
1349         else
1350                 value |= SOR_DP_PADCTL_PD_TXD_0;
1351
1352         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1353
1354         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1355         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1356         value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
1357         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1358
1359         /* start lane sequencer */
1360         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
1361                 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
1362         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1363
1364         while (true) {
1365                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1366                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1367                         break;
1368
1369                 usleep_range(250, 1000);
1370         }
1371
1372         /* set link bandwidth */
1373         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1374         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1375         value |= drm_dp_link_rate_to_bw_code(link.rate) << 2;
1376         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1377
1378         /* set linkctl */
1379         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1380         value |= SOR_DP_LINKCTL_ENABLE;
1381
1382         value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1383         value |= SOR_DP_LINKCTL_TU_SIZE(config.tu_size);
1384
1385         value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1386         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1387
1388         for (i = 0, value = 0; i < 4; i++) {
1389                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1390                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
1391                                      SOR_DP_TPG_PATTERN_NONE;
1392                 value = (value << 8) | lane;
1393         }
1394
1395         tegra_sor_writel(sor, value, SOR_DP_TPG);
1396
1397         value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1398         value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1399         value |= SOR_DP_CONFIG_WATERMARK(config.watermark);
1400
1401         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1402         value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config.active_count);
1403
1404         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1405         value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config.active_frac);
1406
1407         if (config.active_polarity)
1408                 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1409         else
1410                 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1411
1412         value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1413         value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1414         tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1415
1416         value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1417         value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1418         value |= config.hblank_symbols & 0xffff;
1419         tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1420
1421         value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1422         value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1423         value |= config.vblank_symbols & 0xffff;
1424         tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1425
1426         /* enable pad calibration logic */
1427         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1428         value |= SOR_DP_PADCTL_PAD_CAL_PD;
1429         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1430
1431         err = drm_dp_link_probe(sor->aux, &link);
1432         if (err < 0)
1433                 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1434
1435         err = drm_dp_link_power_up(sor->aux, &link);
1436         if (err < 0)
1437                 dev_err(sor->dev, "failed to power up eDP link: %d\n", err);
1438
1439         err = drm_dp_link_configure(sor->aux, &link);
1440         if (err < 0)
1441                 dev_err(sor->dev, "failed to configure eDP link: %d\n", err);
1442
1443         rate = drm_dp_link_rate_to_bw_code(link.rate);
1444         lanes = link.num_lanes;
1445
1446         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1447         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1448         value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
1449         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1450
1451         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1452         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1453         value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
1454
1455         if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1456                 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1457
1458         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1459
1460         /* disable training pattern generator */
1461
1462         for (i = 0; i < link.num_lanes; i++) {
1463                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1464                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
1465                                      SOR_DP_TPG_PATTERN_NONE;
1466                 value = (value << 8) | lane;
1467         }
1468
1469         tegra_sor_writel(sor, value, SOR_DP_TPG);
1470
1471         err = tegra_sor_dp_train_fast(sor, &link);
1472         if (err < 0)
1473                 dev_err(sor->dev, "DP fast link training failed: %d\n", err);
1474
1475         dev_dbg(sor->dev, "fast link training succeeded\n");
1476
1477         err = tegra_sor_power_up(sor, 250);
1478         if (err < 0)
1479                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
1480
1481         /*
1482          * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete
1483          * raster, associate with display controller)
1484          */
1485         value = SOR_STATE_ASY_PROTOCOL_DP_A |
1486                 SOR_STATE_ASY_CRC_MODE_COMPLETE |
1487                 SOR_STATE_ASY_OWNER(dc->pipe + 1);
1488
1489         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1490                 value &= ~SOR_STATE_ASY_HSYNCPOL;
1491
1492         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1493                 value |= SOR_STATE_ASY_HSYNCPOL;
1494
1495         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1496                 value &= ~SOR_STATE_ASY_VSYNCPOL;
1497
1498         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1499                 value |= SOR_STATE_ASY_VSYNCPOL;
1500
1501         switch (config.bits_per_pixel) {
1502         case 24:
1503                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1504                 break;
1505
1506         case 18:
1507                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1508                 break;
1509
1510         default:
1511                 BUG();
1512                 break;
1513         }
1514
1515         tegra_sor_writel(sor, value, SOR_STATE1);
1516
1517         /*
1518          * TODO: The video timing programming below doesn't seem to match the
1519          * register definitions.
1520          */
1521
1522         value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1523         tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe));
1524
1525         vse = mode->vsync_end - mode->vsync_start - 1;
1526         hse = mode->hsync_end - mode->hsync_start - 1;
1527
1528         value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1529         tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe));
1530
1531         vbe = vse + (mode->vsync_start - mode->vdisplay);
1532         hbe = hse + (mode->hsync_start - mode->hdisplay);
1533
1534         value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1535         tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe));
1536
1537         vbs = vbe + mode->vdisplay;
1538         hbs = hbe + mode->hdisplay;
1539
1540         value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1541         tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe));
1542
1543         tegra_sor_writel(sor, 0x1, SOR_HEAD_STATE5(dc->pipe));
1544
1545         /* CSTM (LVDS, link A/B, upper) */
1546         value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
1547                 SOR_CSTM_UPPER;
1548         tegra_sor_writel(sor, value, SOR_CSTM);
1549
1550         /* PWM setup */
1551         err = tegra_sor_setup_pwm(sor, 250);
1552         if (err < 0)
1553                 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
1554
1555         tegra_sor_update(sor);
1556
1557         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1558         value |= SOR_ENABLE;
1559         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1560
1561         tegra_dc_commit(dc);
1562
1563         err = tegra_sor_attach(sor);
1564         if (err < 0)
1565                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
1566
1567         err = tegra_sor_wakeup(sor);
1568         if (err < 0)
1569                 dev_err(sor->dev, "failed to enable DC: %d\n", err);
1570
1571         if (output->panel)
1572                 drm_panel_enable(output->panel);
1573 }
1574
1575 static int
1576 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1577                                struct drm_crtc_state *crtc_state,
1578                                struct drm_connector_state *conn_state)
1579 {
1580         struct tegra_output *output = encoder_to_output(encoder);
1581         struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1582         unsigned long pclk = crtc_state->mode.clock * 1000;
1583         struct tegra_sor *sor = to_sor(output);
1584         int err;
1585
1586         err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
1587                                          pclk, 0);
1588         if (err < 0) {
1589                 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1590                 return err;
1591         }
1592
1593         return 0;
1594 }
1595
1596 static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = {
1597         .disable = tegra_sor_edp_disable,
1598         .enable = tegra_sor_edp_enable,
1599         .atomic_check = tegra_sor_encoder_atomic_check,
1600 };
1601
1602 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
1603 {
1604         u32 value = 0;
1605         size_t i;
1606
1607         for (i = size; i > 0; i--)
1608                 value = (value << 8) | ptr[i - 1];
1609
1610         return value;
1611 }
1612
1613 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
1614                                           const void *data, size_t size)
1615 {
1616         const u8 *ptr = data;
1617         unsigned long offset;
1618         size_t i, j;
1619         u32 value;
1620
1621         switch (ptr[0]) {
1622         case HDMI_INFOFRAME_TYPE_AVI:
1623                 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
1624                 break;
1625
1626         case HDMI_INFOFRAME_TYPE_AUDIO:
1627                 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
1628                 break;
1629
1630         case HDMI_INFOFRAME_TYPE_VENDOR:
1631                 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
1632                 break;
1633
1634         default:
1635                 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
1636                         ptr[0]);
1637                 return;
1638         }
1639
1640         value = INFOFRAME_HEADER_TYPE(ptr[0]) |
1641                 INFOFRAME_HEADER_VERSION(ptr[1]) |
1642                 INFOFRAME_HEADER_LEN(ptr[2]);
1643         tegra_sor_writel(sor, value, offset);
1644         offset++;
1645
1646         /*
1647          * Each subpack contains 7 bytes, divided into:
1648          * - subpack_low: bytes 0 - 3
1649          * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
1650          */
1651         for (i = 3, j = 0; i < size; i += 7, j += 8) {
1652                 size_t rem = size - i, num = min_t(size_t, rem, 4);
1653
1654                 value = tegra_sor_hdmi_subpack(&ptr[i], num);
1655                 tegra_sor_writel(sor, value, offset++);
1656
1657                 num = min_t(size_t, rem - num, 3);
1658
1659                 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
1660                 tegra_sor_writel(sor, value, offset++);
1661         }
1662 }
1663
1664 static int
1665 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
1666                                    const struct drm_display_mode *mode)
1667 {
1668         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
1669         struct hdmi_avi_infoframe frame;
1670         u32 value;
1671         int err;
1672
1673         /* disable AVI infoframe */
1674         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1675         value &= ~INFOFRAME_CTRL_SINGLE;
1676         value &= ~INFOFRAME_CTRL_OTHER;
1677         value &= ~INFOFRAME_CTRL_ENABLE;
1678         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1679
1680         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1681         if (err < 0) {
1682                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
1683                 return err;
1684         }
1685
1686         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1687         if (err < 0) {
1688                 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
1689                 return err;
1690         }
1691
1692         tegra_sor_hdmi_write_infopack(sor, buffer, err);
1693
1694         /* enable AVI infoframe */
1695         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1696         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
1697         value |= INFOFRAME_CTRL_ENABLE;
1698         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1699
1700         return 0;
1701 }
1702
1703 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
1704 {
1705         u32 value;
1706
1707         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
1708         value &= ~INFOFRAME_CTRL_ENABLE;
1709         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
1710 }
1711
1712 static struct tegra_sor_hdmi_settings *
1713 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
1714 {
1715         unsigned int i;
1716
1717         for (i = 0; i < sor->num_settings; i++)
1718                 if (frequency <= sor->settings[i].frequency)
1719                         return &sor->settings[i];
1720
1721         return NULL;
1722 }
1723
1724 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
1725 {
1726         struct tegra_output *output = encoder_to_output(encoder);
1727         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1728         struct tegra_sor *sor = to_sor(output);
1729         u32 value;
1730         int err;
1731
1732         err = tegra_sor_detach(sor);
1733         if (err < 0)
1734                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1735
1736         tegra_sor_writel(sor, 0, SOR_STATE1);
1737         tegra_sor_update(sor);
1738
1739         /* disable display to SOR clock */
1740         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1741         value &= ~SOR1_TIMING_CYA;
1742         value &= ~SOR1_ENABLE;
1743         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1744
1745         tegra_dc_commit(dc);
1746
1747         err = tegra_sor_power_down(sor);
1748         if (err < 0)
1749                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1750
1751         err = tegra_io_rail_power_off(TEGRA_IO_RAIL_HDMI);
1752         if (err < 0)
1753                 dev_err(sor->dev, "failed to power off HDMI rail: %d\n", err);
1754
1755         reset_control_assert(sor->rst);
1756         usleep_range(1000, 2000);
1757         clk_disable_unprepare(sor->clk);
1758 }
1759
1760 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
1761 {
1762         struct tegra_output *output = encoder_to_output(encoder);
1763         unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
1764         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1765         unsigned int vbe, vse, hbe, hse, vbs, hbs, div;
1766         struct tegra_sor_hdmi_settings *settings;
1767         struct tegra_sor *sor = to_sor(output);
1768         struct drm_display_mode *mode;
1769         struct drm_display_info *info;
1770         u32 value;
1771         int err;
1772
1773         mode = &encoder->crtc->state->adjusted_mode;
1774         info = &output->connector.display_info;
1775
1776         err = clk_prepare_enable(sor->clk);
1777         if (err < 0)
1778                 dev_err(sor->dev, "failed to enable clock: %d\n", err);
1779
1780         usleep_range(1000, 2000);
1781
1782         reset_control_deassert(sor->rst);
1783
1784         err = clk_set_parent(sor->clk, sor->clk_safe);
1785         if (err < 0)
1786                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1787
1788         div = clk_get_rate(sor->clk) / 1000000 * 4;
1789
1790         err = tegra_io_rail_power_on(TEGRA_IO_RAIL_HDMI);
1791         if (err < 0)
1792                 dev_err(sor->dev, "failed to power on HDMI rail: %d\n", err);
1793
1794         usleep_range(20, 100);
1795
1796         value = tegra_sor_readl(sor, SOR_PLL2);
1797         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1798         tegra_sor_writel(sor, value, SOR_PLL2);
1799
1800         usleep_range(20, 100);
1801
1802         value = tegra_sor_readl(sor, SOR_PLL3);
1803         value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
1804         tegra_sor_writel(sor, value, SOR_PLL3);
1805
1806         value = tegra_sor_readl(sor, SOR_PLL0);
1807         value &= ~SOR_PLL0_VCOPD;
1808         value &= ~SOR_PLL0_PWR;
1809         tegra_sor_writel(sor, value, SOR_PLL0);
1810
1811         value = tegra_sor_readl(sor, SOR_PLL2);
1812         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1813         tegra_sor_writel(sor, value, SOR_PLL2);
1814
1815         usleep_range(200, 400);
1816
1817         value = tegra_sor_readl(sor, SOR_PLL2);
1818         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1819         value &= ~SOR_PLL2_PORT_POWERDOWN;
1820         tegra_sor_writel(sor, value, SOR_PLL2);
1821
1822         usleep_range(20, 100);
1823
1824         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1825         value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
1826                  SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
1827         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1828
1829         while (true) {
1830                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1831                 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
1832                         break;
1833
1834                 usleep_range(250, 1000);
1835         }
1836
1837         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
1838                 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
1839         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1840
1841         while (true) {
1842                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1843                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1844                         break;
1845
1846                 usleep_range(250, 1000);
1847         }
1848
1849         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1850         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1851         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1852
1853         if (mode->clock < 340000)
1854                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
1855         else
1856                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
1857
1858         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
1859         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1860
1861         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
1862         value |= SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
1863         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
1864         value |= SOR_DP_SPARE_SEQ_ENABLE;
1865         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
1866
1867         value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
1868                 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
1869         tegra_sor_writel(sor, value, SOR_SEQ_CTL);
1870
1871         value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
1872                 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
1873         tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
1874         tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
1875
1876         /* program the reference clock */
1877         value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
1878         tegra_sor_writel(sor, value, SOR_REFCLK);
1879
1880         /* XXX don't hardcode */
1881         value = SOR_XBAR_CTRL_LINK1_XSEL(4, 4) |
1882                 SOR_XBAR_CTRL_LINK1_XSEL(3, 3) |
1883                 SOR_XBAR_CTRL_LINK1_XSEL(2, 2) |
1884                 SOR_XBAR_CTRL_LINK1_XSEL(1, 1) |
1885                 SOR_XBAR_CTRL_LINK1_XSEL(0, 0) |
1886                 SOR_XBAR_CTRL_LINK0_XSEL(4, 4) |
1887                 SOR_XBAR_CTRL_LINK0_XSEL(3, 3) |
1888                 SOR_XBAR_CTRL_LINK0_XSEL(2, 0) |
1889                 SOR_XBAR_CTRL_LINK0_XSEL(1, 1) |
1890                 SOR_XBAR_CTRL_LINK0_XSEL(0, 2);
1891         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
1892
1893         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
1894
1895         err = clk_set_parent(sor->clk, sor->clk_parent);
1896         if (err < 0)
1897                 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
1898
1899         value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
1900
1901         /* XXX is this the proper check? */
1902         if (mode->clock < 75000)
1903                 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
1904
1905         tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
1906
1907         max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
1908
1909         value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
1910                 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
1911         tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
1912
1913         /* H_PULSE2 setup */
1914         pulse_start = h_ref_to_sync + (mode->hsync_end - mode->hsync_start) +
1915                       (mode->htotal - mode->hsync_end) - 10;
1916
1917         value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
1918                 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
1919         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
1920
1921         value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
1922         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
1923
1924         value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
1925         value |= H_PULSE2_ENABLE;
1926         tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
1927
1928         /* infoframe setup */
1929         err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
1930         if (err < 0)
1931                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
1932
1933         /* XXX HDMI audio support not implemented yet */
1934         tegra_sor_hdmi_disable_audio_infoframe(sor);
1935
1936         /* use single TMDS protocol */
1937         value = tegra_sor_readl(sor, SOR_STATE1);
1938         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
1939         value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
1940         tegra_sor_writel(sor, value, SOR_STATE1);
1941
1942         /* power up pad calibration */
1943         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1944         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
1945         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1946
1947         /* production settings */
1948         settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
1949         if (!settings) {
1950                 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
1951                         mode->clock * 1000);
1952                 return;
1953         }
1954
1955         value = tegra_sor_readl(sor, SOR_PLL0);
1956         value &= ~SOR_PLL0_ICHPMP_MASK;
1957         value &= ~SOR_PLL0_VCOCAP_MASK;
1958         value |= SOR_PLL0_ICHPMP(settings->ichpmp);
1959         value |= SOR_PLL0_VCOCAP(settings->vcocap);
1960         tegra_sor_writel(sor, value, SOR_PLL0);
1961
1962         tegra_sor_dp_term_calibrate(sor);
1963
1964         value = tegra_sor_readl(sor, SOR_PLL1);
1965         value &= ~SOR_PLL1_LOADADJ_MASK;
1966         value |= SOR_PLL1_LOADADJ(settings->loadadj);
1967         tegra_sor_writel(sor, value, SOR_PLL1);
1968
1969         value = tegra_sor_readl(sor, SOR_PLL3);
1970         value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
1971         value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref);
1972         tegra_sor_writel(sor, value, SOR_PLL3);
1973
1974         value = settings->drive_current[0] << 24 |
1975                 settings->drive_current[1] << 16 |
1976                 settings->drive_current[2] <<  8 |
1977                 settings->drive_current[3] <<  0;
1978         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
1979
1980         value = settings->preemphasis[0] << 24 |
1981                 settings->preemphasis[1] << 16 |
1982                 settings->preemphasis[2] <<  8 |
1983                 settings->preemphasis[3] <<  0;
1984         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
1985
1986         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1987         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
1988         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
1989         value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu);
1990         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1991
1992         /* power down pad calibration */
1993         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1994         value |= SOR_DP_PADCTL_PAD_CAL_PD;
1995         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1996
1997         /* miscellaneous display controller settings */
1998         value = VSYNC_H_POSITION(1);
1999         tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2000
2001         value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2002         value &= ~DITHER_CONTROL_MASK;
2003         value &= ~BASE_COLOR_SIZE_MASK;
2004
2005         switch (info->bpc) {
2006         case 6:
2007                 value |= BASE_COLOR_SIZE_666;
2008                 break;
2009
2010         case 8:
2011                 value |= BASE_COLOR_SIZE_888;
2012                 break;
2013
2014         default:
2015                 WARN(1, "%u bits-per-color not supported\n", info->bpc);
2016                 break;
2017         }
2018
2019         tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2020
2021         err = tegra_sor_power_up(sor, 250);
2022         if (err < 0)
2023                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2024
2025         /* configure mode */
2026         value = tegra_sor_readl(sor, SOR_STATE1);
2027         value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
2028         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
2029         value &= ~SOR_STATE_ASY_OWNER_MASK;
2030
2031         value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
2032                  SOR_STATE_ASY_OWNER(dc->pipe + 1);
2033
2034         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
2035                 value &= ~SOR_STATE_ASY_HSYNCPOL;
2036
2037         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2038                 value |= SOR_STATE_ASY_HSYNCPOL;
2039
2040         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
2041                 value &= ~SOR_STATE_ASY_VSYNCPOL;
2042
2043         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2044                 value |= SOR_STATE_ASY_VSYNCPOL;
2045
2046         switch (info->bpc) {
2047         case 8:
2048                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
2049                 break;
2050
2051         case 6:
2052                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
2053                 break;
2054
2055         default:
2056                 BUG();
2057                 break;
2058         }
2059
2060         tegra_sor_writel(sor, value, SOR_STATE1);
2061
2062         value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe));
2063         value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2064         value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2065         tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe));
2066
2067         value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe));
2068         value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2069         value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2070         tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe));
2071
2072         /*
2073          * TODO: The video timing programming below doesn't seem to match the
2074          * register definitions.
2075          */
2076
2077         value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
2078         tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe));
2079
2080         /* sync end = sync width - 1 */
2081         vse = mode->vsync_end - mode->vsync_start - 1;
2082         hse = mode->hsync_end - mode->hsync_start - 1;
2083
2084         value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
2085         tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe));
2086
2087         /* blank end = sync end + back porch */
2088         vbe = vse + (mode->vtotal - mode->vsync_end);
2089         hbe = hse + (mode->htotal - mode->hsync_end);
2090
2091         value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
2092         tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe));
2093
2094         /* blank start = blank end + active */
2095         vbs = vbe + mode->vdisplay;
2096         hbs = hbe + mode->hdisplay;
2097
2098         value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
2099         tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe));
2100
2101         tegra_sor_writel(sor, 0x1, SOR_HEAD_STATE5(dc->pipe));
2102
2103         tegra_sor_update(sor);
2104
2105         err = tegra_sor_attach(sor);
2106         if (err < 0)
2107                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2108
2109         /* enable display to SOR clock and generate HDMI preamble */
2110         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2111         value |= SOR1_ENABLE | SOR1_TIMING_CYA;
2112         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2113
2114         tegra_dc_commit(dc);
2115
2116         err = tegra_sor_wakeup(sor);
2117         if (err < 0)
2118                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2119 }
2120
2121 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2122         .disable = tegra_sor_hdmi_disable,
2123         .enable = tegra_sor_hdmi_enable,
2124         .atomic_check = tegra_sor_encoder_atomic_check,
2125 };
2126
2127 static int tegra_sor_init(struct host1x_client *client)
2128 {
2129         struct drm_device *drm = dev_get_drvdata(client->parent);
2130         const struct drm_encoder_helper_funcs *helpers = NULL;
2131         struct tegra_sor *sor = host1x_client_to_sor(client);
2132         int connector = DRM_MODE_CONNECTOR_Unknown;
2133         int encoder = DRM_MODE_ENCODER_NONE;
2134         int err;
2135
2136         if (!sor->aux) {
2137                 if (sor->soc->supports_hdmi) {
2138                         connector = DRM_MODE_CONNECTOR_HDMIA;
2139                         encoder = DRM_MODE_ENCODER_TMDS;
2140                         helpers = &tegra_sor_hdmi_helpers;
2141                 } else if (sor->soc->supports_lvds) {
2142                         connector = DRM_MODE_CONNECTOR_LVDS;
2143                         encoder = DRM_MODE_ENCODER_LVDS;
2144                 }
2145         } else {
2146                 if (sor->soc->supports_edp) {
2147                         connector = DRM_MODE_CONNECTOR_eDP;
2148                         encoder = DRM_MODE_ENCODER_TMDS;
2149                         helpers = &tegra_sor_edp_helpers;
2150                 } else if (sor->soc->supports_dp) {
2151                         connector = DRM_MODE_CONNECTOR_DisplayPort;
2152                         encoder = DRM_MODE_ENCODER_TMDS;
2153                 }
2154         }
2155
2156         sor->output.dev = sor->dev;
2157
2158         drm_connector_init(drm, &sor->output.connector,
2159                            &tegra_sor_connector_funcs,
2160                            connector);
2161         drm_connector_helper_add(&sor->output.connector,
2162                                  &tegra_sor_connector_helper_funcs);
2163         sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
2164
2165         drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
2166                          encoder, NULL);
2167         drm_encoder_helper_add(&sor->output.encoder, helpers);
2168
2169         drm_mode_connector_attach_encoder(&sor->output.connector,
2170                                           &sor->output.encoder);
2171         drm_connector_register(&sor->output.connector);
2172
2173         err = tegra_output_init(drm, &sor->output);
2174         if (err < 0) {
2175                 dev_err(client->dev, "failed to initialize output: %d\n", err);
2176                 return err;
2177         }
2178
2179         sor->output.encoder.possible_crtcs = 0x3;
2180
2181         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2182                 err = tegra_sor_debugfs_init(sor, drm->primary);
2183                 if (err < 0)
2184                         dev_err(sor->dev, "debugfs setup failed: %d\n", err);
2185         }
2186
2187         if (sor->aux) {
2188                 err = drm_dp_aux_attach(sor->aux, &sor->output);
2189                 if (err < 0) {
2190                         dev_err(sor->dev, "failed to attach DP: %d\n", err);
2191                         return err;
2192                 }
2193         }
2194
2195         /*
2196          * XXX: Remove this reset once proper hand-over from firmware to
2197          * kernel is possible.
2198          */
2199         err = reset_control_assert(sor->rst);
2200         if (err < 0) {
2201                 dev_err(sor->dev, "failed to assert SOR reset: %d\n", err);
2202                 return err;
2203         }
2204
2205         err = clk_prepare_enable(sor->clk);
2206         if (err < 0) {
2207                 dev_err(sor->dev, "failed to enable clock: %d\n", err);
2208                 return err;
2209         }
2210
2211         usleep_range(1000, 3000);
2212
2213         err = reset_control_deassert(sor->rst);
2214         if (err < 0) {
2215                 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", err);
2216                 return err;
2217         }
2218
2219         err = clk_prepare_enable(sor->clk_safe);
2220         if (err < 0)
2221                 return err;
2222
2223         err = clk_prepare_enable(sor->clk_dp);
2224         if (err < 0)
2225                 return err;
2226
2227         return 0;
2228 }
2229
2230 static int tegra_sor_exit(struct host1x_client *client)
2231 {
2232         struct tegra_sor *sor = host1x_client_to_sor(client);
2233         int err;
2234
2235         tegra_output_exit(&sor->output);
2236
2237         if (sor->aux) {
2238                 err = drm_dp_aux_detach(sor->aux);
2239                 if (err < 0) {
2240                         dev_err(sor->dev, "failed to detach DP: %d\n", err);
2241                         return err;
2242                 }
2243         }
2244
2245         clk_disable_unprepare(sor->clk_safe);
2246         clk_disable_unprepare(sor->clk_dp);
2247         clk_disable_unprepare(sor->clk);
2248
2249         if (IS_ENABLED(CONFIG_DEBUG_FS))
2250                 tegra_sor_debugfs_exit(sor);
2251
2252         return 0;
2253 }
2254
2255 static const struct host1x_client_ops sor_client_ops = {
2256         .init = tegra_sor_init,
2257         .exit = tegra_sor_exit,
2258 };
2259
2260 static const struct tegra_sor_ops tegra_sor_edp_ops = {
2261         .name = "eDP",
2262 };
2263
2264 static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2265 {
2266         int err;
2267
2268         sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io");
2269         if (IS_ERR(sor->avdd_io_supply)) {
2270                 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
2271                         PTR_ERR(sor->avdd_io_supply));
2272                 return PTR_ERR(sor->avdd_io_supply);
2273         }
2274
2275         err = regulator_enable(sor->avdd_io_supply);
2276         if (err < 0) {
2277                 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2278                         err);
2279                 return err;
2280         }
2281
2282         sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll");
2283         if (IS_ERR(sor->vdd_pll_supply)) {
2284                 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
2285                         PTR_ERR(sor->vdd_pll_supply));
2286                 return PTR_ERR(sor->vdd_pll_supply);
2287         }
2288
2289         err = regulator_enable(sor->vdd_pll_supply);
2290         if (err < 0) {
2291                 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2292                         err);
2293                 return err;
2294         }
2295
2296         sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2297         if (IS_ERR(sor->hdmi_supply)) {
2298                 dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
2299                         PTR_ERR(sor->hdmi_supply));
2300                 return PTR_ERR(sor->hdmi_supply);
2301         }
2302
2303         err = regulator_enable(sor->hdmi_supply);
2304         if (err < 0) {
2305                 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
2306                 return err;
2307         }
2308
2309         return 0;
2310 }
2311
2312 static int tegra_sor_hdmi_remove(struct tegra_sor *sor)
2313 {
2314         regulator_disable(sor->hdmi_supply);
2315         regulator_disable(sor->vdd_pll_supply);
2316         regulator_disable(sor->avdd_io_supply);
2317
2318         return 0;
2319 }
2320
2321 static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
2322         .name = "HDMI",
2323         .probe = tegra_sor_hdmi_probe,
2324         .remove = tegra_sor_hdmi_remove,
2325 };
2326
2327 static const struct tegra_sor_soc tegra124_sor = {
2328         .supports_edp = true,
2329         .supports_lvds = true,
2330         .supports_hdmi = false,
2331         .supports_dp = false,
2332 };
2333
2334 static const struct tegra_sor_soc tegra210_sor = {
2335         .supports_edp = true,
2336         .supports_lvds = false,
2337         .supports_hdmi = false,
2338         .supports_dp = false,
2339 };
2340
2341 static const struct tegra_sor_soc tegra210_sor1 = {
2342         .supports_edp = false,
2343         .supports_lvds = false,
2344         .supports_hdmi = true,
2345         .supports_dp = true,
2346
2347         .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
2348         .settings = tegra210_sor_hdmi_defaults,
2349 };
2350
2351 static const struct of_device_id tegra_sor_of_match[] = {
2352         { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
2353         { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
2354         { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
2355         { },
2356 };
2357 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
2358
2359 static int tegra_sor_probe(struct platform_device *pdev)
2360 {
2361         const struct of_device_id *match;
2362         struct device_node *np;
2363         struct tegra_sor *sor;
2364         struct resource *regs;
2365         int err;
2366
2367         match = of_match_device(tegra_sor_of_match, &pdev->dev);
2368
2369         sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
2370         if (!sor)
2371                 return -ENOMEM;
2372
2373         sor->output.dev = sor->dev = &pdev->dev;
2374         sor->soc = match->data;
2375
2376         sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
2377                                      sor->soc->num_settings *
2378                                         sizeof(*sor->settings),
2379                                      GFP_KERNEL);
2380         if (!sor->settings)
2381                 return -ENOMEM;
2382
2383         sor->num_settings = sor->soc->num_settings;
2384
2385         np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
2386         if (np) {
2387                 sor->aux = drm_dp_aux_find_by_of_node(np);
2388                 of_node_put(np);
2389
2390                 if (!sor->aux)
2391                         return -EPROBE_DEFER;
2392         }
2393
2394         if (!sor->aux) {
2395                 if (sor->soc->supports_hdmi) {
2396                         sor->ops = &tegra_sor_hdmi_ops;
2397                 } else if (sor->soc->supports_lvds) {
2398                         dev_err(&pdev->dev, "LVDS not supported yet\n");
2399                         return -ENODEV;
2400                 } else {
2401                         dev_err(&pdev->dev, "unknown (non-DP) support\n");
2402                         return -ENODEV;
2403                 }
2404         } else {
2405                 if (sor->soc->supports_edp) {
2406                         sor->ops = &tegra_sor_edp_ops;
2407                 } else if (sor->soc->supports_dp) {
2408                         dev_err(&pdev->dev, "DisplayPort not supported yet\n");
2409                         return -ENODEV;
2410                 } else {
2411                         dev_err(&pdev->dev, "unknown (DP) support\n");
2412                         return -ENODEV;
2413                 }
2414         }
2415
2416         err = tegra_output_probe(&sor->output);
2417         if (err < 0) {
2418                 dev_err(&pdev->dev, "failed to probe output: %d\n", err);
2419                 return err;
2420         }
2421
2422         if (sor->ops && sor->ops->probe) {
2423                 err = sor->ops->probe(sor);
2424                 if (err < 0) {
2425                         dev_err(&pdev->dev, "failed to probe %s: %d\n",
2426                                 sor->ops->name, err);
2427                         goto output;
2428                 }
2429         }
2430
2431         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2432         sor->regs = devm_ioremap_resource(&pdev->dev, regs);
2433         if (IS_ERR(sor->regs)) {
2434                 err = PTR_ERR(sor->regs);
2435                 goto remove;
2436         }
2437
2438         sor->rst = devm_reset_control_get(&pdev->dev, "sor");
2439         if (IS_ERR(sor->rst)) {
2440                 err = PTR_ERR(sor->rst);
2441                 dev_err(&pdev->dev, "failed to get reset control: %d\n", err);
2442                 goto remove;
2443         }
2444
2445         sor->clk = devm_clk_get(&pdev->dev, NULL);
2446         if (IS_ERR(sor->clk)) {
2447                 err = PTR_ERR(sor->clk);
2448                 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
2449                 goto remove;
2450         }
2451
2452         sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
2453         if (IS_ERR(sor->clk_parent)) {
2454                 err = PTR_ERR(sor->clk_parent);
2455                 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
2456                 goto remove;
2457         }
2458
2459         sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
2460         if (IS_ERR(sor->clk_safe)) {
2461                 err = PTR_ERR(sor->clk_safe);
2462                 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
2463                 goto remove;
2464         }
2465
2466         sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
2467         if (IS_ERR(sor->clk_dp)) {
2468                 err = PTR_ERR(sor->clk_dp);
2469                 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
2470                 goto remove;
2471         }
2472
2473         INIT_LIST_HEAD(&sor->client.list);
2474         sor->client.ops = &sor_client_ops;
2475         sor->client.dev = &pdev->dev;
2476
2477         err = host1x_client_register(&sor->client);
2478         if (err < 0) {
2479                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2480                         err);
2481                 goto remove;
2482         }
2483
2484         platform_set_drvdata(pdev, sor);
2485
2486         return 0;
2487
2488 remove:
2489         if (sor->ops && sor->ops->remove)
2490                 sor->ops->remove(sor);
2491 output:
2492         tegra_output_remove(&sor->output);
2493         return err;
2494 }
2495
2496 static int tegra_sor_remove(struct platform_device *pdev)
2497 {
2498         struct tegra_sor *sor = platform_get_drvdata(pdev);
2499         int err;
2500
2501         err = host1x_client_unregister(&sor->client);
2502         if (err < 0) {
2503                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2504                         err);
2505                 return err;
2506         }
2507
2508         if (sor->ops && sor->ops->remove) {
2509                 err = sor->ops->remove(sor);
2510                 if (err < 0)
2511                         dev_err(&pdev->dev, "failed to remove SOR: %d\n", err);
2512         }
2513
2514         tegra_output_remove(&sor->output);
2515
2516         return 0;
2517 }
2518
2519 struct platform_driver tegra_sor_driver = {
2520         .driver = {
2521                 .name = "tegra-sor",
2522                 .of_match_table = tegra_sor_of_match,
2523         },
2524         .probe = tegra_sor_probe,
2525         .remove = tegra_sor_remove,
2526 };