drivers/gpu/drm/tilcdc/tilcdc_crtc.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_crtc.h>
  21 #include <drm/drm_flip_work.h>
  22 #include <drm/drm_plane_helper.h>
  23
  24 #include "tilcdc_drv.h"
  25 #include "tilcdc_regs.h"
  26
  27 #define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000
  28
  29 struct tilcdc_crtc {
  30         struct drm_crtc base;
  31
  32         struct drm_plane primary;
  33         const struct tilcdc_panel_info *info;
  34         struct drm_pending_vblank_event *event;
  35         bool enabled;
  36         wait_queue_head_t frame_done_wq;
  37         bool frame_done;
  38         spinlock_t irq_lock;
  39
  40         ktime_t last_vblank;
  41
  42         struct drm_framebuffer *curr_fb;
  43         struct drm_framebuffer *next_fb;
  44
  45         /* for deferred fb unref's: */
  46         struct drm_flip_work unref_work;
  47
  48         /* Only set if an external encoder is connected */
  49         bool simulate_vesa_sync;
  50
  51         int sync_lost_count;
  52         bool frame_intact;
  53 };
  54 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
  55
  56 static void unref_worker(struct drm_flip_work *work, void *val)
  57 {
  58         struct tilcdc_crtc *tilcdc_crtc =
  59                 container_of(work, struct tilcdc_crtc, unref_work);
  60         struct drm_device *dev = tilcdc_crtc->base.dev;
  61
  62         mutex_lock(&dev->mode_config.mutex);
  63         drm_framebuffer_unreference(val);
  64         mutex_unlock(&dev->mode_config.mutex);
  65 }
  66
  67 static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
  68 {
  69         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
  70         struct drm_device *dev = crtc->dev;
  71         struct drm_gem_cma_object *gem;
  72         unsigned int depth, bpp;
  73         dma_addr_t start, end;
  74         u64 dma_base_and_ceiling;
  75
  76         drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
  77         gem = drm_fb_cma_get_gem_obj(fb, 0);
  78
  79         start = gem->paddr + fb->offsets[0] +
  80                 crtc->y * fb->pitches[0] +
  81                 crtc->x * bpp / 8;
  82
  83         end = start + (crtc->mode.vdisplay * fb->pitches[0]);
  84
  85         /* Write LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG
  86          * with a single insruction, if available. This should make it more
  87          * unlikely that LCDC would fetch the DMA addresses in the middle of
  88          * an update.
  89          */
  90         dma_base_and_ceiling = (u64)(end - 1) << 32 | start;
  91         tilcdc_write64(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_base_and_ceiling);
  92
  93         if (tilcdc_crtc->curr_fb)
  94                 drm_flip_work_queue(&tilcdc_crtc->unref_work,
  95                         tilcdc_crtc->curr_fb);
  96
  97         tilcdc_crtc->curr_fb = fb;
  98 }
  99
 100 static void tilcdc_crtc_enable_irqs(struct drm_device *dev)
 101 {
 102         struct tilcdc_drm_private *priv = dev->dev_private;
 103
 104         tilcdc_clear_irqstatus(dev, 0xffffffff);
 105
 106         if (priv->rev == 1) {
 107                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
 108                         LCDC_V1_UNDERFLOW_INT_ENA);
 109                 tilcdc_set(dev, LCDC_DMA_CTRL_REG,
 110                         LCDC_V1_END_OF_FRAME_INT_ENA);
 111         } else {
 112                 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG,
 113                         LCDC_V2_UNDERFLOW_INT_ENA |
 114                         LCDC_V2_END_OF_FRAME0_INT_ENA |
 115                         LCDC_FRAME_DONE | LCDC_SYNC_LOST);
 116         }
 117 }
 118
 119 static void tilcdc_crtc_disable_irqs(struct drm_device *dev)
 120 {
 121         struct tilcdc_drm_private *priv = dev->dev_private;
 122
 123         /* disable irqs that we might have enabled: */
 124         if (priv->rev == 1) {
 125                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
 126                         LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
 127                 tilcdc_clear(dev, LCDC_DMA_CTRL_REG,
 128                         LCDC_V1_END_OF_FRAME_INT_ENA);
 129         } else {
 130                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
 131                         LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
 132                         LCDC_V2_END_OF_FRAME0_INT_ENA |
 133                         LCDC_FRAME_DONE | LCDC_SYNC_LOST);
 134         }
 135 }
 136
 137 static void reset(struct drm_crtc *crtc)
 138 {
 139         struct drm_device *dev = crtc->dev;
 140         struct tilcdc_drm_private *priv = dev->dev_private;
 141
 142         if (priv->rev != 2)
 143                 return;
 144
 145         tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 146         usleep_range(250, 1000);
 147         tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 148 }
 149
 150 static void tilcdc_crtc_enable(struct drm_crtc *crtc)
 151 {
 152         struct drm_device *dev = crtc->dev;
 153         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 154
 155         if (tilcdc_crtc->enabled)
 156                 return;
 157
 158         pm_runtime_get_sync(dev->dev);
 159
 160         reset(crtc);
 161
 162         tilcdc_crtc_enable_irqs(dev);
 163
 164         tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
 165         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY));
 166         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 167
 168         drm_crtc_vblank_on(crtc);
 169
 170         tilcdc_crtc->enabled = true;
 171 }
 172
 173 void tilcdc_crtc_disable(struct drm_crtc *crtc)
 174 {
 175         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 176         struct drm_device *dev = crtc->dev;
 177         struct tilcdc_drm_private *priv = dev->dev_private;
 178
 179         if (!tilcdc_crtc->enabled)
 180                 return;
 181
 182         tilcdc_crtc->frame_done = false;
 183         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 184
 185         /*
 186          * if necessary wait for framedone irq which will still come
 187          * before putting things to sleep..
 188          */
 189         if (priv->rev == 2) {
 190                 int ret = wait_event_timeout(tilcdc_crtc->frame_done_wq,
 191                                              tilcdc_crtc->frame_done,
 192                                              msecs_to_jiffies(500));
 193                 if (ret == 0)
 194                         dev_err(dev->dev, "%s: timeout waiting for framedone\n",
 195                                 __func__);
 196         }
 197
 198         drm_crtc_vblank_off(crtc);
 199
 200         tilcdc_crtc_disable_irqs(dev);
 201
 202         pm_runtime_put_sync(dev->dev);
 203
 204         if (tilcdc_crtc->next_fb) {
 205                 drm_flip_work_queue(&tilcdc_crtc->unref_work,
 206                                     tilcdc_crtc->next_fb);
 207                 tilcdc_crtc->next_fb = NULL;
 208         }
 209
 210         if (tilcdc_crtc->curr_fb) {
 211                 drm_flip_work_queue(&tilcdc_crtc->unref_work,
 212                                     tilcdc_crtc->curr_fb);
 213                 tilcdc_crtc->curr_fb = NULL;
 214         }
 215
 216         drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
 217         tilcdc_crtc->last_vblank = ktime_set(0, 0);
 218
 219         tilcdc_crtc->enabled = false;
 220 }
 221
 222 static bool tilcdc_crtc_is_on(struct drm_crtc *crtc)
 223 {
 224         return crtc->state && crtc->state->enable && crtc->state->active;
 225 }
 226
 227 static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
 228 {
 229         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 230
 231         tilcdc_crtc_disable(crtc);
 232
 233         of_node_put(crtc->port);
 234         drm_crtc_cleanup(crtc);
 235         drm_flip_work_cleanup(&tilcdc_crtc->unref_work);
 236 }
 237
 238 int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
 239                 struct drm_framebuffer *fb,
 240                 struct drm_pending_vblank_event *event)
 241 {
 242         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 243         struct drm_device *dev = crtc->dev;
 244         unsigned long flags;
 245
 246         if (tilcdc_crtc->event) {
 247                 dev_err(dev->dev, "already pending page flip!\n");
 248                 return -EBUSY;
 249         }
 250
 251         drm_framebuffer_reference(fb);
 252
 253         crtc->primary->fb = fb;
 254
 255         spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 256
 257         if (crtc->hwmode.vrefresh && ktime_to_ns(tilcdc_crtc->last_vblank)) {
 258                 ktime_t next_vblank;
 259                 s64 tdiff;
 260
 261                 next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,
 262                         1000000 / crtc->hwmode.vrefresh);
 263
 264                 tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get()));
 265
 266                 if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US)
 267                         tilcdc_crtc->next_fb = fb;
 268         }
 269
 270         if (tilcdc_crtc->next_fb != fb)
 271                 set_scanout(crtc, fb);
 272
 273         tilcdc_crtc->event = event;
 274
 275         spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 276
 277         return 0;
 278 }
 279
 280 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
 281                 const struct drm_display_mode *mode,
 282                 struct drm_display_mode *adjusted_mode)
 283 {
 284         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 285
 286         if (!tilcdc_crtc->simulate_vesa_sync)
 287                 return true;
 288
 289         /*
 290          * tilcdc does not generate VESA-compliant sync but aligns
 291          * VS on the second edge of HS instead of first edge.
 292          * We use adjusted_mode, to fixup sync by aligning both rising
 293          * edges and add HSKEW offset to fix the sync.
 294          */
 295         adjusted_mode->hskew = mode->hsync_end - mode->hsync_start;
 296         adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW;
 297
 298         if (mode->flags & DRM_MODE_FLAG_NHSYNC) {
 299                 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
 300                 adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC;
 301         } else {
 302                 adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC;
 303                 adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC;
 304         }
 305
 306         return true;
 307 }
 308
 309 static void tilcdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
 310 {
 311         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 312         struct drm_device *dev = crtc->dev;
 313         struct tilcdc_drm_private *priv = dev->dev_private;
 314         const struct tilcdc_panel_info *info = tilcdc_crtc->info;
 315         uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
 316         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 317         struct drm_framebuffer *fb = crtc->primary->state->fb;
 318
 319         if (WARN_ON(!info))
 320                 return;
 321
 322         if (WARN_ON(!fb))
 323                 return;
 324
 325         /* Configure the Burst Size and fifo threshold of DMA: */
 326         reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
 327         switch (info->dma_burst_sz) {
 328         case 1:
 329                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
 330                 break;
 331         case 2:
 332                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
 333                 break;
 334         case 4:
 335                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
 336                 break;
 337         case 8:
 338                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
 339                 break;
 340         case 16:
 341                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
 342                 break;
 343         default:
 344                 dev_err(dev->dev, "invalid burst size\n");
 345                 return;
 346         }
 347         reg |= (info->fifo_th << 8);
 348         tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
 349
 350         /* Configure timings: */
 351         hbp = mode->htotal - mode->hsync_end;
 352         hfp = mode->hsync_start - mode->hdisplay;
 353         hsw = mode->hsync_end - mode->hsync_start;
 354         vbp = mode->vtotal - mode->vsync_end;
 355         vfp = mode->vsync_start - mode->vdisplay;
 356         vsw = mode->vsync_end - mode->vsync_start;
 357
 358         DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
 359             mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
 360
 361         /* Set AC Bias Period and Number of Transitions per Interrupt: */
 362         reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
 363         reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
 364                 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
 365
 366         /*
 367          * subtract one from hfp, hbp, hsw because the hardware uses
 368          * a value of 0 as 1
 369          */
 370         if (priv->rev == 2) {
 371                 /* clear bits we're going to set */
 372                 reg &= ~0x78000033;
 373                 reg |= ((hfp-1) & 0x300) >> 8;
 374                 reg |= ((hbp-1) & 0x300) >> 4;
 375                 reg |= ((hsw-1) & 0x3c0) << 21;
 376         }
 377         tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
 378
 379         reg = (((mode->hdisplay >> 4) - 1) << 4) |
 380                 (((hbp-1) & 0xff) << 24) |
 381                 (((hfp-1) & 0xff) << 16) |
 382                 (((hsw-1) & 0x3f) << 10);
 383         if (priv->rev == 2)
 384                 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
 385         tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
 386
 387         reg = ((mode->vdisplay - 1) & 0x3ff) |
 388                 ((vbp & 0xff) << 24) |
 389                 ((vfp & 0xff) << 16) |
 390                 (((vsw-1) & 0x3f) << 10);
 391         tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
 392
 393         /*
 394          * be sure to set Bit 10 for the V2 LCDC controller,
 395          * otherwise limited to 1024 pixels width, stopping
 396          * 1920x1080 being supported.
 397          */
 398         if (priv->rev == 2) {
 399                 if ((mode->vdisplay - 1) & 0x400) {
 400                         tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
 401                                 LCDC_LPP_B10);
 402                 } else {
 403                         tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
 404                                 LCDC_LPP_B10);
 405                 }
 406         }
 407
 408         /* Configure display type: */
 409         reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
 410                 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
 411                   LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK |
 412                   0x000ff000 /* Palette Loading Delay bits */);
 413         reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
 414         if (info->tft_alt_mode)
 415                 reg |= LCDC_TFT_ALT_ENABLE;
 416         if (priv->rev == 2) {
 417                 unsigned int depth, bpp;
 418
 419                 drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
 420                 switch (bpp) {
 421                 case 16:
 422                         break;
 423                 case 32:
 424                         reg |= LCDC_V2_TFT_24BPP_UNPACK;
 425                         /* fallthrough */
 426                 case 24:
 427                         reg |= LCDC_V2_TFT_24BPP_MODE;
 428                         break;
 429                 default:
 430                         dev_err(dev->dev, "invalid pixel format\n");
 431                         return;
 432                 }
 433         }
 434         reg |= info->fdd < 12;
 435         tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
 436
 437         if (info->invert_pxl_clk)
 438                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 439         else
 440                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 441
 442         if (info->sync_ctrl)
 443                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 444         else
 445                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 446
 447         if (info->sync_edge)
 448                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 449         else
 450                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 451
 452         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 453                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 454         else
 455                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 456
 457         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 458                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 459         else
 460                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 461
 462         if (info->raster_order)
 463                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 464         else
 465                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 466
 467         drm_framebuffer_reference(fb);
 468
 469         set_scanout(crtc, fb);
 470
 471         tilcdc_crtc_update_clk(crtc);
 472
 473         crtc->hwmode = crtc->state->adjusted_mode;
 474 }
 475
 476 static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc,
 477                                     struct drm_crtc_state *state)
 478 {
 479         struct drm_display_mode *mode = &state->mode;
 480         int ret;
 481
 482         /* If we are not active we don't care */
 483         if (!state->active)
 484                 return 0;
 485
 486         if (state->state->planes[0].ptr != crtc->primary ||
 487             state->state->planes[0].state == NULL ||
 488             state->state->planes[0].state->crtc != crtc) {
 489                 dev_dbg(crtc->dev->dev, "CRTC primary plane must be present");
 490                 return -EINVAL;
 491         }
 492
 493         ret = tilcdc_crtc_mode_valid(crtc, mode);
 494         if (ret) {
 495                 dev_dbg(crtc->dev->dev, "Mode \"%s\" not valid", mode->name);
 496                 return -EINVAL;
 497         }
 498
 499         return 0;
 500 }
 501
 502 static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
 503         .destroy        = tilcdc_crtc_destroy,
 504         .set_config     = drm_atomic_helper_set_config,
 505         .page_flip      = drm_atomic_helper_page_flip,
 506         .reset          = drm_atomic_helper_crtc_reset,
 507         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 508         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 509 };
 510
 511 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
 512                 .mode_fixup     = tilcdc_crtc_mode_fixup,
 513                 .enable         = tilcdc_crtc_enable,
 514                 .disable        = tilcdc_crtc_disable,
 515                 .atomic_check   = tilcdc_crtc_atomic_check,
 516                 .mode_set_nofb  = tilcdc_crtc_mode_set_nofb,
 517 };
 518
 519 int tilcdc_crtc_max_width(struct drm_crtc *crtc)
 520 {
 521         struct drm_device *dev = crtc->dev;
 522         struct tilcdc_drm_private *priv = dev->dev_private;
 523         int max_width = 0;
 524
 525         if (priv->rev == 1)
 526                 max_width = 1024;
 527         else if (priv->rev == 2)
 528                 max_width = 2048;
 529
 530         return max_width;
 531 }
 532
 533 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
 534 {
 535         struct tilcdc_drm_private *priv = crtc->dev->dev_private;
 536         unsigned int bandwidth;
 537         uint32_t hbp, hfp, hsw, vbp, vfp, vsw;
 538
 539         /*
 540          * check to see if the width is within the range that
 541          * the LCD Controller physically supports
 542          */
 543         if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
 544                 return MODE_VIRTUAL_X;
 545
 546         /* width must be multiple of 16 */
 547         if (mode->hdisplay & 0xf)
 548                 return MODE_VIRTUAL_X;
 549
 550         if (mode->vdisplay > 2048)
 551                 return MODE_VIRTUAL_Y;
 552
 553         DBG("Processing mode %dx%d@%d with pixel clock %d",
 554                 mode->hdisplay, mode->vdisplay,
 555                 drm_mode_vrefresh(mode), mode->clock);
 556
 557         hbp = mode->htotal - mode->hsync_end;
 558         hfp = mode->hsync_start - mode->hdisplay;
 559         hsw = mode->hsync_end - mode->hsync_start;
 560         vbp = mode->vtotal - mode->vsync_end;
 561         vfp = mode->vsync_start - mode->vdisplay;
 562         vsw = mode->vsync_end - mode->vsync_start;
 563
 564         if ((hbp-1) & ~0x3ff) {
 565                 DBG("Pruning mode: Horizontal Back Porch out of range");
 566                 return MODE_HBLANK_WIDE;
 567         }
 568
 569         if ((hfp-1) & ~0x3ff) {
 570                 DBG("Pruning mode: Horizontal Front Porch out of range");
 571                 return MODE_HBLANK_WIDE;
 572         }
 573
 574         if ((hsw-1) & ~0x3ff) {
 575                 DBG("Pruning mode: Horizontal Sync Width out of range");
 576                 return MODE_HSYNC_WIDE;
 577         }
 578
 579         if (vbp & ~0xff) {
 580                 DBG("Pruning mode: Vertical Back Porch out of range");
 581                 return MODE_VBLANK_WIDE;
 582         }
 583
 584         if (vfp & ~0xff) {
 585                 DBG("Pruning mode: Vertical Front Porch out of range");
 586                 return MODE_VBLANK_WIDE;
 587         }
 588
 589         if ((vsw-1) & ~0x3f) {
 590                 DBG("Pruning mode: Vertical Sync Width out of range");
 591                 return MODE_VSYNC_WIDE;
 592         }
 593
 594         /*
 595          * some devices have a maximum allowed pixel clock
 596          * configured from the DT
 597          */
 598         if (mode->clock > priv->max_pixelclock) {
 599                 DBG("Pruning mode: pixel clock too high");
 600                 return MODE_CLOCK_HIGH;
 601         }
 602
 603         /*
 604          * some devices further limit the max horizontal resolution
 605          * configured from the DT
 606          */
 607         if (mode->hdisplay > priv->max_width)
 608                 return MODE_BAD_WIDTH;
 609
 610         /* filter out modes that would require too much memory bandwidth: */
 611         bandwidth = mode->hdisplay * mode->vdisplay *
 612                 drm_mode_vrefresh(mode);
 613         if (bandwidth > priv->max_bandwidth) {
 614                 DBG("Pruning mode: exceeds defined bandwidth limit");
 615                 return MODE_BAD;
 616         }
 617
 618         return MODE_OK;
 619 }
 620
 621 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
 622                 const struct tilcdc_panel_info *info)
 623 {
 624         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 625         tilcdc_crtc->info = info;
 626 }
 627
 628 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
 629                                         bool simulate_vesa_sync)
 630 {
 631         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 632
 633         tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync;
 634 }
 635
 636 void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
 637 {
 638         struct drm_device *dev = crtc->dev;
 639         struct tilcdc_drm_private *priv = dev->dev_private;
 640         unsigned long lcd_clk;
 641         const unsigned clkdiv = 2; /* using a fixed divider of 2 */
 642         int ret;
 643
 644         pm_runtime_get_sync(dev->dev);
 645
 646         tilcdc_crtc_disable(crtc);
 647
 648         /* mode.clock is in KHz, set_rate wants parameter in Hz */
 649         ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv);
 650         if (ret < 0) {
 651                 dev_err(dev->dev, "failed to set display clock rate to: %d\n",
 652                                 crtc->mode.clock);
 653                 goto out;
 654         }
 655
 656         lcd_clk = clk_get_rate(priv->clk);
 657
 658         DBG("lcd_clk=%lu, mode clock=%d, div=%u",
 659                 lcd_clk, crtc->mode.clock, clkdiv);
 660
 661         /* Configure the LCD clock divisor. */
 662         tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |
 663                         LCDC_RASTER_MODE);
 664
 665         if (priv->rev == 2)
 666                 tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
 667                                 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
 668                                 LCDC_V2_CORE_CLK_EN);
 669
 670         if (tilcdc_crtc_is_on(crtc))
 671                 tilcdc_crtc_enable(crtc);
 672
 673 out:
 674         pm_runtime_put_sync(dev->dev);
 675 }
 676
 677 #define SYNC_LOST_COUNT_LIMIT 50
 678
 679 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
 680 {
 681         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 682         struct drm_device *dev = crtc->dev;
 683         struct tilcdc_drm_private *priv = dev->dev_private;
 684         uint32_t stat;
 685
 686         stat = tilcdc_read_irqstatus(dev);
 687         tilcdc_clear_irqstatus(dev, stat);
 688
 689         if (stat & LCDC_END_OF_FRAME0) {
 690                 unsigned long flags;
 691                 bool skip_event = false;
 692                 ktime_t now;
 693
 694                 now = ktime_get();
 695
 696                 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
 697
 698                 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 699
 700                 tilcdc_crtc->last_vblank = now;
 701
 702                 if (tilcdc_crtc->next_fb) {
 703                         set_scanout(crtc, tilcdc_crtc->next_fb);
 704                         tilcdc_crtc->next_fb = NULL;
 705                         skip_event = true;
 706                 }
 707
 708                 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 709
 710                 drm_crtc_handle_vblank(crtc);
 711
 712                 if (!skip_event) {
 713                         struct drm_pending_vblank_event *event;
 714
 715                         spin_lock_irqsave(&dev->event_lock, flags);
 716
 717                         event = tilcdc_crtc->event;
 718                         tilcdc_crtc->event = NULL;
 719                         if (event)
 720                                 drm_crtc_send_vblank_event(crtc, event);
 721
 722                         spin_unlock_irqrestore(&dev->event_lock, flags);
 723                 }
 724
 725                 if (tilcdc_crtc->frame_intact)
 726                         tilcdc_crtc->sync_lost_count = 0;
 727                 else
 728                         tilcdc_crtc->frame_intact = true;
 729         }
 730
 731         if (stat & LCDC_FIFO_UNDERFLOW)
 732                 dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underfow",
 733                                     __func__, stat);
 734
 735         /* For revision 2 only */
 736         if (priv->rev == 2) {
 737                 if (stat & LCDC_FRAME_DONE) {
 738                         tilcdc_crtc->frame_done = true;
 739                         wake_up(&tilcdc_crtc->frame_done_wq);
 740                 }
 741
 742                 if (stat & LCDC_SYNC_LOST) {
 743                         dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost",
 744                                             __func__, stat);
 745                         tilcdc_crtc->frame_intact = false;
 746                         if (tilcdc_crtc->sync_lost_count++ >
 747                             SYNC_LOST_COUNT_LIMIT) {
 748                                 dev_err(dev->dev, "%s(0x%08x): Sync lost flood detected, disabling the interrupt", __func__, stat);
 749                                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
 750                                              LCDC_SYNC_LOST);
 751                         }
 752                 }
 753
 754                 /* Indicate to LCDC that the interrupt service routine has
 755                  * completed, see 13.3.6.1.6 in AM335x TRM.
 756                  */
 757                 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
 758         }
 759
 760         return IRQ_HANDLED;
 761 }
 762
 763 struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
 764 {
 765         struct tilcdc_drm_private *priv = dev->dev_private;
 766         struct tilcdc_crtc *tilcdc_crtc;
 767         struct drm_crtc *crtc;
 768         int ret;
 769
 770         tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL);
 771         if (!tilcdc_crtc) {
 772                 dev_err(dev->dev, "allocation failed\n");
 773                 return NULL;
 774         }
 775
 776         crtc = &tilcdc_crtc->base;
 777
 778         ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary);
 779         if (ret < 0)
 780                 goto fail;
 781
 782         init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
 783
 784         drm_flip_work_init(&tilcdc_crtc->unref_work,
 785                         "unref", unref_worker);
 786
 787         spin_lock_init(&tilcdc_crtc->irq_lock);
 788
 789         ret = drm_crtc_init_with_planes(dev, crtc,
 790                                         &tilcdc_crtc->primary,
 791                                         NULL,
 792                                         &tilcdc_crtc_funcs,
 793                                         "tilcdc crtc");
 794         if (ret < 0)
 795                 goto fail;
 796
 797         drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
 798
 799         if (priv->is_componentized) {
 800                 struct device_node *ports =
 801                         of_get_child_by_name(dev->dev->of_node, "ports");
 802
 803                 if (ports) {
 804                         crtc->port = of_get_child_by_name(ports, "port");
 805                         of_node_put(ports);
 806                 } else {
 807                         crtc->port =
 808                                 of_get_child_by_name(dev->dev->of_node, "port");
 809                 }
 810                 if (!crtc->port) { /* This should never happen */
 811                         dev_err(dev->dev, "Port node not found in %s\n",
 812                                 dev->dev->of_node->full_name);
 813                         goto fail;
 814                 }
 815         }
 816
 817         return crtc;
 818
 819 fail:
 820         tilcdc_crtc_destroy(crtc);
 821         return NULL;
 822 }