2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __TILCDC_DRV_H__
19 #define __TILCDC_DRV_H__
21 #include <linux/clk.h>
22 #include <linux/cpufreq.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/slab.h>
29 #include <linux/of_device.h>
30 #include <linux/list.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_gem_cma_helper.h>
35 #include <drm/drm_fb_cma_helper.h>
37 /* Defaulting to pixel clock defined on AM335x */
38 #define TILCDC_DEFAULT_MAX_PIXELCLOCK 126000
39 /* Defaulting to max width as defined on AM335x */
40 #define TILCDC_DEFAULT_MAX_WIDTH 2048
42 * This may need some tweaking, but want to allow at least 1280x1024@60
43 * with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to
46 #define TILCDC_DEFAULT_MAX_BANDWIDTH (1280*1024*60)
49 struct tilcdc_drm_private {
52 struct clk *clk; /* functional clock */
53 int rev; /* IP revision */
55 /* don't attempt resolutions w/ higher W * H * Hz: */
56 uint32_t max_bandwidth;
58 * Pixel Clock will be restricted to some value as
59 * defined in the device datasheet measured in KHz
61 uint32_t max_pixelclock;
63 * Max allowable width is limited on a per device basis
68 /* The context for pm susped/resume cycle is stored here */
69 struct drm_atomic_state *saved_state;
71 #ifdef CONFIG_CPU_FREQ
72 struct notifier_block freq_transition;
73 unsigned int lcd_fck_rate;
76 struct workqueue_struct *wq;
78 struct drm_fbdev_cma *fbdev;
80 struct drm_crtc *crtc;
82 unsigned int num_encoders;
83 struct drm_encoder *encoders[8];
85 unsigned int num_connectors;
86 struct drm_connector *connectors[8];
87 const struct drm_connector_helper_funcs *connector_funcs[8];
89 bool is_componentized;
92 /* Sub-module for display. Since we don't know at compile time what panels
93 * or display adapter(s) might be present (for ex, off chip dvi/tfp410,
94 * hdmi encoder, various lcd panels), the connector/encoder(s) are split into
95 * separate drivers. If they are probed and found to be present, they
96 * register themselves with tilcdc_register_module().
100 struct tilcdc_module_ops {
101 /* create appropriate encoders/connectors: */
102 int (*modeset_init)(struct tilcdc_module *mod, struct drm_device *dev);
103 #ifdef CONFIG_DEBUG_FS
104 /* create debugfs nodes (can be NULL): */
105 int (*debugfs_init)(struct tilcdc_module *mod, struct drm_minor *minor);
106 /* cleanup debugfs nodes (can be NULL): */
107 void (*debugfs_cleanup)(struct tilcdc_module *mod, struct drm_minor *minor);
111 struct tilcdc_module {
113 struct list_head list;
114 const struct tilcdc_module_ops *funcs;
115 unsigned int preferred_bpp;
118 void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
119 const struct tilcdc_module_ops *funcs);
120 void tilcdc_module_cleanup(struct tilcdc_module *mod);
122 /* Panel config that needs to be set in the crtc, but is not coming from
123 * the mode timings. The display module is expected to call
124 * tilcdc_crtc_set_panel_info() to set this during modeset.
126 struct tilcdc_panel_info {
128 /* AC Bias Pin Frequency */
131 /* AC Bias Pin Transitions per Interrupt */
132 uint32_t ac_bias_intrpt;
135 uint32_t dma_burst_sz;
140 /* FIFO DMA Request Delay */
143 /* TFT Alternative Signal Mapping (Only for active) */
146 /* Invert pixel clock */
149 /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
152 /* Horizontal and Vertical Sync: Control: 0=ignore */
155 /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
156 uint32_t raster_order;
158 /* DMA FIFO threshold */
162 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
164 struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev);
165 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc);
166 void tilcdc_crtc_update_clk(struct drm_crtc *crtc);
167 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
168 const struct tilcdc_panel_info *info);
169 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
170 bool simulate_vesa_sync);
171 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode);
172 int tilcdc_crtc_max_width(struct drm_crtc *crtc);
173 void tilcdc_crtc_disable(struct drm_crtc *crtc);
174 int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
175 struct drm_framebuffer *fb,
176 struct drm_pending_vblank_event *event);
178 int tilcdc_plane_init(struct drm_device *dev, struct drm_plane *plane);
180 #endif /* __TILCDC_DRV_H__ */