drivers/gpu/drm/vc4/vc4_crtc.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 CRTC module
  11  *
  12  * In VC4, the Pixel Valve is what most closely corresponds to the
  13  * DRM's concept of a CRTC.  The PV generates video timings from the
  14  * output's clock plus its configuration.  It pulls scaled pixels from
  15  * the HVS at that timing, and feeds it to the encoder.
  16  *
  17  * However, the DRM CRTC also collects the configuration of all the
  18  * DRM planes attached to it.  As a result, this file also manages
  19  * setup of the VC4 HVS's display elements on the CRTC.
  20  *
  21  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  22  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  23  * image domain can feed either HDMI or the SDTV controller.  The
  24  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  25  * SDTV, etc.) according to which output type is chosen in the mux.
  26  *
  27  * For power management, the pixel valve's registers are all clocked
  28  * by the AXI clock, while the timings and FIFOs make use of the
  29  * output-specific clock.  Since the encoders also directly consume
  30  * the CPRMAN clocks, and know what timings they need, they are the
  31  * ones that set the clock.
  32  */
  33
  34 #include "drm_atomic.h"
  35 #include "drm_atomic_helper.h"
  36 #include "drm_crtc_helper.h"
  37 #include "linux/clk.h"
  38 #include "drm_fb_cma_helper.h"
  39 #include "linux/component.h"
  40 #include "linux/of_device.h"
  41 #include "vc4_drv.h"
  42 #include "vc4_regs.h"
  43
  44 struct vc4_crtc {
  45         struct drm_crtc base;
  46         const struct vc4_crtc_data *data;
  47         void __iomem *regs;
  48
  49         /* Which HVS channel we're using for our CRTC. */
  50         int channel;
  51
  52         u8 lut_r[256];
  53         u8 lut_g[256];
  54         u8 lut_b[256];
  55
  56         struct drm_pending_vblank_event *event;
  57 };
  58
  59 struct vc4_crtc_state {
  60         struct drm_crtc_state base;
  61         /* Dlist area for this CRTC configuration. */
  62         struct drm_mm_node mm;
  63 };
  64
  65 static inline struct vc4_crtc *
  66 to_vc4_crtc(struct drm_crtc *crtc)
  67 {
  68         return (struct vc4_crtc *)crtc;
  69 }
  70
  71 static inline struct vc4_crtc_state *
  72 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
  73 {
  74         return (struct vc4_crtc_state *)crtc_state;
  75 }
  76
  77 struct vc4_crtc_data {
  78         /* Which channel of the HVS this pixelvalve sources from. */
  79         int hvs_channel;
  80
  81         enum vc4_encoder_type encoder0_type;
  82         enum vc4_encoder_type encoder1_type;
  83 };
  84
  85 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  86 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  87
  88 #define CRTC_REG(reg) { reg, #reg }
  89 static const struct {
  90         u32 reg;
  91         const char *name;
  92 } crtc_regs[] = {
  93         CRTC_REG(PV_CONTROL),
  94         CRTC_REG(PV_V_CONTROL),
  95         CRTC_REG(PV_VSYNCD_EVEN),
  96         CRTC_REG(PV_HORZA),
  97         CRTC_REG(PV_HORZB),
  98         CRTC_REG(PV_VERTA),
  99         CRTC_REG(PV_VERTB),
 100         CRTC_REG(PV_VERTA_EVEN),
 101         CRTC_REG(PV_VERTB_EVEN),
 102         CRTC_REG(PV_INTEN),
 103         CRTC_REG(PV_INTSTAT),
 104         CRTC_REG(PV_STAT),
 105         CRTC_REG(PV_HACT_ACT),
 106 };
 107
 108 static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
 109 {
 110         int i;
 111
 112         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 113                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 114                          crtc_regs[i].reg, crtc_regs[i].name,
 115                          CRTC_READ(crtc_regs[i].reg));
 116         }
 117 }
 118
 119 #ifdef CONFIG_DEBUG_FS
 120 int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
 121 {
 122         struct drm_info_node *node = (struct drm_info_node *)m->private;
 123         struct drm_device *dev = node->minor->dev;
 124         int crtc_index = (uintptr_t)node->info_ent->data;
 125         struct drm_crtc *crtc;
 126         struct vc4_crtc *vc4_crtc;
 127         int i;
 128
 129         i = 0;
 130         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 131                 if (i == crtc_index)
 132                         break;
 133                 i++;
 134         }
 135         if (!crtc)
 136                 return 0;
 137         vc4_crtc = to_vc4_crtc(crtc);
 138
 139         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 140                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 141                            crtc_regs[i].name, crtc_regs[i].reg,
 142                            CRTC_READ(crtc_regs[i].reg));
 143         }
 144
 145         return 0;
 146 }
 147 #endif
 148
 149 static void vc4_crtc_destroy(struct drm_crtc *crtc)
 150 {
 151         drm_crtc_cleanup(crtc);
 152 }
 153
 154 static void
 155 vc4_crtc_lut_load(struct drm_crtc *crtc)
 156 {
 157         struct drm_device *dev = crtc->dev;
 158         struct vc4_dev *vc4 = to_vc4_dev(dev);
 159         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 160         u32 i;
 161
 162         /* The LUT memory is laid out with each HVS channel in order,
 163          * each of which takes 256 writes for R, 256 for G, then 256
 164          * for B.
 165          */
 166         HVS_WRITE(SCALER_GAMADDR,
 167                   SCALER_GAMADDR_AUTOINC |
 168                   (vc4_crtc->channel * 3 * crtc->gamma_size));
 169
 170         for (i = 0; i < crtc->gamma_size; i++)
 171                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
 172         for (i = 0; i < crtc->gamma_size; i++)
 173                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
 174         for (i = 0; i < crtc->gamma_size; i++)
 175                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
 176 }
 177
 178 static int
 179 vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 180                    uint32_t size)
 181 {
 182         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 183         u32 i;
 184
 185         for (i = 0; i < size; i++) {
 186                 vc4_crtc->lut_r[i] = r[i] >> 8;
 187                 vc4_crtc->lut_g[i] = g[i] >> 8;
 188                 vc4_crtc->lut_b[i] = b[i] >> 8;
 189         }
 190
 191         vc4_crtc_lut_load(crtc);
 192
 193         return 0;
 194 }
 195
 196 static u32 vc4_get_fifo_full_level(u32 format)
 197 {
 198         static const u32 fifo_len_bytes = 64;
 199         static const u32 hvs_latency_pix = 6;
 200
 201         switch (format) {
 202         case PV_CONTROL_FORMAT_DSIV_16:
 203         case PV_CONTROL_FORMAT_DSIC_16:
 204                 return fifo_len_bytes - 2 * hvs_latency_pix;
 205         case PV_CONTROL_FORMAT_DSIV_18:
 206                 return fifo_len_bytes - 14;
 207         case PV_CONTROL_FORMAT_24:
 208         case PV_CONTROL_FORMAT_DSIV_24:
 209         default:
 210                 return fifo_len_bytes - 3 * hvs_latency_pix;
 211         }
 212 }
 213
 214 /*
 215  * Returns the clock select bit for the connector attached to the
 216  * CRTC.
 217  */
 218 static int vc4_get_clock_select(struct drm_crtc *crtc)
 219 {
 220         struct drm_connector *connector;
 221
 222         drm_for_each_connector(connector, crtc->dev) {
 223                 if (connector->state->crtc == crtc) {
 224                         struct drm_encoder *encoder = connector->encoder;
 225                         struct vc4_encoder *vc4_encoder =
 226                                 to_vc4_encoder(encoder);
 227
 228                         return vc4_encoder->clock_select;
 229                 }
 230         }
 231
 232         return -1;
 233 }
 234
 235 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 236 {
 237         struct drm_device *dev = crtc->dev;
 238         struct vc4_dev *vc4 = to_vc4_dev(dev);
 239         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 240         struct drm_crtc_state *state = crtc->state;
 241         struct drm_display_mode *mode = &state->adjusted_mode;
 242         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 243         u32 vactive = (mode->vdisplay >> (interlace ? 1 : 0));
 244         u32 format = PV_CONTROL_FORMAT_24;
 245         bool debug_dump_regs = false;
 246         int clock_select = vc4_get_clock_select(crtc);
 247
 248         if (debug_dump_regs) {
 249                 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
 250                 vc4_crtc_dump_regs(vc4_crtc);
 251         }
 252
 253         /* Reset the PV fifo. */
 254         CRTC_WRITE(PV_CONTROL, 0);
 255         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
 256         CRTC_WRITE(PV_CONTROL, 0);
 257
 258         CRTC_WRITE(PV_HORZA,
 259                    VC4_SET_FIELD(mode->htotal - mode->hsync_end,
 260                                  PV_HORZA_HBP) |
 261                    VC4_SET_FIELD(mode->hsync_end - mode->hsync_start,
 262                                  PV_HORZA_HSYNC));
 263         CRTC_WRITE(PV_HORZB,
 264                    VC4_SET_FIELD(mode->hsync_start - mode->hdisplay,
 265                                  PV_HORZB_HFP) |
 266                    VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));
 267
 268         CRTC_WRITE(PV_VERTA,
 269                    VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
 270                                  PV_VERTA_VBP) |
 271                    VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
 272                                  PV_VERTA_VSYNC));
 273         CRTC_WRITE(PV_VERTB,
 274                    VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
 275                                  PV_VERTB_VFP) |
 276                    VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
 277
 278         if (interlace) {
 279                 CRTC_WRITE(PV_VERTA_EVEN,
 280                            VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,
 281                                          PV_VERTA_VBP) |
 282                            VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
 283                                          PV_VERTA_VSYNC));
 284                 CRTC_WRITE(PV_VERTB_EVEN,
 285                            VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
 286                                          PV_VERTB_VFP) |
 287                            VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
 288         }
 289
 290         CRTC_WRITE(PV_HACT_ACT, mode->hdisplay);
 291
 292         CRTC_WRITE(PV_V_CONTROL,
 293                    PV_VCONTROL_CONTINUOUS |
 294                    (interlace ? PV_VCONTROL_INTERLACE : 0));
 295
 296         CRTC_WRITE(PV_CONTROL,
 297                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 298                    VC4_SET_FIELD(vc4_get_fifo_full_level(format),
 299                                  PV_CONTROL_FIFO_LEVEL) |
 300                    PV_CONTROL_CLR_AT_START |
 301                    PV_CONTROL_TRIGGER_UNDERFLOW |
 302                    PV_CONTROL_WAIT_HSTART |
 303                    VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) |
 304                    PV_CONTROL_FIFO_CLR |
 305                    PV_CONTROL_EN);
 306
 307         HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
 308                   SCALER_DISPBKGND_AUTOHS |
 309                   SCALER_DISPBKGND_GAMMA |
 310                   (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
 311
 312         /* Reload the LUT, since the SRAMs would have been disabled if
 313          * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
 314          */
 315         vc4_crtc_lut_load(crtc);
 316
 317         if (debug_dump_regs) {
 318                 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
 319                 vc4_crtc_dump_regs(vc4_crtc);
 320         }
 321 }
 322
 323 static void require_hvs_enabled(struct drm_device *dev)
 324 {
 325         struct vc4_dev *vc4 = to_vc4_dev(dev);
 326
 327         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 328                      SCALER_DISPCTRL_ENABLE);
 329 }
 330
 331 static void vc4_crtc_disable(struct drm_crtc *crtc)
 332 {
 333         struct drm_device *dev = crtc->dev;
 334         struct vc4_dev *vc4 = to_vc4_dev(dev);
 335         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 336         u32 chan = vc4_crtc->channel;
 337         int ret;
 338         require_hvs_enabled(dev);
 339
 340         CRTC_WRITE(PV_V_CONTROL,
 341                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 342         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 343         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 344
 345         if (HVS_READ(SCALER_DISPCTRLX(chan)) &
 346             SCALER_DISPCTRLX_ENABLE) {
 347                 HVS_WRITE(SCALER_DISPCTRLX(chan),
 348                           SCALER_DISPCTRLX_RESET);
 349
 350                 /* While the docs say that reset is self-clearing, it
 351                  * seems it doesn't actually.
 352                  */
 353                 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
 354         }
 355
 356         /* Once we leave, the scaler should be disabled and its fifo empty. */
 357
 358         WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
 359
 360         WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
 361                                    SCALER_DISPSTATX_MODE) !=
 362                      SCALER_DISPSTATX_MODE_DISABLED);
 363
 364         WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
 365                       (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
 366                      SCALER_DISPSTATX_EMPTY);
 367 }
 368
 369 static void vc4_crtc_enable(struct drm_crtc *crtc)
 370 {
 371         struct drm_device *dev = crtc->dev;
 372         struct vc4_dev *vc4 = to_vc4_dev(dev);
 373         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 374         struct drm_crtc_state *state = crtc->state;
 375         struct drm_display_mode *mode = &state->adjusted_mode;
 376
 377         require_hvs_enabled(dev);
 378
 379         /* Turn on the scaler, which will wait for vstart to start
 380          * compositing.
 381          */
 382         HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
 383                   VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
 384                   VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
 385                   SCALER_DISPCTRLX_ENABLE);
 386
 387         /* Turn on the pixel valve, which will emit the vstart signal. */
 388         CRTC_WRITE(PV_V_CONTROL,
 389                    CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 390 }
 391
 392 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 393                                  struct drm_crtc_state *state)
 394 {
 395         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 396         struct drm_device *dev = crtc->dev;
 397         struct vc4_dev *vc4 = to_vc4_dev(dev);
 398         struct drm_plane *plane;
 399         unsigned long flags;
 400         const struct drm_plane_state *plane_state;
 401         u32 dlist_count = 0;
 402         int ret;
 403
 404         /* The pixelvalve can only feed one encoder (and encoders are
 405          * 1:1 with connectors.)
 406          */
 407         if (hweight32(state->connector_mask) > 1)
 408                 return -EINVAL;
 409
 410         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
 411                 dlist_count += vc4_plane_dlist_size(plane_state);
 412
 413         dlist_count++; /* Account for SCALER_CTL0_END. */
 414
 415         spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 416         ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
 417                                  dlist_count, 1, 0);
 418         spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 419         if (ret)
 420                 return ret;
 421
 422         return 0;
 423 }
 424
 425 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
 426                                   struct drm_crtc_state *old_state)
 427 {
 428         struct drm_device *dev = crtc->dev;
 429         struct vc4_dev *vc4 = to_vc4_dev(dev);
 430         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 431         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 432         struct drm_plane *plane;
 433         bool debug_dump_regs = false;
 434         u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
 435         u32 __iomem *dlist_next = dlist_start;
 436
 437         if (debug_dump_regs) {
 438                 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
 439                 vc4_hvs_dump_state(dev);
 440         }
 441
 442         /* Copy all the active planes' dlist contents to the hardware dlist. */
 443         drm_atomic_crtc_for_each_plane(plane, crtc) {
 444                 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
 445         }
 446
 447         writel(SCALER_CTL0_END, dlist_next);
 448         dlist_next++;
 449
 450         WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
 451
 452         if (crtc->state->event) {
 453                 unsigned long flags;
 454
 455                 crtc->state->event->pipe = drm_crtc_index(crtc);
 456
 457                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 458
 459                 spin_lock_irqsave(&dev->event_lock, flags);
 460                 vc4_crtc->event = crtc->state->event;
 461                 crtc->state->event = NULL;
 462
 463                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 464                           vc4_state->mm.start);
 465
 466                 spin_unlock_irqrestore(&dev->event_lock, flags);
 467         } else {
 468                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 469                           vc4_state->mm.start);
 470         }
 471
 472         if (debug_dump_regs) {
 473                 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
 474                 vc4_hvs_dump_state(dev);
 475         }
 476 }
 477
 478 int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id)
 479 {
 480         struct vc4_dev *vc4 = to_vc4_dev(dev);
 481         struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
 482
 483         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 484
 485         return 0;
 486 }
 487
 488 void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id)
 489 {
 490         struct vc4_dev *vc4 = to_vc4_dev(dev);
 491         struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
 492
 493         CRTC_WRITE(PV_INTEN, 0);
 494 }
 495
 496 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 497 {
 498         struct drm_crtc *crtc = &vc4_crtc->base;
 499         struct drm_device *dev = crtc->dev;
 500         struct vc4_dev *vc4 = to_vc4_dev(dev);
 501         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 502         u32 chan = vc4_crtc->channel;
 503         unsigned long flags;
 504
 505         spin_lock_irqsave(&dev->event_lock, flags);
 506         if (vc4_crtc->event &&
 507             (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
 508                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 509                 vc4_crtc->event = NULL;
 510                 drm_crtc_vblank_put(crtc);
 511         }
 512         spin_unlock_irqrestore(&dev->event_lock, flags);
 513 }
 514
 515 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 516 {
 517         struct vc4_crtc *vc4_crtc = data;
 518         u32 stat = CRTC_READ(PV_INTSTAT);
 519         irqreturn_t ret = IRQ_NONE;
 520
 521         if (stat & PV_INT_VFP_START) {
 522                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 523                 drm_crtc_handle_vblank(&vc4_crtc->base);
 524                 vc4_crtc_handle_page_flip(vc4_crtc);
 525                 ret = IRQ_HANDLED;
 526         }
 527
 528         return ret;
 529 }
 530
 531 struct vc4_async_flip_state {
 532         struct drm_crtc *crtc;
 533         struct drm_framebuffer *fb;
 534         struct drm_pending_vblank_event *event;
 535
 536         struct vc4_seqno_cb cb;
 537 };
 538
 539 /* Called when the V3D execution for the BO being flipped to is done, so that
 540  * we can actually update the plane's address to point to it.
 541  */
 542 static void
 543 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
 544 {
 545         struct vc4_async_flip_state *flip_state =
 546                 container_of(cb, struct vc4_async_flip_state, cb);
 547         struct drm_crtc *crtc = flip_state->crtc;
 548         struct drm_device *dev = crtc->dev;
 549         struct vc4_dev *vc4 = to_vc4_dev(dev);
 550         struct drm_plane *plane = crtc->primary;
 551
 552         vc4_plane_async_set_fb(plane, flip_state->fb);
 553         if (flip_state->event) {
 554                 unsigned long flags;
 555
 556                 spin_lock_irqsave(&dev->event_lock, flags);
 557                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 558                 spin_unlock_irqrestore(&dev->event_lock, flags);
 559         }
 560
 561         drm_crtc_vblank_put(crtc);
 562         drm_framebuffer_unreference(flip_state->fb);
 563         kfree(flip_state);
 564
 565         up(&vc4->async_modeset);
 566 }
 567
 568 /* Implements async (non-vblank-synced) page flips.
 569  *
 570  * The page flip ioctl needs to return immediately, so we grab the
 571  * modeset semaphore on the pipe, and queue the address update for
 572  * when V3D is done with the BO being flipped to.
 573  */
 574 static int vc4_async_page_flip(struct drm_crtc *crtc,
 575                                struct drm_framebuffer *fb,
 576                                struct drm_pending_vblank_event *event,
 577                                uint32_t flags)
 578 {
 579         struct drm_device *dev = crtc->dev;
 580         struct vc4_dev *vc4 = to_vc4_dev(dev);
 581         struct drm_plane *plane = crtc->primary;
 582         int ret = 0;
 583         struct vc4_async_flip_state *flip_state;
 584         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 585         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 586
 587         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 588         if (!flip_state)
 589                 return -ENOMEM;
 590
 591         drm_framebuffer_reference(fb);
 592         flip_state->fb = fb;
 593         flip_state->crtc = crtc;
 594         flip_state->event = event;
 595
 596         /* Make sure all other async modesetes have landed. */
 597         ret = down_interruptible(&vc4->async_modeset);
 598         if (ret) {
 599                 drm_framebuffer_unreference(fb);
 600                 kfree(flip_state);
 601                 return ret;
 602         }
 603
 604         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 605
 606         /* Immediately update the plane's legacy fb pointer, so that later
 607          * modeset prep sees the state that will be present when the semaphore
 608          * is released.
 609          */
 610         drm_atomic_set_fb_for_plane(plane->state, fb);
 611         plane->fb = fb;
 612
 613         vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
 614                            vc4_async_page_flip_complete);
 615
 616         /* Driver takes ownership of state on successful async commit. */
 617         return 0;
 618 }
 619
 620 static int vc4_page_flip(struct drm_crtc *crtc,
 621                          struct drm_framebuffer *fb,
 622                          struct drm_pending_vblank_event *event,
 623                          uint32_t flags)
 624 {
 625         if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
 626                 return vc4_async_page_flip(crtc, fb, event, flags);
 627         else
 628                 return drm_atomic_helper_page_flip(crtc, fb, event, flags);
 629 }
 630
 631 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
 632 {
 633         struct vc4_crtc_state *vc4_state;
 634
 635         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 636         if (!vc4_state)
 637                 return NULL;
 638
 639         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
 640         return &vc4_state->base;
 641 }
 642
 643 static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
 644                                    struct drm_crtc_state *state)
 645 {
 646         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
 647         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 648
 649         if (vc4_state->mm.allocated) {
 650                 unsigned long flags;
 651
 652                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 653                 drm_mm_remove_node(&vc4_state->mm);
 654                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 655
 656         }
 657
 658         __drm_atomic_helper_crtc_destroy_state(state);
 659 }
 660
 661 static const struct drm_crtc_funcs vc4_crtc_funcs = {
 662         .set_config = drm_atomic_helper_set_config,
 663         .destroy = vc4_crtc_destroy,
 664         .page_flip = vc4_page_flip,
 665         .set_property = NULL,
 666         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
 667         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
 668         .reset = drm_atomic_helper_crtc_reset,
 669         .atomic_duplicate_state = vc4_crtc_duplicate_state,
 670         .atomic_destroy_state = vc4_crtc_destroy_state,
 671         .gamma_set = vc4_crtc_gamma_set,
 672 };
 673
 674 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
 675         .mode_set_nofb = vc4_crtc_mode_set_nofb,
 676         .disable = vc4_crtc_disable,
 677         .enable = vc4_crtc_enable,
 678         .atomic_check = vc4_crtc_atomic_check,
 679         .atomic_flush = vc4_crtc_atomic_flush,
 680 };
 681
 682 static const struct vc4_crtc_data pv0_data = {
 683         .hvs_channel = 0,
 684         .encoder0_type = VC4_ENCODER_TYPE_DSI0,
 685         .encoder1_type = VC4_ENCODER_TYPE_DPI,
 686 };
 687
 688 static const struct vc4_crtc_data pv1_data = {
 689         .hvs_channel = 2,
 690         .encoder0_type = VC4_ENCODER_TYPE_DSI1,
 691         .encoder1_type = VC4_ENCODER_TYPE_SMI,
 692 };
 693
 694 static const struct vc4_crtc_data pv2_data = {
 695         .hvs_channel = 1,
 696         .encoder0_type = VC4_ENCODER_TYPE_VEC,
 697         .encoder1_type = VC4_ENCODER_TYPE_HDMI,
 698 };
 699
 700 static const struct of_device_id vc4_crtc_dt_match[] = {
 701         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
 702         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
 703         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
 704         {}
 705 };
 706
 707 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
 708                                         struct drm_crtc *crtc)
 709 {
 710         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 711         struct drm_encoder *encoder;
 712
 713         drm_for_each_encoder(encoder, drm) {
 714                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 715
 716                 if (vc4_encoder->type == vc4_crtc->data->encoder0_type) {
 717                         vc4_encoder->clock_select = 0;
 718                         encoder->possible_crtcs |= drm_crtc_mask(crtc);
 719                 } else if (vc4_encoder->type == vc4_crtc->data->encoder1_type) {
 720                         vc4_encoder->clock_select = 1;
 721                         encoder->possible_crtcs |= drm_crtc_mask(crtc);
 722                 }
 723         }
 724 }
 725
 726 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
 727 {
 728         struct platform_device *pdev = to_platform_device(dev);
 729         struct drm_device *drm = dev_get_drvdata(master);
 730         struct vc4_dev *vc4 = to_vc4_dev(drm);
 731         struct vc4_crtc *vc4_crtc;
 732         struct drm_crtc *crtc;
 733         struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
 734         const struct of_device_id *match;
 735         int ret, i;
 736
 737         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
 738         if (!vc4_crtc)
 739                 return -ENOMEM;
 740         crtc = &vc4_crtc->base;
 741
 742         match = of_match_device(vc4_crtc_dt_match, dev);
 743         if (!match)
 744                 return -ENODEV;
 745         vc4_crtc->data = match->data;
 746
 747         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
 748         if (IS_ERR(vc4_crtc->regs))
 749                 return PTR_ERR(vc4_crtc->regs);
 750
 751         /* For now, we create just the primary and the legacy cursor
 752          * planes.  We should be able to stack more planes on easily,
 753          * but to do that we would need to compute the bandwidth
 754          * requirement of the plane configuration, and reject ones
 755          * that will take too much.
 756          */
 757         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
 758         if (IS_ERR(primary_plane)) {
 759                 dev_err(dev, "failed to construct primary plane\n");
 760                 ret = PTR_ERR(primary_plane);
 761                 goto err;
 762         }
 763
 764         drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
 765                                   &vc4_crtc_funcs, NULL);
 766         drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
 767         primary_plane->crtc = crtc;
 768         vc4->crtc[drm_crtc_index(crtc)] = vc4_crtc;
 769         vc4_crtc->channel = vc4_crtc->data->hvs_channel;
 770         drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
 771
 772         /* Set up some arbitrary number of planes.  We're not limited
 773          * by a set number of physical registers, just the space in
 774          * the HVS (16k) and how small an plane can be (28 bytes).
 775          * However, each plane we set up takes up some memory, and
 776          * increases the cost of looping over planes, which atomic
 777          * modesetting does quite a bit.  As a result, we pick a
 778          * modest number of planes to expose, that should hopefully
 779          * still cover any sane usecase.
 780          */
 781         for (i = 0; i < 8; i++) {
 782                 struct drm_plane *plane =
 783                         vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
 784
 785                 if (IS_ERR(plane))
 786                         continue;
 787
 788                 plane->possible_crtcs = 1 << drm_crtc_index(crtc);
 789         }
 790
 791         /* Set up the legacy cursor after overlay initialization,
 792          * since we overlay planes on the CRTC in the order they were
 793          * initialized.
 794          */
 795         cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
 796         if (!IS_ERR(cursor_plane)) {
 797                 cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc);
 798                 cursor_plane->crtc = crtc;
 799                 crtc->cursor = cursor_plane;
 800         }
 801
 802         CRTC_WRITE(PV_INTEN, 0);
 803         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 804         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
 805                                vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
 806         if (ret)
 807                 goto err_destroy_planes;
 808
 809         vc4_set_crtc_possible_masks(drm, crtc);
 810
 811         for (i = 0; i < crtc->gamma_size; i++) {
 812                 vc4_crtc->lut_r[i] = i;
 813                 vc4_crtc->lut_g[i] = i;
 814                 vc4_crtc->lut_b[i] = i;
 815         }
 816
 817         platform_set_drvdata(pdev, vc4_crtc);
 818
 819         return 0;
 820
 821 err_destroy_planes:
 822         list_for_each_entry_safe(destroy_plane, temp,
 823                                  &drm->mode_config.plane_list, head) {
 824                 if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))
 825                     destroy_plane->funcs->destroy(destroy_plane);
 826         }
 827 err:
 828         return ret;
 829 }
 830
 831 static void vc4_crtc_unbind(struct device *dev, struct device *master,
 832                             void *data)
 833 {
 834         struct platform_device *pdev = to_platform_device(dev);
 835         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
 836
 837         vc4_crtc_destroy(&vc4_crtc->base);
 838
 839         CRTC_WRITE(PV_INTEN, 0);
 840
 841         platform_set_drvdata(pdev, NULL);
 842 }
 843
 844 static const struct component_ops vc4_crtc_ops = {
 845         .bind   = vc4_crtc_bind,
 846         .unbind = vc4_crtc_unbind,
 847 };
 848
 849 static int vc4_crtc_dev_probe(struct platform_device *pdev)
 850 {
 851         return component_add(&pdev->dev, &vc4_crtc_ops);
 852 }
 853
 854 static int vc4_crtc_dev_remove(struct platform_device *pdev)
 855 {
 856         component_del(&pdev->dev, &vc4_crtc_ops);
 857         return 0;
 858 }
 859
 860 struct platform_driver vc4_crtc_driver = {
 861         .probe = vc4_crtc_dev_probe,
 862         .remove = vc4_crtc_dev_remove,
 863         .driver = {
 864                 .name = "vc4_crtc",
 865                 .of_match_table = vc4_crtc_dt_match,
 866         },
 867 };