2 * Copyright (C) 2015 Broadcom
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include "drm_gem_cma_helper.h"
13 struct drm_device *dev;
15 struct vc4_hdmi *hdmi;
17 struct vc4_crtc *crtc[3];
21 struct drm_fbdev_cma *fbdev;
23 struct vc4_hang_state *hang_state;
25 /* The kernel-space BO cache. Tracks buffers that have been
26 * unreferenced by all other users (refcounts of 0!) but not
27 * yet freed, so we can do cheap allocations.
30 /* Array of list heads for entries in the BO cache,
31 * based on number of pages, so we can do O(1) lookups
32 * in the cache when allocating.
34 struct list_head *size_list;
35 uint32_t size_list_size;
37 /* List of all BOs in the cache, ordered by age, so we
38 * can do O(1) lookups when trying to free old
41 struct list_head time_list;
42 struct work_struct time_work;
43 struct timer_list time_timer;
53 /* Protects bo_cache and the BO stats. */
56 /* Sequence number for the last job queued in bin_job_list.
57 * Starts at 0 (no jobs emitted).
61 /* Sequence number for the last completed job on the GPU.
62 * Starts at 0 (no jobs completed).
64 uint64_t finished_seqno;
66 /* List of all struct vc4_exec_info for jobs to be executed in
67 * the binner. The first job in the list is the one currently
68 * programmed into ct0ca for execution.
70 struct list_head bin_job_list;
72 /* List of all struct vc4_exec_info for jobs that have
73 * completed binning and are ready for rendering. The first
74 * job in the list is the one currently programmed into ct1ca
77 struct list_head render_job_list;
79 /* List of the finished vc4_exec_infos waiting to be freed by
82 struct list_head job_done_list;
83 /* Spinlock used to synchronize the job_list and seqno
84 * accesses between the IRQ handler and GEM ioctls.
87 wait_queue_head_t job_wait_queue;
88 struct work_struct job_done_work;
90 /* List of struct vc4_seqno_cb for callbacks to be made from a
91 * workqueue when the given seqno is passed.
93 struct list_head seqno_cb_list;
95 /* The binner overflow memory that's currently set up in
96 * BPOA/BPOS registers. When overflow occurs and a new one is
97 * allocated, the previous one will be moved to
98 * vc4->current_exec's free list.
100 struct vc4_bo *overflow_mem;
101 struct work_struct overflow_mem_work;
105 /* Mutex controlling the power refcount. */
106 struct mutex power_lock;
109 struct timer_list timer;
110 struct work_struct reset_work;
113 struct semaphore async_modeset;
116 static inline struct vc4_dev *
117 to_vc4_dev(struct drm_device *dev)
119 return (struct vc4_dev *)dev->dev_private;
123 struct drm_gem_cma_object base;
125 /* seqno of the last job to render using this BO. */
128 /* seqno of the last job to use the RCL to write to this BO.
130 * Note that this doesn't include binner overflow memory
133 uint64_t write_seqno;
135 /* List entry for the BO's position in either
136 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
138 struct list_head unref_head;
140 /* Time in jiffies when the BO was put in vc4->bo_cache. */
141 unsigned long free_time;
143 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
144 struct list_head size_head;
146 /* Struct for shader validation state, if created by
147 * DRM_IOCTL_VC4_CREATE_SHADER_BO.
149 struct vc4_validated_shader_info *validated_shader;
152 static inline struct vc4_bo *
153 to_vc4_bo(struct drm_gem_object *bo)
155 return (struct vc4_bo *)bo;
158 struct vc4_seqno_cb {
159 struct work_struct work;
161 void (*func)(struct vc4_seqno_cb *cb);
166 struct platform_device *pdev;
171 struct platform_device *pdev;
175 /* Memory manager for CRTCs to allocate space in the display
176 * list. Units are dwords.
178 struct drm_mm dlist_mm;
179 /* Memory manager for the LBM memory used by HVS scaling. */
180 struct drm_mm lbm_mm;
183 struct drm_mm_node mitchell_netravali_filter;
187 struct drm_plane base;
190 static inline struct vc4_plane *
191 to_vc4_plane(struct drm_plane *plane)
193 return (struct vc4_plane *)plane;
196 enum vc4_encoder_type {
197 VC4_ENCODER_TYPE_HDMI,
198 VC4_ENCODER_TYPE_VEC,
199 VC4_ENCODER_TYPE_DSI0,
200 VC4_ENCODER_TYPE_DSI1,
201 VC4_ENCODER_TYPE_SMI,
202 VC4_ENCODER_TYPE_DPI,
206 struct drm_encoder base;
207 enum vc4_encoder_type type;
211 static inline struct vc4_encoder *
212 to_vc4_encoder(struct drm_encoder *encoder)
214 return container_of(encoder, struct vc4_encoder, base);
217 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
218 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
219 #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
220 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
222 struct vc4_exec_info {
223 /* Sequence number for this bin/render job. */
226 /* Latest write_seqno of any BO that binning depends on. */
227 uint64_t bin_dep_seqno;
229 /* Last current addresses the hardware was processing when the
230 * hangcheck timer checked on us.
232 uint32_t last_ct0ca, last_ct1ca;
234 /* Kernel-space copy of the ioctl arguments */
235 struct drm_vc4_submit_cl *args;
237 /* This is the array of BOs that were looked up at the start of exec.
238 * Command validation will use indices into this array.
240 struct drm_gem_cma_object **bo;
243 /* List of BOs that are being written by the RCL. Other than
244 * the binner temporary storage, this is all the BOs written
247 struct drm_gem_cma_object *rcl_write_bo[4];
248 uint32_t rcl_write_bo_count;
250 /* Pointers for our position in vc4->job_list */
251 struct list_head head;
253 /* List of other BOs used in the job that need to be released
254 * once the job is complete.
256 struct list_head unref_list;
258 /* Current unvalidated indices into @bo loaded by the non-hardware
259 * VC4_PACKET_GEM_HANDLES.
261 uint32_t bo_index[2];
263 /* This is the BO where we store the validated command lists, shader
264 * records, and uniforms.
266 struct drm_gem_cma_object *exec_bo;
269 * This tracks the per-shader-record state (packet 64) that
270 * determines the length of the shader record and the offset
271 * it's expected to be found at. It gets read in from the
274 struct vc4_shader_state {
276 /* Maximum vertex index referenced by any primitive using this
282 /** How many shader states the user declared they were using. */
283 uint32_t shader_state_size;
284 /** How many shader state records the validator has seen. */
285 uint32_t shader_state_count;
287 bool found_tile_binning_mode_config_packet;
288 bool found_start_tile_binning_packet;
289 bool found_increment_semaphore_packet;
291 uint8_t bin_tiles_x, bin_tiles_y;
292 struct drm_gem_cma_object *tile_bo;
293 uint32_t tile_alloc_offset;
296 * Computed addresses pointing into exec_bo where we start the
297 * bin thread (ct0) and render thread (ct1).
299 uint32_t ct0ca, ct0ea;
300 uint32_t ct1ca, ct1ea;
302 /* Pointer to the unvalidated bin CL (if present). */
305 /* Pointers to the shader recs. These paddr gets incremented as CL
306 * packets are relocated in validate_gl_shader_state, and the vaddrs
307 * (u and v) get incremented and size decremented as the shader recs
308 * themselves are validated.
312 uint32_t shader_rec_p;
313 uint32_t shader_rec_size;
315 /* Pointers to the uniform data. These pointers are incremented, and
316 * size decremented, as each batch of uniforms is uploaded.
321 uint32_t uniforms_size;
324 static inline struct vc4_exec_info *
325 vc4_first_bin_job(struct vc4_dev *vc4)
327 return list_first_entry_or_null(&vc4->bin_job_list,
328 struct vc4_exec_info, head);
331 static inline struct vc4_exec_info *
332 vc4_first_render_job(struct vc4_dev *vc4)
334 return list_first_entry_or_null(&vc4->render_job_list,
335 struct vc4_exec_info, head);
338 static inline struct vc4_exec_info *
339 vc4_last_render_job(struct vc4_dev *vc4)
341 if (list_empty(&vc4->render_job_list))
343 return list_last_entry(&vc4->render_job_list,
344 struct vc4_exec_info, head);
348 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
351 * This will be used at draw time to relocate the reference to the texture
352 * contents in p0, and validate that the offset combined with
353 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
354 * Note that the hardware treats unprovided config parameters as 0, so not all
355 * of them need to be set up for every texure sample, and we'll store ~0 as
356 * the offset to mark the unused ones.
358 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
359 * Setup") for definitions of the texture parameters.
361 struct vc4_texture_sample_info {
363 uint32_t p_offset[4];
367 * struct vc4_validated_shader_info - information about validated shaders that
368 * needs to be used from command list validation.
370 * For a given shader, each time a shader state record references it, we need
371 * to verify that the shader doesn't read more uniforms than the shader state
372 * record's uniform BO pointer can provide, and we need to apply relocations
373 * and validate the shader state record's uniforms that define the texture
376 struct vc4_validated_shader_info {
377 uint32_t uniforms_size;
378 uint32_t uniforms_src_size;
379 uint32_t num_texture_samples;
380 struct vc4_texture_sample_info *texture_samples;
382 uint32_t num_uniform_addr_offsets;
383 uint32_t *uniform_addr_offsets;
387 * _wait_for - magic (register) wait macro
389 * Does the right thing for modeset paths when run under kdgb or similar atomic
390 * contexts. Note that it's important that we check the condition again after
391 * having timed out, since the timeout could be due to preemption or similar and
392 * we've never had a chance to check the condition before the timeout.
394 #define _wait_for(COND, MS, W) ({ \
395 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
398 if (time_after(jiffies, timeout__)) { \
400 ret__ = -ETIMEDOUT; \
403 if (W && drm_can_sleep()) { \
412 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
415 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
416 void vc4_free_object(struct drm_gem_object *gem_obj);
417 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
419 int vc4_dumb_create(struct drm_file *file_priv,
420 struct drm_device *dev,
421 struct drm_mode_create_dumb *args);
422 struct dma_buf *vc4_prime_export(struct drm_device *dev,
423 struct drm_gem_object *obj, int flags);
424 int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
425 struct drm_file *file_priv);
426 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
427 struct drm_file *file_priv);
428 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
429 struct drm_file *file_priv);
430 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
431 struct drm_file *file_priv);
432 int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
433 int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
434 void *vc4_prime_vmap(struct drm_gem_object *obj);
435 void vc4_bo_cache_init(struct drm_device *dev);
436 void vc4_bo_cache_destroy(struct drm_device *dev);
437 int vc4_bo_stats_debugfs(struct seq_file *m, void *arg);
440 extern struct platform_driver vc4_crtc_driver;
441 int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id);
442 void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id);
443 int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg);
444 int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
445 unsigned int flags, int *vpos, int *hpos,
446 ktime_t *stime, ktime_t *etime,
447 const struct drm_display_mode *mode);
448 int vc4_crtc_get_vblank_timestamp(struct drm_device *dev, unsigned int crtc_id,
449 int *max_error, struct timeval *vblank_time,
453 int vc4_debugfs_init(struct drm_minor *minor);
454 void vc4_debugfs_cleanup(struct drm_minor *minor);
457 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
460 extern struct platform_driver vc4_dpi_driver;
461 int vc4_dpi_debugfs_regs(struct seq_file *m, void *unused);
464 void vc4_gem_init(struct drm_device *dev);
465 void vc4_gem_destroy(struct drm_device *dev);
466 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
467 struct drm_file *file_priv);
468 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
469 struct drm_file *file_priv);
470 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
471 struct drm_file *file_priv);
472 void vc4_submit_next_bin_job(struct drm_device *dev);
473 void vc4_submit_next_render_job(struct drm_device *dev);
474 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
475 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
476 uint64_t timeout_ns, bool interruptible);
477 void vc4_job_handle_completed(struct vc4_dev *vc4);
478 int vc4_queue_seqno_cb(struct drm_device *dev,
479 struct vc4_seqno_cb *cb, uint64_t seqno,
480 void (*func)(struct vc4_seqno_cb *cb));
483 extern struct platform_driver vc4_hdmi_driver;
484 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused);
487 irqreturn_t vc4_irq(int irq, void *arg);
488 void vc4_irq_preinstall(struct drm_device *dev);
489 int vc4_irq_postinstall(struct drm_device *dev);
490 void vc4_irq_uninstall(struct drm_device *dev);
491 void vc4_irq_reset(struct drm_device *dev);
494 extern struct platform_driver vc4_hvs_driver;
495 void vc4_hvs_dump_state(struct drm_device *dev);
496 int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused);
499 int vc4_kms_load(struct drm_device *dev);
502 struct drm_plane *vc4_plane_init(struct drm_device *dev,
503 enum drm_plane_type type);
504 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
505 u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
506 void vc4_plane_async_set_fb(struct drm_plane *plane,
507 struct drm_framebuffer *fb);
510 extern struct platform_driver vc4_v3d_driver;
511 int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused);
512 int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused);
516 vc4_validate_bin_cl(struct drm_device *dev,
519 struct vc4_exec_info *exec);
522 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
524 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
527 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
529 bool vc4_check_tex_size(struct vc4_exec_info *exec,
530 struct drm_gem_cma_object *fbo,
531 uint32_t offset, uint8_t tiling_format,
532 uint32_t width, uint32_t height, uint8_t cpp);
534 /* vc4_validate_shader.c */
535 struct vc4_validated_shader_info *
536 vc4_validate_shader(struct drm_gem_cma_object *shader_obj);