1 /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/types.h>
17 #include <linux/device.h>
19 #include <linux/err.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/smp.h>
24 #include <linux/sysfs.h>
25 #include <linux/stat.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/cpu.h>
29 #include <linux/coresight.h>
30 #include <linux/amba/bus.h>
31 #include <linux/seq_file.h>
32 #include <linux/uaccess.h>
33 #include <linux/clk.h>
34 #include <linux/perf_event.h>
35 #include <asm/sections.h>
37 #include "coresight-etm.h"
38 #include "coresight-etm-perf.h"
40 static int boot_enable;
41 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
43 /* The number of ETM/PTM currently registered */
45 static struct etm_drvdata *etmdrvdata[NR_CPUS];
48 * Memory mapped writes to clear os lock are not supported on some processors
49 * and OS lock must be unlocked before any memory mapped access on such
50 * processors, otherwise memory mapped reads/writes will be invalid.
52 static void etm_os_unlock(struct etm_drvdata *drvdata)
54 /* Writing any value to ETMOSLAR unlocks the trace registers */
55 etm_writel(drvdata, 0x0, ETMOSLAR);
56 drvdata->os_unlock = true;
60 static void etm_set_pwrdwn(struct etm_drvdata *drvdata)
64 /* Ensure pending cp14 accesses complete before setting pwrdwn */
67 etmcr = etm_readl(drvdata, ETMCR);
68 etmcr |= ETMCR_PWD_DWN;
69 etm_writel(drvdata, etmcr, ETMCR);
72 static void etm_clr_pwrdwn(struct etm_drvdata *drvdata)
76 etmcr = etm_readl(drvdata, ETMCR);
77 etmcr &= ~ETMCR_PWD_DWN;
78 etm_writel(drvdata, etmcr, ETMCR);
79 /* Ensure pwrup completes before subsequent cp14 accesses */
84 static void etm_set_pwrup(struct etm_drvdata *drvdata)
88 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
89 etmpdcr |= ETMPDCR_PWD_UP;
90 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
91 /* Ensure pwrup completes before subsequent cp14 accesses */
96 static void etm_clr_pwrup(struct etm_drvdata *drvdata)
100 /* Ensure pending cp14 accesses complete before clearing pwrup */
103 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
104 etmpdcr &= ~ETMPDCR_PWD_UP;
105 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
109 * coresight_timeout_etm - loop until a bit has changed to a specific state.
110 * @drvdata: etm's private data structure.
111 * @offset: address of a register, starting from @addr.
112 * @position: the position of the bit of interest.
113 * @value: the value the bit should have.
115 * Basically the same as @coresight_timeout except for the register access
116 * method where we have to account for CP14 configurations.
118 * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
119 * TIMEOUT_US has elapsed, which ever happens first.
122 static int coresight_timeout_etm(struct etm_drvdata *drvdata, u32 offset,
123 int position, int value)
128 for (i = TIMEOUT_US; i > 0; i--) {
129 val = etm_readl(drvdata, offset);
130 /* Waiting on the bit to go from 0 to 1 */
132 if (val & BIT(position))
134 /* Waiting on the bit to go from 1 to 0 */
136 if (!(val & BIT(position)))
141 * Delay is arbitrary - the specification doesn't say how long
142 * we are expected to wait. Extra check required to make sure
143 * we don't wait needlessly on the last iteration.
153 static void etm_set_prog(struct etm_drvdata *drvdata)
157 etmcr = etm_readl(drvdata, ETMCR);
158 etmcr |= ETMCR_ETM_PRG;
159 etm_writel(drvdata, etmcr, ETMCR);
161 * Recommended by spec for cp14 accesses to ensure etmcr write is
162 * complete before polling etmsr
165 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 1)) {
166 dev_err(drvdata->dev,
167 "%s: timeout observed when probing at offset %#x\n",
172 static void etm_clr_prog(struct etm_drvdata *drvdata)
176 etmcr = etm_readl(drvdata, ETMCR);
177 etmcr &= ~ETMCR_ETM_PRG;
178 etm_writel(drvdata, etmcr, ETMCR);
180 * Recommended by spec for cp14 accesses to ensure etmcr write is
181 * complete before polling etmsr
184 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 0)) {
185 dev_err(drvdata->dev,
186 "%s: timeout observed when probing at offset %#x\n",
191 void etm_set_default(struct etm_config *config)
195 if (WARN_ON_ONCE(!config))
199 * Taken verbatim from the TRM:
201 * To trace all memory:
202 * set bit [24] in register 0x009, the ETMTECR1, to 1
203 * set all other bits in register 0x009, the ETMTECR1, to 0
204 * set all bits in register 0x007, the ETMTECR2, to 0
205 * set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
207 config->enable_ctrl1 = BIT(24);
208 config->enable_ctrl2 = 0x0;
209 config->enable_event = ETM_HARD_WIRE_RES_A;
211 config->trigger_event = ETM_DEFAULT_EVENT_VAL;
212 config->enable_event = ETM_HARD_WIRE_RES_A;
214 config->seq_12_event = ETM_DEFAULT_EVENT_VAL;
215 config->seq_21_event = ETM_DEFAULT_EVENT_VAL;
216 config->seq_23_event = ETM_DEFAULT_EVENT_VAL;
217 config->seq_31_event = ETM_DEFAULT_EVENT_VAL;
218 config->seq_32_event = ETM_DEFAULT_EVENT_VAL;
219 config->seq_13_event = ETM_DEFAULT_EVENT_VAL;
220 config->timestamp_event = ETM_DEFAULT_EVENT_VAL;
222 for (i = 0; i < ETM_MAX_CNTR; i++) {
223 config->cntr_rld_val[i] = 0x0;
224 config->cntr_event[i] = ETM_DEFAULT_EVENT_VAL;
225 config->cntr_rld_event[i] = ETM_DEFAULT_EVENT_VAL;
226 config->cntr_val[i] = 0x0;
229 config->seq_curr_state = 0x0;
230 config->ctxid_idx = 0x0;
231 for (i = 0; i < ETM_MAX_CTXID_CMP; i++) {
232 config->ctxid_pid[i] = 0x0;
233 config->ctxid_vpid[i] = 0x0;
236 config->ctxid_mask = 0x0;
239 void etm_config_trace_mode(struct etm_config *config)
245 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
247 /* excluding kernel AND user space doesn't make sense */
248 if (mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER))
251 /* nothing to do if neither flags are set */
252 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
255 flags = (1 << 0 | /* instruction execute */
256 3 << 3 | /* ARM instruction */
257 0 << 5 | /* No data value comparison */
258 0 << 7 | /* No exact mach */
259 0 << 8); /* Ignore context ID */
261 /* No need to worry about single address comparators. */
262 config->enable_ctrl2 = 0x0;
264 /* Bit 0 is address range comparator 1 */
265 config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
269 * ETMACTRn[13,11] == Non-secure state comparison control
270 * ETMACTRn[12,10] == Secure state comparison control
272 * b00 == Match in all modes in this state
273 * b01 == Do not match in any more in this state
274 * b10 == Match in all modes excepts user mode in this state
275 * b11 == Match only in user mode in this state
278 /* Tracing in secure mode is not supported at this time */
279 flags |= (0 << 12 | 1 << 10);
281 if (mode & ETM_MODE_EXCL_USER) {
282 /* exclude user, match all modes except user mode */
283 flags |= (1 << 13 | 0 << 11);
285 /* exclude kernel, match only in user mode */
286 flags |= (1 << 13 | 1 << 11);
290 * The ETMEEVR register is already set to "hard wire A". As such
291 * all there is to do is setup an address comparator that spans
292 * the entire address range and configure the state and mode bits.
294 config->addr_val[0] = (u32) 0x0;
295 config->addr_val[1] = (u32) ~0x0;
296 config->addr_acctype[0] = flags;
297 config->addr_acctype[1] = flags;
298 config->addr_type[0] = ETM_ADDR_TYPE_RANGE;
299 config->addr_type[1] = ETM_ADDR_TYPE_RANGE;
302 #define ETM3X_SUPPORTED_OPTIONS (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN)
304 static int etm_parse_event_config(struct etm_drvdata *drvdata,
305 struct perf_event_attr *attr)
307 struct etm_config *config = &drvdata->config;
312 /* Clear configuration from previous run */
313 memset(config, 0, sizeof(struct etm_config));
315 if (attr->exclude_kernel)
316 config->mode = ETM_MODE_EXCL_KERN;
318 if (attr->exclude_user)
319 config->mode = ETM_MODE_EXCL_USER;
321 /* Always start from the default config */
322 etm_set_default(config);
325 * By default the tracers are configured to trace the whole address
326 * range. Narrow the field only if requested by user space.
329 etm_config_trace_mode(config);
332 * At this time only cycle accurate and timestamp options are
335 if (attr->config & ~ETM3X_SUPPORTED_OPTIONS)
338 config->ctrl = attr->config;
343 static void etm_enable_hw(void *info)
347 struct etm_drvdata *drvdata = info;
348 struct etm_config *config = &drvdata->config;
350 CS_UNLOCK(drvdata->base);
353 etm_clr_pwrdwn(drvdata);
354 /* Apply power to trace registers */
355 etm_set_pwrup(drvdata);
356 /* Make sure all registers are accessible */
357 etm_os_unlock(drvdata);
359 etm_set_prog(drvdata);
361 etmcr = etm_readl(drvdata, ETMCR);
362 /* Clear setting from a previous run if need be */
363 etmcr &= ~ETM3X_SUPPORTED_OPTIONS;
364 etmcr |= drvdata->port_size;
365 etmcr |= ETMCR_ETM_EN;
366 etm_writel(drvdata, config->ctrl | etmcr, ETMCR);
367 etm_writel(drvdata, config->trigger_event, ETMTRIGGER);
368 etm_writel(drvdata, config->startstop_ctrl, ETMTSSCR);
369 etm_writel(drvdata, config->enable_event, ETMTEEVR);
370 etm_writel(drvdata, config->enable_ctrl1, ETMTECR1);
371 etm_writel(drvdata, config->fifofull_level, ETMFFLR);
372 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
373 etm_writel(drvdata, config->addr_val[i], ETMACVRn(i));
374 etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i));
376 for (i = 0; i < drvdata->nr_cntr; i++) {
377 etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i));
378 etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i));
379 etm_writel(drvdata, config->cntr_rld_event[i],
381 etm_writel(drvdata, config->cntr_val[i], ETMCNTVRn(i));
383 etm_writel(drvdata, config->seq_12_event, ETMSQ12EVR);
384 etm_writel(drvdata, config->seq_21_event, ETMSQ21EVR);
385 etm_writel(drvdata, config->seq_23_event, ETMSQ23EVR);
386 etm_writel(drvdata, config->seq_31_event, ETMSQ31EVR);
387 etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR);
388 etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR);
389 etm_writel(drvdata, config->seq_curr_state, ETMSQR);
390 for (i = 0; i < drvdata->nr_ext_out; i++)
391 etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
392 for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
393 etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i));
394 etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR);
395 etm_writel(drvdata, config->sync_freq, ETMSYNCFR);
396 /* No external input selected */
397 etm_writel(drvdata, 0x0, ETMEXTINSELR);
398 etm_writel(drvdata, config->timestamp_event, ETMTSEVR);
399 /* No auxiliary control selected */
400 etm_writel(drvdata, 0x0, ETMAUXCR);
401 etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR);
402 /* No VMID comparator value selected */
403 etm_writel(drvdata, 0x0, ETMVMIDCVR);
405 etm_clr_prog(drvdata);
406 CS_LOCK(drvdata->base);
408 dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
411 static int etm_cpu_id(struct coresight_device *csdev)
413 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
418 int etm_get_trace_id(struct etm_drvdata *drvdata)
426 if (!local_read(&drvdata->mode))
427 return drvdata->traceid;
429 pm_runtime_get_sync(drvdata->dev);
431 spin_lock_irqsave(&drvdata->spinlock, flags);
433 CS_UNLOCK(drvdata->base);
434 trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
435 CS_LOCK(drvdata->base);
437 spin_unlock_irqrestore(&drvdata->spinlock, flags);
438 pm_runtime_put(drvdata->dev);
445 static int etm_trace_id(struct coresight_device *csdev)
447 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
449 return etm_get_trace_id(drvdata);
452 static int etm_enable_perf(struct coresight_device *csdev,
453 struct perf_event_attr *attr)
455 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
457 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
460 /* Configure the tracer based on the session's specifics */
461 etm_parse_event_config(drvdata, attr);
463 etm_enable_hw(drvdata);
468 static int etm_enable_sysfs(struct coresight_device *csdev)
470 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
473 spin_lock(&drvdata->spinlock);
476 * Configure the ETM only if the CPU is online. If it isn't online
477 * hw configuration will take place when 'CPU_STARTING' is received
478 * in @etm_cpu_callback.
480 if (cpu_online(drvdata->cpu)) {
481 ret = smp_call_function_single(drvdata->cpu,
482 etm_enable_hw, drvdata, 1);
487 drvdata->sticky_enable = true;
488 spin_unlock(&drvdata->spinlock);
490 dev_info(drvdata->dev, "ETM tracing enabled\n");
494 spin_unlock(&drvdata->spinlock);
498 static int etm_enable(struct coresight_device *csdev,
499 struct perf_event_attr *attr, u32 mode)
503 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
505 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
507 /* Someone is already using the tracer */
513 ret = etm_enable_sysfs(csdev);
516 ret = etm_enable_perf(csdev, attr);
522 /* The tracer didn't start */
524 local_set(&drvdata->mode, CS_MODE_DISABLED);
529 static void etm_disable_hw(void *info)
532 struct etm_drvdata *drvdata = info;
533 struct etm_config *config = &drvdata->config;
535 CS_UNLOCK(drvdata->base);
536 etm_set_prog(drvdata);
538 /* Read back sequencer and counters for post trace analysis */
539 config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
541 for (i = 0; i < drvdata->nr_cntr; i++)
542 config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
544 etm_set_pwrdwn(drvdata);
545 CS_LOCK(drvdata->base);
547 dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
550 static void etm_disable_perf(struct coresight_device *csdev)
552 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
554 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
557 CS_UNLOCK(drvdata->base);
559 /* Setting the prog bit disables tracing immediately */
560 etm_set_prog(drvdata);
563 * There is no way to know when the tracer will be used again so
564 * power down the tracer.
566 etm_set_pwrdwn(drvdata);
568 CS_LOCK(drvdata->base);
571 static void etm_disable_sysfs(struct coresight_device *csdev)
573 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
576 * Taking hotplug lock here protects from clocks getting disabled
577 * with tracing being left on (crash scenario) if user disable occurs
578 * after cpu online mask indicates the cpu is offline but before the
579 * DYING hotplug callback is serviced by the ETM driver.
582 spin_lock(&drvdata->spinlock);
585 * Executing etm_disable_hw on the cpu whose ETM is being disabled
586 * ensures that register writes occur when cpu is powered.
588 smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1);
590 spin_unlock(&drvdata->spinlock);
593 dev_info(drvdata->dev, "ETM tracing disabled\n");
596 static void etm_disable(struct coresight_device *csdev)
599 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
602 * For as long as the tracer isn't disabled another entity can't
603 * change its status. As such we can read the status here without
604 * fearing it will change under us.
606 mode = local_read(&drvdata->mode);
609 case CS_MODE_DISABLED:
612 etm_disable_sysfs(csdev);
615 etm_disable_perf(csdev);
623 local_set(&drvdata->mode, CS_MODE_DISABLED);
626 static const struct coresight_ops_source etm_source_ops = {
627 .cpu_id = etm_cpu_id,
628 .trace_id = etm_trace_id,
629 .enable = etm_enable,
630 .disable = etm_disable,
633 static const struct coresight_ops etm_cs_ops = {
634 .source_ops = &etm_source_ops,
637 static int etm_cpu_callback(struct notifier_block *nfb, unsigned long action,
640 unsigned int cpu = (unsigned long)hcpu;
642 if (!etmdrvdata[cpu])
645 switch (action & (~CPU_TASKS_FROZEN)) {
647 spin_lock(&etmdrvdata[cpu]->spinlock);
648 if (!etmdrvdata[cpu]->os_unlock) {
649 etm_os_unlock(etmdrvdata[cpu]);
650 etmdrvdata[cpu]->os_unlock = true;
653 if (local_read(&etmdrvdata[cpu]->mode))
654 etm_enable_hw(etmdrvdata[cpu]);
655 spin_unlock(&etmdrvdata[cpu]->spinlock);
659 if (etmdrvdata[cpu]->boot_enable &&
660 !etmdrvdata[cpu]->sticky_enable)
661 coresight_enable(etmdrvdata[cpu]->csdev);
665 spin_lock(&etmdrvdata[cpu]->spinlock);
666 if (local_read(&etmdrvdata[cpu]->mode))
667 etm_disable_hw(etmdrvdata[cpu]);
668 spin_unlock(&etmdrvdata[cpu]->spinlock);
675 static struct notifier_block etm_cpu_notifier = {
676 .notifier_call = etm_cpu_callback,
679 static bool etm_arch_supported(u8 arch)
696 static void etm_init_arch_data(void *info)
700 struct etm_drvdata *drvdata = info;
702 /* Make sure all registers are accessible */
703 etm_os_unlock(drvdata);
705 CS_UNLOCK(drvdata->base);
707 /* First dummy read */
708 (void)etm_readl(drvdata, ETMPDSR);
709 /* Provide power to ETM: ETMPDCR[3] == 1 */
710 etm_set_pwrup(drvdata);
712 * Clear power down bit since when this bit is set writes to
713 * certain registers might be ignored.
715 etm_clr_pwrdwn(drvdata);
717 * Set prog bit. It will be set from reset but this is included to
720 etm_set_prog(drvdata);
722 /* Find all capabilities */
723 etmidr = etm_readl(drvdata, ETMIDR);
724 drvdata->arch = BMVAL(etmidr, 4, 11);
725 drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
727 drvdata->etmccer = etm_readl(drvdata, ETMCCER);
728 etmccr = etm_readl(drvdata, ETMCCR);
729 drvdata->etmccr = etmccr;
730 drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
731 drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
732 drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
733 drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
734 drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
736 etm_set_pwrdwn(drvdata);
737 etm_clr_pwrup(drvdata);
738 CS_LOCK(drvdata->base);
741 static void etm_init_trace_id(struct etm_drvdata *drvdata)
744 * A trace ID of value 0 is invalid, so let's start at some
745 * random value that fits in 7 bits and go from there.
747 drvdata->traceid = 0x10 + drvdata->cpu;
750 static int etm_probe(struct amba_device *adev, const struct amba_id *id)
754 struct device *dev = &adev->dev;
755 struct coresight_platform_data *pdata = NULL;
756 struct etm_drvdata *drvdata;
757 struct resource *res = &adev->res;
758 struct coresight_desc *desc;
759 struct device_node *np = adev->dev.of_node;
761 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
765 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
770 pdata = of_get_coresight_platform_data(dev, np);
772 return PTR_ERR(pdata);
774 adev->dev.platform_data = pdata;
775 drvdata->use_cp14 = of_property_read_bool(np, "arm,cp14");
778 drvdata->dev = &adev->dev;
779 dev_set_drvdata(dev, drvdata);
781 /* Validity for the resource is already checked by the AMBA core */
782 base = devm_ioremap_resource(dev, res);
784 return PTR_ERR(base);
786 drvdata->base = base;
788 spin_lock_init(&drvdata->spinlock);
790 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
791 if (!IS_ERR(drvdata->atclk)) {
792 ret = clk_prepare_enable(drvdata->atclk);
797 drvdata->cpu = pdata ? pdata->cpu : 0;
800 etmdrvdata[drvdata->cpu] = drvdata;
802 if (smp_call_function_single(drvdata->cpu,
803 etm_init_arch_data, drvdata, 1))
804 dev_err(dev, "ETM arch init failed\n");
807 register_hotcpu_notifier(&etm_cpu_notifier);
811 if (etm_arch_supported(drvdata->arch) == false) {
813 goto err_arch_supported;
816 etm_init_trace_id(drvdata);
817 etm_set_default(&drvdata->config);
819 desc->type = CORESIGHT_DEV_TYPE_SOURCE;
820 desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
821 desc->ops = &etm_cs_ops;
824 desc->groups = coresight_etm_groups;
825 drvdata->csdev = coresight_register(desc);
826 if (IS_ERR(drvdata->csdev)) {
827 ret = PTR_ERR(drvdata->csdev);
828 goto err_arch_supported;
831 ret = etm_perf_symlink(drvdata->csdev, true);
833 coresight_unregister(drvdata->csdev);
834 goto err_arch_supported;
837 pm_runtime_put(&adev->dev);
838 dev_info(dev, "%s initialized\n", (char *)id->data);
841 coresight_enable(drvdata->csdev);
842 drvdata->boot_enable = true;
848 if (--etm_count == 0)
849 unregister_hotcpu_notifier(&etm_cpu_notifier);
854 static int etm_runtime_suspend(struct device *dev)
856 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
858 if (drvdata && !IS_ERR(drvdata->atclk))
859 clk_disable_unprepare(drvdata->atclk);
864 static int etm_runtime_resume(struct device *dev)
866 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
868 if (drvdata && !IS_ERR(drvdata->atclk))
869 clk_prepare_enable(drvdata->atclk);
875 static const struct dev_pm_ops etm_dev_pm_ops = {
876 SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL)
879 static struct amba_id etm_ids[] = {
900 { /* PTM 1.1 Qualcomm */
908 static struct amba_driver etm_driver = {
910 .name = "coresight-etm3x",
911 .owner = THIS_MODULE,
912 .pm = &etm_dev_pm_ops,
913 .suppress_bind_attrs = true,
919 module_amba_driver(etm_driver);
921 MODULE_LICENSE("GPL v2");
922 MODULE_DESCRIPTION("CoreSight Program Flow Trace driver");