drivers/hwtracing/coresight/coresight-etm3x.c

   1 /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/types.h>
  17 #include <linux/device.h>
  18 #include <linux/io.h>
  19 #include <linux/err.h>
  20 #include <linux/fs.h>
  21 #include <linux/slab.h>
  22 #include <linux/delay.h>
  23 #include <linux/smp.h>
  24 #include <linux/sysfs.h>
  25 #include <linux/stat.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/cpu.h>
  28 #include <linux/of.h>
  29 #include <linux/coresight.h>
  30 #include <linux/amba/bus.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/uaccess.h>
  33 #include <linux/clk.h>
  34 #include <asm/sections.h>
  35
  36 #include "coresight-etm.h"
  37
  38 static int boot_enable;
  39 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
  40
  41 /* The number of ETM/PTM currently registered */
  42 static int etm_count;
  43 static struct etm_drvdata *etmdrvdata[NR_CPUS];
  44
  45 static inline void etm_writel(struct etm_drvdata *drvdata,
  46                               u32 val, u32 off)
  47 {
  48         if (drvdata->use_cp14) {
  49                 if (etm_writel_cp14(off, val)) {
  50                         dev_err(drvdata->dev,
  51                                 "invalid CP14 access to ETM reg: %#x", off);
  52                 }
  53         } else {
  54                 writel_relaxed(val, drvdata->base + off);
  55         }
  56 }
  57
  58 static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off)
  59 {
  60         u32 val;
  61
  62         if (drvdata->use_cp14) {
  63                 if (etm_readl_cp14(off, &val)) {
  64                         dev_err(drvdata->dev,
  65                                 "invalid CP14 access to ETM reg: %#x", off);
  66                 }
  67         } else {
  68                 val = readl_relaxed(drvdata->base + off);
  69         }
  70
  71         return val;
  72 }
  73
  74 /*
  75  * Memory mapped writes to clear os lock are not supported on some processors
  76  * and OS lock must be unlocked before any memory mapped access on such
  77  * processors, otherwise memory mapped reads/writes will be invalid.
  78  */
  79 static void etm_os_unlock(void *info)
  80 {
  81         struct etm_drvdata *drvdata = (struct etm_drvdata *)info;
  82         /* Writing any value to ETMOSLAR unlocks the trace registers */
  83         etm_writel(drvdata, 0x0, ETMOSLAR);
  84         isb();
  85 }
  86
  87 static void etm_set_pwrdwn(struct etm_drvdata *drvdata)
  88 {
  89         u32 etmcr;
  90
  91         /* Ensure pending cp14 accesses complete before setting pwrdwn */
  92         mb();
  93         isb();
  94         etmcr = etm_readl(drvdata, ETMCR);
  95         etmcr |= ETMCR_PWD_DWN;
  96         etm_writel(drvdata, etmcr, ETMCR);
  97 }
  98
  99 static void etm_clr_pwrdwn(struct etm_drvdata *drvdata)
 100 {
 101         u32 etmcr;
 102
 103         etmcr = etm_readl(drvdata, ETMCR);
 104         etmcr &= ~ETMCR_PWD_DWN;
 105         etm_writel(drvdata, etmcr, ETMCR);
 106         /* Ensure pwrup completes before subsequent cp14 accesses */
 107         mb();
 108         isb();
 109 }
 110
 111 static void etm_set_pwrup(struct etm_drvdata *drvdata)
 112 {
 113         u32 etmpdcr;
 114
 115         etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
 116         etmpdcr |= ETMPDCR_PWD_UP;
 117         writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
 118         /* Ensure pwrup completes before subsequent cp14 accesses */
 119         mb();
 120         isb();
 121 }
 122
 123 static void etm_clr_pwrup(struct etm_drvdata *drvdata)
 124 {
 125         u32 etmpdcr;
 126
 127         /* Ensure pending cp14 accesses complete before clearing pwrup */
 128         mb();
 129         isb();
 130         etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
 131         etmpdcr &= ~ETMPDCR_PWD_UP;
 132         writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
 133 }
 134
 135 /**
 136  * coresight_timeout_etm - loop until a bit has changed to a specific state.
 137  * @drvdata: etm's private data structure.
 138  * @offset: address of a register, starting from @addr.
 139  * @position: the position of the bit of interest.
 140  * @value: the value the bit should have.
 141  *
 142  * Basically the same as @coresight_timeout except for the register access
 143  * method where we have to account for CP14 configurations.
 144
 145  * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
 146  * TIMEOUT_US has elapsed, which ever happens first.
 147  */
 148
 149 static int coresight_timeout_etm(struct etm_drvdata *drvdata, u32 offset,
 150                                   int position, int value)
 151 {
 152         int i;
 153         u32 val;
 154
 155         for (i = TIMEOUT_US; i > 0; i--) {
 156                 val = etm_readl(drvdata, offset);
 157                 /* Waiting on the bit to go from 0 to 1 */
 158                 if (value) {
 159                         if (val & BIT(position))
 160                                 return 0;
 161                 /* Waiting on the bit to go from 1 to 0 */
 162                 } else {
 163                         if (!(val & BIT(position)))
 164                                 return 0;
 165                 }
 166
 167                 /*
 168                  * Delay is arbitrary - the specification doesn't say how long
 169                  * we are expected to wait.  Extra check required to make sure
 170                  * we don't wait needlessly on the last iteration.
 171                  */
 172                 if (i - 1)
 173                         udelay(1);
 174         }
 175
 176         return -EAGAIN;
 177 }
 178
 179
 180 static void etm_set_prog(struct etm_drvdata *drvdata)
 181 {
 182         u32 etmcr;
 183
 184         etmcr = etm_readl(drvdata, ETMCR);
 185         etmcr |= ETMCR_ETM_PRG;
 186         etm_writel(drvdata, etmcr, ETMCR);
 187         /*
 188          * Recommended by spec for cp14 accesses to ensure etmcr write is
 189          * complete before polling etmsr
 190          */
 191         isb();
 192         if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 1)) {
 193                 dev_err(drvdata->dev,
 194                         "%s: timeout observed when probing at offset %#x\n",
 195                         __func__, ETMSR);
 196         }
 197 }
 198
 199 static void etm_clr_prog(struct etm_drvdata *drvdata)
 200 {
 201         u32 etmcr;
 202
 203         etmcr = etm_readl(drvdata, ETMCR);
 204         etmcr &= ~ETMCR_ETM_PRG;
 205         etm_writel(drvdata, etmcr, ETMCR);
 206         /*
 207          * Recommended by spec for cp14 accesses to ensure etmcr write is
 208          * complete before polling etmsr
 209          */
 210         isb();
 211         if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 0)) {
 212                 dev_err(drvdata->dev,
 213                         "%s: timeout observed when probing at offset %#x\n",
 214                         __func__, ETMSR);
 215         }
 216 }
 217
 218 static void etm_set_default(struct etm_drvdata *drvdata)
 219 {
 220         int i;
 221
 222         drvdata->trigger_event = ETM_DEFAULT_EVENT_VAL;
 223         drvdata->enable_event = ETM_HARD_WIRE_RES_A;
 224
 225         drvdata->seq_12_event = ETM_DEFAULT_EVENT_VAL;
 226         drvdata->seq_21_event = ETM_DEFAULT_EVENT_VAL;
 227         drvdata->seq_23_event = ETM_DEFAULT_EVENT_VAL;
 228         drvdata->seq_31_event = ETM_DEFAULT_EVENT_VAL;
 229         drvdata->seq_32_event = ETM_DEFAULT_EVENT_VAL;
 230         drvdata->seq_13_event = ETM_DEFAULT_EVENT_VAL;
 231         drvdata->timestamp_event = ETM_DEFAULT_EVENT_VAL;
 232
 233         for (i = 0; i < drvdata->nr_cntr; i++) {
 234                 drvdata->cntr_rld_val[i] = 0x0;
 235                 drvdata->cntr_event[i] = ETM_DEFAULT_EVENT_VAL;
 236                 drvdata->cntr_rld_event[i] = ETM_DEFAULT_EVENT_VAL;
 237                 drvdata->cntr_val[i] = 0x0;
 238         }
 239
 240         drvdata->seq_curr_state = 0x0;
 241         drvdata->ctxid_idx = 0x0;
 242         for (i = 0; i < drvdata->nr_ctxid_cmp; i++) {
 243                 drvdata->ctxid_pid[i] = 0x0;
 244                 drvdata->ctxid_vpid[i] = 0x0;
 245         }
 246
 247         drvdata->ctxid_mask = 0x0;
 248 }
 249
 250 static void etm_enable_hw(void *info)
 251 {
 252         int i;
 253         u32 etmcr;
 254         struct etm_drvdata *drvdata = info;
 255
 256         CS_UNLOCK(drvdata->base);
 257
 258         /* Turn engine on */
 259         etm_clr_pwrdwn(drvdata);
 260         /* Apply power to trace registers */
 261         etm_set_pwrup(drvdata);
 262         /* Make sure all registers are accessible */
 263         etm_os_unlock(drvdata);
 264
 265         etm_set_prog(drvdata);
 266
 267         etmcr = etm_readl(drvdata, ETMCR);
 268         etmcr &= (ETMCR_PWD_DWN | ETMCR_ETM_PRG);
 269         etmcr |= drvdata->port_size;
 270         etm_writel(drvdata, drvdata->ctrl | etmcr, ETMCR);
 271         etm_writel(drvdata, drvdata->trigger_event, ETMTRIGGER);
 272         etm_writel(drvdata, drvdata->startstop_ctrl, ETMTSSCR);
 273         etm_writel(drvdata, drvdata->enable_event, ETMTEEVR);
 274         etm_writel(drvdata, drvdata->enable_ctrl1, ETMTECR1);
 275         etm_writel(drvdata, drvdata->fifofull_level, ETMFFLR);
 276         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 277                 etm_writel(drvdata, drvdata->addr_val[i], ETMACVRn(i));
 278                 etm_writel(drvdata, drvdata->addr_acctype[i], ETMACTRn(i));
 279         }
 280         for (i = 0; i < drvdata->nr_cntr; i++) {
 281                 etm_writel(drvdata, drvdata->cntr_rld_val[i], ETMCNTRLDVRn(i));
 282                 etm_writel(drvdata, drvdata->cntr_event[i], ETMCNTENRn(i));
 283                 etm_writel(drvdata, drvdata->cntr_rld_event[i],
 284                            ETMCNTRLDEVRn(i));
 285                 etm_writel(drvdata, drvdata->cntr_val[i], ETMCNTVRn(i));
 286         }
 287         etm_writel(drvdata, drvdata->seq_12_event, ETMSQ12EVR);
 288         etm_writel(drvdata, drvdata->seq_21_event, ETMSQ21EVR);
 289         etm_writel(drvdata, drvdata->seq_23_event, ETMSQ23EVR);
 290         etm_writel(drvdata, drvdata->seq_31_event, ETMSQ31EVR);
 291         etm_writel(drvdata, drvdata->seq_32_event, ETMSQ32EVR);
 292         etm_writel(drvdata, drvdata->seq_13_event, ETMSQ13EVR);
 293         etm_writel(drvdata, drvdata->seq_curr_state, ETMSQR);
 294         for (i = 0; i < drvdata->nr_ext_out; i++)
 295                 etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
 296         for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
 297                 etm_writel(drvdata, drvdata->ctxid_pid[i], ETMCIDCVRn(i));
 298         etm_writel(drvdata, drvdata->ctxid_mask, ETMCIDCMR);
 299         etm_writel(drvdata, drvdata->sync_freq, ETMSYNCFR);
 300         /* No external input selected */
 301         etm_writel(drvdata, 0x0, ETMEXTINSELR);
 302         etm_writel(drvdata, drvdata->timestamp_event, ETMTSEVR);
 303         /* No auxiliary control selected */
 304         etm_writel(drvdata, 0x0, ETMAUXCR);
 305         etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR);
 306         /* No VMID comparator value selected */
 307         etm_writel(drvdata, 0x0, ETMVMIDCVR);
 308
 309         /* Ensures trace output is enabled from this ETM */
 310         etm_writel(drvdata, drvdata->ctrl | ETMCR_ETM_EN | etmcr, ETMCR);
 311
 312         etm_clr_prog(drvdata);
 313         CS_LOCK(drvdata->base);
 314
 315         dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
 316 }
 317
 318 static int etm_cpu_id(struct coresight_device *csdev)
 319 {
 320         struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 321
 322         return drvdata->cpu;
 323 }
 324
 325 static int etm_trace_id(struct coresight_device *csdev)
 326 {
 327         struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 328         unsigned long flags;
 329         int trace_id = -1;
 330
 331         if (!drvdata->enable)
 332                 return drvdata->traceid;
 333         pm_runtime_get_sync(csdev->dev.parent);
 334
 335         spin_lock_irqsave(&drvdata->spinlock, flags);
 336
 337         CS_UNLOCK(drvdata->base);
 338         trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
 339         CS_LOCK(drvdata->base);
 340
 341         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 342         pm_runtime_put(csdev->dev.parent);
 343
 344         return trace_id;
 345 }
 346
 347 static int etm_enable(struct coresight_device *csdev)
 348 {
 349         struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 350         int ret;
 351
 352         pm_runtime_get_sync(csdev->dev.parent);
 353         spin_lock(&drvdata->spinlock);
 354
 355         /*
 356          * Configure the ETM only if the CPU is online.  If it isn't online
 357          * hw configuration will take place when 'CPU_STARTING' is received
 358          * in @etm_cpu_callback.
 359          */
 360         if (cpu_online(drvdata->cpu)) {
 361                 ret = smp_call_function_single(drvdata->cpu,
 362                                                etm_enable_hw, drvdata, 1);
 363                 if (ret)
 364                         goto err;
 365         }
 366
 367         drvdata->enable = true;
 368         drvdata->sticky_enable = true;
 369
 370         spin_unlock(&drvdata->spinlock);
 371
 372         dev_info(drvdata->dev, "ETM tracing enabled\n");
 373         return 0;
 374 err:
 375         spin_unlock(&drvdata->spinlock);
 376         pm_runtime_put(csdev->dev.parent);
 377         return ret;
 378 }
 379
 380 static void etm_disable_hw(void *info)
 381 {
 382         int i;
 383         struct etm_drvdata *drvdata = info;
 384
 385         CS_UNLOCK(drvdata->base);
 386         etm_set_prog(drvdata);
 387
 388         /* Program trace enable to low by using always false event */
 389         etm_writel(drvdata, ETM_HARD_WIRE_RES_A | ETM_EVENT_NOT_A, ETMTEEVR);
 390
 391         /* Read back sequencer and counters for post trace analysis */
 392         drvdata->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
 393
 394         for (i = 0; i < drvdata->nr_cntr; i++)
 395                 drvdata->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
 396
 397         etm_set_pwrdwn(drvdata);
 398         CS_LOCK(drvdata->base);
 399
 400         dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
 401 }
 402
 403 static void etm_disable(struct coresight_device *csdev)
 404 {
 405         struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 406
 407         /*
 408          * Taking hotplug lock here protects from clocks getting disabled
 409          * with tracing being left on (crash scenario) if user disable occurs
 410          * after cpu online mask indicates the cpu is offline but before the
 411          * DYING hotplug callback is serviced by the ETM driver.
 412          */
 413         get_online_cpus();
 414         spin_lock(&drvdata->spinlock);
 415
 416         /*
 417          * Executing etm_disable_hw on the cpu whose ETM is being disabled
 418          * ensures that register writes occur when cpu is powered.
 419          */
 420         smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1);
 421         drvdata->enable = false;
 422
 423         spin_unlock(&drvdata->spinlock);
 424         put_online_cpus();
 425         pm_runtime_put(csdev->dev.parent);
 426
 427         dev_info(drvdata->dev, "ETM tracing disabled\n");
 428 }
 429
 430 static const struct coresight_ops_source etm_source_ops = {
 431         .cpu_id         = etm_cpu_id,
 432         .trace_id       = etm_trace_id,
 433         .enable         = etm_enable,
 434         .disable        = etm_disable,
 435 };
 436
 437 static const struct coresight_ops etm_cs_ops = {
 438         .source_ops     = &etm_source_ops,
 439 };
 440
 441 static ssize_t nr_addr_cmp_show(struct device *dev,
 442                                 struct device_attribute *attr, char *buf)
 443 {
 444         unsigned long val;
 445         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 446
 447         val = drvdata->nr_addr_cmp;
 448         return sprintf(buf, "%#lx\n", val);
 449 }
 450 static DEVICE_ATTR_RO(nr_addr_cmp);
 451
 452 static ssize_t nr_cntr_show(struct device *dev,
 453                             struct device_attribute *attr, char *buf)
 454 {       unsigned long val;
 455         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 456
 457         val = drvdata->nr_cntr;
 458         return sprintf(buf, "%#lx\n", val);
 459 }
 460 static DEVICE_ATTR_RO(nr_cntr);
 461
 462 static ssize_t nr_ctxid_cmp_show(struct device *dev,
 463                                  struct device_attribute *attr, char *buf)
 464 {
 465         unsigned long val;
 466         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 467
 468         val = drvdata->nr_ctxid_cmp;
 469         return sprintf(buf, "%#lx\n", val);
 470 }
 471 static DEVICE_ATTR_RO(nr_ctxid_cmp);
 472
 473 static ssize_t etmsr_show(struct device *dev,
 474                           struct device_attribute *attr, char *buf)
 475 {
 476         unsigned long flags, val;
 477         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 478
 479         pm_runtime_get_sync(drvdata->dev);
 480         spin_lock_irqsave(&drvdata->spinlock, flags);
 481         CS_UNLOCK(drvdata->base);
 482
 483         val = etm_readl(drvdata, ETMSR);
 484
 485         CS_LOCK(drvdata->base);
 486         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 487         pm_runtime_put(drvdata->dev);
 488
 489         return sprintf(buf, "%#lx\n", val);
 490 }
 491 static DEVICE_ATTR_RO(etmsr);
 492
 493 static ssize_t reset_store(struct device *dev,
 494                            struct device_attribute *attr,
 495                            const char *buf, size_t size)
 496 {
 497         int i, ret;
 498         unsigned long val;
 499         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 500
 501         ret = kstrtoul(buf, 16, &val);
 502         if (ret)
 503                 return ret;
 504
 505         if (val) {
 506                 spin_lock(&drvdata->spinlock);
 507                 drvdata->mode = ETM_MODE_EXCLUDE;
 508                 drvdata->ctrl = 0x0;
 509                 drvdata->trigger_event = ETM_DEFAULT_EVENT_VAL;
 510                 drvdata->startstop_ctrl = 0x0;
 511                 drvdata->addr_idx = 0x0;
 512                 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 513                         drvdata->addr_val[i] = 0x0;
 514                         drvdata->addr_acctype[i] = 0x0;
 515                         drvdata->addr_type[i] = ETM_ADDR_TYPE_NONE;
 516                 }
 517                 drvdata->cntr_idx = 0x0;
 518
 519                 etm_set_default(drvdata);
 520                 spin_unlock(&drvdata->spinlock);
 521         }
 522
 523         return size;
 524 }
 525 static DEVICE_ATTR_WO(reset);
 526
 527 static ssize_t mode_show(struct device *dev,
 528                          struct device_attribute *attr, char *buf)
 529 {
 530         unsigned long val;
 531         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 532
 533         val = drvdata->mode;
 534         return sprintf(buf, "%#lx\n", val);
 535 }
 536
 537 static ssize_t mode_store(struct device *dev,
 538                           struct device_attribute *attr,
 539                           const char *buf, size_t size)
 540 {
 541         int ret;
 542         unsigned long val;
 543         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 544
 545         ret = kstrtoul(buf, 16, &val);
 546         if (ret)
 547                 return ret;
 548
 549         spin_lock(&drvdata->spinlock);
 550         drvdata->mode = val & ETM_MODE_ALL;
 551
 552         if (drvdata->mode & ETM_MODE_EXCLUDE)
 553                 drvdata->enable_ctrl1 |= ETMTECR1_INC_EXC;
 554         else
 555                 drvdata->enable_ctrl1 &= ~ETMTECR1_INC_EXC;
 556
 557         if (drvdata->mode & ETM_MODE_CYCACC)
 558                 drvdata->ctrl |= ETMCR_CYC_ACC;
 559         else
 560                 drvdata->ctrl &= ~ETMCR_CYC_ACC;
 561
 562         if (drvdata->mode & ETM_MODE_STALL) {
 563                 if (!(drvdata->etmccr & ETMCCR_FIFOFULL)) {
 564                         dev_warn(drvdata->dev, "stall mode not supported\n");
 565                         ret = -EINVAL;
 566                         goto err_unlock;
 567                 }
 568                 drvdata->ctrl |= ETMCR_STALL_MODE;
 569          } else
 570                 drvdata->ctrl &= ~ETMCR_STALL_MODE;
 571
 572         if (drvdata->mode & ETM_MODE_TIMESTAMP) {
 573                 if (!(drvdata->etmccer & ETMCCER_TIMESTAMP)) {
 574                         dev_warn(drvdata->dev, "timestamp not supported\n");
 575                         ret = -EINVAL;
 576                         goto err_unlock;
 577                 }
 578                 drvdata->ctrl |= ETMCR_TIMESTAMP_EN;
 579         } else
 580                 drvdata->ctrl &= ~ETMCR_TIMESTAMP_EN;
 581
 582         if (drvdata->mode & ETM_MODE_CTXID)
 583                 drvdata->ctrl |= ETMCR_CTXID_SIZE;
 584         else
 585                 drvdata->ctrl &= ~ETMCR_CTXID_SIZE;
 586         spin_unlock(&drvdata->spinlock);
 587
 588         return size;
 589
 590 err_unlock:
 591         spin_unlock(&drvdata->spinlock);
 592         return ret;
 593 }
 594 static DEVICE_ATTR_RW(mode);
 595
 596 static ssize_t trigger_event_show(struct device *dev,
 597                                   struct device_attribute *attr, char *buf)
 598 {
 599         unsigned long val;
 600         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 601
 602         val = drvdata->trigger_event;
 603         return sprintf(buf, "%#lx\n", val);
 604 }
 605
 606 static ssize_t trigger_event_store(struct device *dev,
 607                                    struct device_attribute *attr,
 608                                    const char *buf, size_t size)
 609 {
 610         int ret;
 611         unsigned long val;
 612         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 613
 614         ret = kstrtoul(buf, 16, &val);
 615         if (ret)
 616                 return ret;
 617
 618         drvdata->trigger_event = val & ETM_EVENT_MASK;
 619
 620         return size;
 621 }
 622 static DEVICE_ATTR_RW(trigger_event);
 623
 624 static ssize_t enable_event_show(struct device *dev,
 625                                  struct device_attribute *attr, char *buf)
 626 {
 627         unsigned long val;
 628         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 629
 630         val = drvdata->enable_event;
 631         return sprintf(buf, "%#lx\n", val);
 632 }
 633
 634 static ssize_t enable_event_store(struct device *dev,
 635                                   struct device_attribute *attr,
 636                                   const char *buf, size_t size)
 637 {
 638         int ret;
 639         unsigned long val;
 640         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 641
 642         ret = kstrtoul(buf, 16, &val);
 643         if (ret)
 644                 return ret;
 645
 646         drvdata->enable_event = val & ETM_EVENT_MASK;
 647
 648         return size;
 649 }
 650 static DEVICE_ATTR_RW(enable_event);
 651
 652 static ssize_t fifofull_level_show(struct device *dev,
 653                                    struct device_attribute *attr, char *buf)
 654 {
 655         unsigned long val;
 656         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 657
 658         val = drvdata->fifofull_level;
 659         return sprintf(buf, "%#lx\n", val);
 660 }
 661
 662 static ssize_t fifofull_level_store(struct device *dev,
 663                                     struct device_attribute *attr,
 664                                     const char *buf, size_t size)
 665 {
 666         int ret;
 667         unsigned long val;
 668         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 669
 670         ret = kstrtoul(buf, 16, &val);
 671         if (ret)
 672                 return ret;
 673
 674         drvdata->fifofull_level = val;
 675
 676         return size;
 677 }
 678 static DEVICE_ATTR_RW(fifofull_level);
 679
 680 static ssize_t addr_idx_show(struct device *dev,
 681                              struct device_attribute *attr, char *buf)
 682 {
 683         unsigned long val;
 684         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 685
 686         val = drvdata->addr_idx;
 687         return sprintf(buf, "%#lx\n", val);
 688 }
 689
 690 static ssize_t addr_idx_store(struct device *dev,
 691                               struct device_attribute *attr,
 692                               const char *buf, size_t size)
 693 {
 694         int ret;
 695         unsigned long val;
 696         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 697
 698         ret = kstrtoul(buf, 16, &val);
 699         if (ret)
 700                 return ret;
 701
 702         if (val >= drvdata->nr_addr_cmp)
 703                 return -EINVAL;
 704
 705         /*
 706          * Use spinlock to ensure index doesn't change while it gets
 707          * dereferenced multiple times within a spinlock block elsewhere.
 708          */
 709         spin_lock(&drvdata->spinlock);
 710         drvdata->addr_idx = val;
 711         spin_unlock(&drvdata->spinlock);
 712
 713         return size;
 714 }
 715 static DEVICE_ATTR_RW(addr_idx);
 716
 717 static ssize_t addr_single_show(struct device *dev,
 718                                 struct device_attribute *attr, char *buf)
 719 {
 720         u8 idx;
 721         unsigned long val;
 722         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 723
 724         spin_lock(&drvdata->spinlock);
 725         idx = drvdata->addr_idx;
 726         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 727               drvdata->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) {
 728                 spin_unlock(&drvdata->spinlock);
 729                 return -EINVAL;
 730         }
 731
 732         val = drvdata->addr_val[idx];
 733         spin_unlock(&drvdata->spinlock);
 734
 735         return sprintf(buf, "%#lx\n", val);
 736 }
 737
 738 static ssize_t addr_single_store(struct device *dev,
 739                                  struct device_attribute *attr,
 740                                  const char *buf, size_t size)
 741 {
 742         u8 idx;
 743         int ret;
 744         unsigned long val;
 745         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 746
 747         ret = kstrtoul(buf, 16, &val);
 748         if (ret)
 749                 return ret;
 750
 751         spin_lock(&drvdata->spinlock);
 752         idx = drvdata->addr_idx;
 753         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 754               drvdata->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) {
 755                 spin_unlock(&drvdata->spinlock);
 756                 return -EINVAL;
 757         }
 758
 759         drvdata->addr_val[idx] = val;
 760         drvdata->addr_type[idx] = ETM_ADDR_TYPE_SINGLE;
 761         spin_unlock(&drvdata->spinlock);
 762
 763         return size;
 764 }
 765 static DEVICE_ATTR_RW(addr_single);
 766
 767 static ssize_t addr_range_show(struct device *dev,
 768                                struct device_attribute *attr, char *buf)
 769 {
 770         u8 idx;
 771         unsigned long val1, val2;
 772         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 773
 774         spin_lock(&drvdata->spinlock);
 775         idx = drvdata->addr_idx;
 776         if (idx % 2 != 0) {
 777                 spin_unlock(&drvdata->spinlock);
 778                 return -EPERM;
 779         }
 780         if (!((drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE &&
 781                drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) ||
 782               (drvdata->addr_type[idx] == ETM_ADDR_TYPE_RANGE &&
 783                drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) {
 784                 spin_unlock(&drvdata->spinlock);
 785                 return -EPERM;
 786         }
 787
 788         val1 = drvdata->addr_val[idx];
 789         val2 = drvdata->addr_val[idx + 1];
 790         spin_unlock(&drvdata->spinlock);
 791
 792         return sprintf(buf, "%#lx %#lx\n", val1, val2);
 793 }
 794
 795 static ssize_t addr_range_store(struct device *dev,
 796                               struct device_attribute *attr,
 797                               const char *buf, size_t size)
 798 {
 799         u8 idx;
 800         unsigned long val1, val2;
 801         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 802
 803         if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
 804                 return -EINVAL;
 805         /* Lower address comparator cannot have a higher address value */
 806         if (val1 > val2)
 807                 return -EINVAL;
 808
 809         spin_lock(&drvdata->spinlock);
 810         idx = drvdata->addr_idx;
 811         if (idx % 2 != 0) {
 812                 spin_unlock(&drvdata->spinlock);
 813                 return -EPERM;
 814         }
 815         if (!((drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE &&
 816                drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) ||
 817               (drvdata->addr_type[idx] == ETM_ADDR_TYPE_RANGE &&
 818                drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) {
 819                 spin_unlock(&drvdata->spinlock);
 820                 return -EPERM;
 821         }
 822
 823         drvdata->addr_val[idx] = val1;
 824         drvdata->addr_type[idx] = ETM_ADDR_TYPE_RANGE;
 825         drvdata->addr_val[idx + 1] = val2;
 826         drvdata->addr_type[idx + 1] = ETM_ADDR_TYPE_RANGE;
 827         drvdata->enable_ctrl1 |= (1 << (idx/2));
 828         spin_unlock(&drvdata->spinlock);
 829
 830         return size;
 831 }
 832 static DEVICE_ATTR_RW(addr_range);
 833
 834 static ssize_t addr_start_show(struct device *dev,
 835                                struct device_attribute *attr, char *buf)
 836 {
 837         u8 idx;
 838         unsigned long val;
 839         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 840
 841         spin_lock(&drvdata->spinlock);
 842         idx = drvdata->addr_idx;
 843         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 844               drvdata->addr_type[idx] == ETM_ADDR_TYPE_START)) {
 845                 spin_unlock(&drvdata->spinlock);
 846                 return -EPERM;
 847         }
 848
 849         val = drvdata->addr_val[idx];
 850         spin_unlock(&drvdata->spinlock);
 851
 852         return sprintf(buf, "%#lx\n", val);
 853 }
 854
 855 static ssize_t addr_start_store(struct device *dev,
 856                                 struct device_attribute *attr,
 857                                 const char *buf, size_t size)
 858 {
 859         u8 idx;
 860         int ret;
 861         unsigned long val;
 862         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 863
 864         ret = kstrtoul(buf, 16, &val);
 865         if (ret)
 866                 return ret;
 867
 868         spin_lock(&drvdata->spinlock);
 869         idx = drvdata->addr_idx;
 870         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 871               drvdata->addr_type[idx] == ETM_ADDR_TYPE_START)) {
 872                 spin_unlock(&drvdata->spinlock);
 873                 return -EPERM;
 874         }
 875
 876         drvdata->addr_val[idx] = val;
 877         drvdata->addr_type[idx] = ETM_ADDR_TYPE_START;
 878         drvdata->startstop_ctrl |= (1 << idx);
 879         drvdata->enable_ctrl1 |= BIT(25);
 880         spin_unlock(&drvdata->spinlock);
 881
 882         return size;
 883 }
 884 static DEVICE_ATTR_RW(addr_start);
 885
 886 static ssize_t addr_stop_show(struct device *dev,
 887                               struct device_attribute *attr, char *buf)
 888 {
 889         u8 idx;
 890         unsigned long val;
 891         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 892
 893         spin_lock(&drvdata->spinlock);
 894         idx = drvdata->addr_idx;
 895         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 896               drvdata->addr_type[idx] == ETM_ADDR_TYPE_STOP)) {
 897                 spin_unlock(&drvdata->spinlock);
 898                 return -EPERM;
 899         }
 900
 901         val = drvdata->addr_val[idx];
 902         spin_unlock(&drvdata->spinlock);
 903
 904         return sprintf(buf, "%#lx\n", val);
 905 }
 906
 907 static ssize_t addr_stop_store(struct device *dev,
 908                                struct device_attribute *attr,
 909                                const char *buf, size_t size)
 910 {
 911         u8 idx;
 912         int ret;
 913         unsigned long val;
 914         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 915
 916         ret = kstrtoul(buf, 16, &val);
 917         if (ret)
 918                 return ret;
 919
 920         spin_lock(&drvdata->spinlock);
 921         idx = drvdata->addr_idx;
 922         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 923               drvdata->addr_type[idx] == ETM_ADDR_TYPE_STOP)) {
 924                 spin_unlock(&drvdata->spinlock);
 925                 return -EPERM;
 926         }
 927
 928         drvdata->addr_val[idx] = val;
 929         drvdata->addr_type[idx] = ETM_ADDR_TYPE_STOP;
 930         drvdata->startstop_ctrl |= (1 << (idx + 16));
 931         drvdata->enable_ctrl1 |= ETMTECR1_START_STOP;
 932         spin_unlock(&drvdata->spinlock);
 933
 934         return size;
 935 }
 936 static DEVICE_ATTR_RW(addr_stop);
 937
 938 static ssize_t addr_acctype_show(struct device *dev,
 939                                  struct device_attribute *attr, char *buf)
 940 {
 941         unsigned long val;
 942         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 943
 944         spin_lock(&drvdata->spinlock);
 945         val = drvdata->addr_acctype[drvdata->addr_idx];
 946         spin_unlock(&drvdata->spinlock);
 947
 948         return sprintf(buf, "%#lx\n", val);
 949 }
 950
 951 static ssize_t addr_acctype_store(struct device *dev,
 952                                   struct device_attribute *attr,
 953                                   const char *buf, size_t size)
 954 {
 955         int ret;
 956         unsigned long val;
 957         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 958
 959         ret = kstrtoul(buf, 16, &val);
 960         if (ret)
 961                 return ret;
 962
 963         spin_lock(&drvdata->spinlock);
 964         drvdata->addr_acctype[drvdata->addr_idx] = val;
 965         spin_unlock(&drvdata->spinlock);
 966
 967         return size;
 968 }
 969 static DEVICE_ATTR_RW(addr_acctype);
 970
 971 static ssize_t cntr_idx_show(struct device *dev,
 972                              struct device_attribute *attr, char *buf)
 973 {
 974         unsigned long val;
 975         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 976
 977         val = drvdata->cntr_idx;
 978         return sprintf(buf, "%#lx\n", val);
 979 }
 980
 981 static ssize_t cntr_idx_store(struct device *dev,
 982                               struct device_attribute *attr,
 983                               const char *buf, size_t size)
 984 {
 985         int ret;
 986         unsigned long val;
 987         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 988
 989         ret = kstrtoul(buf, 16, &val);
 990         if (ret)
 991                 return ret;
 992
 993         if (val >= drvdata->nr_cntr)
 994                 return -EINVAL;
 995         /*
 996          * Use spinlock to ensure index doesn't change while it gets
 997          * dereferenced multiple times within a spinlock block elsewhere.
 998          */
 999         spin_lock(&drvdata->spinlock);
1000         drvdata->cntr_idx = val;
1001         spin_unlock(&drvdata->spinlock);
1002
1003         return size;
1004 }
1005 static DEVICE_ATTR_RW(cntr_idx);
1006
1007 static ssize_t cntr_rld_val_show(struct device *dev,
1008                                  struct device_attribute *attr, char *buf)
1009 {
1010         unsigned long val;
1011         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1012
1013         spin_lock(&drvdata->spinlock);
1014         val = drvdata->cntr_rld_val[drvdata->cntr_idx];
1015         spin_unlock(&drvdata->spinlock);
1016
1017         return sprintf(buf, "%#lx\n", val);
1018 }
1019
1020 static ssize_t cntr_rld_val_store(struct device *dev,
1021                                   struct device_attribute *attr,
1022                                   const char *buf, size_t size)
1023 {
1024         int ret;
1025         unsigned long val;
1026         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1027
1028         ret = kstrtoul(buf, 16, &val);
1029         if (ret)
1030                 return ret;
1031
1032         spin_lock(&drvdata->spinlock);
1033         drvdata->cntr_rld_val[drvdata->cntr_idx] = val;
1034         spin_unlock(&drvdata->spinlock);
1035
1036         return size;
1037 }
1038 static DEVICE_ATTR_RW(cntr_rld_val);
1039
1040 static ssize_t cntr_event_show(struct device *dev,
1041                                struct device_attribute *attr, char *buf)
1042 {
1043         unsigned long val;
1044         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1045
1046         spin_lock(&drvdata->spinlock);
1047         val = drvdata->cntr_event[drvdata->cntr_idx];
1048         spin_unlock(&drvdata->spinlock);
1049
1050         return sprintf(buf, "%#lx\n", val);
1051 }
1052
1053 static ssize_t cntr_event_store(struct device *dev,
1054                                 struct device_attribute *attr,
1055                                 const char *buf, size_t size)
1056 {
1057         int ret;
1058         unsigned long val;
1059         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1060
1061         ret = kstrtoul(buf, 16, &val);
1062         if (ret)
1063                 return ret;
1064
1065         spin_lock(&drvdata->spinlock);
1066         drvdata->cntr_event[drvdata->cntr_idx] = val & ETM_EVENT_MASK;
1067         spin_unlock(&drvdata->spinlock);
1068
1069         return size;
1070 }
1071 static DEVICE_ATTR_RW(cntr_event);
1072
1073 static ssize_t cntr_rld_event_show(struct device *dev,
1074                                    struct device_attribute *attr, char *buf)
1075 {
1076         unsigned long val;
1077         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1078
1079         spin_lock(&drvdata->spinlock);
1080         val = drvdata->cntr_rld_event[drvdata->cntr_idx];
1081         spin_unlock(&drvdata->spinlock);
1082
1083         return sprintf(buf, "%#lx\n", val);
1084 }
1085
1086 static ssize_t cntr_rld_event_store(struct device *dev,
1087                                     struct device_attribute *attr,
1088                                     const char *buf, size_t size)
1089 {
1090         int ret;
1091         unsigned long val;
1092         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1093
1094         ret = kstrtoul(buf, 16, &val);
1095         if (ret)
1096                 return ret;
1097
1098         spin_lock(&drvdata->spinlock);
1099         drvdata->cntr_rld_event[drvdata->cntr_idx] = val & ETM_EVENT_MASK;
1100         spin_unlock(&drvdata->spinlock);
1101
1102         return size;
1103 }
1104 static DEVICE_ATTR_RW(cntr_rld_event);
1105
1106 static ssize_t cntr_val_show(struct device *dev,
1107                              struct device_attribute *attr, char *buf)
1108 {
1109         int i, ret = 0;
1110         u32 val;
1111         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1112
1113         if (!drvdata->enable) {
1114                 spin_lock(&drvdata->spinlock);
1115                 for (i = 0; i < drvdata->nr_cntr; i++)
1116                         ret += sprintf(buf, "counter %d: %x\n",
1117                                        i, drvdata->cntr_val[i]);
1118                 spin_unlock(&drvdata->spinlock);
1119                 return ret;
1120         }
1121
1122         for (i = 0; i < drvdata->nr_cntr; i++) {
1123                 val = etm_readl(drvdata, ETMCNTVRn(i));
1124                 ret += sprintf(buf, "counter %d: %x\n", i, val);
1125         }
1126
1127         return ret;
1128 }
1129
1130 static ssize_t cntr_val_store(struct device *dev,
1131                               struct device_attribute *attr,
1132                               const char *buf, size_t size)
1133 {
1134         int ret;
1135         unsigned long val;
1136         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1137
1138         ret = kstrtoul(buf, 16, &val);
1139         if (ret)
1140                 return ret;
1141
1142         spin_lock(&drvdata->spinlock);
1143         drvdata->cntr_val[drvdata->cntr_idx] = val;
1144         spin_unlock(&drvdata->spinlock);
1145
1146         return size;
1147 }
1148 static DEVICE_ATTR_RW(cntr_val);
1149
1150 static ssize_t seq_12_event_show(struct device *dev,
1151                                  struct device_attribute *attr, char *buf)
1152 {
1153         unsigned long val;
1154         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1155
1156         val = drvdata->seq_12_event;
1157         return sprintf(buf, "%#lx\n", val);
1158 }
1159
1160 static ssize_t seq_12_event_store(struct device *dev,
1161                                   struct device_attribute *attr,
1162                                   const char *buf, size_t size)
1163 {
1164         int ret;
1165         unsigned long val;
1166         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1167
1168         ret = kstrtoul(buf, 16, &val);
1169         if (ret)
1170                 return ret;
1171
1172         drvdata->seq_12_event = val & ETM_EVENT_MASK;
1173         return size;
1174 }
1175 static DEVICE_ATTR_RW(seq_12_event);
1176
1177 static ssize_t seq_21_event_show(struct device *dev,
1178                                  struct device_attribute *attr, char *buf)
1179 {
1180         unsigned long val;
1181         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1182
1183         val = drvdata->seq_21_event;
1184         return sprintf(buf, "%#lx\n", val);
1185 }
1186
1187 static ssize_t seq_21_event_store(struct device *dev,
1188                                   struct device_attribute *attr,
1189                                   const char *buf, size_t size)
1190 {
1191         int ret;
1192         unsigned long val;
1193         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1194
1195         ret = kstrtoul(buf, 16, &val);
1196         if (ret)
1197                 return ret;
1198
1199         drvdata->seq_21_event = val & ETM_EVENT_MASK;
1200         return size;
1201 }
1202 static DEVICE_ATTR_RW(seq_21_event);
1203
1204 static ssize_t seq_23_event_show(struct device *dev,
1205                                  struct device_attribute *attr, char *buf)
1206 {
1207         unsigned long val;
1208         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1209
1210         val = drvdata->seq_23_event;
1211         return sprintf(buf, "%#lx\n", val);
1212 }
1213
1214 static ssize_t seq_23_event_store(struct device *dev,
1215                                   struct device_attribute *attr,
1216                                   const char *buf, size_t size)
1217 {
1218         int ret;
1219         unsigned long val;
1220         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1221
1222         ret = kstrtoul(buf, 16, &val);
1223         if (ret)
1224                 return ret;
1225
1226         drvdata->seq_23_event = val & ETM_EVENT_MASK;
1227         return size;
1228 }
1229 static DEVICE_ATTR_RW(seq_23_event);
1230
1231 static ssize_t seq_31_event_show(struct device *dev,
1232                                  struct device_attribute *attr, char *buf)
1233 {
1234         unsigned long val;
1235         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1236
1237         val = drvdata->seq_31_event;
1238         return sprintf(buf, "%#lx\n", val);
1239 }
1240
1241 static ssize_t seq_31_event_store(struct device *dev,
1242                                   struct device_attribute *attr,
1243                                   const char *buf, size_t size)
1244 {
1245         int ret;
1246         unsigned long val;
1247         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1248
1249         ret = kstrtoul(buf, 16, &val);
1250         if (ret)
1251                 return ret;
1252
1253         drvdata->seq_31_event = val & ETM_EVENT_MASK;
1254         return size;
1255 }
1256 static DEVICE_ATTR_RW(seq_31_event);
1257
1258 static ssize_t seq_32_event_show(struct device *dev,
1259                                  struct device_attribute *attr, char *buf)
1260 {
1261         unsigned long val;
1262         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1263
1264         val = drvdata->seq_32_event;
1265         return sprintf(buf, "%#lx\n", val);
1266 }
1267
1268 static ssize_t seq_32_event_store(struct device *dev,
1269                                   struct device_attribute *attr,
1270                                   const char *buf, size_t size)
1271 {
1272         int ret;
1273         unsigned long val;
1274         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1275
1276         ret = kstrtoul(buf, 16, &val);
1277         if (ret)
1278                 return ret;
1279
1280         drvdata->seq_32_event = val & ETM_EVENT_MASK;
1281         return size;
1282 }
1283 static DEVICE_ATTR_RW(seq_32_event);
1284
1285 static ssize_t seq_13_event_show(struct device *dev,
1286                                  struct device_attribute *attr, char *buf)
1287 {
1288         unsigned long val;
1289         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1290
1291         val = drvdata->seq_13_event;
1292         return sprintf(buf, "%#lx\n", val);
1293 }
1294
1295 static ssize_t seq_13_event_store(struct device *dev,
1296                                   struct device_attribute *attr,
1297                                   const char *buf, size_t size)
1298 {
1299         int ret;
1300         unsigned long val;
1301         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1302
1303         ret = kstrtoul(buf, 16, &val);
1304         if (ret)
1305                 return ret;
1306
1307         drvdata->seq_13_event = val & ETM_EVENT_MASK;
1308         return size;
1309 }
1310 static DEVICE_ATTR_RW(seq_13_event);
1311
1312 static ssize_t seq_curr_state_show(struct device *dev,
1313                                    struct device_attribute *attr, char *buf)
1314 {
1315         unsigned long val, flags;
1316         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1317
1318         if (!drvdata->enable) {
1319                 val = drvdata->seq_curr_state;
1320                 goto out;
1321         }
1322
1323         pm_runtime_get_sync(drvdata->dev);
1324         spin_lock_irqsave(&drvdata->spinlock, flags);
1325
1326         CS_UNLOCK(drvdata->base);
1327         val = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
1328         CS_LOCK(drvdata->base);
1329
1330         spin_unlock_irqrestore(&drvdata->spinlock, flags);
1331         pm_runtime_put(drvdata->dev);
1332 out:
1333         return sprintf(buf, "%#lx\n", val);
1334 }
1335
1336 static ssize_t seq_curr_state_store(struct device *dev,
1337                                     struct device_attribute *attr,
1338                                     const char *buf, size_t size)
1339 {
1340         int ret;
1341         unsigned long val;
1342         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1343
1344         ret = kstrtoul(buf, 16, &val);
1345         if (ret)
1346                 return ret;
1347
1348         if (val > ETM_SEQ_STATE_MAX_VAL)
1349                 return -EINVAL;
1350
1351         drvdata->seq_curr_state = val;
1352
1353         return size;
1354 }
1355 static DEVICE_ATTR_RW(seq_curr_state);
1356
1357 static ssize_t ctxid_idx_show(struct device *dev,
1358                               struct device_attribute *attr, char *buf)
1359 {
1360         unsigned long val;
1361         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1362
1363         val = drvdata->ctxid_idx;
1364         return sprintf(buf, "%#lx\n", val);
1365 }
1366
1367 static ssize_t ctxid_idx_store(struct device *dev,
1368                                 struct device_attribute *attr,
1369                                 const char *buf, size_t size)
1370 {
1371         int ret;
1372         unsigned long val;
1373         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1374
1375         ret = kstrtoul(buf, 16, &val);
1376         if (ret)
1377                 return ret;
1378
1379         if (val >= drvdata->nr_ctxid_cmp)
1380                 return -EINVAL;
1381
1382         /*
1383          * Use spinlock to ensure index doesn't change while it gets
1384          * dereferenced multiple times within a spinlock block elsewhere.
1385          */
1386         spin_lock(&drvdata->spinlock);
1387         drvdata->ctxid_idx = val;
1388         spin_unlock(&drvdata->spinlock);
1389
1390         return size;
1391 }
1392 static DEVICE_ATTR_RW(ctxid_idx);
1393
1394 static ssize_t ctxid_pid_show(struct device *dev,
1395                               struct device_attribute *attr, char *buf)
1396 {
1397         unsigned long val;
1398         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1399
1400         spin_lock(&drvdata->spinlock);
1401         val = drvdata->ctxid_vpid[drvdata->ctxid_idx];
1402         spin_unlock(&drvdata->spinlock);
1403
1404         return sprintf(buf, "%#lx\n", val);
1405 }
1406
1407 static ssize_t ctxid_pid_store(struct device *dev,
1408                                struct device_attribute *attr,
1409                                const char *buf, size_t size)
1410 {
1411         int ret;
1412         unsigned long vpid, pid;
1413         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1414
1415         ret = kstrtoul(buf, 16, &vpid);
1416         if (ret)
1417                 return ret;
1418
1419         pid = coresight_vpid_to_pid(vpid);
1420
1421         spin_lock(&drvdata->spinlock);
1422         drvdata->ctxid_pid[drvdata->ctxid_idx] = pid;
1423         drvdata->ctxid_vpid[drvdata->ctxid_idx] = vpid;
1424         spin_unlock(&drvdata->spinlock);
1425
1426         return size;
1427 }
1428 static DEVICE_ATTR_RW(ctxid_pid);
1429
1430 static ssize_t ctxid_mask_show(struct device *dev,
1431                                struct device_attribute *attr, char *buf)
1432 {
1433         unsigned long val;
1434         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1435
1436         val = drvdata->ctxid_mask;
1437         return sprintf(buf, "%#lx\n", val);
1438 }
1439
1440 static ssize_t ctxid_mask_store(struct device *dev,
1441                                 struct device_attribute *attr,
1442                                 const char *buf, size_t size)
1443 {
1444         int ret;
1445         unsigned long val;
1446         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1447
1448         ret = kstrtoul(buf, 16, &val);
1449         if (ret)
1450                 return ret;
1451
1452         drvdata->ctxid_mask = val;
1453         return size;
1454 }
1455 static DEVICE_ATTR_RW(ctxid_mask);
1456
1457 static ssize_t sync_freq_show(struct device *dev,
1458                               struct device_attribute *attr, char *buf)
1459 {
1460         unsigned long val;
1461         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1462
1463         val = drvdata->sync_freq;
1464         return sprintf(buf, "%#lx\n", val);
1465 }
1466
1467 static ssize_t sync_freq_store(struct device *dev,
1468                                struct device_attribute *attr,
1469                                const char *buf, size_t size)
1470 {
1471         int ret;
1472         unsigned long val;
1473         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1474
1475         ret = kstrtoul(buf, 16, &val);
1476         if (ret)
1477                 return ret;
1478
1479         drvdata->sync_freq = val & ETM_SYNC_MASK;
1480         return size;
1481 }
1482 static DEVICE_ATTR_RW(sync_freq);
1483
1484 static ssize_t timestamp_event_show(struct device *dev,
1485                                     struct device_attribute *attr, char *buf)
1486 {
1487         unsigned long val;
1488         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1489
1490         val = drvdata->timestamp_event;
1491         return sprintf(buf, "%#lx\n", val);
1492 }
1493
1494 static ssize_t timestamp_event_store(struct device *dev,
1495                                      struct device_attribute *attr,
1496                                      const char *buf, size_t size)
1497 {
1498         int ret;
1499         unsigned long val;
1500         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1501
1502         ret = kstrtoul(buf, 16, &val);
1503         if (ret)
1504                 return ret;
1505
1506         drvdata->timestamp_event = val & ETM_EVENT_MASK;
1507         return size;
1508 }
1509 static DEVICE_ATTR_RW(timestamp_event);
1510
1511 static ssize_t cpu_show(struct device *dev,
1512                         struct device_attribute *attr, char *buf)
1513 {
1514         int val;
1515         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1516
1517         val = drvdata->cpu;
1518         return scnprintf(buf, PAGE_SIZE, "%d\n", val);
1519
1520 }
1521 static DEVICE_ATTR_RO(cpu);
1522
1523 static ssize_t traceid_show(struct device *dev,
1524                             struct device_attribute *attr, char *buf)
1525 {
1526         unsigned long val, flags;
1527         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1528
1529         if (!drvdata->enable) {
1530                 val = drvdata->traceid;
1531                 goto out;
1532         }
1533
1534         pm_runtime_get_sync(drvdata->dev);
1535         spin_lock_irqsave(&drvdata->spinlock, flags);
1536         CS_UNLOCK(drvdata->base);
1537
1538         val = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
1539
1540         CS_LOCK(drvdata->base);
1541         spin_unlock_irqrestore(&drvdata->spinlock, flags);
1542         pm_runtime_put(drvdata->dev);
1543 out:
1544         return sprintf(buf, "%#lx\n", val);
1545 }
1546
1547 static ssize_t traceid_store(struct device *dev,
1548                              struct device_attribute *attr,
1549                              const char *buf, size_t size)
1550 {
1551         int ret;
1552         unsigned long val;
1553         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1554
1555         ret = kstrtoul(buf, 16, &val);
1556         if (ret)
1557                 return ret;
1558
1559         drvdata->traceid = val & ETM_TRACEID_MASK;
1560         return size;
1561 }
1562 static DEVICE_ATTR_RW(traceid);
1563
1564 static struct attribute *coresight_etm_attrs[] = {
1565         &dev_attr_nr_addr_cmp.attr,
1566         &dev_attr_nr_cntr.attr,
1567         &dev_attr_nr_ctxid_cmp.attr,
1568         &dev_attr_etmsr.attr,
1569         &dev_attr_reset.attr,
1570         &dev_attr_mode.attr,
1571         &dev_attr_trigger_event.attr,
1572         &dev_attr_enable_event.attr,
1573         &dev_attr_fifofull_level.attr,
1574         &dev_attr_addr_idx.attr,
1575         &dev_attr_addr_single.attr,
1576         &dev_attr_addr_range.attr,
1577         &dev_attr_addr_start.attr,
1578         &dev_attr_addr_stop.attr,
1579         &dev_attr_addr_acctype.attr,
1580         &dev_attr_cntr_idx.attr,
1581         &dev_attr_cntr_rld_val.attr,
1582         &dev_attr_cntr_event.attr,
1583         &dev_attr_cntr_rld_event.attr,
1584         &dev_attr_cntr_val.attr,
1585         &dev_attr_seq_12_event.attr,
1586         &dev_attr_seq_21_event.attr,
1587         &dev_attr_seq_23_event.attr,
1588         &dev_attr_seq_31_event.attr,
1589         &dev_attr_seq_32_event.attr,
1590         &dev_attr_seq_13_event.attr,
1591         &dev_attr_seq_curr_state.attr,
1592         &dev_attr_ctxid_idx.attr,
1593         &dev_attr_ctxid_pid.attr,
1594         &dev_attr_ctxid_mask.attr,
1595         &dev_attr_sync_freq.attr,
1596         &dev_attr_timestamp_event.attr,
1597         &dev_attr_traceid.attr,
1598         &dev_attr_cpu.attr,
1599         NULL,
1600 };
1601
1602 #define coresight_simple_func(name, offset)                             \
1603 static ssize_t name##_show(struct device *_dev,                         \
1604                            struct device_attribute *attr, char *buf)    \
1605 {                                                                       \
1606         struct etm_drvdata *drvdata = dev_get_drvdata(_dev->parent);    \
1607         return scnprintf(buf, PAGE_SIZE, "0x%x\n",                      \
1608                          readl_relaxed(drvdata->base + offset));        \
1609 }                                                                       \
1610 DEVICE_ATTR_RO(name)
1611
1612 coresight_simple_func(etmccr, ETMCCR);
1613 coresight_simple_func(etmccer, ETMCCER);
1614 coresight_simple_func(etmscr, ETMSCR);
1615 coresight_simple_func(etmidr, ETMIDR);
1616 coresight_simple_func(etmcr, ETMCR);
1617 coresight_simple_func(etmtraceidr, ETMTRACEIDR);
1618 coresight_simple_func(etmteevr, ETMTEEVR);
1619 coresight_simple_func(etmtssvr, ETMTSSCR);
1620 coresight_simple_func(etmtecr1, ETMTECR1);
1621 coresight_simple_func(etmtecr2, ETMTECR2);
1622
1623 static struct attribute *coresight_etm_mgmt_attrs[] = {
1624         &dev_attr_etmccr.attr,
1625         &dev_attr_etmccer.attr,
1626         &dev_attr_etmscr.attr,
1627         &dev_attr_etmidr.attr,
1628         &dev_attr_etmcr.attr,
1629         &dev_attr_etmtraceidr.attr,
1630         &dev_attr_etmteevr.attr,
1631         &dev_attr_etmtssvr.attr,
1632         &dev_attr_etmtecr1.attr,
1633         &dev_attr_etmtecr2.attr,
1634         NULL,
1635 };
1636
1637 static const struct attribute_group coresight_etm_group = {
1638         .attrs = coresight_etm_attrs,
1639 };
1640
1641
1642 static const struct attribute_group coresight_etm_mgmt_group = {
1643         .attrs = coresight_etm_mgmt_attrs,
1644         .name = "mgmt",
1645 };
1646
1647 static const struct attribute_group *coresight_etm_groups[] = {
1648         &coresight_etm_group,
1649         &coresight_etm_mgmt_group,
1650         NULL,
1651 };
1652
1653 static int etm_cpu_callback(struct notifier_block *nfb, unsigned long action,
1654                             void *hcpu)
1655 {
1656         unsigned int cpu = (unsigned long)hcpu;
1657
1658         if (!etmdrvdata[cpu])
1659                 goto out;
1660
1661         switch (action & (~CPU_TASKS_FROZEN)) {
1662         case CPU_STARTING:
1663                 spin_lock(&etmdrvdata[cpu]->spinlock);
1664                 if (!etmdrvdata[cpu]->os_unlock) {
1665                         etm_os_unlock(etmdrvdata[cpu]);
1666                         etmdrvdata[cpu]->os_unlock = true;
1667                 }
1668
1669                 if (etmdrvdata[cpu]->enable)
1670                         etm_enable_hw(etmdrvdata[cpu]);
1671                 spin_unlock(&etmdrvdata[cpu]->spinlock);
1672                 break;
1673
1674         case CPU_ONLINE:
1675                 if (etmdrvdata[cpu]->boot_enable &&
1676                     !etmdrvdata[cpu]->sticky_enable)
1677                         coresight_enable(etmdrvdata[cpu]->csdev);
1678                 break;
1679
1680         case CPU_DYING:
1681                 spin_lock(&etmdrvdata[cpu]->spinlock);
1682                 if (etmdrvdata[cpu]->enable)
1683                         etm_disable_hw(etmdrvdata[cpu]);
1684                 spin_unlock(&etmdrvdata[cpu]->spinlock);
1685                 break;
1686         }
1687 out:
1688         return NOTIFY_OK;
1689 }
1690
1691 static struct notifier_block etm_cpu_notifier = {
1692         .notifier_call = etm_cpu_callback,
1693 };
1694
1695 static bool etm_arch_supported(u8 arch)
1696 {
1697         switch (arch) {
1698         case ETM_ARCH_V3_3:
1699                 break;
1700         case ETM_ARCH_V3_5:
1701                 break;
1702         case PFT_ARCH_V1_0:
1703                 break;
1704         case PFT_ARCH_V1_1:
1705                 break;
1706         default:
1707                 return false;
1708         }
1709         return true;
1710 }
1711
1712 static void etm_init_arch_data(void *info)
1713 {
1714         u32 etmidr;
1715         u32 etmccr;
1716         struct etm_drvdata *drvdata = info;
1717
1718         CS_UNLOCK(drvdata->base);
1719
1720         /* First dummy read */
1721         (void)etm_readl(drvdata, ETMPDSR);
1722         /* Provide power to ETM: ETMPDCR[3] == 1 */
1723         etm_set_pwrup(drvdata);
1724         /*
1725          * Clear power down bit since when this bit is set writes to
1726          * certain registers might be ignored.
1727          */
1728         etm_clr_pwrdwn(drvdata);
1729         /*
1730          * Set prog bit. It will be set from reset but this is included to
1731          * ensure it is set
1732          */
1733         etm_set_prog(drvdata);
1734
1735         /* Find all capabilities */
1736         etmidr = etm_readl(drvdata, ETMIDR);
1737         drvdata->arch = BMVAL(etmidr, 4, 11);
1738         drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
1739
1740         drvdata->etmccer = etm_readl(drvdata, ETMCCER);
1741         etmccr = etm_readl(drvdata, ETMCCR);
1742         drvdata->etmccr = etmccr;
1743         drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
1744         drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
1745         drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
1746         drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
1747         drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
1748
1749         etm_set_pwrdwn(drvdata);
1750         etm_clr_pwrup(drvdata);
1751         CS_LOCK(drvdata->base);
1752 }
1753
1754 static void etm_init_default_data(struct etm_drvdata *drvdata)
1755 {
1756         /*
1757          * A trace ID of value 0 is invalid, so let's start at some
1758          * random value that fits in 7 bits and will be just as good.
1759          */
1760         static int etm3x_traceid = 0x10;
1761
1762         u32 flags = (1 << 0 | /* instruction execute*/
1763                      3 << 3 | /* ARM instruction */
1764                      0 << 5 | /* No data value comparison */
1765                      0 << 7 | /* No exact mach */
1766                      0 << 8 | /* Ignore context ID */
1767                      0 << 10); /* Security ignored */
1768
1769         /*
1770          * Initial configuration only - guarantees sources handled by
1771          * this driver have a unique ID at startup time but not between
1772          * all other types of sources.  For that we lean on the core
1773          * framework.
1774          */
1775         drvdata->traceid = etm3x_traceid++;
1776         drvdata->ctrl = (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN);
1777         drvdata->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
1778         if (drvdata->nr_addr_cmp >= 2) {
1779                 drvdata->addr_val[0] = (u32) _stext;
1780                 drvdata->addr_val[1] = (u32) _etext;
1781                 drvdata->addr_acctype[0] = flags;
1782                 drvdata->addr_acctype[1] = flags;
1783                 drvdata->addr_type[0] = ETM_ADDR_TYPE_RANGE;
1784                 drvdata->addr_type[1] = ETM_ADDR_TYPE_RANGE;
1785         }
1786
1787         etm_set_default(drvdata);
1788 }
1789
1790 static int etm_probe(struct amba_device *adev, const struct amba_id *id)
1791 {
1792         int ret;
1793         void __iomem *base;
1794         struct device *dev = &adev->dev;
1795         struct coresight_platform_data *pdata = NULL;
1796         struct etm_drvdata *drvdata;
1797         struct resource *res = &adev->res;
1798         struct coresight_desc *desc;
1799         struct device_node *np = adev->dev.of_node;
1800
1801         desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
1802         if (!desc)
1803                 return -ENOMEM;
1804
1805         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1806         if (!drvdata)
1807                 return -ENOMEM;
1808
1809         if (np) {
1810                 pdata = of_get_coresight_platform_data(dev, np);
1811                 if (IS_ERR(pdata))
1812                         return PTR_ERR(pdata);
1813
1814                 adev->dev.platform_data = pdata;
1815                 drvdata->use_cp14 = of_property_read_bool(np, "arm,cp14");
1816         }
1817
1818         drvdata->dev = &adev->dev;
1819         dev_set_drvdata(dev, drvdata);
1820
1821         /* Validity for the resource is already checked by the AMBA core */
1822         base = devm_ioremap_resource(dev, res);
1823         if (IS_ERR(base))
1824                 return PTR_ERR(base);
1825
1826         drvdata->base = base;
1827
1828         spin_lock_init(&drvdata->spinlock);
1829
1830         drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
1831         if (!IS_ERR(drvdata->atclk)) {
1832                 ret = clk_prepare_enable(drvdata->atclk);
1833                 if (ret)
1834                         return ret;
1835         }
1836
1837         drvdata->cpu = pdata ? pdata->cpu : 0;
1838
1839         get_online_cpus();
1840         etmdrvdata[drvdata->cpu] = drvdata;
1841
1842         if (!smp_call_function_single(drvdata->cpu, etm_os_unlock, drvdata, 1))
1843                 drvdata->os_unlock = true;
1844
1845         if (smp_call_function_single(drvdata->cpu,
1846                                      etm_init_arch_data,  drvdata, 1))
1847                 dev_err(dev, "ETM arch init failed\n");
1848
1849         if (!etm_count++)
1850                 register_hotcpu_notifier(&etm_cpu_notifier);
1851
1852         put_online_cpus();
1853
1854         if (etm_arch_supported(drvdata->arch) == false) {
1855                 ret = -EINVAL;
1856                 goto err_arch_supported;
1857         }
1858         etm_init_default_data(drvdata);
1859
1860         desc->type = CORESIGHT_DEV_TYPE_SOURCE;
1861         desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1862         desc->ops = &etm_cs_ops;
1863         desc->pdata = pdata;
1864         desc->dev = dev;
1865         desc->groups = coresight_etm_groups;
1866         drvdata->csdev = coresight_register(desc);
1867         if (IS_ERR(drvdata->csdev)) {
1868                 ret = PTR_ERR(drvdata->csdev);
1869                 goto err_arch_supported;
1870         }
1871
1872         pm_runtime_put(&adev->dev);
1873         dev_info(dev, "%s initialized\n", (char *)id->data);
1874
1875         if (boot_enable) {
1876                 coresight_enable(drvdata->csdev);
1877                 drvdata->boot_enable = true;
1878         }
1879
1880         return 0;
1881
1882 err_arch_supported:
1883         if (--etm_count == 0)
1884                 unregister_hotcpu_notifier(&etm_cpu_notifier);
1885         return ret;
1886 }
1887
1888 #ifdef CONFIG_PM
1889 static int etm_runtime_suspend(struct device *dev)
1890 {
1891         struct etm_drvdata *drvdata = dev_get_drvdata(dev);
1892
1893         if (drvdata && !IS_ERR(drvdata->atclk))
1894                 clk_disable_unprepare(drvdata->atclk);
1895
1896         return 0;
1897 }
1898
1899 static int etm_runtime_resume(struct device *dev)
1900 {
1901         struct etm_drvdata *drvdata = dev_get_drvdata(dev);
1902
1903         if (drvdata && !IS_ERR(drvdata->atclk))
1904                 clk_prepare_enable(drvdata->atclk);
1905
1906         return 0;
1907 }
1908 #endif
1909
1910 static const struct dev_pm_ops etm_dev_pm_ops = {
1911         SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL)
1912 };
1913
1914 static struct amba_id etm_ids[] = {
1915         {       /* ETM 3.3 */
1916                 .id     = 0x0003b921,
1917                 .mask   = 0x0003ffff,
1918                 .data   = "ETM 3.3",
1919         },
1920         {       /* ETM 3.5 */
1921                 .id     = 0x0003b956,
1922                 .mask   = 0x0003ffff,
1923                 .data   = "ETM 3.5",
1924         },
1925         {       /* PTM 1.0 */
1926                 .id     = 0x0003b950,
1927                 .mask   = 0x0003ffff,
1928                 .data   = "PTM 1.0",
1929         },
1930         {       /* PTM 1.1 */
1931                 .id     = 0x0003b95f,
1932                 .mask   = 0x0003ffff,
1933                 .data   = "PTM 1.1",
1934         },
1935         {       /* PTM 1.1 Qualcomm */
1936                 .id     = 0x0003006f,
1937                 .mask   = 0x0003ffff,
1938                 .data   = "PTM 1.1",
1939         },
1940         { 0, 0},
1941 };
1942
1943 static struct amba_driver etm_driver = {
1944         .drv = {
1945                 .name   = "coresight-etm3x",
1946                 .owner  = THIS_MODULE,
1947                 .pm     = &etm_dev_pm_ops,
1948                 .suppress_bind_attrs = true,
1949         },
1950         .probe          = etm_probe,
1951         .id_table       = etm_ids,
1952 };
1953
1954 module_amba_driver(etm_driver);
1955
1956 MODULE_LICENSE("GPL v2");
1957 MODULE_DESCRIPTION("CoreSight Program Flow Trace driver");