drivers/hwtracing/coresight/coresight-etm4x.c

   1 /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/types.h>
  17 #include <linux/device.h>
  18 #include <linux/io.h>
  19 #include <linux/err.h>
  20 #include <linux/fs.h>
  21 #include <linux/slab.h>
  22 #include <linux/delay.h>
  23 #include <linux/smp.h>
  24 #include <linux/sysfs.h>
  25 #include <linux/stat.h>
  26 #include <linux/clk.h>
  27 #include <linux/cpu.h>
  28 #include <linux/coresight.h>
  29 #include <linux/coresight-pmu.h>
  30 #include <linux/pm_wakeup.h>
  31 #include <linux/amba/bus.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/uaccess.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/perf_event.h>
  36 #include <asm/sections.h>
  37 #include <asm/local.h>
  38
  39 #include "coresight-etm4x.h"
  40
  41 static int boot_enable;
  42 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
  43
  44 /* The number of ETMv4 currently registered */
  45 static int etm4_count;
  46 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
  47
  48 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
  49 {
  50         /* Writing any value to ETMOSLAR unlocks the trace registers */
  51         writel_relaxed(0x0, drvdata->base + TRCOSLAR);
  52         drvdata->os_unlock = true;
  53         isb();
  54 }
  55
  56 static bool etm4_arch_supported(u8 arch)
  57 {
  58         switch (arch) {
  59         case ETM_ARCH_V4:
  60                 break;
  61         default:
  62                 return false;
  63         }
  64         return true;
  65 }
  66
  67 static int etm4_cpu_id(struct coresight_device *csdev)
  68 {
  69         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  70
  71         return drvdata->cpu;
  72 }
  73
  74 static int etm4_trace_id(struct coresight_device *csdev)
  75 {
  76         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  77         unsigned long flags;
  78         int trace_id = -1;
  79
  80         if (!local_read(&drvdata->mode))
  81                 return drvdata->trcid;
  82
  83         spin_lock_irqsave(&drvdata->spinlock, flags);
  84
  85         CS_UNLOCK(drvdata->base);
  86         trace_id = readl_relaxed(drvdata->base + TRCTRACEIDR);
  87         trace_id &= ETM_TRACEID_MASK;
  88         CS_LOCK(drvdata->base);
  89
  90         spin_unlock_irqrestore(&drvdata->spinlock, flags);
  91
  92         return trace_id;
  93 }
  94
  95 static void etm4_enable_hw(void *info)
  96 {
  97         int i;
  98         struct etmv4_drvdata *drvdata = info;
  99         struct etmv4_config *config = &drvdata->config;
 100
 101         CS_UNLOCK(drvdata->base);
 102
 103         etm4_os_unlock(drvdata);
 104
 105         /* Disable the trace unit before programming trace registers */
 106         writel_relaxed(0, drvdata->base + TRCPRGCTLR);
 107
 108         /* wait for TRCSTATR.IDLE to go up */
 109         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
 110                 dev_err(drvdata->dev,
 111                         "timeout observed when probing at offset %#x\n",
 112                         TRCSTATR);
 113
 114         writel_relaxed(config->pe_sel, drvdata->base + TRCPROCSELR);
 115         writel_relaxed(config->cfg, drvdata->base + TRCCONFIGR);
 116         /* nothing specific implemented */
 117         writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
 118         writel_relaxed(config->eventctrl0, drvdata->base + TRCEVENTCTL0R);
 119         writel_relaxed(config->eventctrl1, drvdata->base + TRCEVENTCTL1R);
 120         writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR);
 121         writel_relaxed(config->ts_ctrl, drvdata->base + TRCTSCTLR);
 122         writel_relaxed(config->syncfreq, drvdata->base + TRCSYNCPR);
 123         writel_relaxed(config->ccctlr, drvdata->base + TRCCCCTLR);
 124         writel_relaxed(config->bb_ctrl, drvdata->base + TRCBBCTLR);
 125         writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR);
 126         writel_relaxed(config->vinst_ctrl, drvdata->base + TRCVICTLR);
 127         writel_relaxed(config->viiectlr, drvdata->base + TRCVIIECTLR);
 128         writel_relaxed(config->vissctlr,
 129                        drvdata->base + TRCVISSCTLR);
 130         writel_relaxed(config->vipcssctlr,
 131                        drvdata->base + TRCVIPCSSCTLR);
 132         for (i = 0; i < drvdata->nrseqstate - 1; i++)
 133                 writel_relaxed(config->seq_ctrl[i],
 134                                drvdata->base + TRCSEQEVRn(i));
 135         writel_relaxed(config->seq_rst, drvdata->base + TRCSEQRSTEVR);
 136         writel_relaxed(config->seq_state, drvdata->base + TRCSEQSTR);
 137         writel_relaxed(config->ext_inp, drvdata->base + TRCEXTINSELR);
 138         for (i = 0; i < drvdata->nr_cntr; i++) {
 139                 writel_relaxed(config->cntrldvr[i],
 140                                drvdata->base + TRCCNTRLDVRn(i));
 141                 writel_relaxed(config->cntr_ctrl[i],
 142                                drvdata->base + TRCCNTCTLRn(i));
 143                 writel_relaxed(config->cntr_val[i],
 144                                drvdata->base + TRCCNTVRn(i));
 145         }
 146
 147         /* Resource selector pair 0 is always implemented and reserved */
 148         for (i = 0; i < drvdata->nr_resource * 2; i++)
 149                 writel_relaxed(config->res_ctrl[i],
 150                                drvdata->base + TRCRSCTLRn(i));
 151
 152         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 153                 writel_relaxed(config->ss_ctrl[i],
 154                                drvdata->base + TRCSSCCRn(i));
 155                 writel_relaxed(config->ss_status[i],
 156                                drvdata->base + TRCSSCSRn(i));
 157                 writel_relaxed(config->ss_pe_cmp[i],
 158                                drvdata->base + TRCSSPCICRn(i));
 159         }
 160         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 161                 writeq_relaxed(config->addr_val[i],
 162                                drvdata->base + TRCACVRn(i));
 163                 writeq_relaxed(config->addr_acc[i],
 164                                drvdata->base + TRCACATRn(i));
 165         }
 166         for (i = 0; i < drvdata->numcidc; i++)
 167                 writeq_relaxed(config->ctxid_pid[i],
 168                                drvdata->base + TRCCIDCVRn(i));
 169         writel_relaxed(config->ctxid_mask0, drvdata->base + TRCCIDCCTLR0);
 170         writel_relaxed(config->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
 171
 172         for (i = 0; i < drvdata->numvmidc; i++)
 173                 writeq_relaxed(config->vmid_val[i],
 174                                drvdata->base + TRCVMIDCVRn(i));
 175         writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
 176         writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
 177
 178         /* Enable the trace unit */
 179         writel_relaxed(1, drvdata->base + TRCPRGCTLR);
 180
 181         /* wait for TRCSTATR.IDLE to go back down to '0' */
 182         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
 183                 dev_err(drvdata->dev,
 184                         "timeout observed when probing at offset %#x\n",
 185                         TRCSTATR);
 186
 187         CS_LOCK(drvdata->base);
 188
 189         dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
 190 }
 191
 192 static int etm4_enable_sysfs(struct coresight_device *csdev)
 193 {
 194         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 195         int ret;
 196
 197         spin_lock(&drvdata->spinlock);
 198
 199         /*
 200          * Executing etm4_enable_hw on the cpu whose ETM is being enabled
 201          * ensures that register writes occur when cpu is powered.
 202          */
 203         ret = smp_call_function_single(drvdata->cpu,
 204                                        etm4_enable_hw, drvdata, 1);
 205         if (ret)
 206                 goto err;
 207
 208         drvdata->sticky_enable = true;
 209         spin_unlock(&drvdata->spinlock);
 210
 211         dev_info(drvdata->dev, "ETM tracing enabled\n");
 212         return 0;
 213
 214 err:
 215         spin_unlock(&drvdata->spinlock);
 216         return ret;
 217 }
 218
 219 static int etm4_enable(struct coresight_device *csdev,
 220                        struct perf_event_attr *attr, u32 mode)
 221 {
 222         int ret;
 223         u32 val;
 224         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 225
 226         val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
 227
 228         /* Someone is already using the tracer */
 229         if (val)
 230                 return -EBUSY;
 231
 232         switch (mode) {
 233         case CS_MODE_SYSFS:
 234                 ret = etm4_enable_sysfs(csdev);
 235                 break;
 236         default:
 237                 ret = -EINVAL;
 238         }
 239
 240         /* The tracer didn't start */
 241         if (ret)
 242                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 243
 244         return ret;
 245 }
 246
 247 static void etm4_disable_hw(void *info)
 248 {
 249         u32 control;
 250         struct etmv4_drvdata *drvdata = info;
 251
 252         CS_UNLOCK(drvdata->base);
 253
 254         control = readl_relaxed(drvdata->base + TRCPRGCTLR);
 255
 256         /* EN, bit[0] Trace unit enable bit */
 257         control &= ~0x1;
 258
 259         /* make sure everything completes before disabling */
 260         mb();
 261         isb();
 262         writel_relaxed(control, drvdata->base + TRCPRGCTLR);
 263
 264         CS_LOCK(drvdata->base);
 265
 266         dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
 267 }
 268
 269 static void etm4_disable_sysfs(struct coresight_device *csdev)
 270 {
 271         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 272
 273         /*
 274          * Taking hotplug lock here protects from clocks getting disabled
 275          * with tracing being left on (crash scenario) if user disable occurs
 276          * after cpu online mask indicates the cpu is offline but before the
 277          * DYING hotplug callback is serviced by the ETM driver.
 278          */
 279         get_online_cpus();
 280         spin_lock(&drvdata->spinlock);
 281
 282         /*
 283          * Executing etm4_disable_hw on the cpu whose ETM is being disabled
 284          * ensures that register writes occur when cpu is powered.
 285          */
 286         smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
 287
 288         spin_unlock(&drvdata->spinlock);
 289         put_online_cpus();
 290
 291         dev_info(drvdata->dev, "ETM tracing disabled\n");
 292 }
 293
 294 static void etm4_disable(struct coresight_device *csdev)
 295 {
 296         u32 mode;
 297         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 298
 299         /*
 300          * For as long as the tracer isn't disabled another entity can't
 301          * change its status.  As such we can read the status here without
 302          * fearing it will change under us.
 303          */
 304         mode = local_read(&drvdata->mode);
 305
 306         switch (mode) {
 307         case CS_MODE_DISABLED:
 308                 break;
 309         case CS_MODE_SYSFS:
 310                 etm4_disable_sysfs(csdev);
 311                 break;
 312         }
 313
 314         if (mode)
 315                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 316 }
 317
 318 static const struct coresight_ops_source etm4_source_ops = {
 319         .cpu_id         = etm4_cpu_id,
 320         .trace_id       = etm4_trace_id,
 321         .enable         = etm4_enable,
 322         .disable        = etm4_disable,
 323 };
 324
 325 static const struct coresight_ops etm4_cs_ops = {
 326         .source_ops     = &etm4_source_ops,
 327 };
 328
 329 static void etm4_init_arch_data(void *info)
 330 {
 331         u32 etmidr0;
 332         u32 etmidr1;
 333         u32 etmidr2;
 334         u32 etmidr3;
 335         u32 etmidr4;
 336         u32 etmidr5;
 337         struct etmv4_drvdata *drvdata = info;
 338
 339         /* Make sure all registers are accessible */
 340         etm4_os_unlock(drvdata);
 341
 342         CS_UNLOCK(drvdata->base);
 343
 344         /* find all capabilities of the tracing unit */
 345         etmidr0 = readl_relaxed(drvdata->base + TRCIDR0);
 346
 347         /* INSTP0, bits[2:1] P0 tracing support field */
 348         if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
 349                 drvdata->instrp0 = true;
 350         else
 351                 drvdata->instrp0 = false;
 352
 353         /* TRCBB, bit[5] Branch broadcast tracing support bit */
 354         if (BMVAL(etmidr0, 5, 5))
 355                 drvdata->trcbb = true;
 356         else
 357                 drvdata->trcbb = false;
 358
 359         /* TRCCOND, bit[6] Conditional instruction tracing support bit */
 360         if (BMVAL(etmidr0, 6, 6))
 361                 drvdata->trccond = true;
 362         else
 363                 drvdata->trccond = false;
 364
 365         /* TRCCCI, bit[7] Cycle counting instruction bit */
 366         if (BMVAL(etmidr0, 7, 7))
 367                 drvdata->trccci = true;
 368         else
 369                 drvdata->trccci = false;
 370
 371         /* RETSTACK, bit[9] Return stack bit */
 372         if (BMVAL(etmidr0, 9, 9))
 373                 drvdata->retstack = true;
 374         else
 375                 drvdata->retstack = false;
 376
 377         /* NUMEVENT, bits[11:10] Number of events field */
 378         drvdata->nr_event = BMVAL(etmidr0, 10, 11);
 379         /* QSUPP, bits[16:15] Q element support field */
 380         drvdata->q_support = BMVAL(etmidr0, 15, 16);
 381         /* TSSIZE, bits[28:24] Global timestamp size field */
 382         drvdata->ts_size = BMVAL(etmidr0, 24, 28);
 383
 384         /* base architecture of trace unit */
 385         etmidr1 = readl_relaxed(drvdata->base + TRCIDR1);
 386         /*
 387          * TRCARCHMIN, bits[7:4] architecture the minor version number
 388          * TRCARCHMAJ, bits[11:8] architecture major versin number
 389          */
 390         drvdata->arch = BMVAL(etmidr1, 4, 11);
 391
 392         /* maximum size of resources */
 393         etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
 394         /* CIDSIZE, bits[9:5] Indicates the Context ID size */
 395         drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
 396         /* VMIDSIZE, bits[14:10] Indicates the VMID size */
 397         drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
 398         /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
 399         drvdata->ccsize = BMVAL(etmidr2, 25, 28);
 400
 401         etmidr3 = readl_relaxed(drvdata->base + TRCIDR3);
 402         /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
 403         drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
 404         /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
 405         drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
 406         /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
 407         drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
 408
 409         /*
 410          * TRCERR, bit[24] whether a trace unit can trace a
 411          * system error exception.
 412          */
 413         if (BMVAL(etmidr3, 24, 24))
 414                 drvdata->trc_error = true;
 415         else
 416                 drvdata->trc_error = false;
 417
 418         /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
 419         if (BMVAL(etmidr3, 25, 25))
 420                 drvdata->syncpr = true;
 421         else
 422                 drvdata->syncpr = false;
 423
 424         /* STALLCTL, bit[26] is stall control implemented? */
 425         if (BMVAL(etmidr3, 26, 26))
 426                 drvdata->stallctl = true;
 427         else
 428                 drvdata->stallctl = false;
 429
 430         /* SYSSTALL, bit[27] implementation can support stall control? */
 431         if (BMVAL(etmidr3, 27, 27))
 432                 drvdata->sysstall = true;
 433         else
 434                 drvdata->sysstall = false;
 435
 436         /* NUMPROC, bits[30:28] the number of PEs available for tracing */
 437         drvdata->nr_pe = BMVAL(etmidr3, 28, 30);
 438
 439         /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
 440         if (BMVAL(etmidr3, 31, 31))
 441                 drvdata->nooverflow = true;
 442         else
 443                 drvdata->nooverflow = false;
 444
 445         /* number of resources trace unit supports */
 446         etmidr4 = readl_relaxed(drvdata->base + TRCIDR4);
 447         /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
 448         drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
 449         /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
 450         drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
 451         /*
 452          * NUMRSPAIR, bits[19:16]
 453          * The number of resource pairs conveyed by the HW starts at 0, i.e a
 454          * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
 455          * As such add 1 to the value of NUMRSPAIR for a better representation.
 456          */
 457         drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1;
 458         /*
 459          * NUMSSCC, bits[23:20] the number of single-shot
 460          * comparator control for tracing
 461          */
 462         drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
 463         /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
 464         drvdata->numcidc = BMVAL(etmidr4, 24, 27);
 465         /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
 466         drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
 467
 468         etmidr5 = readl_relaxed(drvdata->base + TRCIDR5);
 469         /* NUMEXTIN, bits[8:0] number of external inputs implemented */
 470         drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
 471         /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
 472         drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
 473         /* ATBTRIG, bit[22] implementation can support ATB triggers? */
 474         if (BMVAL(etmidr5, 22, 22))
 475                 drvdata->atbtrig = true;
 476         else
 477                 drvdata->atbtrig = false;
 478         /*
 479          * LPOVERRIDE, bit[23] implementation supports
 480          * low-power state override
 481          */
 482         if (BMVAL(etmidr5, 23, 23))
 483                 drvdata->lpoverride = true;
 484         else
 485                 drvdata->lpoverride = false;
 486         /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
 487         drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
 488         /* NUMCNTR, bits[30:28] number of counters available for tracing */
 489         drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
 490         CS_LOCK(drvdata->base);
 491 }
 492
 493 static void etm4_set_default(struct etmv4_config *config)
 494 {
 495         if (WARN_ON_ONCE(!config))
 496                 return;
 497
 498         /*
 499          * Make default initialisation trace everything
 500          *
 501          * Select the "always true" resource selector on the
 502          * "Enablign Event" line and configure address range comparator
 503          * '0' to trace all the possible address range.  From there
 504          * configure the "include/exclude" engine to include address
 505          * range comparator '0'.
 506          */
 507
 508         /* disable all events tracing */
 509         config->eventctrl0 = 0x0;
 510         config->eventctrl1 = 0x0;
 511
 512         /* disable stalling */
 513         config->stall_ctrl = 0x0;
 514
 515         /* enable trace synchronization every 4096 bytes, if available */
 516         config->syncfreq = 0xC;
 517
 518         /* disable timestamp event */
 519         config->ts_ctrl = 0x0;
 520
 521         /* TRCVICTLR::EVENT = 0x01, select the always on logic */
 522         config->vinst_ctrl |= BIT(0);
 523
 524         /*
 525          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
 526          * in the started state
 527          */
 528         config->vinst_ctrl |= BIT(9);
 529
 530         /*
 531          * Configure address range comparator '0' to encompass all
 532          * possible addresses.
 533          */
 534
 535         /* First half of default address comparator: start at address 0 */
 536         config->addr_val[ETM_DEFAULT_ADDR_COMP] = 0x0;
 537         /* trace instruction addresses */
 538         config->addr_acc[ETM_DEFAULT_ADDR_COMP] &= ~(BIT(0) | BIT(1));
 539         /* EXLEVEL_NS, bits[12:15], only trace application and kernel space */
 540         config->addr_acc[ETM_DEFAULT_ADDR_COMP] |= ETM_EXLEVEL_NS_HYP;
 541         /* EXLEVEL_S, bits[11:8], don't trace anything in secure state */
 542         config->addr_acc[ETM_DEFAULT_ADDR_COMP] |= (ETM_EXLEVEL_S_APP |
 543                                                     ETM_EXLEVEL_S_OS |
 544                                                     ETM_EXLEVEL_S_HYP);
 545         config->addr_type[ETM_DEFAULT_ADDR_COMP] = ETM_ADDR_TYPE_RANGE;
 546
 547         /*
 548          * Second half of default address comparator: go all
 549          * the way to the top.
 550         */
 551         config->addr_val[ETM_DEFAULT_ADDR_COMP + 1] = ~0x0;
 552         /* trace instruction addresses */
 553         config->addr_acc[ETM_DEFAULT_ADDR_COMP + 1] &= ~(BIT(0) | BIT(1));
 554         /* Address comparator type must be equal for both halves */
 555         config->addr_acc[ETM_DEFAULT_ADDR_COMP + 1] =
 556                                         config->addr_acc[ETM_DEFAULT_ADDR_COMP];
 557         config->addr_type[ETM_DEFAULT_ADDR_COMP + 1] = ETM_ADDR_TYPE_RANGE;
 558
 559         /*
 560          * Configure the ViewInst function to filter on address range
 561          * comparator '0'.
 562          */
 563         config->viiectlr = BIT(0);
 564
 565         /* no start-stop filtering for ViewInst */
 566         config->vissctlr = 0x0;
 567 }
 568
 569 static int etm4_cpu_callback(struct notifier_block *nfb, unsigned long action,
 570                             void *hcpu)
 571 {
 572         unsigned int cpu = (unsigned long)hcpu;
 573
 574         if (!etmdrvdata[cpu])
 575                 goto out;
 576
 577         switch (action & (~CPU_TASKS_FROZEN)) {
 578         case CPU_STARTING:
 579                 spin_lock(&etmdrvdata[cpu]->spinlock);
 580                 if (!etmdrvdata[cpu]->os_unlock) {
 581                         etm4_os_unlock(etmdrvdata[cpu]);
 582                         etmdrvdata[cpu]->os_unlock = true;
 583                 }
 584
 585                 if (local_read(&etmdrvdata[cpu]->mode))
 586                         etm4_enable_hw(etmdrvdata[cpu]);
 587                 spin_unlock(&etmdrvdata[cpu]->spinlock);
 588                 break;
 589
 590         case CPU_ONLINE:
 591                 if (etmdrvdata[cpu]->boot_enable &&
 592                         !etmdrvdata[cpu]->sticky_enable)
 593                         coresight_enable(etmdrvdata[cpu]->csdev);
 594                 break;
 595
 596         case CPU_DYING:
 597                 spin_lock(&etmdrvdata[cpu]->spinlock);
 598                 if (local_read(&etmdrvdata[cpu]->mode))
 599                         etm4_disable_hw(etmdrvdata[cpu]);
 600                 spin_unlock(&etmdrvdata[cpu]->spinlock);
 601                 break;
 602         }
 603 out:
 604         return NOTIFY_OK;
 605 }
 606
 607 static struct notifier_block etm4_cpu_notifier = {
 608         .notifier_call = etm4_cpu_callback,
 609 };
 610
 611 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
 612 {
 613         drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
 614 }
 615
 616 static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
 617 {
 618         int ret;
 619         void __iomem *base;
 620         struct device *dev = &adev->dev;
 621         struct coresight_platform_data *pdata = NULL;
 622         struct etmv4_drvdata *drvdata;
 623         struct resource *res = &adev->res;
 624         struct coresight_desc *desc;
 625         struct device_node *np = adev->dev.of_node;
 626
 627         desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
 628         if (!desc)
 629                 return -ENOMEM;
 630
 631         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 632         if (!drvdata)
 633                 return -ENOMEM;
 634
 635         if (np) {
 636                 pdata = of_get_coresight_platform_data(dev, np);
 637                 if (IS_ERR(pdata))
 638                         return PTR_ERR(pdata);
 639                 adev->dev.platform_data = pdata;
 640         }
 641
 642         drvdata->dev = &adev->dev;
 643         dev_set_drvdata(dev, drvdata);
 644
 645         /* Validity for the resource is already checked by the AMBA core */
 646         base = devm_ioremap_resource(dev, res);
 647         if (IS_ERR(base))
 648                 return PTR_ERR(base);
 649
 650         drvdata->base = base;
 651
 652         spin_lock_init(&drvdata->spinlock);
 653
 654         drvdata->cpu = pdata ? pdata->cpu : 0;
 655
 656         get_online_cpus();
 657         etmdrvdata[drvdata->cpu] = drvdata;
 658
 659         if (smp_call_function_single(drvdata->cpu,
 660                                 etm4_init_arch_data,  drvdata, 1))
 661                 dev_err(dev, "ETM arch init failed\n");
 662
 663         if (!etm4_count++)
 664                 register_hotcpu_notifier(&etm4_cpu_notifier);
 665
 666         put_online_cpus();
 667
 668         if (etm4_arch_supported(drvdata->arch) == false) {
 669                 ret = -EINVAL;
 670                 goto err_arch_supported;
 671         }
 672
 673         etm4_init_trace_id(drvdata);
 674         etm4_set_default(&drvdata->config);
 675
 676         pm_runtime_put(&adev->dev);
 677
 678         desc->type = CORESIGHT_DEV_TYPE_SOURCE;
 679         desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
 680         desc->ops = &etm4_cs_ops;
 681         desc->pdata = pdata;
 682         desc->dev = dev;
 683         desc->groups = coresight_etmv4_groups;
 684         drvdata->csdev = coresight_register(desc);
 685         if (IS_ERR(drvdata->csdev)) {
 686                 ret = PTR_ERR(drvdata->csdev);
 687                 goto err_coresight_register;
 688         }
 689
 690         dev_info(dev, "%s initialized\n", (char *)id->data);
 691
 692         if (boot_enable) {
 693                 coresight_enable(drvdata->csdev);
 694                 drvdata->boot_enable = true;
 695         }
 696
 697         return 0;
 698
 699 err_arch_supported:
 700         pm_runtime_put(&adev->dev);
 701 err_coresight_register:
 702         if (--etm4_count == 0)
 703                 unregister_hotcpu_notifier(&etm4_cpu_notifier);
 704         return ret;
 705 }
 706
 707 static struct amba_id etm4_ids[] = {
 708         {       /* ETM 4.0 - Qualcomm */
 709                 .id     = 0x0003b95d,
 710                 .mask   = 0x0003ffff,
 711                 .data   = "ETM 4.0",
 712         },
 713         {       /* ETM 4.0 - Juno board */
 714                 .id     = 0x000bb95e,
 715                 .mask   = 0x000fffff,
 716                 .data   = "ETM 4.0",
 717         },
 718         { 0, 0},
 719 };
 720
 721 static struct amba_driver etm4x_driver = {
 722         .drv = {
 723                 .name   = "coresight-etm4x",
 724                 .suppress_bind_attrs = true,
 725         },
 726         .probe          = etm4_probe,
 727         .id_table       = etm4_ids,
 728 };
 729 builtin_amba_driver(etm4x_driver);