drivers/i2c/busses/i2c-rk3x.c

   1 /*
   2  * Driver for I2C adapter in Rockchip RK3xxx SoC
   3  *
   4  * Max Schwarz <max.schwarz@online.de>
   5  * based on the patches by Rockchip Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/i2c.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/errno.h>
  17 #include <linux/err.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/io.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/clk.h>
  24 #include <linux/wait.h>
  25 #include <linux/mfd/syscon.h>
  26 #include <linux/regmap.h>
  27 #include <linux/math64.h>
  28
  29
  30 /* Register Map */
  31 #define REG_CON        0x00 /* control register */
  32 #define REG_CLKDIV     0x04 /* clock divisor register */
  33 #define REG_MRXADDR    0x08 /* slave address for REGISTER_TX */
  34 #define REG_MRXRADDR   0x0c /* slave register address for REGISTER_TX */
  35 #define REG_MTXCNT     0x10 /* number of bytes to be transmitted */
  36 #define REG_MRXCNT     0x14 /* number of bytes to be received */
  37 #define REG_IEN        0x18 /* interrupt enable */
  38 #define REG_IPD        0x1c /* interrupt pending */
  39 #define REG_FCNT       0x20 /* finished count */
  40
  41 /* Data buffer offsets */
  42 #define TXBUFFER_BASE 0x100
  43 #define RXBUFFER_BASE 0x200
  44
  45 /* REG_CON bits */
  46 #define REG_CON_EN        BIT(0)
  47 enum {
  48         REG_CON_MOD_TX = 0,      /* transmit data */
  49         REG_CON_MOD_REGISTER_TX, /* select register and restart */
  50         REG_CON_MOD_RX,          /* receive data */
  51         REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes
  52                                   * register addr */
  53 };
  54 #define REG_CON_MOD(mod)  ((mod) << 1)
  55 #define REG_CON_MOD_MASK  (BIT(1) | BIT(2))
  56 #define REG_CON_START     BIT(3)
  57 #define REG_CON_STOP      BIT(4)
  58 #define REG_CON_LASTACK   BIT(5) /* 1: send NACK after last received byte */
  59 #define REG_CON_ACTACK    BIT(6) /* 1: stop if NACK is received */
  60
  61 /* REG_MRXADDR bits */
  62 #define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */
  63
  64 /* REG_IEN/REG_IPD bits */
  65 #define REG_INT_BTF       BIT(0) /* a byte was transmitted */
  66 #define REG_INT_BRF       BIT(1) /* a byte was received */
  67 #define REG_INT_MBTF      BIT(2) /* master data transmit finished */
  68 #define REG_INT_MBRF      BIT(3) /* master data receive finished */
  69 #define REG_INT_START     BIT(4) /* START condition generated */
  70 #define REG_INT_STOP      BIT(5) /* STOP condition generated */
  71 #define REG_INT_NAKRCV    BIT(6) /* NACK received */
  72 #define REG_INT_ALL       0x7f
  73
  74 /* Constants */
  75 #define WAIT_TIMEOUT      200 /* ms */
  76 #define DEFAULT_SCL_RATE  (100 * 1000) /* Hz */
  77
  78 enum rk3x_i2c_state {
  79         STATE_IDLE,
  80         STATE_START,
  81         STATE_READ,
  82         STATE_WRITE,
  83         STATE_STOP
  84 };
  85
  86 /**
  87  * @grf_offset: offset inside the grf regmap for setting the i2c type
  88  */
  89 struct rk3x_i2c_soc_data {
  90         int grf_offset;
  91 };
  92
  93 struct rk3x_i2c {
  94         struct i2c_adapter adap;
  95         struct device *dev;
  96         struct rk3x_i2c_soc_data *soc_data;
  97
  98         /* Hardware resources */
  99         void __iomem *regs;
 100         struct clk *clk;
 101         struct notifier_block clk_rate_nb;
 102
 103         /* Settings */
 104         unsigned int scl_frequency;
 105         unsigned int rise_ns;
 106         unsigned int fall_ns;
 107
 108         /* Synchronization & notification */
 109         spinlock_t lock;
 110         wait_queue_head_t wait;
 111         bool busy;
 112
 113         /* Current message */
 114         struct i2c_msg *msg;
 115         u8 addr;
 116         unsigned int mode;
 117         bool is_last_msg;
 118
 119         /* I2C state machine */
 120         enum rk3x_i2c_state state;
 121         unsigned int processed; /* sent/received bytes */
 122         int error;
 123 };
 124
 125 static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value,
 126                               unsigned int offset)
 127 {
 128         writel(value, i2c->regs + offset);
 129 }
 130
 131 static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset)
 132 {
 133         return readl(i2c->regs + offset);
 134 }
 135
 136 /* Reset all interrupt pending bits */
 137 static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c)
 138 {
 139         i2c_writel(i2c, REG_INT_ALL, REG_IPD);
 140 }
 141
 142 /**
 143  * Generate a START condition, which triggers a REG_INT_START interrupt.
 144  */
 145 static void rk3x_i2c_start(struct rk3x_i2c *i2c)
 146 {
 147         u32 val;
 148
 149         rk3x_i2c_clean_ipd(i2c);
 150         i2c_writel(i2c, REG_INT_START, REG_IEN);
 151
 152         /* enable adapter with correct mode, send START condition */
 153         val = REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START;
 154
 155         /* if we want to react to NACK, set ACTACK bit */
 156         if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
 157                 val |= REG_CON_ACTACK;
 158
 159         i2c_writel(i2c, val, REG_CON);
 160 }
 161
 162 /**
 163  * Generate a STOP condition, which triggers a REG_INT_STOP interrupt.
 164  *
 165  * @error: Error code to return in rk3x_i2c_xfer
 166  */
 167 static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error)
 168 {
 169         unsigned int ctrl;
 170
 171         i2c->processed = 0;
 172         i2c->msg = NULL;
 173         i2c->error = error;
 174
 175         if (i2c->is_last_msg) {
 176                 /* Enable stop interrupt */
 177                 i2c_writel(i2c, REG_INT_STOP, REG_IEN);
 178
 179                 i2c->state = STATE_STOP;
 180
 181                 ctrl = i2c_readl(i2c, REG_CON);
 182                 ctrl |= REG_CON_STOP;
 183                 i2c_writel(i2c, ctrl, REG_CON);
 184         } else {
 185                 /* Signal rk3x_i2c_xfer to start the next message. */
 186                 i2c->busy = false;
 187                 i2c->state = STATE_IDLE;
 188
 189                 /*
 190                  * The HW is actually not capable of REPEATED START. But we can
 191                  * get the intended effect by resetting its internal state
 192                  * and issuing an ordinary START.
 193                  */
 194                 i2c_writel(i2c, 0, REG_CON);
 195
 196                 /* signal that we are finished with the current msg */
 197                 wake_up(&i2c->wait);
 198         }
 199 }
 200
 201 /**
 202  * Setup a read according to i2c->msg
 203  */
 204 static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c)
 205 {
 206         unsigned int len = i2c->msg->len - i2c->processed;
 207         u32 con;
 208
 209         con = i2c_readl(i2c, REG_CON);
 210
 211         /*
 212          * The hw can read up to 32 bytes at a time. If we need more than one
 213          * chunk, send an ACK after the last byte of the current chunk.
 214          */
 215         if (len > 32) {
 216                 len = 32;
 217                 con &= ~REG_CON_LASTACK;
 218         } else {
 219                 con |= REG_CON_LASTACK;
 220         }
 221
 222         /* make sure we are in plain RX mode if we read a second chunk */
 223         if (i2c->processed != 0) {
 224                 con &= ~REG_CON_MOD_MASK;
 225                 con |= REG_CON_MOD(REG_CON_MOD_RX);
 226         }
 227
 228         i2c_writel(i2c, con, REG_CON);
 229         i2c_writel(i2c, len, REG_MRXCNT);
 230 }
 231
 232 /**
 233  * Fill the transmit buffer with data from i2c->msg
 234  */
 235 static void rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c)
 236 {
 237         unsigned int i, j;
 238         u32 cnt = 0;
 239         u32 val;
 240         u8 byte;
 241
 242         for (i = 0; i < 8; ++i) {
 243                 val = 0;
 244                 for (j = 0; j < 4; ++j) {
 245                         if ((i2c->processed == i2c->msg->len) && (cnt != 0))
 246                                 break;
 247
 248                         if (i2c->processed == 0 && cnt == 0)
 249                                 byte = (i2c->addr & 0x7f) << 1;
 250                         else
 251                                 byte = i2c->msg->buf[i2c->processed++];
 252
 253                         val |= byte << (j * 8);
 254                         cnt++;
 255                 }
 256
 257                 i2c_writel(i2c, val, TXBUFFER_BASE + 4 * i);
 258
 259                 if (i2c->processed == i2c->msg->len)
 260                         break;
 261         }
 262
 263         i2c_writel(i2c, cnt, REG_MTXCNT);
 264 }
 265
 266
 267 /* IRQ handlers for individual states */
 268
 269 static void rk3x_i2c_handle_start(struct rk3x_i2c *i2c, unsigned int ipd)
 270 {
 271         if (!(ipd & REG_INT_START)) {
 272                 rk3x_i2c_stop(i2c, -EIO);
 273                 dev_warn(i2c->dev, "unexpected irq in START: 0x%x\n", ipd);
 274                 rk3x_i2c_clean_ipd(i2c);
 275                 return;
 276         }
 277
 278         /* ack interrupt */
 279         i2c_writel(i2c, REG_INT_START, REG_IPD);
 280
 281         /* disable start bit */
 282         i2c_writel(i2c, i2c_readl(i2c, REG_CON) & ~REG_CON_START, REG_CON);
 283
 284         /* enable appropriate interrupts and transition */
 285         if (i2c->mode == REG_CON_MOD_TX) {
 286                 i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN);
 287                 i2c->state = STATE_WRITE;
 288                 rk3x_i2c_fill_transmit_buf(i2c);
 289         } else {
 290                 /* in any other case, we are going to be reading. */
 291                 i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN);
 292                 i2c->state = STATE_READ;
 293                 rk3x_i2c_prepare_read(i2c);
 294         }
 295 }
 296
 297 static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd)
 298 {
 299         if (!(ipd & REG_INT_MBTF)) {
 300                 rk3x_i2c_stop(i2c, -EIO);
 301                 dev_err(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd);
 302                 rk3x_i2c_clean_ipd(i2c);
 303                 return;
 304         }
 305
 306         /* ack interrupt */
 307         i2c_writel(i2c, REG_INT_MBTF, REG_IPD);
 308
 309         /* are we finished? */
 310         if (i2c->processed == i2c->msg->len)
 311                 rk3x_i2c_stop(i2c, i2c->error);
 312         else
 313                 rk3x_i2c_fill_transmit_buf(i2c);
 314 }
 315
 316 static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd)
 317 {
 318         unsigned int i;
 319         unsigned int len = i2c->msg->len - i2c->processed;
 320         u32 uninitialized_var(val);
 321         u8 byte;
 322
 323         /* we only care for MBRF here. */
 324         if (!(ipd & REG_INT_MBRF))
 325                 return;
 326
 327         /* ack interrupt */
 328         i2c_writel(i2c, REG_INT_MBRF, REG_IPD);
 329
 330         /* Can only handle a maximum of 32 bytes at a time */
 331         if (len > 32)
 332                 len = 32;
 333
 334         /* read the data from receive buffer */
 335         for (i = 0; i < len; ++i) {
 336                 if (i % 4 == 0)
 337                         val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4);
 338
 339                 byte = (val >> ((i % 4) * 8)) & 0xff;
 340                 i2c->msg->buf[i2c->processed++] = byte;
 341         }
 342
 343         /* are we finished? */
 344         if (i2c->processed == i2c->msg->len)
 345                 rk3x_i2c_stop(i2c, i2c->error);
 346         else
 347                 rk3x_i2c_prepare_read(i2c);
 348 }
 349
 350 static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd)
 351 {
 352         unsigned int con;
 353
 354         if (!(ipd & REG_INT_STOP)) {
 355                 rk3x_i2c_stop(i2c, -EIO);
 356                 dev_err(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd);
 357                 rk3x_i2c_clean_ipd(i2c);
 358                 return;
 359         }
 360
 361         /* ack interrupt */
 362         i2c_writel(i2c, REG_INT_STOP, REG_IPD);
 363
 364         /* disable STOP bit */
 365         con = i2c_readl(i2c, REG_CON);
 366         con &= ~REG_CON_STOP;
 367         i2c_writel(i2c, con, REG_CON);
 368
 369         i2c->busy = false;
 370         i2c->state = STATE_IDLE;
 371
 372         /* signal rk3x_i2c_xfer that we are finished */
 373         wake_up(&i2c->wait);
 374 }
 375
 376 static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id)
 377 {
 378         struct rk3x_i2c *i2c = dev_id;
 379         unsigned int ipd;
 380
 381         spin_lock(&i2c->lock);
 382
 383         ipd = i2c_readl(i2c, REG_IPD);
 384         if (i2c->state == STATE_IDLE) {
 385                 dev_warn(i2c->dev, "irq in STATE_IDLE, ipd = 0x%x\n", ipd);
 386                 rk3x_i2c_clean_ipd(i2c);
 387                 goto out;
 388         }
 389
 390         dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd);
 391
 392         /* Clean interrupt bits we don't care about */
 393         ipd &= ~(REG_INT_BRF | REG_INT_BTF);
 394
 395         if (ipd & REG_INT_NAKRCV) {
 396                 /*
 397                  * We got a NACK in the last operation. Depending on whether
 398                  * IGNORE_NAK is set, we have to stop the operation and report
 399                  * an error.
 400                  */
 401                 i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD);
 402
 403                 ipd &= ~REG_INT_NAKRCV;
 404
 405                 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
 406                         rk3x_i2c_stop(i2c, -ENXIO);
 407         }
 408
 409         /* is there anything left to handle? */
 410         if ((ipd & REG_INT_ALL) == 0)
 411                 goto out;
 412
 413         switch (i2c->state) {
 414         case STATE_START:
 415                 rk3x_i2c_handle_start(i2c, ipd);
 416                 break;
 417         case STATE_WRITE:
 418                 rk3x_i2c_handle_write(i2c, ipd);
 419                 break;
 420         case STATE_READ:
 421                 rk3x_i2c_handle_read(i2c, ipd);
 422                 break;
 423         case STATE_STOP:
 424                 rk3x_i2c_handle_stop(i2c, ipd);
 425                 break;
 426         case STATE_IDLE:
 427                 break;
 428         }
 429
 430 out:
 431         spin_unlock(&i2c->lock);
 432         return IRQ_HANDLED;
 433 }
 434
 435 /**
 436  * Calculate divider values for desired SCL frequency
 437  *
 438  * @clk_rate: I2C input clock rate
 439  * @scl_rate: Desired SCL rate
 440  * @rise_ns: How many ns it takes for signals to rise.
 441  * @fall_ns: How many ns it takes for signals to fall.
 442  * @div_low: Divider output for low
 443  * @div_high: Divider output for high
 444  *
 445  * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
 446  * a best-effort divider value is returned in divs. If the target rate is
 447  * too high, we silently use the highest possible rate.
 448  */
 449 static int rk3x_i2c_calc_divs(unsigned long clk_rate, unsigned long scl_rate,
 450                               unsigned long rise_ns, unsigned long fall_ns,
 451                               unsigned long *div_low, unsigned long *div_high)
 452 {
 453         unsigned long spec_min_low_ns, spec_min_high_ns;
 454         unsigned long spec_max_data_hold_ns;
 455         unsigned long data_hold_buffer_ns;
 456
 457         unsigned long min_low_ns, min_high_ns;
 458         unsigned long max_low_ns, min_total_ns;
 459
 460         unsigned long clk_rate_khz, scl_rate_khz;
 461
 462         unsigned long min_low_div, min_high_div;
 463         unsigned long max_low_div;
 464
 465         unsigned long min_div_for_hold, min_total_div;
 466         unsigned long extra_div, extra_low_div, ideal_low_div;
 467
 468         int ret = 0;
 469
 470         /* Only support standard-mode and fast-mode */
 471         if (WARN_ON(scl_rate > 400000))
 472                 scl_rate = 400000;
 473
 474         /* prevent scl_rate_khz from becoming 0 */
 475         if (WARN_ON(scl_rate < 1000))
 476                 scl_rate = 1000;
 477
 478         /*
 479          * min_low_ns:  The minimum number of ns we need to hold low to
 480          *              meet I2C specification, should include fall time.
 481          * min_high_ns: The minimum number of ns we need to hold high to
 482          *              meet I2C specification, should include rise time.
 483          * max_low_ns:  The maximum number of ns we can hold low to meet
 484          *              I2C specification.
 485          *
 486          * Note: max_low_ns should be (maximum data hold time * 2 - buffer)
 487          *       This is because the i2c host on Rockchip holds the data line
 488          *       for half the low time.
 489          */
 490         if (scl_rate <= 100000) {
 491                 /* Standard-mode */
 492                 spec_min_low_ns = 4700;
 493                 spec_min_high_ns = 4000;
 494                 spec_max_data_hold_ns = 3450;
 495                 data_hold_buffer_ns = 50;
 496         } else {
 497                 /* Fast-mode */
 498                 spec_min_low_ns = 1300;
 499                 spec_min_high_ns = 600;
 500                 spec_max_data_hold_ns = 900;
 501                 data_hold_buffer_ns = 50;
 502         }
 503         min_low_ns = spec_min_low_ns + fall_ns;
 504         min_high_ns = spec_min_high_ns + rise_ns;
 505         max_low_ns = spec_max_data_hold_ns * 2 - data_hold_buffer_ns;
 506         min_total_ns = min_low_ns + min_high_ns;
 507
 508         /* Adjust to avoid overflow */
 509         clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
 510         scl_rate_khz = scl_rate / 1000;
 511
 512         /*
 513          * We need the total div to be >= this number
 514          * so we don't clock too fast.
 515          */
 516         min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
 517
 518         /* These are the min dividers needed for min hold times. */
 519         min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
 520         min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
 521         min_div_for_hold = (min_low_div + min_high_div);
 522
 523         /*
 524          * This is the maximum divider so we don't go over the maximum.
 525          * We don't round up here (we round down) since this is a maximum.
 526          */
 527         max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000);
 528
 529         if (min_low_div > max_low_div) {
 530                 WARN_ONCE(true,
 531                           "Conflicting, min_low_div %lu, max_low_div %lu\n",
 532                           min_low_div, max_low_div);
 533                 max_low_div = min_low_div;
 534         }
 535
 536         if (min_div_for_hold > min_total_div) {
 537                 /*
 538                  * Time needed to meet hold requirements is important.
 539                  * Just use that.
 540                  */
 541                 *div_low = min_low_div;
 542                 *div_high = min_high_div;
 543         } else {
 544                 /*
 545                  * We've got to distribute some time among the low and high
 546                  * so we don't run too fast.
 547                  */
 548                 extra_div = min_total_div - min_div_for_hold;
 549
 550                 /*
 551                  * We'll try to split things up perfectly evenly,
 552                  * biasing slightly towards having a higher div
 553                  * for low (spend more time low).
 554                  */
 555                 ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns,
 556                                              scl_rate_khz * 8 * min_total_ns);
 557
 558                 /* Don't allow it to go over the maximum */
 559                 if (ideal_low_div > max_low_div)
 560                         ideal_low_div = max_low_div;
 561
 562                 /*
 563                  * Handle when the ideal low div is going to take up
 564                  * more than we have.
 565                  */
 566                 if (ideal_low_div > min_low_div + extra_div)
 567                         ideal_low_div = min_low_div + extra_div;
 568
 569                 /* Give low the "ideal" and give high whatever extra is left */
 570                 extra_low_div = ideal_low_div - min_low_div;
 571                 *div_low = ideal_low_div;
 572                 *div_high = min_high_div + (extra_div - extra_low_div);
 573         }
 574
 575         /*
 576          * Adjust to the fact that the hardware has an implicit "+1".
 577          * NOTE: Above calculations always produce div_low > 0 and div_high > 0.
 578          */
 579         *div_low = *div_low - 1;
 580         *div_high = *div_high - 1;
 581
 582         /* Maximum divider supported by hw is 0xffff */
 583         if (*div_low > 0xffff) {
 584                 *div_low = 0xffff;
 585                 ret = -EINVAL;
 586         }
 587
 588         if (*div_high > 0xffff) {
 589                 *div_high = 0xffff;
 590                 ret = -EINVAL;
 591         }
 592
 593         return ret;
 594 }
 595
 596 static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate)
 597 {
 598         unsigned long div_low, div_high;
 599         u64 t_low_ns, t_high_ns;
 600         int ret;
 601
 602         ret = rk3x_i2c_calc_divs(clk_rate, i2c->scl_frequency, i2c->rise_ns,
 603                                  i2c->fall_ns, &div_low, &div_high);
 604
 605         WARN_ONCE(ret != 0, "Could not reach SCL freq %u", i2c->scl_frequency);
 606
 607         clk_enable(i2c->clk);
 608         i2c_writel(i2c, (div_high << 16) | (div_low & 0xffff), REG_CLKDIV);
 609         clk_disable(i2c->clk);
 610
 611         t_low_ns = div_u64(((u64)div_low + 1) * 8 * 1000000000, clk_rate);
 612         t_high_ns = div_u64(((u64)div_high + 1) * 8 * 1000000000, clk_rate);
 613         dev_dbg(i2c->dev,
 614                 "CLK %lukhz, Req %uns, Act low %lluns high %lluns\n",
 615                 clk_rate / 1000,
 616                 1000000000 / i2c->scl_frequency,
 617                 t_low_ns, t_high_ns);
 618 }
 619
 620 /**
 621  * rk3x_i2c_clk_notifier_cb - Clock rate change callback
 622  * @nb:         Pointer to notifier block
 623  * @event:      Notification reason
 624  * @data:       Pointer to notification data object
 625  *
 626  * The callback checks whether a valid bus frequency can be generated after the
 627  * change. If so, the change is acknowledged, otherwise the change is aborted.
 628  * New dividers are written to the HW in the pre- or post change notification
 629  * depending on the scaling direction.
 630  *
 631  * Code adapted from i2c-cadence.c.
 632  *
 633  * Return:      NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
 634  *              to acknowedge the change, NOTIFY_DONE if the notification is
 635  *              considered irrelevant.
 636  */
 637 static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
 638                                     event, void *data)
 639 {
 640         struct clk_notifier_data *ndata = data;
 641         struct rk3x_i2c *i2c = container_of(nb, struct rk3x_i2c, clk_rate_nb);
 642         unsigned long div_low, div_high;
 643
 644         switch (event) {
 645         case PRE_RATE_CHANGE:
 646                 if (rk3x_i2c_calc_divs(ndata->new_rate, i2c->scl_frequency,
 647                                        i2c->rise_ns, i2c->fall_ns, &div_low,
 648                                        &div_high) != 0)
 649                         return NOTIFY_STOP;
 650
 651                 /* scale up */
 652                 if (ndata->new_rate > ndata->old_rate)
 653                         rk3x_i2c_adapt_div(i2c, ndata->new_rate);
 654
 655                 return NOTIFY_OK;
 656         case POST_RATE_CHANGE:
 657                 /* scale down */
 658                 if (ndata->new_rate < ndata->old_rate)
 659                         rk3x_i2c_adapt_div(i2c, ndata->new_rate);
 660                 return NOTIFY_OK;
 661         case ABORT_RATE_CHANGE:
 662                 /* scale up */
 663                 if (ndata->new_rate > ndata->old_rate)
 664                         rk3x_i2c_adapt_div(i2c, ndata->old_rate);
 665                 return NOTIFY_OK;
 666         default:
 667                 return NOTIFY_DONE;
 668         }
 669 }
 670
 671 /**
 672  * Setup I2C registers for an I2C operation specified by msgs, num.
 673  *
 674  * Must be called with i2c->lock held.
 675  *
 676  * @msgs: I2C msgs to process
 677  * @num: Number of msgs
 678  *
 679  * returns: Number of I2C msgs processed or negative in case of error
 680  */
 681 static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num)
 682 {
 683         u32 addr = (msgs[0].addr & 0x7f) << 1;
 684         int ret = 0;
 685
 686         /*
 687          * The I2C adapter can issue a small (len < 4) write packet before
 688          * reading. This speeds up SMBus-style register reads.
 689          * The MRXADDR/MRXRADDR hold the slave address and the slave register
 690          * address in this case.
 691          */
 692
 693         if (num >= 2 && msgs[0].len < 4 &&
 694             !(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
 695                 u32 reg_addr = 0;
 696                 int i;
 697
 698                 dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n",
 699                         addr >> 1);
 700
 701                 /* Fill MRXRADDR with the register address(es) */
 702                 for (i = 0; i < msgs[0].len; ++i) {
 703                         reg_addr |= msgs[0].buf[i] << (i * 8);
 704                         reg_addr |= REG_MRXADDR_VALID(i);
 705                 }
 706
 707                 /* msgs[0] is handled by hw. */
 708                 i2c->msg = &msgs[1];
 709
 710                 i2c->mode = REG_CON_MOD_REGISTER_TX;
 711
 712                 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR);
 713                 i2c_writel(i2c, reg_addr, REG_MRXRADDR);
 714
 715                 ret = 2;
 716         } else {
 717                 /*
 718                  * We'll have to do it the boring way and process the msgs
 719                  * one-by-one.
 720                  */
 721
 722                 if (msgs[0].flags & I2C_M_RD) {
 723                         addr |= 1; /* set read bit */
 724
 725                         /*
 726                          * We have to transmit the slave addr first. Use
 727                          * MOD_REGISTER_TX for that purpose.
 728                          */
 729                         i2c->mode = REG_CON_MOD_REGISTER_TX;
 730                         i2c_writel(i2c, addr | REG_MRXADDR_VALID(0),
 731                                    REG_MRXADDR);
 732                         i2c_writel(i2c, 0, REG_MRXRADDR);
 733                 } else {
 734                         i2c->mode = REG_CON_MOD_TX;
 735                 }
 736
 737                 i2c->msg = &msgs[0];
 738
 739                 ret = 1;
 740         }
 741
 742         i2c->addr = msgs[0].addr;
 743         i2c->busy = true;
 744         i2c->state = STATE_START;
 745         i2c->processed = 0;
 746         i2c->error = 0;
 747
 748         rk3x_i2c_clean_ipd(i2c);
 749
 750         return ret;
 751 }
 752
 753 static int rk3x_i2c_xfer(struct i2c_adapter *adap,
 754                          struct i2c_msg *msgs, int num)
 755 {
 756         struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data;
 757         unsigned long timeout, flags;
 758         int ret = 0;
 759         int i;
 760
 761         spin_lock_irqsave(&i2c->lock, flags);
 762
 763         clk_enable(i2c->clk);
 764
 765         i2c->is_last_msg = false;
 766
 767         /*
 768          * Process msgs. We can handle more than one message at once (see
 769          * rk3x_i2c_setup()).
 770          */
 771         for (i = 0; i < num; i += ret) {
 772                 ret = rk3x_i2c_setup(i2c, msgs + i, num - i);
 773
 774                 if (ret < 0) {
 775                         dev_err(i2c->dev, "rk3x_i2c_setup() failed\n");
 776                         break;
 777                 }
 778
 779                 if (i + ret >= num)
 780                         i2c->is_last_msg = true;
 781
 782                 spin_unlock_irqrestore(&i2c->lock, flags);
 783
 784                 rk3x_i2c_start(i2c);
 785
 786                 timeout = wait_event_timeout(i2c->wait, !i2c->busy,
 787                                              msecs_to_jiffies(WAIT_TIMEOUT));
 788
 789                 spin_lock_irqsave(&i2c->lock, flags);
 790
 791                 if (timeout == 0) {
 792                         dev_err(i2c->dev, "timeout, ipd: 0x%02x, state: %d\n",
 793                                 i2c_readl(i2c, REG_IPD), i2c->state);
 794
 795                         /* Force a STOP condition without interrupt */
 796                         i2c_writel(i2c, 0, REG_IEN);
 797                         i2c_writel(i2c, REG_CON_EN | REG_CON_STOP, REG_CON);
 798
 799                         i2c->state = STATE_IDLE;
 800
 801                         ret = -ETIMEDOUT;
 802                         break;
 803                 }
 804
 805                 if (i2c->error) {
 806                         ret = i2c->error;
 807                         break;
 808                 }
 809         }
 810
 811         clk_disable(i2c->clk);
 812         spin_unlock_irqrestore(&i2c->lock, flags);
 813
 814         return ret;
 815 }
 816
 817 static u32 rk3x_i2c_func(struct i2c_adapter *adap)
 818 {
 819         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 820 }
 821
 822 static const struct i2c_algorithm rk3x_i2c_algorithm = {
 823         .master_xfer            = rk3x_i2c_xfer,
 824         .functionality          = rk3x_i2c_func,
 825 };
 826
 827 static struct rk3x_i2c_soc_data soc_data[3] = {
 828         { .grf_offset = 0x154 }, /* rk3066 */
 829         { .grf_offset = 0x0a4 }, /* rk3188 */
 830         { .grf_offset = -1 },    /* no I2C switching needed */
 831 };
 832
 833 static const struct of_device_id rk3x_i2c_match[] = {
 834         { .compatible = "rockchip,rk3066-i2c", .data = (void *)&soc_data[0] },
 835         { .compatible = "rockchip,rk3188-i2c", .data = (void *)&soc_data[1] },
 836         { .compatible = "rockchip,rk3288-i2c", .data = (void *)&soc_data[2] },
 837         {},
 838 };
 839
 840 static int rk3x_i2c_probe(struct platform_device *pdev)
 841 {
 842         struct device_node *np = pdev->dev.of_node;
 843         const struct of_device_id *match;
 844         struct rk3x_i2c *i2c;
 845         struct resource *mem;
 846         int ret = 0;
 847         int bus_nr;
 848         u32 value;
 849         int irq;
 850         unsigned long clk_rate;
 851
 852         i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL);
 853         if (!i2c)
 854                 return -ENOMEM;
 855
 856         match = of_match_node(rk3x_i2c_match, np);
 857         i2c->soc_data = (struct rk3x_i2c_soc_data *)match->data;
 858
 859         if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
 860                                  &i2c->scl_frequency)) {
 861                 dev_info(&pdev->dev, "using default SCL frequency: %d\n",
 862                          DEFAULT_SCL_RATE);
 863                 i2c->scl_frequency = DEFAULT_SCL_RATE;
 864         }
 865
 866         if (i2c->scl_frequency == 0 || i2c->scl_frequency > 400 * 1000) {
 867                 dev_warn(&pdev->dev, "invalid SCL frequency specified.\n");
 868                 dev_warn(&pdev->dev, "using default SCL frequency: %d\n",
 869                          DEFAULT_SCL_RATE);
 870                 i2c->scl_frequency = DEFAULT_SCL_RATE;
 871         }
 872
 873         /*
 874          * Read rise and fall time from device tree. If not available use
 875          * the default maximum timing from the specification.
 876          */
 877         if (of_property_read_u32(pdev->dev.of_node, "i2c-scl-rising-time-ns",
 878                                  &i2c->rise_ns)) {
 879                 if (i2c->scl_frequency <= 100000)
 880                         i2c->rise_ns = 1000;
 881                 else
 882                         i2c->rise_ns = 300;
 883         }
 884         if (of_property_read_u32(pdev->dev.of_node, "i2c-scl-falling-time-ns",
 885                                  &i2c->fall_ns))
 886                 i2c->fall_ns = 300;
 887
 888         strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
 889         i2c->adap.owner = THIS_MODULE;
 890         i2c->adap.algo = &rk3x_i2c_algorithm;
 891         i2c->adap.retries = 3;
 892         i2c->adap.dev.of_node = np;
 893         i2c->adap.algo_data = i2c;
 894         i2c->adap.dev.parent = &pdev->dev;
 895
 896         i2c->dev = &pdev->dev;
 897
 898         spin_lock_init(&i2c->lock);
 899         init_waitqueue_head(&i2c->wait);
 900
 901         i2c->clk = devm_clk_get(&pdev->dev, NULL);
 902         if (IS_ERR(i2c->clk)) {
 903                 dev_err(&pdev->dev, "cannot get clock\n");
 904                 return PTR_ERR(i2c->clk);
 905         }
 906
 907         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 908         i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
 909         if (IS_ERR(i2c->regs))
 910                 return PTR_ERR(i2c->regs);
 911
 912         /* Try to set the I2C adapter number from dt */
 913         bus_nr = of_alias_get_id(np, "i2c");
 914
 915         /*
 916          * Switch to new interface if the SoC also offers the old one.
 917          * The control bit is located in the GRF register space.
 918          */
 919         if (i2c->soc_data->grf_offset >= 0) {
 920                 struct regmap *grf;
 921
 922                 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
 923                 if (IS_ERR(grf)) {
 924                         dev_err(&pdev->dev,
 925                                 "rk3x-i2c needs 'rockchip,grf' property\n");
 926                         return PTR_ERR(grf);
 927                 }
 928
 929                 if (bus_nr < 0) {
 930                         dev_err(&pdev->dev, "rk3x-i2c needs i2cX alias");
 931                         return -EINVAL;
 932                 }
 933
 934                 /* 27+i: write mask, 11+i: value */
 935                 value = BIT(27 + bus_nr) | BIT(11 + bus_nr);
 936
 937                 ret = regmap_write(grf, i2c->soc_data->grf_offset, value);
 938                 if (ret != 0) {
 939                         dev_err(i2c->dev, "Could not write to GRF: %d\n", ret);
 940                         return ret;
 941                 }
 942         }
 943
 944         /* IRQ setup */
 945         irq = platform_get_irq(pdev, 0);
 946         if (irq < 0) {
 947                 dev_err(&pdev->dev, "cannot find rk3x IRQ\n");
 948                 return irq;
 949         }
 950
 951         ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq,
 952                                0, dev_name(&pdev->dev), i2c);
 953         if (ret < 0) {
 954                 dev_err(&pdev->dev, "cannot request IRQ\n");
 955                 return ret;
 956         }
 957
 958         platform_set_drvdata(pdev, i2c);
 959
 960         ret = clk_prepare(i2c->clk);
 961         if (ret < 0) {
 962                 dev_err(&pdev->dev, "Could not prepare clock\n");
 963                 return ret;
 964         }
 965
 966         i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb;
 967         ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb);
 968         if (ret != 0) {
 969                 dev_err(&pdev->dev, "Unable to register clock notifier\n");
 970                 goto err_clk;
 971         }
 972
 973         clk_rate = clk_get_rate(i2c->clk);
 974         rk3x_i2c_adapt_div(i2c, clk_rate);
 975
 976         ret = i2c_add_adapter(&i2c->adap);
 977         if (ret < 0) {
 978                 dev_err(&pdev->dev, "Could not register adapter\n");
 979                 goto err_clk_notifier;
 980         }
 981
 982         dev_info(&pdev->dev, "Initialized RK3xxx I2C bus at %p\n", i2c->regs);
 983
 984         return 0;
 985
 986 err_clk_notifier:
 987         clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
 988 err_clk:
 989         clk_unprepare(i2c->clk);
 990         return ret;
 991 }
 992
 993 static int rk3x_i2c_remove(struct platform_device *pdev)
 994 {
 995         struct rk3x_i2c *i2c = platform_get_drvdata(pdev);
 996
 997         i2c_del_adapter(&i2c->adap);
 998
 999         clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
1000         clk_unprepare(i2c->clk);
1001
1002         return 0;
1003 }
1004
1005 static struct platform_driver rk3x_i2c_driver = {
1006         .probe   = rk3x_i2c_probe,
1007         .remove  = rk3x_i2c_remove,
1008         .driver  = {
1009                 .name  = "rk3x-i2c",
1010                 .of_match_table = rk3x_i2c_match,
1011         },
1012 };
1013
1014 module_platform_driver(rk3x_i2c_driver);
1015
1016 MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver");
1017 MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>");
1018 MODULE_LICENSE("GPL v2");