2 * intel_idle.c - native hardware idle loop for modern Intel processors
4 * Copyright (c) 2013, Intel Corporation.
5 * Len Brown <len.brown@intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * intel_idle is a cpuidle driver that loads on specific Intel processors
23 * in lieu of the legacy ACPI processor_idle driver. The intent is to
24 * make Linux more efficient on these processors, as intel_idle knows
25 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
31 * All CPUs have same idle states as boot CPU
33 * Chipset BM_STS (bus master status) bit is a NOP
34 * for preventing entry into deep C-stats
40 * The driver currently initializes for_each_online_cpu() upon modprobe.
41 * It it unaware of subsequent processors hot-added to the system.
42 * This means that if you boot with maxcpus=n and later online
43 * processors above n, those processors will use C1 only.
45 * ACPI has a .suspend hack to turn off deep c-statees during suspend
46 * to avoid complications with the lapic timer workaround.
47 * Have not seen issues with suspend, but may need same workaround here.
51 /* un-comment DEBUG to enable pr_debug() statements */
54 #include <linux/kernel.h>
55 #include <linux/cpuidle.h>
56 #include <linux/tick.h>
57 #include <trace/events/power.h>
58 #include <linux/sched.h>
59 #include <linux/notifier.h>
60 #include <linux/cpu.h>
61 #include <linux/moduleparam.h>
62 #include <asm/cpu_device_id.h>
63 #include <asm/intel-family.h>
64 #include <asm/mwait.h>
67 #define INTEL_IDLE_VERSION "0.4.1"
68 #define PREFIX "intel_idle: "
70 static struct cpuidle_driver intel_idle_driver = {
74 /* intel_idle.max_cstate=0 disables driver */
75 static int max_cstate = CPUIDLE_STATE_MAX - 1;
77 static unsigned int mwait_substates;
79 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
80 /* Reliable LAPIC Timer States, bit 1 for C1 etc. */
81 static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
84 struct cpuidle_state *state_table;
87 * Hardware C-state auto-demotion may not always be optimal.
88 * Indicate which enable bits to clear here.
90 unsigned long auto_demotion_disable_flags;
91 bool byt_auto_demotion_disable_flag;
92 bool disable_promotion_to_c1e;
95 static const struct idle_cpu *icpu;
96 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
97 static int intel_idle(struct cpuidle_device *dev,
98 struct cpuidle_driver *drv, int index);
99 static void intel_idle_freeze(struct cpuidle_device *dev,
100 struct cpuidle_driver *drv, int index);
101 static int intel_idle_cpu_init(int cpu);
103 static struct cpuidle_state *cpuidle_state_table;
106 * Set this flag for states where the HW flushes the TLB for us
107 * and so we don't need cross-calls to keep it consistent.
108 * If this flag is set, SW flushes the TLB, so even if the
109 * HW doesn't do the flushing, this flag is safe to use.
111 #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000
114 * MWAIT takes an 8-bit "hint" in EAX "suggesting"
115 * the C-state (top nibble) and sub-state (bottom nibble)
116 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
118 * We store the hint at the top of our "flags" for each state.
120 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
121 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
124 * States are indexed by the cstate number,
125 * which is also the index into the MWAIT hint array.
126 * Thus C0 is a dummy.
128 static struct cpuidle_state nehalem_cstates[] = {
131 .desc = "MWAIT 0x00",
132 .flags = MWAIT2flg(0x00),
134 .target_residency = 6,
135 .enter = &intel_idle,
136 .enter_freeze = intel_idle_freeze, },
139 .desc = "MWAIT 0x01",
140 .flags = MWAIT2flg(0x01),
142 .target_residency = 20,
143 .enter = &intel_idle,
144 .enter_freeze = intel_idle_freeze, },
147 .desc = "MWAIT 0x10",
148 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
150 .target_residency = 80,
151 .enter = &intel_idle,
152 .enter_freeze = intel_idle_freeze, },
155 .desc = "MWAIT 0x20",
156 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
158 .target_residency = 800,
159 .enter = &intel_idle,
160 .enter_freeze = intel_idle_freeze, },
165 static struct cpuidle_state snb_cstates[] = {
168 .desc = "MWAIT 0x00",
169 .flags = MWAIT2flg(0x00),
171 .target_residency = 2,
172 .enter = &intel_idle,
173 .enter_freeze = intel_idle_freeze, },
176 .desc = "MWAIT 0x01",
177 .flags = MWAIT2flg(0x01),
179 .target_residency = 20,
180 .enter = &intel_idle,
181 .enter_freeze = intel_idle_freeze, },
184 .desc = "MWAIT 0x10",
185 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
187 .target_residency = 211,
188 .enter = &intel_idle,
189 .enter_freeze = intel_idle_freeze, },
192 .desc = "MWAIT 0x20",
193 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
195 .target_residency = 345,
196 .enter = &intel_idle,
197 .enter_freeze = intel_idle_freeze, },
200 .desc = "MWAIT 0x30",
201 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
203 .target_residency = 345,
204 .enter = &intel_idle,
205 .enter_freeze = intel_idle_freeze, },
210 static struct cpuidle_state byt_cstates[] = {
213 .desc = "MWAIT 0x00",
214 .flags = MWAIT2flg(0x00),
216 .target_residency = 1,
217 .enter = &intel_idle,
218 .enter_freeze = intel_idle_freeze, },
221 .desc = "MWAIT 0x58",
222 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
224 .target_residency = 275,
225 .enter = &intel_idle,
226 .enter_freeze = intel_idle_freeze, },
229 .desc = "MWAIT 0x52",
230 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
232 .target_residency = 560,
233 .enter = &intel_idle,
234 .enter_freeze = intel_idle_freeze, },
237 .desc = "MWAIT 0x60",
238 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
239 .exit_latency = 1200,
240 .target_residency = 4000,
241 .enter = &intel_idle,
242 .enter_freeze = intel_idle_freeze, },
245 .desc = "MWAIT 0x64",
246 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
247 .exit_latency = 10000,
248 .target_residency = 20000,
249 .enter = &intel_idle,
250 .enter_freeze = intel_idle_freeze, },
255 static struct cpuidle_state cht_cstates[] = {
258 .desc = "MWAIT 0x00",
259 .flags = MWAIT2flg(0x00),
261 .target_residency = 1,
262 .enter = &intel_idle,
263 .enter_freeze = intel_idle_freeze, },
266 .desc = "MWAIT 0x58",
267 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
269 .target_residency = 275,
270 .enter = &intel_idle,
271 .enter_freeze = intel_idle_freeze, },
274 .desc = "MWAIT 0x52",
275 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
277 .target_residency = 560,
278 .enter = &intel_idle,
279 .enter_freeze = intel_idle_freeze, },
282 .desc = "MWAIT 0x60",
283 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
284 .exit_latency = 1200,
285 .target_residency = 4000,
286 .enter = &intel_idle,
287 .enter_freeze = intel_idle_freeze, },
290 .desc = "MWAIT 0x64",
291 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
292 .exit_latency = 10000,
293 .target_residency = 20000,
294 .enter = &intel_idle,
295 .enter_freeze = intel_idle_freeze, },
300 static struct cpuidle_state ivb_cstates[] = {
303 .desc = "MWAIT 0x00",
304 .flags = MWAIT2flg(0x00),
306 .target_residency = 1,
307 .enter = &intel_idle,
308 .enter_freeze = intel_idle_freeze, },
311 .desc = "MWAIT 0x01",
312 .flags = MWAIT2flg(0x01),
314 .target_residency = 20,
315 .enter = &intel_idle,
316 .enter_freeze = intel_idle_freeze, },
319 .desc = "MWAIT 0x10",
320 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
322 .target_residency = 156,
323 .enter = &intel_idle,
324 .enter_freeze = intel_idle_freeze, },
327 .desc = "MWAIT 0x20",
328 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
330 .target_residency = 300,
331 .enter = &intel_idle,
332 .enter_freeze = intel_idle_freeze, },
335 .desc = "MWAIT 0x30",
336 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
338 .target_residency = 300,
339 .enter = &intel_idle,
340 .enter_freeze = intel_idle_freeze, },
345 static struct cpuidle_state ivt_cstates[] = {
348 .desc = "MWAIT 0x00",
349 .flags = MWAIT2flg(0x00),
351 .target_residency = 1,
352 .enter = &intel_idle,
353 .enter_freeze = intel_idle_freeze, },
356 .desc = "MWAIT 0x01",
357 .flags = MWAIT2flg(0x01),
359 .target_residency = 80,
360 .enter = &intel_idle,
361 .enter_freeze = intel_idle_freeze, },
364 .desc = "MWAIT 0x10",
365 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
367 .target_residency = 156,
368 .enter = &intel_idle,
369 .enter_freeze = intel_idle_freeze, },
372 .desc = "MWAIT 0x20",
373 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
375 .target_residency = 300,
376 .enter = &intel_idle,
377 .enter_freeze = intel_idle_freeze, },
382 static struct cpuidle_state ivt_cstates_4s[] = {
385 .desc = "MWAIT 0x00",
386 .flags = MWAIT2flg(0x00),
388 .target_residency = 1,
389 .enter = &intel_idle,
390 .enter_freeze = intel_idle_freeze, },
392 .name = "C1E-IVT-4S",
393 .desc = "MWAIT 0x01",
394 .flags = MWAIT2flg(0x01),
396 .target_residency = 250,
397 .enter = &intel_idle,
398 .enter_freeze = intel_idle_freeze, },
401 .desc = "MWAIT 0x10",
402 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
404 .target_residency = 300,
405 .enter = &intel_idle,
406 .enter_freeze = intel_idle_freeze, },
409 .desc = "MWAIT 0x20",
410 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
412 .target_residency = 400,
413 .enter = &intel_idle,
414 .enter_freeze = intel_idle_freeze, },
419 static struct cpuidle_state ivt_cstates_8s[] = {
422 .desc = "MWAIT 0x00",
423 .flags = MWAIT2flg(0x00),
425 .target_residency = 1,
426 .enter = &intel_idle,
427 .enter_freeze = intel_idle_freeze, },
429 .name = "C1E-IVT-8S",
430 .desc = "MWAIT 0x01",
431 .flags = MWAIT2flg(0x01),
433 .target_residency = 500,
434 .enter = &intel_idle,
435 .enter_freeze = intel_idle_freeze, },
438 .desc = "MWAIT 0x10",
439 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
441 .target_residency = 600,
442 .enter = &intel_idle,
443 .enter_freeze = intel_idle_freeze, },
446 .desc = "MWAIT 0x20",
447 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
449 .target_residency = 700,
450 .enter = &intel_idle,
451 .enter_freeze = intel_idle_freeze, },
456 static struct cpuidle_state hsw_cstates[] = {
459 .desc = "MWAIT 0x00",
460 .flags = MWAIT2flg(0x00),
462 .target_residency = 2,
463 .enter = &intel_idle,
464 .enter_freeze = intel_idle_freeze, },
467 .desc = "MWAIT 0x01",
468 .flags = MWAIT2flg(0x01),
470 .target_residency = 20,
471 .enter = &intel_idle,
472 .enter_freeze = intel_idle_freeze, },
475 .desc = "MWAIT 0x10",
476 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
478 .target_residency = 100,
479 .enter = &intel_idle,
480 .enter_freeze = intel_idle_freeze, },
483 .desc = "MWAIT 0x20",
484 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
486 .target_residency = 400,
487 .enter = &intel_idle,
488 .enter_freeze = intel_idle_freeze, },
491 .desc = "MWAIT 0x32",
492 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
494 .target_residency = 500,
495 .enter = &intel_idle,
496 .enter_freeze = intel_idle_freeze, },
499 .desc = "MWAIT 0x40",
500 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
502 .target_residency = 900,
503 .enter = &intel_idle,
504 .enter_freeze = intel_idle_freeze, },
507 .desc = "MWAIT 0x50",
508 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
510 .target_residency = 1800,
511 .enter = &intel_idle,
512 .enter_freeze = intel_idle_freeze, },
515 .desc = "MWAIT 0x60",
516 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
517 .exit_latency = 2600,
518 .target_residency = 7700,
519 .enter = &intel_idle,
520 .enter_freeze = intel_idle_freeze, },
524 static struct cpuidle_state bdw_cstates[] = {
527 .desc = "MWAIT 0x00",
528 .flags = MWAIT2flg(0x00),
530 .target_residency = 2,
531 .enter = &intel_idle,
532 .enter_freeze = intel_idle_freeze, },
535 .desc = "MWAIT 0x01",
536 .flags = MWAIT2flg(0x01),
538 .target_residency = 20,
539 .enter = &intel_idle,
540 .enter_freeze = intel_idle_freeze, },
543 .desc = "MWAIT 0x10",
544 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
546 .target_residency = 100,
547 .enter = &intel_idle,
548 .enter_freeze = intel_idle_freeze, },
551 .desc = "MWAIT 0x20",
552 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
554 .target_residency = 400,
555 .enter = &intel_idle,
556 .enter_freeze = intel_idle_freeze, },
559 .desc = "MWAIT 0x32",
560 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
562 .target_residency = 500,
563 .enter = &intel_idle,
564 .enter_freeze = intel_idle_freeze, },
567 .desc = "MWAIT 0x40",
568 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
570 .target_residency = 900,
571 .enter = &intel_idle,
572 .enter_freeze = intel_idle_freeze, },
575 .desc = "MWAIT 0x50",
576 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
578 .target_residency = 1800,
579 .enter = &intel_idle,
580 .enter_freeze = intel_idle_freeze, },
583 .desc = "MWAIT 0x60",
584 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
585 .exit_latency = 2600,
586 .target_residency = 7700,
587 .enter = &intel_idle,
588 .enter_freeze = intel_idle_freeze, },
593 static struct cpuidle_state skl_cstates[] = {
596 .desc = "MWAIT 0x00",
597 .flags = MWAIT2flg(0x00),
599 .target_residency = 2,
600 .enter = &intel_idle,
601 .enter_freeze = intel_idle_freeze, },
604 .desc = "MWAIT 0x01",
605 .flags = MWAIT2flg(0x01),
607 .target_residency = 20,
608 .enter = &intel_idle,
609 .enter_freeze = intel_idle_freeze, },
612 .desc = "MWAIT 0x10",
613 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
615 .target_residency = 100,
616 .enter = &intel_idle,
617 .enter_freeze = intel_idle_freeze, },
620 .desc = "MWAIT 0x20",
621 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
623 .target_residency = 200,
624 .enter = &intel_idle,
625 .enter_freeze = intel_idle_freeze, },
628 .desc = "MWAIT 0x33",
629 .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED,
631 .target_residency = 800,
632 .enter = &intel_idle,
633 .enter_freeze = intel_idle_freeze, },
636 .desc = "MWAIT 0x40",
637 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
639 .target_residency = 800,
640 .enter = &intel_idle,
641 .enter_freeze = intel_idle_freeze, },
644 .desc = "MWAIT 0x50",
645 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
647 .target_residency = 5000,
648 .enter = &intel_idle,
649 .enter_freeze = intel_idle_freeze, },
652 .desc = "MWAIT 0x60",
653 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
655 .target_residency = 5000,
656 .enter = &intel_idle,
657 .enter_freeze = intel_idle_freeze, },
662 static struct cpuidle_state skx_cstates[] = {
665 .desc = "MWAIT 0x00",
666 .flags = MWAIT2flg(0x00),
668 .target_residency = 2,
669 .enter = &intel_idle,
670 .enter_freeze = intel_idle_freeze, },
673 .desc = "MWAIT 0x01",
674 .flags = MWAIT2flg(0x01),
676 .target_residency = 20,
677 .enter = &intel_idle,
678 .enter_freeze = intel_idle_freeze, },
681 .desc = "MWAIT 0x20",
682 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
684 .target_residency = 600,
685 .enter = &intel_idle,
686 .enter_freeze = intel_idle_freeze, },
691 static struct cpuidle_state atom_cstates[] = {
694 .desc = "MWAIT 0x00",
695 .flags = MWAIT2flg(0x00),
697 .target_residency = 20,
698 .enter = &intel_idle,
699 .enter_freeze = intel_idle_freeze, },
702 .desc = "MWAIT 0x10",
703 .flags = MWAIT2flg(0x10),
705 .target_residency = 80,
706 .enter = &intel_idle,
707 .enter_freeze = intel_idle_freeze, },
710 .desc = "MWAIT 0x30",
711 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
713 .target_residency = 400,
714 .enter = &intel_idle,
715 .enter_freeze = intel_idle_freeze, },
718 .desc = "MWAIT 0x52",
719 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
721 .target_residency = 560,
722 .enter = &intel_idle,
723 .enter_freeze = intel_idle_freeze, },
727 static struct cpuidle_state avn_cstates[] = {
730 .desc = "MWAIT 0x00",
731 .flags = MWAIT2flg(0x00),
733 .target_residency = 2,
734 .enter = &intel_idle,
735 .enter_freeze = intel_idle_freeze, },
738 .desc = "MWAIT 0x51",
739 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
741 .target_residency = 45,
742 .enter = &intel_idle,
743 .enter_freeze = intel_idle_freeze, },
747 static struct cpuidle_state knl_cstates[] = {
750 .desc = "MWAIT 0x00",
751 .flags = MWAIT2flg(0x00),
753 .target_residency = 2,
754 .enter = &intel_idle,
755 .enter_freeze = intel_idle_freeze },
758 .desc = "MWAIT 0x10",
759 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
761 .target_residency = 500,
762 .enter = &intel_idle,
763 .enter_freeze = intel_idle_freeze },
768 static struct cpuidle_state bxt_cstates[] = {
771 .desc = "MWAIT 0x00",
772 .flags = MWAIT2flg(0x00),
774 .target_residency = 2,
775 .enter = &intel_idle,
776 .enter_freeze = intel_idle_freeze, },
779 .desc = "MWAIT 0x01",
780 .flags = MWAIT2flg(0x01),
782 .target_residency = 20,
783 .enter = &intel_idle,
784 .enter_freeze = intel_idle_freeze, },
787 .desc = "MWAIT 0x20",
788 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
790 .target_residency = 133,
791 .enter = &intel_idle,
792 .enter_freeze = intel_idle_freeze, },
795 .desc = "MWAIT 0x31",
796 .flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED,
798 .target_residency = 155,
799 .enter = &intel_idle,
800 .enter_freeze = intel_idle_freeze, },
803 .desc = "MWAIT 0x40",
804 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
805 .exit_latency = 1000,
806 .target_residency = 1000,
807 .enter = &intel_idle,
808 .enter_freeze = intel_idle_freeze, },
811 .desc = "MWAIT 0x50",
812 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
813 .exit_latency = 2000,
814 .target_residency = 2000,
815 .enter = &intel_idle,
816 .enter_freeze = intel_idle_freeze, },
819 .desc = "MWAIT 0x60",
820 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
821 .exit_latency = 10000,
822 .target_residency = 10000,
823 .enter = &intel_idle,
824 .enter_freeze = intel_idle_freeze, },
831 * @dev: cpuidle_device
832 * @drv: cpuidle driver
833 * @index: index of cpuidle state
835 * Must be called under local_irq_disable().
837 static int intel_idle(struct cpuidle_device *dev,
838 struct cpuidle_driver *drv, int index)
840 unsigned long ecx = 1; /* break on interrupt flag */
841 struct cpuidle_state *state = &drv->states[index];
842 unsigned long eax = flg2MWAIT(state->flags);
844 int cpu = smp_processor_id();
846 cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
849 * leave_mm() to avoid costly and often unnecessary wakeups
850 * for flushing the user TLB's associated with the active mm.
852 if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
855 if (!(lapic_timer_reliable_states & (1 << (cstate))))
856 tick_broadcast_enter();
858 mwait_idle_with_hints(eax, ecx);
860 if (!(lapic_timer_reliable_states & (1 << (cstate))))
861 tick_broadcast_exit();
867 * intel_idle_freeze - simplified "enter" callback routine for suspend-to-idle
868 * @dev: cpuidle_device
869 * @drv: cpuidle driver
870 * @index: state index
872 static void intel_idle_freeze(struct cpuidle_device *dev,
873 struct cpuidle_driver *drv, int index)
875 unsigned long ecx = 1; /* break on interrupt flag */
876 unsigned long eax = flg2MWAIT(drv->states[index].flags);
878 mwait_idle_with_hints(eax, ecx);
881 static void __setup_broadcast_timer(void *arg)
883 unsigned long on = (unsigned long)arg;
886 tick_broadcast_enable();
888 tick_broadcast_disable();
891 static int cpu_hotplug_notify(struct notifier_block *n,
892 unsigned long action, void *hcpu)
894 int hotcpu = (unsigned long)hcpu;
895 struct cpuidle_device *dev;
897 switch (action & ~CPU_TASKS_FROZEN) {
900 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
901 smp_call_function_single(hotcpu, __setup_broadcast_timer,
905 * Some systems can hotplug a cpu at runtime after
906 * the kernel has booted, we have to initialize the
907 * driver in this case
909 dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
913 if (intel_idle_cpu_init(hotcpu))
921 static struct notifier_block cpu_hotplug_notifier = {
922 .notifier_call = cpu_hotplug_notify,
925 static void auto_demotion_disable(void *dummy)
927 unsigned long long msr_bits;
929 rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
930 msr_bits &= ~(icpu->auto_demotion_disable_flags);
931 wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
933 static void c1e_promotion_disable(void *dummy)
935 unsigned long long msr_bits;
937 rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
939 wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
942 static const struct idle_cpu idle_cpu_nehalem = {
943 .state_table = nehalem_cstates,
944 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
945 .disable_promotion_to_c1e = true,
948 static const struct idle_cpu idle_cpu_atom = {
949 .state_table = atom_cstates,
952 static const struct idle_cpu idle_cpu_lincroft = {
953 .state_table = atom_cstates,
954 .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
957 static const struct idle_cpu idle_cpu_snb = {
958 .state_table = snb_cstates,
959 .disable_promotion_to_c1e = true,
962 static const struct idle_cpu idle_cpu_byt = {
963 .state_table = byt_cstates,
964 .disable_promotion_to_c1e = true,
965 .byt_auto_demotion_disable_flag = true,
968 static const struct idle_cpu idle_cpu_cht = {
969 .state_table = cht_cstates,
970 .disable_promotion_to_c1e = true,
971 .byt_auto_demotion_disable_flag = true,
974 static const struct idle_cpu idle_cpu_ivb = {
975 .state_table = ivb_cstates,
976 .disable_promotion_to_c1e = true,
979 static const struct idle_cpu idle_cpu_ivt = {
980 .state_table = ivt_cstates,
981 .disable_promotion_to_c1e = true,
984 static const struct idle_cpu idle_cpu_hsw = {
985 .state_table = hsw_cstates,
986 .disable_promotion_to_c1e = true,
989 static const struct idle_cpu idle_cpu_bdw = {
990 .state_table = bdw_cstates,
991 .disable_promotion_to_c1e = true,
994 static const struct idle_cpu idle_cpu_skl = {
995 .state_table = skl_cstates,
996 .disable_promotion_to_c1e = true,
999 static const struct idle_cpu idle_cpu_skx = {
1000 .state_table = skx_cstates,
1001 .disable_promotion_to_c1e = true,
1004 static const struct idle_cpu idle_cpu_avn = {
1005 .state_table = avn_cstates,
1006 .disable_promotion_to_c1e = true,
1009 static const struct idle_cpu idle_cpu_knl = {
1010 .state_table = knl_cstates,
1013 static const struct idle_cpu idle_cpu_bxt = {
1014 .state_table = bxt_cstates,
1015 .disable_promotion_to_c1e = true,
1018 #define ICPU(model, cpu) \
1019 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
1021 static const struct x86_cpu_id intel_idle_ids[] __initconst = {
1022 ICPU(INTEL_FAM6_NEHALEM_EP, idle_cpu_nehalem),
1023 ICPU(INTEL_FAM6_NEHALEM, idle_cpu_nehalem),
1024 ICPU(INTEL_FAM6_WESTMERE2, idle_cpu_nehalem),
1025 ICPU(INTEL_FAM6_WESTMERE, idle_cpu_nehalem),
1026 ICPU(INTEL_FAM6_WESTMERE_EP, idle_cpu_nehalem),
1027 ICPU(INTEL_FAM6_NEHALEM_EX, idle_cpu_nehalem),
1028 ICPU(INTEL_FAM6_ATOM_PINEVIEW, idle_cpu_atom),
1029 ICPU(INTEL_FAM6_ATOM_LINCROFT, idle_cpu_lincroft),
1030 ICPU(INTEL_FAM6_WESTMERE_EX, idle_cpu_nehalem),
1031 ICPU(INTEL_FAM6_SANDYBRIDGE, idle_cpu_snb),
1032 ICPU(INTEL_FAM6_SANDYBRIDGE_X, idle_cpu_snb),
1033 ICPU(INTEL_FAM6_ATOM_CEDARVIEW, idle_cpu_atom),
1034 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, idle_cpu_byt),
1035 ICPU(INTEL_FAM6_ATOM_AIRMONT, idle_cpu_cht),
1036 ICPU(INTEL_FAM6_IVYBRIDGE, idle_cpu_ivb),
1037 ICPU(INTEL_FAM6_IVYBRIDGE_X, idle_cpu_ivt),
1038 ICPU(INTEL_FAM6_HASWELL_CORE, idle_cpu_hsw),
1039 ICPU(INTEL_FAM6_HASWELL_X, idle_cpu_hsw),
1040 ICPU(INTEL_FAM6_HASWELL_ULT, idle_cpu_hsw),
1041 ICPU(INTEL_FAM6_HASWELL_GT3E, idle_cpu_hsw),
1042 ICPU(INTEL_FAM6_ATOM_SILVERMONT2, idle_cpu_avn),
1043 ICPU(INTEL_FAM6_BROADWELL_CORE, idle_cpu_bdw),
1044 ICPU(INTEL_FAM6_BROADWELL_GT3E, idle_cpu_bdw),
1045 ICPU(INTEL_FAM6_BROADWELL_X, idle_cpu_bdw),
1046 ICPU(INTEL_FAM6_BROADWELL_XEON_D, idle_cpu_bdw),
1047 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, idle_cpu_skl),
1048 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, idle_cpu_skl),
1049 ICPU(INTEL_FAM6_KABYLAKE_MOBILE, idle_cpu_skl),
1050 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, idle_cpu_skl),
1051 ICPU(INTEL_FAM6_SKYLAKE_X, idle_cpu_skx),
1052 ICPU(INTEL_FAM6_XEON_PHI_KNL, idle_cpu_knl),
1053 ICPU(INTEL_FAM6_ATOM_GOLDMONT, idle_cpu_bxt),
1058 * intel_idle_probe()
1060 static int __init intel_idle_probe(void)
1062 unsigned int eax, ebx, ecx;
1063 const struct x86_cpu_id *id;
1065 if (max_cstate == 0) {
1066 pr_debug(PREFIX "disabled\n");
1070 id = x86_match_cpu(intel_idle_ids);
1072 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
1073 boot_cpu_data.x86 == 6)
1074 pr_debug(PREFIX "does not run on family %d model %d\n",
1075 boot_cpu_data.x86, boot_cpu_data.x86_model);
1079 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
1082 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
1084 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
1085 !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
1089 pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
1091 icpu = (const struct idle_cpu *)id->driver_data;
1092 cpuidle_state_table = icpu->state_table;
1094 pr_debug(PREFIX "v" INTEL_IDLE_VERSION
1095 " model 0x%X\n", boot_cpu_data.x86_model);
1101 * intel_idle_cpuidle_devices_uninit()
1102 * Unregisters the cpuidle devices.
1104 static void intel_idle_cpuidle_devices_uninit(void)
1107 struct cpuidle_device *dev;
1109 for_each_online_cpu(i) {
1110 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
1111 cpuidle_unregister_device(dev);
1116 * ivt_idle_state_table_update(void)
1118 * Tune IVT multi-socket targets
1119 * Assumption: num_sockets == (max_package_num + 1)
1121 static void ivt_idle_state_table_update(void)
1123 /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
1124 int cpu, package_num, num_sockets = 1;
1126 for_each_online_cpu(cpu) {
1127 package_num = topology_physical_package_id(cpu);
1128 if (package_num + 1 > num_sockets) {
1129 num_sockets = package_num + 1;
1131 if (num_sockets > 4) {
1132 cpuidle_state_table = ivt_cstates_8s;
1138 if (num_sockets > 2)
1139 cpuidle_state_table = ivt_cstates_4s;
1141 /* else, 1 and 2 socket systems use default ivt_cstates */
1145 * Translate IRTL (Interrupt Response Time Limit) MSR to usec
1148 static unsigned int irtl_ns_units[] = {
1149 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
1151 static unsigned long long irtl_2_usec(unsigned long long irtl)
1153 unsigned long long ns;
1155 ns = irtl_ns_units[(irtl >> 10) & 0x3];
1157 return div64_u64((irtl & 0x3FF) * ns, 1000);
1160 * bxt_idle_state_table_update(void)
1162 * On BXT, we trust the IRTL to show the definitive maximum latency
1163 * We use the same value for target_residency.
1165 static void bxt_idle_state_table_update(void)
1167 unsigned long long msr;
1169 rdmsrl(MSR_PKGC6_IRTL, msr);
1171 unsigned int usec = irtl_2_usec(msr);
1173 bxt_cstates[2].exit_latency = usec;
1174 bxt_cstates[2].target_residency = usec;
1177 rdmsrl(MSR_PKGC7_IRTL, msr);
1179 unsigned int usec = irtl_2_usec(msr);
1181 bxt_cstates[3].exit_latency = usec;
1182 bxt_cstates[3].target_residency = usec;
1185 rdmsrl(MSR_PKGC8_IRTL, msr);
1187 unsigned int usec = irtl_2_usec(msr);
1189 bxt_cstates[4].exit_latency = usec;
1190 bxt_cstates[4].target_residency = usec;
1193 rdmsrl(MSR_PKGC9_IRTL, msr);
1195 unsigned int usec = irtl_2_usec(msr);
1197 bxt_cstates[5].exit_latency = usec;
1198 bxt_cstates[5].target_residency = usec;
1201 rdmsrl(MSR_PKGC10_IRTL, msr);
1203 unsigned int usec = irtl_2_usec(msr);
1205 bxt_cstates[6].exit_latency = usec;
1206 bxt_cstates[6].target_residency = usec;
1211 * sklh_idle_state_table_update(void)
1213 * On SKL-H (model 0x5e) disable C8 and C9 if:
1214 * C10 is enabled and SGX disabled
1216 static void sklh_idle_state_table_update(void)
1218 unsigned long long msr;
1219 unsigned int eax, ebx, ecx, edx;
1222 /* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */
1223 if (max_cstate <= 7)
1226 /* if PC10 not present in CPUID.MWAIT.EDX */
1227 if ((mwait_substates & (0xF << 28)) == 0)
1230 rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr);
1232 /* PC10 is not enabled in PKG C-state limit */
1233 if ((msr & 0xF) != 8)
1237 cpuid(7, &eax, &ebx, &ecx, &edx);
1239 /* if SGX is present */
1240 if (ebx & (1 << 2)) {
1242 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1244 /* if SGX is enabled */
1245 if (msr & (1 << 18))
1249 skl_cstates[5].disabled = 1; /* C8-SKL */
1250 skl_cstates[6].disabled = 1; /* C9-SKL */
1253 * intel_idle_state_table_update()
1255 * Update the default state_table for this CPU-id
1258 static void intel_idle_state_table_update(void)
1260 switch (boot_cpu_data.x86_model) {
1262 case INTEL_FAM6_IVYBRIDGE_X:
1263 ivt_idle_state_table_update();
1265 case INTEL_FAM6_ATOM_GOLDMONT:
1266 bxt_idle_state_table_update();
1268 case INTEL_FAM6_SKYLAKE_DESKTOP:
1269 sklh_idle_state_table_update();
1275 * intel_idle_cpuidle_driver_init()
1276 * allocate, initialize cpuidle_states
1278 static void __init intel_idle_cpuidle_driver_init(void)
1281 struct cpuidle_driver *drv = &intel_idle_driver;
1283 intel_idle_state_table_update();
1285 drv->state_count = 1;
1287 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
1288 int num_substates, mwait_hint, mwait_cstate;
1290 if ((cpuidle_state_table[cstate].enter == NULL) &&
1291 (cpuidle_state_table[cstate].enter_freeze == NULL))
1294 if (cstate + 1 > max_cstate) {
1295 printk(PREFIX "max_cstate %d reached\n",
1300 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
1301 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
1303 /* number of sub-states for this state in CPUID.MWAIT */
1304 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
1305 & MWAIT_SUBSTATE_MASK;
1307 /* if NO sub-states for this state in CPUID, skip it */
1308 if (num_substates == 0)
1311 /* if state marked as disabled, skip it */
1312 if (cpuidle_state_table[cstate].disabled != 0) {
1313 pr_debug(PREFIX "state %s is disabled",
1314 cpuidle_state_table[cstate].name);
1319 if (((mwait_cstate + 1) > 2) &&
1320 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
1321 mark_tsc_unstable("TSC halts in idle"
1322 " states deeper than C2");
1324 drv->states[drv->state_count] = /* structure copy */
1325 cpuidle_state_table[cstate];
1327 drv->state_count += 1;
1330 if (icpu->byt_auto_demotion_disable_flag) {
1331 wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
1332 wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
1338 * intel_idle_cpu_init()
1339 * allocate, initialize, register cpuidle_devices
1340 * @cpu: cpu/core to initialize
1342 static int intel_idle_cpu_init(int cpu)
1344 struct cpuidle_device *dev;
1346 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1350 if (cpuidle_register_device(dev)) {
1351 pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
1355 if (icpu->auto_demotion_disable_flags)
1356 smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);
1358 if (icpu->disable_promotion_to_c1e)
1359 smp_call_function_single(cpu, c1e_promotion_disable, NULL, 1);
1364 static int __init intel_idle_init(void)
1368 /* Do not load intel_idle at all for now if idle= is passed */
1369 if (boot_option_idle_override != IDLE_NO_OVERRIDE)
1372 retval = intel_idle_probe();
1376 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
1377 if (intel_idle_cpuidle_devices == NULL)
1380 intel_idle_cpuidle_driver_init();
1381 retval = cpuidle_register_driver(&intel_idle_driver);
1383 struct cpuidle_driver *drv = cpuidle_get_driver();
1384 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
1385 drv ? drv->name : "none");
1386 free_percpu(intel_idle_cpuidle_devices);
1390 cpu_notifier_register_begin();
1392 for_each_online_cpu(i) {
1393 retval = intel_idle_cpu_init(i);
1395 intel_idle_cpuidle_devices_uninit();
1396 cpu_notifier_register_done();
1397 cpuidle_unregister_driver(&intel_idle_driver);
1398 free_percpu(intel_idle_cpuidle_devices);
1402 __register_cpu_notifier(&cpu_hotplug_notifier);
1404 if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
1405 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
1407 on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
1409 cpu_notifier_register_done();
1411 pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
1412 lapic_timer_reliable_states);
1416 device_initcall(intel_idle_init);
1419 * We are not really modular, but we used to support that. Meaning we also
1420 * support "intel_idle.max_cstate=..." at boot and also a read-only export of
1421 * it at /sys/module/intel_idle/parameters/max_cstate -- so using module_param
1422 * is the easiest way (currently) to continue doing that.
1424 module_param(max_cstate, int, 0444);