drivers/infiniband/hw/cxgb4/qp.c

   1 /*
   2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34
  35 #include "iw_cxgb4.h"
  36
  37 static int db_delay_usecs = 1;
  38 module_param(db_delay_usecs, int, 0644);
  39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
  40
  41 static int ocqp_support = 1;
  42 module_param(ocqp_support, int, 0644);
  43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
  44
  45 int db_fc_threshold = 1000;
  46 module_param(db_fc_threshold, int, 0644);
  47 MODULE_PARM_DESC(db_fc_threshold,
  48                  "QP count/threshold that triggers"
  49                  " automatic db flow control mode (default = 1000)");
  50
  51 int db_coalescing_threshold;
  52 module_param(db_coalescing_threshold, int, 0644);
  53 MODULE_PARM_DESC(db_coalescing_threshold,
  54                  "QP count/threshold that triggers"
  55                  " disabling db coalescing (default = 0)");
  56
  57 static int max_fr_immd = T4_MAX_FR_IMMD;
  58 module_param(max_fr_immd, int, 0644);
  59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
  60
  61 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
  62 {
  63         unsigned long flag;
  64         spin_lock_irqsave(&qhp->lock, flag);
  65         qhp->attr.state = state;
  66         spin_unlock_irqrestore(&qhp->lock, flag);
  67 }
  68
  69 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  70 {
  71         c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
  72 }
  73
  74 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  75 {
  76         dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
  77                           pci_unmap_addr(sq, mapping));
  78 }
  79
  80 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  81 {
  82         if (t4_sq_onchip(sq))
  83                 dealloc_oc_sq(rdev, sq);
  84         else
  85                 dealloc_host_sq(rdev, sq);
  86 }
  87
  88 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  89 {
  90         if (!ocqp_support || !ocqp_supported(&rdev->lldi))
  91                 return -ENOSYS;
  92         sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
  93         if (!sq->dma_addr)
  94                 return -ENOMEM;
  95         sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
  96                         rdev->lldi.vr->ocq.start;
  97         sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
  98                                             rdev->lldi.vr->ocq.start);
  99         sq->flags |= T4_SQ_ONCHIP;
 100         return 0;
 101 }
 102
 103 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
 104 {
 105         sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
 106                                        &(sq->dma_addr), GFP_KERNEL);
 107         if (!sq->queue)
 108                 return -ENOMEM;
 109         sq->phys_addr = virt_to_phys(sq->queue);
 110         pci_unmap_addr_set(sq, mapping, sq->dma_addr);
 111         return 0;
 112 }
 113
 114 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 115                       struct c4iw_dev_ucontext *uctx)
 116 {
 117         /*
 118          * uP clears EQ contexts when the connection exits rdma mode,
 119          * so no need to post a RESET WR for these EQs.
 120          */
 121         dma_free_coherent(&(rdev->lldi.pdev->dev),
 122                           wq->rq.memsize, wq->rq.queue,
 123                           dma_unmap_addr(&wq->rq, mapping));
 124         dealloc_sq(rdev, &wq->sq);
 125         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 126         kfree(wq->rq.sw_rq);
 127         kfree(wq->sq.sw_sq);
 128         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 129         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 130         return 0;
 131 }
 132
 133 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 134                      struct t4_cq *rcq, struct t4_cq *scq,
 135                      struct c4iw_dev_ucontext *uctx)
 136 {
 137         int user = (uctx != &rdev->uctx);
 138         struct fw_ri_res_wr *res_wr;
 139         struct fw_ri_res *res;
 140         int wr_len;
 141         struct c4iw_wr_wait wr_wait;
 142         struct sk_buff *skb;
 143         int ret = 0;
 144         int eqsize;
 145
 146         wq->sq.qid = c4iw_get_qpid(rdev, uctx);
 147         if (!wq->sq.qid)
 148                 return -ENOMEM;
 149
 150         wq->rq.qid = c4iw_get_qpid(rdev, uctx);
 151         if (!wq->rq.qid) {
 152                 ret = -ENOMEM;
 153                 goto free_sq_qid;
 154         }
 155
 156         if (!user) {
 157                 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
 158                                  GFP_KERNEL);
 159                 if (!wq->sq.sw_sq) {
 160                         ret = -ENOMEM;
 161                         goto free_rq_qid;
 162                 }
 163
 164                 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
 165                                  GFP_KERNEL);
 166                 if (!wq->rq.sw_rq) {
 167                         ret = -ENOMEM;
 168                         goto free_sw_sq;
 169                 }
 170         }
 171
 172         /*
 173          * RQT must be a power of 2.
 174          */
 175         wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
 176         wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
 177         if (!wq->rq.rqt_hwaddr) {
 178                 ret = -ENOMEM;
 179                 goto free_sw_rq;
 180         }
 181
 182         if (user) {
 183                 if (alloc_oc_sq(rdev, &wq->sq) && alloc_host_sq(rdev, &wq->sq))
 184                         goto free_hwaddr;
 185         } else {
 186                 ret = alloc_host_sq(rdev, &wq->sq);
 187                 if (ret)
 188                         goto free_hwaddr;
 189         }
 190
 191         memset(wq->sq.queue, 0, wq->sq.memsize);
 192         dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
 193
 194         wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
 195                                           wq->rq.memsize, &(wq->rq.dma_addr),
 196                                           GFP_KERNEL);
 197         if (!wq->rq.queue)
 198                 goto free_sq;
 199         PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
 200                 __func__, wq->sq.queue,
 201                 (unsigned long long)virt_to_phys(wq->sq.queue),
 202                 wq->rq.queue,
 203                 (unsigned long long)virt_to_phys(wq->rq.queue));
 204         memset(wq->rq.queue, 0, wq->rq.memsize);
 205         dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
 206
 207         wq->db = rdev->lldi.db_reg;
 208         wq->gts = rdev->lldi.gts_reg;
 209         if (user) {
 210                 wq->sq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
 211                                         (wq->sq.qid << rdev->qpshift);
 212                 wq->sq.udb &= PAGE_MASK;
 213                 wq->rq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
 214                                         (wq->rq.qid << rdev->qpshift);
 215                 wq->rq.udb &= PAGE_MASK;
 216         }
 217         wq->rdev = rdev;
 218         wq->rq.msn = 1;
 219
 220         /* build fw_ri_res_wr */
 221         wr_len = sizeof *res_wr + 2 * sizeof *res;
 222
 223         skb = alloc_skb(wr_len, GFP_KERNEL);
 224         if (!skb) {
 225                 ret = -ENOMEM;
 226                 goto free_dma;
 227         }
 228         set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
 229
 230         res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
 231         memset(res_wr, 0, wr_len);
 232         res_wr->op_nres = cpu_to_be32(
 233                         FW_WR_OP(FW_RI_RES_WR) |
 234                         V_FW_RI_RES_WR_NRES(2) |
 235                         FW_WR_COMPL(1));
 236         res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
 237         res_wr->cookie = (unsigned long) &wr_wait;
 238         res = res_wr->res;
 239         res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
 240         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 241
 242         /*
 243          * eqsize is the number of 64B entries plus the status page size.
 244          */
 245         eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
 246
 247         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
 248                 V_FW_RI_RES_WR_HOSTFCMODE(0) |  /* no host cidx updates */
 249                 V_FW_RI_RES_WR_CPRIO(0) |       /* don't keep in chip cache */
 250                 V_FW_RI_RES_WR_PCIECHN(0) |     /* set by uP at ri_init time */
 251                 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
 252                 V_FW_RI_RES_WR_IQID(scq->cqid));
 253         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
 254                 V_FW_RI_RES_WR_DCAEN(0) |
 255                 V_FW_RI_RES_WR_DCACPU(0) |
 256                 V_FW_RI_RES_WR_FBMIN(2) |
 257                 V_FW_RI_RES_WR_FBMAX(2) |
 258                 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
 259                 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
 260                 V_FW_RI_RES_WR_EQSIZE(eqsize));
 261         res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
 262         res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
 263         res++;
 264         res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
 265         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 266
 267         /*
 268          * eqsize is the number of 64B entries plus the status page size.
 269          */
 270         eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
 271         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
 272                 V_FW_RI_RES_WR_HOSTFCMODE(0) |  /* no host cidx updates */
 273                 V_FW_RI_RES_WR_CPRIO(0) |       /* don't keep in chip cache */
 274                 V_FW_RI_RES_WR_PCIECHN(0) |     /* set by uP at ri_init time */
 275                 V_FW_RI_RES_WR_IQID(rcq->cqid));
 276         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
 277                 V_FW_RI_RES_WR_DCAEN(0) |
 278                 V_FW_RI_RES_WR_DCACPU(0) |
 279                 V_FW_RI_RES_WR_FBMIN(2) |
 280                 V_FW_RI_RES_WR_FBMAX(2) |
 281                 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
 282                 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
 283                 V_FW_RI_RES_WR_EQSIZE(eqsize));
 284         res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
 285         res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
 286
 287         c4iw_init_wr_wait(&wr_wait);
 288
 289         ret = c4iw_ofld_send(rdev, skb);
 290         if (ret)
 291                 goto free_dma;
 292         ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
 293         if (ret)
 294                 goto free_dma;
 295
 296         PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n",
 297              __func__, wq->sq.qid, wq->rq.qid, wq->db,
 298              (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb);
 299
 300         return 0;
 301 free_dma:
 302         dma_free_coherent(&(rdev->lldi.pdev->dev),
 303                           wq->rq.memsize, wq->rq.queue,
 304                           dma_unmap_addr(&wq->rq, mapping));
 305 free_sq:
 306         dealloc_sq(rdev, &wq->sq);
 307 free_hwaddr:
 308         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 309 free_sw_rq:
 310         kfree(wq->rq.sw_rq);
 311 free_sw_sq:
 312         kfree(wq->sq.sw_sq);
 313 free_rq_qid:
 314         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 315 free_sq_qid:
 316         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 317         return ret;
 318 }
 319
 320 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
 321                       struct ib_send_wr *wr, int max, u32 *plenp)
 322 {
 323         u8 *dstp, *srcp;
 324         u32 plen = 0;
 325         int i;
 326         int rem, len;
 327
 328         dstp = (u8 *)immdp->data;
 329         for (i = 0; i < wr->num_sge; i++) {
 330                 if ((plen + wr->sg_list[i].length) > max)
 331                         return -EMSGSIZE;
 332                 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
 333                 plen += wr->sg_list[i].length;
 334                 rem = wr->sg_list[i].length;
 335                 while (rem) {
 336                         if (dstp == (u8 *)&sq->queue[sq->size])
 337                                 dstp = (u8 *)sq->queue;
 338                         if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
 339                                 len = rem;
 340                         else
 341                                 len = (u8 *)&sq->queue[sq->size] - dstp;
 342                         memcpy(dstp, srcp, len);
 343                         dstp += len;
 344                         srcp += len;
 345                         rem -= len;
 346                 }
 347         }
 348         len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
 349         if (len)
 350                 memset(dstp, 0, len);
 351         immdp->op = FW_RI_DATA_IMMD;
 352         immdp->r1 = 0;
 353         immdp->r2 = 0;
 354         immdp->immdlen = cpu_to_be32(plen);
 355         *plenp = plen;
 356         return 0;
 357 }
 358
 359 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
 360                       struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
 361                       int num_sge, u32 *plenp)
 362
 363 {
 364         int i;
 365         u32 plen = 0;
 366         __be64 *flitp = (__be64 *)isglp->sge;
 367
 368         for (i = 0; i < num_sge; i++) {
 369                 if ((plen + sg_list[i].length) < plen)
 370                         return -EMSGSIZE;
 371                 plen += sg_list[i].length;
 372                 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
 373                                      sg_list[i].length);
 374                 if (++flitp == queue_end)
 375                         flitp = queue_start;
 376                 *flitp = cpu_to_be64(sg_list[i].addr);
 377                 if (++flitp == queue_end)
 378                         flitp = queue_start;
 379         }
 380         *flitp = (__force __be64)0;
 381         isglp->op = FW_RI_DATA_ISGL;
 382         isglp->r1 = 0;
 383         isglp->nsge = cpu_to_be16(num_sge);
 384         isglp->r2 = 0;
 385         if (plenp)
 386                 *plenp = plen;
 387         return 0;
 388 }
 389
 390 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
 391                            struct ib_send_wr *wr, u8 *len16)
 392 {
 393         u32 plen;
 394         int size;
 395         int ret;
 396
 397         if (wr->num_sge > T4_MAX_SEND_SGE)
 398                 return -EINVAL;
 399         switch (wr->opcode) {
 400         case IB_WR_SEND:
 401                 if (wr->send_flags & IB_SEND_SOLICITED)
 402                         wqe->send.sendop_pkd = cpu_to_be32(
 403                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
 404                 else
 405                         wqe->send.sendop_pkd = cpu_to_be32(
 406                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
 407                 wqe->send.stag_inv = 0;
 408                 break;
 409         case IB_WR_SEND_WITH_INV:
 410                 if (wr->send_flags & IB_SEND_SOLICITED)
 411                         wqe->send.sendop_pkd = cpu_to_be32(
 412                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
 413                 else
 414                         wqe->send.sendop_pkd = cpu_to_be32(
 415                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
 416                 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 417                 break;
 418
 419         default:
 420                 return -EINVAL;
 421         }
 422
 423         plen = 0;
 424         if (wr->num_sge) {
 425                 if (wr->send_flags & IB_SEND_INLINE) {
 426                         ret = build_immd(sq, wqe->send.u.immd_src, wr,
 427                                          T4_MAX_SEND_INLINE, &plen);
 428                         if (ret)
 429                                 return ret;
 430                         size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
 431                                plen;
 432                 } else {
 433                         ret = build_isgl((__be64 *)sq->queue,
 434                                          (__be64 *)&sq->queue[sq->size],
 435                                          wqe->send.u.isgl_src,
 436                                          wr->sg_list, wr->num_sge, &plen);
 437                         if (ret)
 438                                 return ret;
 439                         size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
 440                                wr->num_sge * sizeof(struct fw_ri_sge);
 441                 }
 442         } else {
 443                 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
 444                 wqe->send.u.immd_src[0].r1 = 0;
 445                 wqe->send.u.immd_src[0].r2 = 0;
 446                 wqe->send.u.immd_src[0].immdlen = 0;
 447                 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
 448                 plen = 0;
 449         }
 450         *len16 = DIV_ROUND_UP(size, 16);
 451         wqe->send.plen = cpu_to_be32(plen);
 452         return 0;
 453 }
 454
 455 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
 456                             struct ib_send_wr *wr, u8 *len16)
 457 {
 458         u32 plen;
 459         int size;
 460         int ret;
 461
 462         if (wr->num_sge > T4_MAX_SEND_SGE)
 463                 return -EINVAL;
 464         wqe->write.r2 = 0;
 465         wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
 466         wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
 467         if (wr->num_sge) {
 468                 if (wr->send_flags & IB_SEND_INLINE) {
 469                         ret = build_immd(sq, wqe->write.u.immd_src, wr,
 470                                          T4_MAX_WRITE_INLINE, &plen);
 471                         if (ret)
 472                                 return ret;
 473                         size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
 474                                plen;
 475                 } else {
 476                         ret = build_isgl((__be64 *)sq->queue,
 477                                          (__be64 *)&sq->queue[sq->size],
 478                                          wqe->write.u.isgl_src,
 479                                          wr->sg_list, wr->num_sge, &plen);
 480                         if (ret)
 481                                 return ret;
 482                         size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
 483                                wr->num_sge * sizeof(struct fw_ri_sge);
 484                 }
 485         } else {
 486                 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
 487                 wqe->write.u.immd_src[0].r1 = 0;
 488                 wqe->write.u.immd_src[0].r2 = 0;
 489                 wqe->write.u.immd_src[0].immdlen = 0;
 490                 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
 491                 plen = 0;
 492         }
 493         *len16 = DIV_ROUND_UP(size, 16);
 494         wqe->write.plen = cpu_to_be32(plen);
 495         return 0;
 496 }
 497
 498 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
 499 {
 500         if (wr->num_sge > 1)
 501                 return -EINVAL;
 502         if (wr->num_sge) {
 503                 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
 504                 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
 505                                                         >> 32));
 506                 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
 507                 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
 508                 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
 509                 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
 510                                                          >> 32));
 511                 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
 512         } else {
 513                 wqe->read.stag_src = cpu_to_be32(2);
 514                 wqe->read.to_src_hi = 0;
 515                 wqe->read.to_src_lo = 0;
 516                 wqe->read.stag_sink = cpu_to_be32(2);
 517                 wqe->read.plen = 0;
 518                 wqe->read.to_sink_hi = 0;
 519                 wqe->read.to_sink_lo = 0;
 520         }
 521         wqe->read.r2 = 0;
 522         wqe->read.r5 = 0;
 523         *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
 524         return 0;
 525 }
 526
 527 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
 528                            struct ib_recv_wr *wr, u8 *len16)
 529 {
 530         int ret;
 531
 532         ret = build_isgl((__be64 *)qhp->wq.rq.queue,
 533                          (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
 534                          &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
 535         if (ret)
 536                 return ret;
 537         *len16 = DIV_ROUND_UP(sizeof wqe->recv +
 538                               wr->num_sge * sizeof(struct fw_ri_sge), 16);
 539         return 0;
 540 }
 541
 542 static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
 543                          struct ib_send_wr *wr, u8 *len16, u8 t5dev)
 544 {
 545
 546         struct fw_ri_immd *imdp;
 547         __be64 *p;
 548         int i;
 549         int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
 550         int rem;
 551
 552         if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
 553                 return -EINVAL;
 554
 555         wqe->fr.qpbinde_to_dcacpu = 0;
 556         wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
 557         wqe->fr.addr_type = FW_RI_VA_BASED_TO;
 558         wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
 559         wqe->fr.len_hi = 0;
 560         wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
 561         wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
 562         wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
 563         wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
 564                                         0xffffffff);
 565
 566         if (t5dev && use_dsgl && (pbllen > max_fr_immd)) {
 567                 struct c4iw_fr_page_list *c4pl =
 568                         to_c4iw_fr_page_list(wr->wr.fast_reg.page_list);
 569                 struct fw_ri_dsgl *sglp;
 570
 571                 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
 572                         wr->wr.fast_reg.page_list->page_list[i] = (__force u64)
 573                                 cpu_to_be64((u64)
 574                                 wr->wr.fast_reg.page_list->page_list[i]);
 575                 }
 576
 577                 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
 578                 sglp->op = FW_RI_DATA_DSGL;
 579                 sglp->r1 = 0;
 580                 sglp->nsge = cpu_to_be16(1);
 581                 sglp->addr0 = cpu_to_be64(c4pl->dma_addr);
 582                 sglp->len0 = cpu_to_be32(pbllen);
 583
 584                 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
 585         } else {
 586                 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
 587                 imdp->op = FW_RI_DATA_IMMD;
 588                 imdp->r1 = 0;
 589                 imdp->r2 = 0;
 590                 imdp->immdlen = cpu_to_be32(pbllen);
 591                 p = (__be64 *)(imdp + 1);
 592                 rem = pbllen;
 593                 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
 594                         *p = cpu_to_be64(
 595                                 (u64)wr->wr.fast_reg.page_list->page_list[i]);
 596                         rem -= sizeof(*p);
 597                         if (++p == (__be64 *)&sq->queue[sq->size])
 598                                 p = (__be64 *)sq->queue;
 599                 }
 600                 BUG_ON(rem < 0);
 601                 while (rem) {
 602                         *p = 0;
 603                         rem -= sizeof(*p);
 604                         if (++p == (__be64 *)&sq->queue[sq->size])
 605                                 p = (__be64 *)sq->queue;
 606                 }
 607                 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
 608                                       + pbllen, 16);
 609         }
 610         return 0;
 611 }
 612
 613 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
 614                           u8 *len16)
 615 {
 616         wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 617         wqe->inv.r2 = 0;
 618         *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
 619         return 0;
 620 }
 621
 622 void c4iw_qp_add_ref(struct ib_qp *qp)
 623 {
 624         PDBG("%s ib_qp %p\n", __func__, qp);
 625         atomic_inc(&(to_c4iw_qp(qp)->refcnt));
 626 }
 627
 628 void c4iw_qp_rem_ref(struct ib_qp *qp)
 629 {
 630         PDBG("%s ib_qp %p\n", __func__, qp);
 631         if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
 632                 wake_up(&(to_c4iw_qp(qp)->wait));
 633 }
 634
 635 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 636                    struct ib_send_wr **bad_wr)
 637 {
 638         int err = 0;
 639         u8 len16 = 0;
 640         enum fw_wr_opcodes fw_opcode = 0;
 641         enum fw_ri_wr_flags fw_flags;
 642         struct c4iw_qp *qhp;
 643         union t4_wr *wqe;
 644         u32 num_wrs;
 645         struct t4_swsqe *swsqe;
 646         unsigned long flag;
 647         u16 idx = 0;
 648
 649         qhp = to_c4iw_qp(ibqp);
 650         spin_lock_irqsave(&qhp->lock, flag);
 651         if (t4_wq_in_error(&qhp->wq)) {
 652                 spin_unlock_irqrestore(&qhp->lock, flag);
 653                 return -EINVAL;
 654         }
 655         num_wrs = t4_sq_avail(&qhp->wq);
 656         if (num_wrs == 0) {
 657                 spin_unlock_irqrestore(&qhp->lock, flag);
 658                 return -ENOMEM;
 659         }
 660         while (wr) {
 661                 if (num_wrs == 0) {
 662                         err = -ENOMEM;
 663                         *bad_wr = wr;
 664                         break;
 665                 }
 666                 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
 667                       qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
 668
 669                 fw_flags = 0;
 670                 if (wr->send_flags & IB_SEND_SOLICITED)
 671                         fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
 672                 if (wr->send_flags & IB_SEND_SIGNALED)
 673                         fw_flags |= FW_RI_COMPLETION_FLAG;
 674                 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
 675                 switch (wr->opcode) {
 676                 case IB_WR_SEND_WITH_INV:
 677                 case IB_WR_SEND:
 678                         if (wr->send_flags & IB_SEND_FENCE)
 679                                 fw_flags |= FW_RI_READ_FENCE_FLAG;
 680                         fw_opcode = FW_RI_SEND_WR;
 681                         if (wr->opcode == IB_WR_SEND)
 682                                 swsqe->opcode = FW_RI_SEND;
 683                         else
 684                                 swsqe->opcode = FW_RI_SEND_WITH_INV;
 685                         err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
 686                         break;
 687                 case IB_WR_RDMA_WRITE:
 688                         fw_opcode = FW_RI_RDMA_WRITE_WR;
 689                         swsqe->opcode = FW_RI_RDMA_WRITE;
 690                         err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
 691                         break;
 692                 case IB_WR_RDMA_READ:
 693                 case IB_WR_RDMA_READ_WITH_INV:
 694                         fw_opcode = FW_RI_RDMA_READ_WR;
 695                         swsqe->opcode = FW_RI_READ_REQ;
 696                         if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
 697                                 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
 698                         else
 699                                 fw_flags = 0;
 700                         err = build_rdma_read(wqe, wr, &len16);
 701                         if (err)
 702                                 break;
 703                         swsqe->read_len = wr->sg_list[0].length;
 704                         if (!qhp->wq.sq.oldest_read)
 705                                 qhp->wq.sq.oldest_read = swsqe;
 706                         break;
 707                 case IB_WR_FAST_REG_MR:
 708                         fw_opcode = FW_RI_FR_NSMR_WR;
 709                         swsqe->opcode = FW_RI_FAST_REGISTER;
 710                         err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16,
 711                                             is_t5(
 712                                             qhp->rhp->rdev.lldi.adapter_type) ?
 713                                             1 : 0);
 714                         break;
 715                 case IB_WR_LOCAL_INV:
 716                         if (wr->send_flags & IB_SEND_FENCE)
 717                                 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
 718                         fw_opcode = FW_RI_INV_LSTAG_WR;
 719                         swsqe->opcode = FW_RI_LOCAL_INV;
 720                         err = build_inv_stag(wqe, wr, &len16);
 721                         break;
 722                 default:
 723                         PDBG("%s post of type=%d TBD!\n", __func__,
 724                              wr->opcode);
 725                         err = -EINVAL;
 726                 }
 727                 if (err) {
 728                         *bad_wr = wr;
 729                         break;
 730                 }
 731                 swsqe->idx = qhp->wq.sq.pidx;
 732                 swsqe->complete = 0;
 733                 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED);
 734                 swsqe->wr_id = wr->wr_id;
 735
 736                 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
 737
 738                 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
 739                      __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
 740                      swsqe->opcode, swsqe->read_len);
 741                 wr = wr->next;
 742                 num_wrs--;
 743                 t4_sq_produce(&qhp->wq, len16);
 744                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
 745         }
 746         if (t4_wq_db_enabled(&qhp->wq))
 747                 t4_ring_sq_db(&qhp->wq, idx);
 748         spin_unlock_irqrestore(&qhp->lock, flag);
 749         return err;
 750 }
 751
 752 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 753                       struct ib_recv_wr **bad_wr)
 754 {
 755         int err = 0;
 756         struct c4iw_qp *qhp;
 757         union t4_recv_wr *wqe;
 758         u32 num_wrs;
 759         u8 len16 = 0;
 760         unsigned long flag;
 761         u16 idx = 0;
 762
 763         qhp = to_c4iw_qp(ibqp);
 764         spin_lock_irqsave(&qhp->lock, flag);
 765         if (t4_wq_in_error(&qhp->wq)) {
 766                 spin_unlock_irqrestore(&qhp->lock, flag);
 767                 return -EINVAL;
 768         }
 769         num_wrs = t4_rq_avail(&qhp->wq);
 770         if (num_wrs == 0) {
 771                 spin_unlock_irqrestore(&qhp->lock, flag);
 772                 return -ENOMEM;
 773         }
 774         while (wr) {
 775                 if (wr->num_sge > T4_MAX_RECV_SGE) {
 776                         err = -EINVAL;
 777                         *bad_wr = wr;
 778                         break;
 779                 }
 780                 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
 781                                            qhp->wq.rq.wq_pidx *
 782                                            T4_EQ_ENTRY_SIZE);
 783                 if (num_wrs)
 784                         err = build_rdma_recv(qhp, wqe, wr, &len16);
 785                 else
 786                         err = -ENOMEM;
 787                 if (err) {
 788                         *bad_wr = wr;
 789                         break;
 790                 }
 791
 792                 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
 793
 794                 wqe->recv.opcode = FW_RI_RECV_WR;
 795                 wqe->recv.r1 = 0;
 796                 wqe->recv.wrid = qhp->wq.rq.pidx;
 797                 wqe->recv.r2[0] = 0;
 798                 wqe->recv.r2[1] = 0;
 799                 wqe->recv.r2[2] = 0;
 800                 wqe->recv.len16 = len16;
 801                 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
 802                      (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
 803                 t4_rq_produce(&qhp->wq, len16);
 804                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
 805                 wr = wr->next;
 806                 num_wrs--;
 807         }
 808         if (t4_wq_db_enabled(&qhp->wq))
 809                 t4_ring_rq_db(&qhp->wq, idx);
 810         spin_unlock_irqrestore(&qhp->lock, flag);
 811         return err;
 812 }
 813
 814 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
 815 {
 816         return -ENOSYS;
 817 }
 818
 819 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
 820                                     u8 *ecode)
 821 {
 822         int status;
 823         int tagged;
 824         int opcode;
 825         int rqtype;
 826         int send_inv;
 827
 828         if (!err_cqe) {
 829                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
 830                 *ecode = 0;
 831                 return;
 832         }
 833
 834         status = CQE_STATUS(err_cqe);
 835         opcode = CQE_OPCODE(err_cqe);
 836         rqtype = RQ_TYPE(err_cqe);
 837         send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
 838                    (opcode == FW_RI_SEND_WITH_SE_INV);
 839         tagged = (opcode == FW_RI_RDMA_WRITE) ||
 840                  (rqtype && (opcode == FW_RI_READ_RESP));
 841
 842         switch (status) {
 843         case T4_ERR_STAG:
 844                 if (send_inv) {
 845                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 846                         *ecode = RDMAP_CANT_INV_STAG;
 847                 } else {
 848                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 849                         *ecode = RDMAP_INV_STAG;
 850                 }
 851                 break;
 852         case T4_ERR_PDID:
 853                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 854                 if ((opcode == FW_RI_SEND_WITH_INV) ||
 855                     (opcode == FW_RI_SEND_WITH_SE_INV))
 856                         *ecode = RDMAP_CANT_INV_STAG;
 857                 else
 858                         *ecode = RDMAP_STAG_NOT_ASSOC;
 859                 break;
 860         case T4_ERR_QPID:
 861                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 862                 *ecode = RDMAP_STAG_NOT_ASSOC;
 863                 break;
 864         case T4_ERR_ACCESS:
 865                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 866                 *ecode = RDMAP_ACC_VIOL;
 867                 break;
 868         case T4_ERR_WRAP:
 869                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 870                 *ecode = RDMAP_TO_WRAP;
 871                 break;
 872         case T4_ERR_BOUND:
 873                 if (tagged) {
 874                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 875                         *ecode = DDPT_BASE_BOUNDS;
 876                 } else {
 877                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 878                         *ecode = RDMAP_BASE_BOUNDS;
 879                 }
 880                 break;
 881         case T4_ERR_INVALIDATE_SHARED_MR:
 882         case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
 883                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 884                 *ecode = RDMAP_CANT_INV_STAG;
 885                 break;
 886         case T4_ERR_ECC:
 887         case T4_ERR_ECC_PSTAG:
 888         case T4_ERR_INTERNAL_ERR:
 889                 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
 890                 *ecode = 0;
 891                 break;
 892         case T4_ERR_OUT_OF_RQE:
 893                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 894                 *ecode = DDPU_INV_MSN_NOBUF;
 895                 break;
 896         case T4_ERR_PBL_ADDR_BOUND:
 897                 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 898                 *ecode = DDPT_BASE_BOUNDS;
 899                 break;
 900         case T4_ERR_CRC:
 901                 *layer_type = LAYER_MPA|DDP_LLP;
 902                 *ecode = MPA_CRC_ERR;
 903                 break;
 904         case T4_ERR_MARKER:
 905                 *layer_type = LAYER_MPA|DDP_LLP;
 906                 *ecode = MPA_MARKER_ERR;
 907                 break;
 908         case T4_ERR_PDU_LEN_ERR:
 909                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 910                 *ecode = DDPU_MSG_TOOBIG;
 911                 break;
 912         case T4_ERR_DDP_VERSION:
 913                 if (tagged) {
 914                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 915                         *ecode = DDPT_INV_VERS;
 916                 } else {
 917                         *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 918                         *ecode = DDPU_INV_VERS;
 919                 }
 920                 break;
 921         case T4_ERR_RDMA_VERSION:
 922                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 923                 *ecode = RDMAP_INV_VERS;
 924                 break;
 925         case T4_ERR_OPCODE:
 926                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 927                 *ecode = RDMAP_INV_OPCODE;
 928                 break;
 929         case T4_ERR_DDP_QUEUE_NUM:
 930                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 931                 *ecode = DDPU_INV_QN;
 932                 break;
 933         case T4_ERR_MSN:
 934         case T4_ERR_MSN_GAP:
 935         case T4_ERR_MSN_RANGE:
 936         case T4_ERR_IRD_OVERFLOW:
 937                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 938                 *ecode = DDPU_INV_MSN_RANGE;
 939                 break;
 940         case T4_ERR_TBIT:
 941                 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
 942                 *ecode = 0;
 943                 break;
 944         case T4_ERR_MO:
 945                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 946                 *ecode = DDPU_INV_MO;
 947                 break;
 948         default:
 949                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
 950                 *ecode = 0;
 951                 break;
 952         }
 953 }
 954
 955 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
 956                            gfp_t gfp)
 957 {
 958         struct fw_ri_wr *wqe;
 959         struct sk_buff *skb;
 960         struct terminate_message *term;
 961
 962         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
 963              qhp->ep->hwtid);
 964
 965         skb = alloc_skb(sizeof *wqe, gfp);
 966         if (!skb)
 967                 return;
 968         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
 969
 970         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
 971         memset(wqe, 0, sizeof *wqe);
 972         wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
 973         wqe->flowid_len16 = cpu_to_be32(
 974                 FW_WR_FLOWID(qhp->ep->hwtid) |
 975                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
 976
 977         wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
 978         wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
 979         term = (struct terminate_message *)wqe->u.terminate.termmsg;
 980         if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
 981                 term->layer_etype = qhp->attr.layer_etype;
 982                 term->ecode = qhp->attr.ecode;
 983         } else
 984                 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
 985         c4iw_ofld_send(&qhp->rhp->rdev, skb);
 986 }
 987
 988 /*
 989  * Assumes qhp lock is held.
 990  */
 991 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
 992                        struct c4iw_cq *schp)
 993 {
 994         int count;
 995         int flushed;
 996         unsigned long flag;
 997
 998         PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
 999
1000         /* locking hierarchy: cq lock first, then qp lock. */
1001         spin_lock_irqsave(&rchp->lock, flag);
1002         spin_lock(&qhp->lock);
1003         c4iw_flush_hw_cq(&rchp->cq);
1004         c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1005         flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1006         spin_unlock(&qhp->lock);
1007         spin_unlock_irqrestore(&rchp->lock, flag);
1008         if (flushed) {
1009                 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1010                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1011                 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1012         }
1013
1014         /* locking hierarchy: cq lock first, then qp lock. */
1015         spin_lock_irqsave(&schp->lock, flag);
1016         spin_lock(&qhp->lock);
1017         c4iw_flush_hw_cq(&schp->cq);
1018         c4iw_count_scqes(&schp->cq, &qhp->wq, &count);
1019         flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count);
1020         spin_unlock(&qhp->lock);
1021         spin_unlock_irqrestore(&schp->lock, flag);
1022         if (flushed) {
1023                 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1024                 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
1025                 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1026         }
1027 }
1028
1029 static void flush_qp(struct c4iw_qp *qhp)
1030 {
1031         struct c4iw_cq *rchp, *schp;
1032         unsigned long flag;
1033
1034         rchp = get_chp(qhp->rhp, qhp->attr.rcq);
1035         schp = get_chp(qhp->rhp, qhp->attr.scq);
1036
1037         if (qhp->ibqp.uobject) {
1038                 t4_set_wq_in_error(&qhp->wq);
1039                 t4_set_cq_in_error(&rchp->cq);
1040                 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1041                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1042                 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1043                 if (schp != rchp) {
1044                         t4_set_cq_in_error(&schp->cq);
1045                         spin_lock_irqsave(&schp->comp_handler_lock, flag);
1046                         (*schp->ibcq.comp_handler)(&schp->ibcq,
1047                                         schp->ibcq.cq_context);
1048                         spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1049                 }
1050                 return;
1051         }
1052         __flush_qp(qhp, rchp, schp);
1053 }
1054
1055 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1056                      struct c4iw_ep *ep)
1057 {
1058         struct fw_ri_wr *wqe;
1059         int ret;
1060         struct sk_buff *skb;
1061
1062         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1063              ep->hwtid);
1064
1065         skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1066         if (!skb)
1067                 return -ENOMEM;
1068         set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1069
1070         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1071         memset(wqe, 0, sizeof *wqe);
1072         wqe->op_compl = cpu_to_be32(
1073                 FW_WR_OP(FW_RI_INIT_WR) |
1074                 FW_WR_COMPL(1));
1075         wqe->flowid_len16 = cpu_to_be32(
1076                 FW_WR_FLOWID(ep->hwtid) |
1077                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1078         wqe->cookie = (unsigned long) &ep->com.wr_wait;
1079
1080         wqe->u.fini.type = FW_RI_TYPE_FINI;
1081         ret = c4iw_ofld_send(&rhp->rdev, skb);
1082         if (ret)
1083                 goto out;
1084
1085         ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
1086                              qhp->wq.sq.qid, __func__);
1087 out:
1088         PDBG("%s ret %d\n", __func__, ret);
1089         return ret;
1090 }
1091
1092 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1093 {
1094         PDBG("%s p2p_type = %d\n", __func__, p2p_type);
1095         memset(&init->u, 0, sizeof init->u);
1096         switch (p2p_type) {
1097         case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1098                 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1099                 init->u.write.stag_sink = cpu_to_be32(1);
1100                 init->u.write.to_sink = cpu_to_be64(1);
1101                 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1102                 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1103                                                    sizeof(struct fw_ri_immd),
1104                                                    16);
1105                 break;
1106         case FW_RI_INIT_P2PTYPE_READ_REQ:
1107                 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1108                 init->u.read.stag_src = cpu_to_be32(1);
1109                 init->u.read.to_src_lo = cpu_to_be32(1);
1110                 init->u.read.stag_sink = cpu_to_be32(1);
1111                 init->u.read.to_sink_lo = cpu_to_be32(1);
1112                 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1113                 break;
1114         }
1115 }
1116
1117 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1118 {
1119         struct fw_ri_wr *wqe;
1120         int ret;
1121         struct sk_buff *skb;
1122
1123         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1124              qhp->ep->hwtid);
1125
1126         skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1127         if (!skb)
1128                 return -ENOMEM;
1129         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1130
1131         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1132         memset(wqe, 0, sizeof *wqe);
1133         wqe->op_compl = cpu_to_be32(
1134                 FW_WR_OP(FW_RI_INIT_WR) |
1135                 FW_WR_COMPL(1));
1136         wqe->flowid_len16 = cpu_to_be32(
1137                 FW_WR_FLOWID(qhp->ep->hwtid) |
1138                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1139
1140         wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
1141
1142         wqe->u.init.type = FW_RI_TYPE_INIT;
1143         wqe->u.init.mpareqbit_p2ptype =
1144                 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1145                 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1146         wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1147         if (qhp->attr.mpa_attr.recv_marker_enabled)
1148                 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1149         if (qhp->attr.mpa_attr.xmit_marker_enabled)
1150                 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1151         if (qhp->attr.mpa_attr.crc_enabled)
1152                 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1153
1154         wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1155                             FW_RI_QP_RDMA_WRITE_ENABLE |
1156                             FW_RI_QP_BIND_ENABLE;
1157         if (!qhp->ibqp.uobject)
1158                 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1159                                      FW_RI_QP_STAG0_ENABLE;
1160         wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1161         wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1162         wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1163         wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1164         wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1165         wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1166         wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1167         wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1168         wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1169         wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1170         wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1171         wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1172         wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1173                                          rhp->rdev.lldi.vr->rq.start);
1174         if (qhp->attr.mpa_attr.initiator)
1175                 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1176
1177         ret = c4iw_ofld_send(&rhp->rdev, skb);
1178         if (ret)
1179                 goto out;
1180
1181         ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1182                                   qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1183 out:
1184         PDBG("%s ret %d\n", __func__, ret);
1185         return ret;
1186 }
1187
1188 /*
1189  * Called by the library when the qp has user dbs disabled due to
1190  * a DB_FULL condition.  This function will single-thread all user
1191  * DB rings to avoid overflowing the hw db-fifo.
1192  */
1193 static int ring_kernel_db(struct c4iw_qp *qhp, u32 qid, u16 inc)
1194 {
1195         int delay = db_delay_usecs;
1196
1197         mutex_lock(&qhp->rhp->db_mutex);
1198         do {
1199
1200                 /*
1201                  * The interrupt threshold is dbfifo_int_thresh << 6. So
1202                  * make sure we don't cross that and generate an interrupt.
1203                  */
1204                 if (cxgb4_dbfifo_count(qhp->rhp->rdev.lldi.ports[0], 1) <
1205                     (qhp->rhp->rdev.lldi.dbfifo_int_thresh << 5)) {
1206                         writel(QID(qid) | PIDX(inc), qhp->wq.db);
1207                         break;
1208                 }
1209                 set_current_state(TASK_UNINTERRUPTIBLE);
1210                 schedule_timeout(usecs_to_jiffies(delay));
1211                 delay = min(delay << 1, 2000);
1212         } while (1);
1213         mutex_unlock(&qhp->rhp->db_mutex);
1214         return 0;
1215 }
1216
1217 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1218                    enum c4iw_qp_attr_mask mask,
1219                    struct c4iw_qp_attributes *attrs,
1220                    int internal)
1221 {
1222         int ret = 0;
1223         struct c4iw_qp_attributes newattr = qhp->attr;
1224         int disconnect = 0;
1225         int terminate = 0;
1226         int abort = 0;
1227         int free = 0;
1228         struct c4iw_ep *ep = NULL;
1229
1230         PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1231              qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1232              (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1233
1234         mutex_lock(&qhp->mutex);
1235
1236         /* Process attr changes if in IDLE */
1237         if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1238                 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1239                         ret = -EIO;
1240                         goto out;
1241                 }
1242                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1243                         newattr.enable_rdma_read = attrs->enable_rdma_read;
1244                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1245                         newattr.enable_rdma_write = attrs->enable_rdma_write;
1246                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1247                         newattr.enable_bind = attrs->enable_bind;
1248                 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1249                         if (attrs->max_ord > c4iw_max_read_depth) {
1250                                 ret = -EINVAL;
1251                                 goto out;
1252                         }
1253                         newattr.max_ord = attrs->max_ord;
1254                 }
1255                 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1256                         if (attrs->max_ird > c4iw_max_read_depth) {
1257                                 ret = -EINVAL;
1258                                 goto out;
1259                         }
1260                         newattr.max_ird = attrs->max_ird;
1261                 }
1262                 qhp->attr = newattr;
1263         }
1264
1265         if (mask & C4IW_QP_ATTR_SQ_DB) {
1266                 ret = ring_kernel_db(qhp, qhp->wq.sq.qid, attrs->sq_db_inc);
1267                 goto out;
1268         }
1269         if (mask & C4IW_QP_ATTR_RQ_DB) {
1270                 ret = ring_kernel_db(qhp, qhp->wq.rq.qid, attrs->rq_db_inc);
1271                 goto out;
1272         }
1273
1274         if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1275                 goto out;
1276         if (qhp->attr.state == attrs->next_state)
1277                 goto out;
1278
1279         switch (qhp->attr.state) {
1280         case C4IW_QP_STATE_IDLE:
1281                 switch (attrs->next_state) {
1282                 case C4IW_QP_STATE_RTS:
1283                         if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1284                                 ret = -EINVAL;
1285                                 goto out;
1286                         }
1287                         if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1288                                 ret = -EINVAL;
1289                                 goto out;
1290                         }
1291                         qhp->attr.mpa_attr = attrs->mpa_attr;
1292                         qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1293                         qhp->ep = qhp->attr.llp_stream_handle;
1294                         set_state(qhp, C4IW_QP_STATE_RTS);
1295
1296                         /*
1297                          * Ref the endpoint here and deref when we
1298                          * disassociate the endpoint from the QP.  This
1299                          * happens in CLOSING->IDLE transition or *->ERROR
1300                          * transition.
1301                          */
1302                         c4iw_get_ep(&qhp->ep->com);
1303                         ret = rdma_init(rhp, qhp);
1304                         if (ret)
1305                                 goto err;
1306                         break;
1307                 case C4IW_QP_STATE_ERROR:
1308                         set_state(qhp, C4IW_QP_STATE_ERROR);
1309                         flush_qp(qhp);
1310                         break;
1311                 default:
1312                         ret = -EINVAL;
1313                         goto out;
1314                 }
1315                 break;
1316         case C4IW_QP_STATE_RTS:
1317                 switch (attrs->next_state) {
1318                 case C4IW_QP_STATE_CLOSING:
1319                         BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1320                         set_state(qhp, C4IW_QP_STATE_CLOSING);
1321                         ep = qhp->ep;
1322                         if (!internal) {
1323                                 abort = 0;
1324                                 disconnect = 1;
1325                                 c4iw_get_ep(&qhp->ep->com);
1326                         }
1327                         if (qhp->ibqp.uobject)
1328                                 t4_set_wq_in_error(&qhp->wq);
1329                         ret = rdma_fini(rhp, qhp, ep);
1330                         if (ret)
1331                                 goto err;
1332                         break;
1333                 case C4IW_QP_STATE_TERMINATE:
1334                         set_state(qhp, C4IW_QP_STATE_TERMINATE);
1335                         qhp->attr.layer_etype = attrs->layer_etype;
1336                         qhp->attr.ecode = attrs->ecode;
1337                         if (qhp->ibqp.uobject)
1338                                 t4_set_wq_in_error(&qhp->wq);
1339                         ep = qhp->ep;
1340                         if (!internal)
1341                                 terminate = 1;
1342                         disconnect = 1;
1343                         c4iw_get_ep(&qhp->ep->com);
1344                         break;
1345                 case C4IW_QP_STATE_ERROR:
1346                         set_state(qhp, C4IW_QP_STATE_ERROR);
1347                         if (qhp->ibqp.uobject)
1348                                 t4_set_wq_in_error(&qhp->wq);
1349                         if (!internal) {
1350                                 abort = 1;
1351                                 disconnect = 1;
1352                                 ep = qhp->ep;
1353                                 c4iw_get_ep(&qhp->ep->com);
1354                         }
1355                         goto err;
1356                         break;
1357                 default:
1358                         ret = -EINVAL;
1359                         goto out;
1360                 }
1361                 break;
1362         case C4IW_QP_STATE_CLOSING:
1363                 if (!internal) {
1364                         ret = -EINVAL;
1365                         goto out;
1366                 }
1367                 switch (attrs->next_state) {
1368                 case C4IW_QP_STATE_IDLE:
1369                         flush_qp(qhp);
1370                         set_state(qhp, C4IW_QP_STATE_IDLE);
1371                         qhp->attr.llp_stream_handle = NULL;
1372                         c4iw_put_ep(&qhp->ep->com);
1373                         qhp->ep = NULL;
1374                         wake_up(&qhp->wait);
1375                         break;
1376                 case C4IW_QP_STATE_ERROR:
1377                         goto err;
1378                 default:
1379                         ret = -EINVAL;
1380                         goto err;
1381                 }
1382                 break;
1383         case C4IW_QP_STATE_ERROR:
1384                 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1385                         ret = -EINVAL;
1386                         goto out;
1387                 }
1388                 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1389                         ret = -EINVAL;
1390                         goto out;
1391                 }
1392                 set_state(qhp, C4IW_QP_STATE_IDLE);
1393                 break;
1394         case C4IW_QP_STATE_TERMINATE:
1395                 if (!internal) {
1396                         ret = -EINVAL;
1397                         goto out;
1398                 }
1399                 goto err;
1400                 break;
1401         default:
1402                 printk(KERN_ERR "%s in a bad state %d\n",
1403                        __func__, qhp->attr.state);
1404                 ret = -EINVAL;
1405                 goto err;
1406                 break;
1407         }
1408         goto out;
1409 err:
1410         PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1411              qhp->wq.sq.qid);
1412
1413         /* disassociate the LLP connection */
1414         qhp->attr.llp_stream_handle = NULL;
1415         if (!ep)
1416                 ep = qhp->ep;
1417         qhp->ep = NULL;
1418         set_state(qhp, C4IW_QP_STATE_ERROR);
1419         free = 1;
1420         abort = 1;
1421         wake_up(&qhp->wait);
1422         BUG_ON(!ep);
1423         flush_qp(qhp);
1424 out:
1425         mutex_unlock(&qhp->mutex);
1426
1427         if (terminate)
1428                 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1429
1430         /*
1431          * If disconnect is 1, then we need to initiate a disconnect
1432          * on the EP.  This can be a normal close (RTS->CLOSING) or
1433          * an abnormal close (RTS/CLOSING->ERROR).
1434          */
1435         if (disconnect) {
1436                 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1437                                                          GFP_KERNEL);
1438                 c4iw_put_ep(&ep->com);
1439         }
1440
1441         /*
1442          * If free is 1, then we've disassociated the EP from the QP
1443          * and we need to dereference the EP.
1444          */
1445         if (free)
1446                 c4iw_put_ep(&ep->com);
1447         PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1448         return ret;
1449 }
1450
1451 static int enable_qp_db(int id, void *p, void *data)
1452 {
1453         struct c4iw_qp *qp = p;
1454
1455         t4_enable_wq_db(&qp->wq);
1456         return 0;
1457 }
1458
1459 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1460 {
1461         struct c4iw_dev *rhp;
1462         struct c4iw_qp *qhp;
1463         struct c4iw_qp_attributes attrs;
1464         struct c4iw_ucontext *ucontext;
1465
1466         qhp = to_c4iw_qp(ib_qp);
1467         rhp = qhp->rhp;
1468
1469         attrs.next_state = C4IW_QP_STATE_ERROR;
1470         if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1471                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1472         else
1473                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1474         wait_event(qhp->wait, !qhp->ep);
1475
1476         spin_lock_irq(&rhp->lock);
1477         remove_handle_nolock(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1478         rhp->qpcnt--;
1479         BUG_ON(rhp->qpcnt < 0);
1480         if (rhp->qpcnt <= db_fc_threshold && rhp->db_state == FLOW_CONTROL) {
1481                 rhp->rdev.stats.db_state_transitions++;
1482                 rhp->db_state = NORMAL;
1483                 idr_for_each(&rhp->qpidr, enable_qp_db, NULL);
1484         }
1485         if (db_coalescing_threshold >= 0)
1486                 if (rhp->qpcnt <= db_coalescing_threshold)
1487                         cxgb4_enable_db_coalescing(rhp->rdev.lldi.ports[0]);
1488         spin_unlock_irq(&rhp->lock);
1489         atomic_dec(&qhp->refcnt);
1490         wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1491
1492         ucontext = ib_qp->uobject ?
1493                    to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1494         destroy_qp(&rhp->rdev, &qhp->wq,
1495                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1496
1497         PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1498         kfree(qhp);
1499         return 0;
1500 }
1501
1502 static int disable_qp_db(int id, void *p, void *data)
1503 {
1504         struct c4iw_qp *qp = p;
1505
1506         t4_disable_wq_db(&qp->wq);
1507         return 0;
1508 }
1509
1510 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1511                              struct ib_udata *udata)
1512 {
1513         struct c4iw_dev *rhp;
1514         struct c4iw_qp *qhp;
1515         struct c4iw_pd *php;
1516         struct c4iw_cq *schp;
1517         struct c4iw_cq *rchp;
1518         struct c4iw_create_qp_resp uresp;
1519         int sqsize, rqsize;
1520         struct c4iw_ucontext *ucontext;
1521         int ret;
1522         struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
1523
1524         PDBG("%s ib_pd %p\n", __func__, pd);
1525
1526         if (attrs->qp_type != IB_QPT_RC)
1527                 return ERR_PTR(-EINVAL);
1528
1529         php = to_c4iw_pd(pd);
1530         rhp = php->rhp;
1531         schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1532         rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1533         if (!schp || !rchp)
1534                 return ERR_PTR(-EINVAL);
1535
1536         if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1537                 return ERR_PTR(-EINVAL);
1538
1539         rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1540         if (rqsize > T4_MAX_RQ_SIZE)
1541                 return ERR_PTR(-E2BIG);
1542
1543         sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1544         if (sqsize > T4_MAX_SQ_SIZE)
1545                 return ERR_PTR(-E2BIG);
1546
1547         ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1548
1549
1550         qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1551         if (!qhp)
1552                 return ERR_PTR(-ENOMEM);
1553         qhp->wq.sq.size = sqsize;
1554         qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1555         qhp->wq.rq.size = rqsize;
1556         qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1557
1558         if (ucontext) {
1559                 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1560                 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1561         }
1562
1563         PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1564              __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1565
1566         ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1567                         ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1568         if (ret)
1569                 goto err1;
1570
1571         attrs->cap.max_recv_wr = rqsize - 1;
1572         attrs->cap.max_send_wr = sqsize - 1;
1573         attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1574
1575         qhp->rhp = rhp;
1576         qhp->attr.pd = php->pdid;
1577         qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1578         qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1579         qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1580         qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1581         qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1582         qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1583         qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1584         qhp->attr.state = C4IW_QP_STATE_IDLE;
1585         qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1586         qhp->attr.enable_rdma_read = 1;
1587         qhp->attr.enable_rdma_write = 1;
1588         qhp->attr.enable_bind = 1;
1589         qhp->attr.max_ord = 1;
1590         qhp->attr.max_ird = 1;
1591         spin_lock_init(&qhp->lock);
1592         mutex_init(&qhp->mutex);
1593         init_waitqueue_head(&qhp->wait);
1594         atomic_set(&qhp->refcnt, 1);
1595
1596         spin_lock_irq(&rhp->lock);
1597         if (rhp->db_state != NORMAL)
1598                 t4_disable_wq_db(&qhp->wq);
1599         rhp->qpcnt++;
1600         if (rhp->qpcnt > db_fc_threshold && rhp->db_state == NORMAL) {
1601                 rhp->rdev.stats.db_state_transitions++;
1602                 rhp->db_state = FLOW_CONTROL;
1603                 idr_for_each(&rhp->qpidr, disable_qp_db, NULL);
1604         }
1605         if (db_coalescing_threshold >= 0)
1606                 if (rhp->qpcnt > db_coalescing_threshold)
1607                         cxgb4_disable_db_coalescing(rhp->rdev.lldi.ports[0]);
1608         ret = insert_handle_nolock(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1609         spin_unlock_irq(&rhp->lock);
1610         if (ret)
1611                 goto err2;
1612
1613         if (udata) {
1614                 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1615                 if (!mm1) {
1616                         ret = -ENOMEM;
1617                         goto err3;
1618                 }
1619                 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1620                 if (!mm2) {
1621                         ret = -ENOMEM;
1622                         goto err4;
1623                 }
1624                 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1625                 if (!mm3) {
1626                         ret = -ENOMEM;
1627                         goto err5;
1628                 }
1629                 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1630                 if (!mm4) {
1631                         ret = -ENOMEM;
1632                         goto err6;
1633                 }
1634                 if (t4_sq_onchip(&qhp->wq.sq)) {
1635                         mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1636                         if (!mm5) {
1637                                 ret = -ENOMEM;
1638                                 goto err7;
1639                         }
1640                         uresp.flags = C4IW_QPF_ONCHIP;
1641                 } else
1642                         uresp.flags = 0;
1643                 uresp.qid_mask = rhp->rdev.qpmask;
1644                 uresp.sqid = qhp->wq.sq.qid;
1645                 uresp.sq_size = qhp->wq.sq.size;
1646                 uresp.sq_memsize = qhp->wq.sq.memsize;
1647                 uresp.rqid = qhp->wq.rq.qid;
1648                 uresp.rq_size = qhp->wq.rq.size;
1649                 uresp.rq_memsize = qhp->wq.rq.memsize;
1650                 spin_lock(&ucontext->mmap_lock);
1651                 if (mm5) {
1652                         uresp.ma_sync_key = ucontext->key;
1653                         ucontext->key += PAGE_SIZE;
1654                 }
1655                 uresp.sq_key = ucontext->key;
1656                 ucontext->key += PAGE_SIZE;
1657                 uresp.rq_key = ucontext->key;
1658                 ucontext->key += PAGE_SIZE;
1659                 uresp.sq_db_gts_key = ucontext->key;
1660                 ucontext->key += PAGE_SIZE;
1661                 uresp.rq_db_gts_key = ucontext->key;
1662                 ucontext->key += PAGE_SIZE;
1663                 spin_unlock(&ucontext->mmap_lock);
1664                 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1665                 if (ret)
1666                         goto err8;
1667                 mm1->key = uresp.sq_key;
1668                 mm1->addr = qhp->wq.sq.phys_addr;
1669                 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1670                 insert_mmap(ucontext, mm1);
1671                 mm2->key = uresp.rq_key;
1672                 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1673                 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1674                 insert_mmap(ucontext, mm2);
1675                 mm3->key = uresp.sq_db_gts_key;
1676                 mm3->addr = qhp->wq.sq.udb;
1677                 mm3->len = PAGE_SIZE;
1678                 insert_mmap(ucontext, mm3);
1679                 mm4->key = uresp.rq_db_gts_key;
1680                 mm4->addr = qhp->wq.rq.udb;
1681                 mm4->len = PAGE_SIZE;
1682                 insert_mmap(ucontext, mm4);
1683                 if (mm5) {
1684                         mm5->key = uresp.ma_sync_key;
1685                         mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1686                                     + A_PCIE_MA_SYNC) & PAGE_MASK;
1687                         mm5->len = PAGE_SIZE;
1688                         insert_mmap(ucontext, mm5);
1689                 }
1690         }
1691         qhp->ibqp.qp_num = qhp->wq.sq.qid;
1692         init_timer(&(qhp->timer));
1693         PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1694              __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1695              qhp->wq.sq.qid);
1696         return &qhp->ibqp;
1697 err8:
1698         kfree(mm5);
1699 err7:
1700         kfree(mm4);
1701 err6:
1702         kfree(mm3);
1703 err5:
1704         kfree(mm2);
1705 err4:
1706         kfree(mm1);
1707 err3:
1708         remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1709 err2:
1710         destroy_qp(&rhp->rdev, &qhp->wq,
1711                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1712 err1:
1713         kfree(qhp);
1714         return ERR_PTR(ret);
1715 }
1716
1717 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1718                       int attr_mask, struct ib_udata *udata)
1719 {
1720         struct c4iw_dev *rhp;
1721         struct c4iw_qp *qhp;
1722         enum c4iw_qp_attr_mask mask = 0;
1723         struct c4iw_qp_attributes attrs;
1724
1725         PDBG("%s ib_qp %p\n", __func__, ibqp);
1726
1727         /* iwarp does not support the RTR state */
1728         if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1729                 attr_mask &= ~IB_QP_STATE;
1730
1731         /* Make sure we still have something left to do */
1732         if (!attr_mask)
1733                 return 0;
1734
1735         memset(&attrs, 0, sizeof attrs);
1736         qhp = to_c4iw_qp(ibqp);
1737         rhp = qhp->rhp;
1738
1739         attrs.next_state = c4iw_convert_state(attr->qp_state);
1740         attrs.enable_rdma_read = (attr->qp_access_flags &
1741                                IB_ACCESS_REMOTE_READ) ?  1 : 0;
1742         attrs.enable_rdma_write = (attr->qp_access_flags &
1743                                 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1744         attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1745
1746
1747         mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1748         mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1749                         (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1750                          C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1751                          C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1752
1753         /*
1754          * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1755          * ringing the queue db when we're in DB_FULL mode.
1756          */
1757         attrs.sq_db_inc = attr->sq_psn;
1758         attrs.rq_db_inc = attr->rq_psn;
1759         mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1760         mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1761
1762         return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1763 }
1764
1765 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1766 {
1767         PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1768         return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1769 }
1770
1771 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1772                      int attr_mask, struct ib_qp_init_attr *init_attr)
1773 {
1774         struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1775
1776         memset(attr, 0, sizeof *attr);
1777         memset(init_attr, 0, sizeof *init_attr);
1778         attr->qp_state = to_ib_qp_state(qhp->attr.state);
1779         return 0;
1780 }