4 * Copyright(c) 2015, 2016 Intel Corporation.
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
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23 * modification, are permitted provided that the following conditions
26 * - Redistributions of source code must retain the above copyright
27 * notice, this list of conditions and the following disclaimer.
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29 * notice, this list of conditions and the following disclaimer in
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36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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50 #include <linux/interrupt.h>
51 #include <linux/pci.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/mutex.h>
54 #include <linux/list.h>
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
59 #include <linux/completion.h>
60 #include <linux/kref.h>
61 #include <linux/sched.h>
62 #include <linux/cdev.h>
63 #include <linux/delay.h>
64 #include <linux/kthread.h>
65 #include <linux/i2c.h>
66 #include <linux/i2c-algo-bit.h>
67 #include <rdma/rdma_vt.h>
69 #include "chip_registers.h"
79 /* bumped 1 from s/w major version of TrueScale */
80 #define HFI1_CHIP_VERS_MAJ 3U
82 /* don't care about this except printing */
83 #define HFI1_CHIP_VERS_MIN 0U
85 /* The Organization Unique Identifier (Mfg code), and its position in GUID */
86 #define HFI1_OUI 0x001175
87 #define HFI1_OUI_LSB 40
89 #define DROP_PACKET_OFF 0
90 #define DROP_PACKET_ON 1
92 extern unsigned long hfi1_cap_mask;
93 #define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap)
94 #define HFI1_CAP_UGET_MASK(mask, cap) \
95 (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap)
96 #define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap))
97 #define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap))
98 #define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap))
99 #define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap))
100 #define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \
102 /* Offline Disabled Reason is 4-bits */
103 #define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON)
106 * Control context is always 0 and handles the error packets.
107 * It also handles the VL15 and multicast packets.
109 #define HFI1_CTRL_CTXT 0
112 * Driver context will store software counters for each of the events
113 * associated with these status registers
115 #define NUM_CCE_ERR_STATUS_COUNTERS 41
116 #define NUM_RCV_ERR_STATUS_COUNTERS 64
117 #define NUM_MISC_ERR_STATUS_COUNTERS 13
118 #define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36
119 #define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4
120 #define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64
121 #define NUM_SEND_ERR_STATUS_COUNTERS 3
122 #define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5
123 #define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24
126 * per driver stats, either not device nor port-specific, or
127 * summed over all of the devices and ports.
128 * They are described by name via ipathfs filesystem, so layout
129 * and number of elements can change without breaking compatibility.
130 * If members are added or deleted hfi1_statnames[] in debugfs.c must
133 struct hfi1_ib_stats {
134 __u64 sps_ints; /* number of interrupts handled */
135 __u64 sps_errints; /* number of error interrupts */
136 __u64 sps_txerrs; /* tx-related packet errors */
137 __u64 sps_rcverrs; /* non-crc rcv packet errors */
138 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */
139 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */
140 __u64 sps_ctxts; /* number of contexts currently open */
141 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */
146 extern struct hfi1_ib_stats hfi1_stats;
147 extern const struct pci_error_handlers hfi1_pci_err_handler;
150 * First-cut criterion for "device is active" is
151 * two thousand dwords combined Tx, Rx traffic per
152 * 5-second interval. SMA packets are 64 dwords,
153 * and occur "a few per second", presumably each way.
155 #define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000)
158 * Below contains all data related to a single context (formerly called port).
161 #ifdef CONFIG_DEBUG_FS
162 struct hfi1_opcode_stats_perctx;
165 struct ctxt_eager_bufs {
166 ssize_t size; /* total size of eager buffers */
167 u32 count; /* size of buffers array */
168 u32 numbufs; /* number of buffers allocated */
169 u32 alloced; /* number of rcvarray entries used */
170 u32 rcvtid_size; /* size of each eager rcv tid */
171 u32 threshold; /* head update threshold */
172 struct eager_buffer {
184 struct list_head list;
188 struct hfi1_ctxtdata {
189 /* shadow the ctxt's RcvCtrl register */
191 /* rcvhdrq base, needs mmap before useful */
193 /* kernel virtual address where hdrqtail is updated */
194 volatile __le64 *rcvhdrtail_kvaddr;
196 * Shared page for kernel to signal user processes that send buffers
197 * need disarming. The process should call HFI1_CMD_DISARM_BUFS
198 * or HFI1_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set.
200 unsigned long *user_event_mask;
201 /* when waiting for rcv or pioavail */
202 wait_queue_head_t wait;
203 /* rcvhdrq size (for freeing) */
205 /* number of rcvhdrq entries */
207 /* size of each of the rcvhdrq entries */
209 /* mmap of hdrq, must fit in 44 bits */
210 dma_addr_t rcvhdrq_phys;
211 dma_addr_t rcvhdrqtailaddr_phys;
212 struct ctxt_eager_bufs egrbufs;
213 /* this receive context's assigned PIO ACK send context */
214 struct send_context *sc;
216 /* dynamic receive available interrupt timeout */
217 u32 rcvavail_timeout;
219 * number of opens (including slave sub-contexts) on this instance
220 * (ignoring forks, dup, etc. for now)
224 * how much space to leave at start of eager TID entries for
225 * protocol use, on each TID
227 /* instead of calculating it */
229 /* non-zero if ctxt is being shared. */
231 /* non-zero if ctxt is being shared. */
236 /* number of RcvArray groups for this context. */
237 u32 rcv_array_groups;
238 /* index of first eager TID entry. */
240 /* number of expected TID entries */
242 /* index of first expected TID entry. */
245 struct exp_tid_set tid_group_list;
246 struct exp_tid_set tid_used_list;
247 struct exp_tid_set tid_full_list;
249 /* lock protecting all Expected TID data */
250 struct mutex exp_lock;
251 /* number of pio bufs for this ctxt (all procs, if shared) */
253 /* first pio buffer for this ctxt */
255 /* chip offset of PIO buffers for this ctxt */
257 /* per-context configuration flags */
259 /* per-context event flags for fileops/intr communication */
260 unsigned long event_flags;
261 /* WAIT_RCV that timed out, no interrupt */
263 /* WAIT_PIO that timed out, no interrupt */
265 /* WAIT_RCV already happened, no wait */
267 /* WAIT_PIO already happened, no wait */
269 /* total number of polled urgent packets */
271 /* saved total number of polled urgent packets for poll edge trigger */
273 /* pid of process using this ctxt */
275 pid_t subpid[HFI1_MAX_SHARED_CTXTS];
276 /* same size as task_struct .comm[], command that opened context */
277 char comm[TASK_COMM_LEN];
278 /* so file ops can get at unit */
279 struct hfi1_devdata *dd;
280 /* so functions that need physical port can get it easily */
281 struct hfi1_pportdata *ppd;
282 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
283 void *subctxt_uregbase;
284 /* An array of pages for the eager receive buffers * N */
285 void *subctxt_rcvegrbuf;
286 /* An array of pages for the eager header queue entries * N */
287 void *subctxt_rcvhdr_base;
288 /* The version of the library which opened this ctxt */
290 /* Bitmask of active slaves */
292 /* Type of packets or conditions we want to poll for */
294 /* receive packet sequence counter */
297 /* ctxt rcvhdrq head offset */
300 /* QPs waiting for context processing */
301 struct list_head qp_wait_list;
302 /* interrupt handling */
303 u64 imask; /* clear interrupt mask */
304 int ireg; /* clear interrupt register */
305 unsigned numa_id; /* numa node of this context */
306 /* verbs stats per CTX */
307 struct hfi1_opcode_stats_perctx *opstats;
309 * This is the kernel thread that will keep making
310 * progress on the user sdma requests behind the scenes.
311 * There is one per context (shared contexts use the master's).
313 struct task_struct *progress;
314 struct list_head sdma_queues;
315 /* protect sdma queues */
316 spinlock_t sdma_qlock;
318 /* Is ASPM interrupt supported for this context */
319 bool aspm_intr_supported;
320 /* ASPM state (enabled/disabled) for this context */
322 /* Timer for re-enabling ASPM if interrupt activity quietens down */
323 struct timer_list aspm_timer;
324 /* Lock to serialize between intr, timer intr and user threads */
325 spinlock_t aspm_lock;
326 /* Is ASPM processing enabled for this context (in intr context) */
327 bool aspm_intr_enable;
328 /* Last interrupt timestamp */
329 ktime_t aspm_ts_last_intr;
330 /* Last timestamp at which we scheduled a timer for this context */
331 ktime_t aspm_ts_timer_sched;
334 * The interrupt handler for a particular receive context can vary
335 * throughout it's lifetime. This is not a lock protected data member so
336 * it must be updated atomically and the prev and new value must always
337 * be valid. Worst case is we process an extra interrupt and up to 64
338 * packets with the wrong interrupt handler.
340 int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded);
344 * Represents a single packet at a high level. Put commonly computed things in
345 * here so we do not have to keep doing them over and over. The rule of thumb is
346 * if something is used one time to derive some value, store that something in
347 * here. If it is used multiple times, then store the result of that derivation
353 struct hfi1_ctxtdata *rcd;
356 struct hfi1_other_headers *ohdr;
371 static inline bool has_sc4_bit(struct hfi1_packet *p)
373 return !!rhf_dc_info(p->rhf);
377 * Private data for snoop/capture support.
379 struct hfi1_snoop_data {
382 struct device *class_dev;
383 /* protect snoop data */
384 spinlock_t snoop_lock;
385 struct list_head queue;
386 wait_queue_head_t waitq;
388 int (*filter_callback)(void *hdr, void *data, void *value);
389 u64 dcc_cfg; /* saved value of DCC Cfg register */
392 /* snoop mode_flag values */
393 #define HFI1_PORT_SNOOP_MODE 1U
394 #define HFI1_PORT_CAPTURE_MODE 2U
396 struct rvt_sge_state;
399 * Get/Set IB link-level config parameters for f_get/set_ib_cfg()
400 * Mostly for MADs that set or query link parameters, also ipath
403 #define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
404 #define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */
405 #define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */
406 #define HFI1_IB_CFG_LWID 3 /* currently active Link-width */
407 #define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */
408 #define HFI1_IB_CFG_SPD 5 /* current Link spd */
409 #define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */
410 #define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */
411 #define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */
412 #define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */
413 #define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */
414 #define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */
415 #define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */
416 #define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */
417 #define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */
418 #define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */
419 #define HFI1_IB_CFG_PKEYS 16 /* update partition keys */
420 #define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */
421 #define HFI1_IB_CFG_VL_HIGH_LIMIT 19
422 #define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */
423 #define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */
426 * HFI or Host Link States
428 * These describe the states the driver thinks the logical and physical
429 * states are in. Used as an argument to set_link_state(). Implemented
430 * as bits for easy multi-state checking. The actual state can only be
433 #define __HLS_UP_INIT_BP 0
434 #define __HLS_UP_ARMED_BP 1
435 #define __HLS_UP_ACTIVE_BP 2
436 #define __HLS_DN_DOWNDEF_BP 3 /* link down default */
437 #define __HLS_DN_POLL_BP 4
438 #define __HLS_DN_DISABLE_BP 5
439 #define __HLS_DN_OFFLINE_BP 6
440 #define __HLS_VERIFY_CAP_BP 7
441 #define __HLS_GOING_UP_BP 8
442 #define __HLS_GOING_OFFLINE_BP 9
443 #define __HLS_LINK_COOLDOWN_BP 10
445 #define HLS_UP_INIT BIT(__HLS_UP_INIT_BP)
446 #define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP)
447 #define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP)
448 #define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */
449 #define HLS_DN_POLL BIT(__HLS_DN_POLL_BP)
450 #define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP)
451 #define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP)
452 #define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP)
453 #define HLS_GOING_UP BIT(__HLS_GOING_UP_BP)
454 #define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP)
455 #define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP)
457 #define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE)
458 #define HLS_DOWN ~(HLS_UP)
460 /* use this MTU size if none other is given */
461 #define HFI1_DEFAULT_ACTIVE_MTU 10240
462 /* use this MTU size as the default maximum */
463 #define HFI1_DEFAULT_MAX_MTU 10240
464 /* default partition key */
465 #define DEFAULT_PKEY 0xffff
468 * Possible fabric manager config parameters for fm_{get,set}_table()
470 #define FM_TBL_VL_HIGH_ARB 1 /* Get/set VL high prio weights */
471 #define FM_TBL_VL_LOW_ARB 2 /* Get/set VL low prio weights */
472 #define FM_TBL_BUFFER_CONTROL 3 /* Get/set Buffer Control */
473 #define FM_TBL_SC2VLNT 4 /* Get/set SC->VLnt */
474 #define FM_TBL_VL_PREEMPT_ELEMS 5 /* Get (no set) VL preempt elems */
475 #define FM_TBL_VL_PREEMPT_MATRIX 6 /* Get (no set) VL preempt matrix */
478 * Possible "operations" for f_rcvctrl(ppd, op, ctxt)
479 * these are bits so they can be combined, e.g.
480 * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB
482 #define HFI1_RCVCTRL_TAILUPD_ENB 0x01
483 #define HFI1_RCVCTRL_TAILUPD_DIS 0x02
484 #define HFI1_RCVCTRL_CTXT_ENB 0x04
485 #define HFI1_RCVCTRL_CTXT_DIS 0x08
486 #define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10
487 #define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20
488 #define HFI1_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */
489 #define HFI1_RCVCTRL_PKEY_DIS 0x80
490 #define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400
491 #define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800
492 #define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000
493 #define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000
494 #define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000
495 #define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000
496 #define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000
497 #define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000
499 /* partition enforcement flags */
500 #define HFI1_PART_ENFORCE_IN 0x1
501 #define HFI1_PART_ENFORCE_OUT 0x2
503 /* how often we check for synthetic counter wrap around */
504 #define SYNTH_CNT_TIME 2
507 #define CNTR_NORMAL 0x0 /* Normal counters, just read register */
508 #define CNTR_SYNTH 0x1 /* Synthetic counters, saturate at all 1s */
509 #define CNTR_DISABLED 0x2 /* Disable this counter */
510 #define CNTR_32BIT 0x4 /* Simulate 64 bits for this counter */
511 #define CNTR_VL 0x8 /* Per VL counter */
512 #define CNTR_SDMA 0x10
513 #define CNTR_INVALID_VL -1 /* Specifies invalid VL */
514 #define CNTR_MODE_W 0x0
515 #define CNTR_MODE_R 0x1
517 /* VLs Supported/Operational */
518 #define HFI1_MIN_VLS_SUPPORTED 1
519 #define HFI1_MAX_VLS_SUPPORTED 8
521 static inline void incr_cntr64(u64 *cntr)
523 if (*cntr < (u64)-1LL)
527 static inline void incr_cntr32(u32 *cntr)
529 if (*cntr < (u32)-1LL)
533 #define MAX_NAME_SIZE 64
534 struct hfi1_msix_entry {
536 struct msix_entry msix;
538 char name[MAX_NAME_SIZE];
542 /* per-SL CCA information */
544 struct hrtimer hrtimer;
545 struct hfi1_pportdata *ppd; /* read-only */
546 int sl; /* read-only */
547 u16 ccti; /* read/write - current value of CCTI */
550 struct link_down_reason {
552 * SMA-facing value. Should be set from .latest when
553 * HLS_UP_* -> HLS_DN_* transition actually occurs.
565 struct vl_arb_cache {
566 /* protect vl arb cache */
568 struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE];
572 * The structure below encapsulates data relevant to a physical IB Port.
573 * Current chips support only one such port, but the separation
574 * clarifies things a bit. Note that to conform to IB conventions,
575 * port-numbers are one-based. The first or only port is port1.
577 struct hfi1_pportdata {
578 struct hfi1_ibport ibport_data;
580 struct hfi1_devdata *dd;
581 struct kobject pport_cc_kobj;
582 struct kobject sc2vl_kobj;
583 struct kobject sl2sc_kobj;
584 struct kobject vl2mtu_kobj;
588 struct qsfp_data qsfp_info;
590 /* GUID for this interface, in host order */
592 /* GUID for peer interface, in host order */
595 /* up or down physical link state */
599 * this address is mapped read-only into user processes so they can
600 * get status cheaply, whenever they want. One qword of status per port
604 /* SendDMA related entries */
606 struct workqueue_struct *hfi1_wq;
608 /* move out of interrupt context */
609 struct work_struct link_vc_work;
610 struct work_struct link_up_work;
611 struct work_struct link_down_work;
612 struct work_struct sma_message_work;
613 struct work_struct freeze_work;
614 struct work_struct link_downgrade_work;
615 struct work_struct link_bounce_work;
616 /* host link state variables */
617 struct mutex hls_lock;
620 spinlock_t sdma_alllock ____cacheline_aligned_in_smp;
622 u32 lstate; /* logical link state */
624 /* these are the "32 bit" regs */
626 u32 ibmtu; /* The MTU programmed for this unit */
628 * Current max size IB packet (in bytes) including IB headers, that
629 * we can send. Changes when ibmtu changes.
632 u32 current_egress_rate; /* units [10^6 bits/sec] */
633 /* LID programmed for this instance */
635 /* list of pkeys programmed; 0 if not set */
636 u16 pkeys[MAX_PKEY_VALUES];
637 u16 link_width_supported;
638 u16 link_width_downgrade_supported;
639 u16 link_speed_supported;
640 u16 link_width_enabled;
641 u16 link_width_downgrade_enabled;
642 u16 link_speed_enabled;
643 u16 link_width_active;
644 u16 link_width_downgrade_tx_active;
645 u16 link_width_downgrade_rx_active;
646 u16 link_speed_active;
649 u8 actual_vls_operational;
650 /* LID mask control */
652 /* Rx Polarity inversion (compensate for ~tx on partner) */
655 u8 hw_pidx; /* physical port index */
656 u8 port; /* IB port number and index into dd->pports - 1 */
657 /* type of neighbor node */
660 u8 neighbor_fm_security; /* 1 if firmware checking is disabled */
661 u8 neighbor_port_number;
662 u8 is_sm_config_started;
663 u8 offline_disabled_reason;
664 u8 is_active_optimize_enabled;
665 u8 driver_link_ready; /* driver ready for active link */
666 u8 link_enabled; /* link enabled? */
668 u8 local_tx_rate; /* rate given to 8051 firmware */
669 u8 last_pstate; /* info only */
671 /* placeholders for IB MAD packet settings */
672 u8 overrun_threshold;
673 u8 phy_error_threshold;
675 /* Used to override LED behavior for things like maintenance beaconing*/
677 * Alternates per phase of blink
678 * [0] holds LED off duration, [1] holds LED on duration
680 unsigned long led_override_vals[2];
681 u8 led_override_phase; /* LSB picks from vals[] */
682 atomic_t led_override_timer_active;
683 /* Used to flash LEDs in override mode */
684 struct timer_list led_override_timer;
690 * cca_timer_lock protects access to the per-SL cca_timer
691 * structures (specifically the ccti member).
693 spinlock_t cca_timer_lock ____cacheline_aligned_in_smp;
694 struct cca_timer cca_timer[OPA_MAX_SLS];
696 /* List of congestion control table entries */
697 struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX];
699 /* congestion entries, each entry corresponding to a SL */
700 struct opa_congestion_setting_entry_shadow
701 congestion_entries[OPA_MAX_SLS];
704 * cc_state_lock protects (write) access to the per-port
707 spinlock_t cc_state_lock ____cacheline_aligned_in_smp;
709 struct cc_state __rcu *cc_state;
711 /* Total number of congestion control table entries */
714 /* Bit map identifying service level */
715 u32 cc_sl_control_map;
717 /* CA's max number of 64 entry units in the congestion control table */
718 u8 cc_max_table_entries;
721 * begin congestion log related entries
722 * cc_log_lock protects all congestion log related data
724 spinlock_t cc_log_lock ____cacheline_aligned_in_smp;
725 u8 threshold_cong_event_map[OPA_MAX_SLS / 8];
726 u16 threshold_event_counter;
727 struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS];
728 int cc_log_idx; /* index for logging events */
729 int cc_mad_idx; /* index for reporting events */
730 /* end congestion log related entries */
732 struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE];
734 /* port relative counter buffer */
736 /* port relative synthetic counter buffer */
738 /* port_xmit_discards are synthesized from different egress errors */
739 u64 port_xmit_discards;
740 u64 port_xmit_discards_vl[C_VL_COUNT];
741 u64 port_xmit_constraint_errors;
742 u64 port_rcv_constraint_errors;
743 /* count of 'link_err' interrupts from DC */
745 /* number of times link retrained successfully */
747 /* number of times a link unknown frame was reported */
748 u64 unknown_frame_count;
749 /* port_ltp_crc_mode is returned in 'portinfo' MADs */
750 u16 port_ltp_crc_mode;
751 /* port_crc_mode_enabled is the crc we support */
752 u8 port_crc_mode_enabled;
753 /* mgmt_allowed is also returned in 'portinfo' MADs */
755 u8 part_enforce; /* partition enforcement flags */
756 struct link_down_reason local_link_down_reason;
757 struct link_down_reason neigh_link_down_reason;
758 /* Value to be sent to link peer on LinkDown .*/
759 u8 remote_link_down_reason;
760 /* Error events that will cause a port bounce. */
761 u32 port_error_action;
762 struct work_struct linkstate_active_work;
763 /* Does this port need to prescan for FECNs */
767 typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet);
769 typedef void (*opcode_handler)(struct hfi1_packet *packet);
771 /* return values for the RHF receive functions */
772 #define RHF_RCV_CONTINUE 0 /* keep going */
773 #define RHF_RCV_DONE 1 /* stop, this packet processed */
774 #define RHF_RCV_REPROCESS 2 /* stop. retain this packet */
776 struct rcv_array_data {
784 struct send_context *sc;
787 /* 16 to directly index */
788 #define PER_VL_SEND_CONTEXTS 16
790 struct err_info_rcvport {
796 struct err_info_constraint {
803 unsigned int curr; /* current temperature */
804 unsigned int lo_lim; /* low temperature limit */
805 unsigned int hi_lim; /* high temperature limit */
806 unsigned int crit_lim; /* critical temperature limit */
807 u8 triggers; /* temperature triggers */
810 struct hfi1_i2c_bus {
811 struct hfi1_devdata *controlling_dd; /* current controlling device */
812 struct i2c_adapter adapter; /* bus details */
813 struct i2c_algo_bit_data algo; /* bus algorithm details */
814 int num; /* bus number, 0 or 1 */
817 /* common data between shared ASIC HFIs */
818 struct hfi1_asic_data {
819 struct hfi1_devdata *dds[2]; /* back pointers */
820 struct mutex asic_resource_mutex;
821 struct hfi1_i2c_bus *i2c_bus0;
822 struct hfi1_i2c_bus *i2c_bus1;
825 /* device data struct now contains only "general per-device" info.
826 * fields related to a physical IB port are in a hfi1_pportdata struct.
831 #define BOARD_VERS_MAX 96 /* how long the version string can be */
832 #define SERIAL_MAX 16 /* length of the serial number */
834 typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64);
835 struct hfi1_devdata {
836 struct hfi1_ibdev verbs_dev; /* must be first */
837 struct list_head list;
838 /* pointers to related structs for this device */
839 /* pci access data structure */
840 struct pci_dev *pcidev;
841 struct cdev user_cdev;
842 struct cdev diag_cdev;
844 struct device *user_device;
845 struct device *diag_device;
846 struct device *ui_device;
848 /* mem-mapped pointer to base of chip regs */
849 u8 __iomem *kregbase;
850 /* end of mem-mapped chip space excluding sendbuf and user regs */
852 /* physical address of chip for io_remap, etc. */
853 resource_size_t physaddr;
854 /* receive context data */
855 struct hfi1_ctxtdata **rcd;
856 /* send context data */
857 struct send_context_info *send_contexts;
858 /* map hardware send contexts to software index */
860 /* spinlock for allocating and releasing send context resources */
862 /* Per VL data. Enough for all VLs but not all elements are set/used. */
863 struct per_vl_data vld[PER_VL_SEND_CONTEXTS];
864 /* lock for pio_map */
865 spinlock_t pio_map_lock;
866 /* array of kernel send contexts */
867 struct send_context **kernel_send_context;
868 /* array of vl maps */
869 struct pio_vl_map __rcu *pio_map;
870 /* seqlock for sc2vl */
871 seqlock_t sc2vl_lock;
873 /* Send Context initialization lock. */
874 spinlock_t sc_init_lock;
876 /* fields common to all SDMA engines */
878 /* default flags to last descriptor */
880 volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */
881 dma_addr_t sdma_heads_phys;
882 void *sdma_pad_dma; /* DMA'ed by chip */
883 dma_addr_t sdma_pad_phys;
884 /* for deallocation */
885 size_t sdma_heads_size;
886 /* number from the chip */
887 u32 chip_sdma_engines;
890 /* lock for sdma_map */
891 spinlock_t sde_map_lock;
892 /* array of engines sized by num_sdma */
893 struct sdma_engine *per_sdma;
894 /* array of vl maps */
895 struct sdma_vl_map __rcu *sdma_map;
896 /* SPC freeze waitqueue and variable */
897 wait_queue_head_t sdma_unfreeze_wq;
898 atomic_t sdma_unfreeze_count;
900 /* common data between shared ASIC HFIs in this OS */
901 struct hfi1_asic_data *asic_data;
903 /* hfi1_pportdata, points to array of (physical) port-specific
904 * data structs, indexed by pidx (0..n-1)
906 struct hfi1_pportdata *pport;
908 /* mem-mapped pointer to base of PIO buffers */
909 void __iomem *piobase;
911 * write-combining mem-mapped pointer to base of RcvArray
914 void __iomem *rcvarray_wc;
916 * credit return base - a per-NUMA range of DMA address that
917 * the chip will use to update the per-context free counter
919 struct credit_return_base *cr_base;
921 /* send context numbers and sizes for each type */
922 struct sc_config_sizes sc_sizes[SC_MAX];
924 u32 lcb_access_count; /* count of LCB users */
926 char *boardname; /* human readable board info */
928 /* device (not port) flags, basically device capabilities */
935 /* percpu int_counter */
936 u64 __percpu *int_counter;
937 u64 __percpu *rcv_limit;
938 u64 __percpu *send_schedule;
939 /* number of receive contexts in use by the driver */
940 u32 num_rcv_contexts;
941 /* number of pio send contexts in use by the driver */
942 u32 num_send_contexts;
944 * number of ctxts available for PSM open
947 /* total number of available user/PSM contexts */
948 u32 num_user_contexts;
949 /* base receive interrupt timeout, in CSR units */
950 u32 rcv_intr_timeout_csr;
952 u64 __iomem *egrtidbase;
953 spinlock_t sendctrl_lock; /* protect changes to SendCtrl */
954 spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */
955 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */
956 spinlock_t uctxt_lock; /* rcd and user context changes */
957 /* exclusive access to 8051 */
958 spinlock_t dc8051_lock;
959 /* exclusive access to 8051 memory */
960 spinlock_t dc8051_memlock;
961 int dc8051_timed_out; /* remember if the 8051 timed out */
963 * A page that will hold event notification bitmaps for all
964 * contexts. This page will be mapped into all processes.
966 unsigned long *events;
968 * per unit status, see also portdata statusp
969 * mapped read-only into user processes so they can get unit and
970 * IB link status cheaply
972 struct hfi1_status *status;
973 u32 freezelen; /* max length of freezemsg */
975 /* revision register shadow */
977 /* Base GUID for device (network order) */
980 /* these are the "32 bit" regs */
982 /* value we put in kr_rcvhdrsize */
984 /* number of receive contexts the chip supports */
985 u32 chip_rcv_contexts;
986 /* number of receive array entries */
987 u32 chip_rcv_array_count;
988 /* number of PIO send contexts the chip supports */
989 u32 chip_send_contexts;
990 /* number of bytes in the PIO memory buffer */
991 u32 chip_pio_mem_size;
992 /* number of bytes in the SDMA memory buffer */
993 u32 chip_sdma_mem_size;
995 /* size of each rcvegrbuffer */
998 u16 rcvegrbufsize_shift;
999 /* both sides of the PCIe link are gen3 capable */
1000 u8 link_gen3_capable;
1001 /* localbus width (1, 2,4,8,16,32) from config space */
1003 /* localbus speed in MHz */
1005 int unit; /* unit # of this chip */
1006 int node; /* home node of this chip */
1008 /* save these PCI fields to restore after a reset */
1021 * ASCII serial number, from flash, large enough for original
1022 * all digit strings, and longer serial number format
1024 u8 serial[SERIAL_MAX];
1025 /* human readable board version */
1026 u8 boardversion[BOARD_VERS_MAX];
1027 u8 lbus_info[32]; /* human readable localbus info */
1028 /* chip major rev, from CceRevision */
1030 /* chip minor rev, from CceRevision */
1034 /* implementation code */
1036 /* default link down value (poll/sleep) */
1038 /* vAU of this device */
1040 /* vCU of this device */
1042 /* link credits of this device */
1044 /* initial vl15 credits to use */
1047 /* Misc small ints */
1048 /* Number of physical ports available */
1050 /* Lowest context number which can be used by user processes */
1056 u16 rhf_offset; /* offset of RHF within receive header entry */
1057 u16 irev; /* implementation revision */
1058 u16 dc8051_ver; /* 8051 firmware version */
1060 struct platform_config platform_config;
1061 struct platform_config_cache pcfg_cache;
1063 struct diag_client *diag_client;
1064 spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */
1066 u8 psxmitwait_supported;
1067 /* cycle length of PS* counters in HW (in picoseconds) */
1068 u16 psxmitwait_check_rate;
1069 /* high volume overflow errors deferred to tasklet */
1070 struct tasklet_struct error_tasklet;
1072 /* MSI-X information */
1073 struct hfi1_msix_entry *msix_entries;
1074 u32 num_msix_entries;
1076 /* INTx information */
1077 u32 requested_intx_irq; /* did we request one? */
1078 char intx_name[MAX_NAME_SIZE]; /* INTx name */
1080 /* general interrupt: mask of handled interrupts */
1081 u64 gi_mask[CCE_NUM_INT_CSRS];
1083 struct rcv_array_data rcv_entries;
1086 * 64 bit synthetic counters
1088 struct timer_list synth_stats_timer;
1094 size_t cntrnameslen;
1100 * remembered values for synthetic counters
1109 char *portcntrnames;
1110 size_t portcntrnameslen;
1112 struct hfi1_snoop_data hfi1_snoop;
1114 struct err_info_rcvport err_info_rcvport;
1115 struct err_info_constraint err_info_rcv_constraint;
1116 struct err_info_constraint err_info_xmit_constraint;
1117 u8 err_info_uncorrectable;
1118 u8 err_info_fmconfig;
1120 atomic_t drop_packet;
1124 * Software counters for the status bits defined by the
1125 * associated error status registers
1127 u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS];
1128 u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS];
1129 u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS];
1130 u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS];
1131 u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS];
1132 u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS];
1133 u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS];
1135 /* Software counter that spans all contexts */
1136 u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS];
1137 /* Software counter that spans all DMA engines */
1138 u64 sw_send_dma_eng_err_status_cnt[
1139 NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS];
1140 /* Software counter that aggregates all cce_err_status errors */
1141 u64 sw_cce_err_status_aggregate;
1142 /* Software counter that aggregates all bypass packet rcv errors */
1143 u64 sw_rcv_bypass_packet_errors;
1144 /* receive interrupt functions */
1145 rhf_rcv_function_ptr *rhf_rcv_function_map;
1146 rhf_rcv_function_ptr normal_rhf_rcv_functions[8];
1149 * Handlers for outgoing data so that snoop/capture does not
1150 * have to have its hooks in the send path
1152 send_routine process_pio_send;
1153 send_routine process_dma_send;
1154 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf,
1155 u64 pbc, const void *from, size_t count);
1157 /* OUI comes from the HW. Used everywhere as 3 separate bytes. */
1161 /* Timer and counter used to detect RcvBufOvflCnt changes */
1162 struct timer_list rcverr_timer;
1165 wait_queue_head_t event_queue;
1167 /* Save the enabled LCB error bits */
1171 /* receive context tail dummy address */
1172 __le64 *rcvhdrtail_dummy_kvaddr;
1173 dma_addr_t rcvhdrtail_dummy_physaddr;
1175 bool eprom_available; /* true if EPROM is available for this device */
1176 bool aspm_supported; /* Does HW support ASPM */
1177 bool aspm_enabled; /* ASPM state: enabled/disabled */
1178 /* Serialize ASPM enable/disable between multiple verbs contexts */
1179 spinlock_t aspm_lock;
1180 /* Number of verbs contexts which have disabled ASPM */
1181 atomic_t aspm_disabled_cnt;
1183 struct hfi1_affinity *affinity;
1184 struct kobject kobj;
1187 /* 8051 firmware version helper */
1188 #define dc8051_ver(a, b) ((a) << 8 | (b))
1190 /* f_put_tid types */
1191 #define PT_EXPECTED 0
1193 #define PT_INVALID 2
1198 /* Private data for file operations */
1199 struct hfi1_filedata {
1200 struct hfi1_ctxtdata *uctxt;
1202 struct hfi1_user_sdma_comp_q *cq;
1203 struct hfi1_user_sdma_pkt_q *pq;
1204 /* for cpu affinity; -1 if none */
1207 struct rb_root tid_rb_root;
1208 struct tid_rb_node **entry_to_rb;
1209 spinlock_t tid_lock; /* protect tid_[limit,used] counters */
1213 u32 invalid_tid_idx;
1214 /* protect invalid_tids array and invalid_tid_idx */
1215 spinlock_t invalid_lock;
1218 extern struct list_head hfi1_dev_list;
1219 extern spinlock_t hfi1_devs_lock;
1220 struct hfi1_devdata *hfi1_lookup(int unit);
1221 extern u32 hfi1_cpulist_count;
1222 extern unsigned long *hfi1_cpulist;
1224 extern unsigned int snoop_drop_send;
1225 extern unsigned int snoop_force_capture;
1226 int hfi1_init(struct hfi1_devdata *, int);
1227 int hfi1_count_units(int *npresentp, int *nupp);
1228 int hfi1_count_active_units(void);
1230 int hfi1_diag_add(struct hfi1_devdata *);
1231 void hfi1_diag_remove(struct hfi1_devdata *);
1232 void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup);
1234 void handle_user_interrupt(struct hfi1_ctxtdata *rcd);
1236 int hfi1_create_rcvhdrq(struct hfi1_devdata *, struct hfi1_ctxtdata *);
1237 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *);
1238 int hfi1_create_ctxts(struct hfi1_devdata *dd);
1239 struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *, u32, int);
1240 void hfi1_init_pportdata(struct pci_dev *, struct hfi1_pportdata *,
1241 struct hfi1_devdata *, u8, u8);
1242 void hfi1_free_ctxtdata(struct hfi1_devdata *, struct hfi1_ctxtdata *);
1244 int handle_receive_interrupt(struct hfi1_ctxtdata *, int);
1245 int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *, int);
1246 int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *, int);
1247 void set_all_slowpath(struct hfi1_devdata *dd);
1249 extern const struct pci_device_id hfi1_pci_tbl[];
1251 /* receive packet handler dispositions */
1252 #define RCV_PKT_OK 0x0 /* keep going */
1253 #define RCV_PKT_LIMIT 0x1 /* stop, hit limit, start thread */
1254 #define RCV_PKT_DONE 0x2 /* stop, no more packets detected */
1256 /* calculate the current RHF address */
1257 static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd)
1259 return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->dd->rhf_offset;
1262 int hfi1_reset_device(int);
1264 /* return the driver's idea of the logical OPA port state */
1265 static inline u32 driver_lstate(struct hfi1_pportdata *ppd)
1267 return ppd->lstate; /* use the cached value */
1270 void receive_interrupt_work(struct work_struct *work);
1272 /* extract service channel from header and rhf */
1273 static inline int hdr2sc(struct hfi1_message_header *hdr, u64 rhf)
1275 return ((be16_to_cpu(hdr->lrh[0]) >> 12) & 0xf) |
1276 ((!!(rhf & RHF_DC_INFO_SMASK)) << 4);
1279 static inline u16 generate_jkey(kuid_t uid)
1281 return from_kuid(current_user_ns(), uid) & 0xffff;
1285 * active_egress_rate
1287 * returns the active egress rate in units of [10^6 bits/sec]
1289 static inline u32 active_egress_rate(struct hfi1_pportdata *ppd)
1291 u16 link_speed = ppd->link_speed_active;
1292 u16 link_width = ppd->link_width_active;
1295 if (link_speed == OPA_LINK_SPEED_25G)
1296 egress_rate = 25000;
1297 else /* assume OPA_LINK_SPEED_12_5G */
1298 egress_rate = 12500;
1300 switch (link_width) {
1301 case OPA_LINK_WIDTH_4X:
1304 case OPA_LINK_WIDTH_3X:
1307 case OPA_LINK_WIDTH_2X:
1311 /* assume IB_WIDTH_1X */
1321 * Returns the number of 'fabric clock cycles' to egress a packet
1322 * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock
1323 * rate is (approximately) 805 MHz, the units of the returned value
1326 static inline u32 egress_cycles(u32 len, u32 rate)
1333 * (length) [bits] / (rate) [bits/sec]
1334 * ---------------------------------------------------
1335 * fabric_clock_period == 1 /(805 * 10^6) [cycles/sec]
1338 cycles = len * 8; /* bits */
1345 void set_link_ipg(struct hfi1_pportdata *ppd);
1346 void process_becn(struct hfi1_pportdata *ppd, u8 sl, u16 rlid, u32 lqpn,
1347 u32 rqpn, u8 svc_type);
1348 void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn,
1349 u32 pkey, u32 slid, u32 dlid, u8 sc5,
1350 const struct ib_grh *old_grh);
1351 #define PKEY_CHECK_INVALID -1
1352 int egress_pkey_check(struct hfi1_pportdata *ppd, __be16 *lrh, __be32 *bth,
1353 u8 sc5, int8_t s_pkey_index);
1355 #define PACKET_EGRESS_TIMEOUT 350
1356 static inline void pause_for_credit_return(struct hfi1_devdata *dd)
1358 /* Pause at least 1us, to ensure chip returns all credits */
1359 u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000;
1361 udelay(usec ? usec : 1);
1365 * sc_to_vlt() reverse lookup sc to vl
1369 static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5)
1374 if (sc5 >= OPA_MAX_SCS)
1378 seq = read_seqbegin(&dd->sc2vl_lock);
1379 rval = *(((u8 *)dd->sc2vl) + sc5);
1380 } while (read_seqretry(&dd->sc2vl_lock, seq));
1385 #define PKEY_MEMBER_MASK 0x8000
1386 #define PKEY_LOW_15_MASK 0x7fff
1389 * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1390 * being an entry from the ingress partition key table), return 0
1391 * otherwise. Use the matching criteria for ingress partition keys
1392 * specified in the OPAv1 spec., section 9.10.14.
1394 static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent)
1396 u16 mkey = pkey & PKEY_LOW_15_MASK;
1397 u16 ment = ent & PKEY_LOW_15_MASK;
1401 * If pkey[15] is clear (limited partition member),
1402 * is bit 15 in the corresponding table element
1403 * clear (limited member)?
1405 if (!(pkey & PKEY_MEMBER_MASK))
1406 return !!(ent & PKEY_MEMBER_MASK);
1413 * ingress_pkey_table_search - search the entire pkey table for
1414 * an entry which matches 'pkey'. return 0 if a match is found,
1417 static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey)
1421 for (i = 0; i < MAX_PKEY_VALUES; i++) {
1422 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1429 * ingress_pkey_table_fail - record a failure of ingress pkey validation,
1430 * i.e., increment port_rcv_constraint_errors for the port, and record
1431 * the 'error info' for this failure.
1433 static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey,
1436 struct hfi1_devdata *dd = ppd->dd;
1438 incr_cntr64(&ppd->port_rcv_constraint_errors);
1439 if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) {
1440 dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK;
1441 dd->err_info_rcv_constraint.slid = slid;
1442 dd->err_info_rcv_constraint.pkey = pkey;
1447 * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1
1448 * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx
1449 * is a hint as to the best place in the partition key table to begin
1450 * searching. This function should not be called on the data path because
1451 * of performance reasons. On datapath pkey check is expected to be done
1452 * by HW and rcv_pkey_check function should be called instead.
1454 static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1455 u8 sc5, u8 idx, u16 slid)
1457 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1460 /* If SC15, pkey[0:14] must be 0x7fff */
1461 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1464 /* Is the pkey = 0x0, or 0x8000? */
1465 if ((pkey & PKEY_LOW_15_MASK) == 0)
1468 /* The most likely matching pkey has index 'idx' */
1469 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx]))
1472 /* no match - try the whole table */
1473 if (!ingress_pkey_table_search(ppd, pkey))
1477 ingress_pkey_table_fail(ppd, pkey, slid);
1482 * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1
1483 * otherwise. It only ensures pkey is vlid for QP0. This function
1484 * should be called on the data path instead of ingress_pkey_check
1485 * as on data path, pkey check is done by HW (except for QP0).
1487 static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1490 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1493 /* If SC15, pkey[0:14] must be 0x7fff */
1494 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1499 ingress_pkey_table_fail(ppd, pkey, slid);
1505 /* MTU enumeration, 256-4k match IB */
1507 #define OPA_MTU_256 1
1508 #define OPA_MTU_512 2
1509 #define OPA_MTU_1024 3
1510 #define OPA_MTU_2048 4
1511 #define OPA_MTU_4096 5
1513 u32 lrh_max_header_bytes(struct hfi1_devdata *dd);
1514 int mtu_to_enum(u32 mtu, int default_if_bad);
1515 u16 enum_to_mtu(int);
1516 static inline int valid_ib_mtu(unsigned int mtu)
1518 return mtu == 256 || mtu == 512 ||
1519 mtu == 1024 || mtu == 2048 ||
1523 static inline int valid_opa_max_mtu(unsigned int mtu)
1525 return mtu >= 2048 &&
1526 (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240);
1529 int set_mtu(struct hfi1_pportdata *);
1531 int hfi1_set_lid(struct hfi1_pportdata *, u32, u8);
1532 void hfi1_disable_after_error(struct hfi1_devdata *);
1533 int hfi1_set_uevent_bits(struct hfi1_pportdata *, const int);
1534 int hfi1_rcvbuf_validate(u32, u8, u16 *);
1536 int fm_get_table(struct hfi1_pportdata *, int, void *);
1537 int fm_set_table(struct hfi1_pportdata *, int, void *);
1539 void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf);
1540 void reset_link_credits(struct hfi1_devdata *dd);
1541 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu);
1543 int snoop_recv_handler(struct hfi1_packet *packet);
1544 int snoop_send_dma_handler(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
1546 int snoop_send_pio_handler(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
1548 void snoop_inline_pio_send(struct hfi1_devdata *dd, struct pio_buf *pbuf,
1549 u64 pbc, const void *from, size_t count);
1550 int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc);
1552 static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd)
1557 static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev)
1559 return container_of(dev, struct hfi1_devdata, verbs_dev);
1562 static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev)
1564 return dd_from_dev(to_idev(ibdev));
1567 static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp)
1569 return container_of(ibp, struct hfi1_pportdata, ibport_data);
1572 static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi)
1574 return container_of(rdi, struct hfi1_ibdev, rdi);
1577 static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port)
1579 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1580 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */
1582 WARN_ON(pidx >= dd->num_pports);
1583 return &dd->pport[pidx].ibport_data;
1587 * Return the indexed PKEY from the port PKEY table.
1589 static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index)
1591 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1594 if (index >= ARRAY_SIZE(ppd->pkeys))
1597 ret = ppd->pkeys[index];
1603 * Readers of cc_state must call get_cc_state() under rcu_read_lock().
1604 * Writers of cc_state must call get_cc_state() under cc_state_lock.
1606 static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd)
1608 return rcu_dereference(ppd->cc_state);
1612 * values for dd->flags (_device_ related flags)
1614 #define HFI1_INITTED 0x1 /* chip and driver up and initted */
1615 #define HFI1_PRESENT 0x2 /* chip accesses can be done */
1616 #define HFI1_FROZEN 0x4 /* chip in SPC freeze */
1617 #define HFI1_HAS_SDMA_TIMEOUT 0x8
1618 #define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */
1619 #define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */
1621 /* IB dword length mask in PBC (lower 11 bits); same for all chips */
1622 #define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1)
1624 /* ctxt_flag bit offsets */
1625 /* context has been setup */
1626 #define HFI1_CTXT_SETUP_DONE 1
1627 /* waiting for a packet to arrive */
1628 #define HFI1_CTXT_WAITING_RCV 2
1629 /* master has not finished initializing */
1630 #define HFI1_CTXT_MASTER_UNINIT 4
1631 /* waiting for an urgent packet to arrive */
1632 #define HFI1_CTXT_WAITING_URG 5
1634 /* free up any allocated data at closes */
1635 struct hfi1_devdata *hfi1_init_dd(struct pci_dev *,
1636 const struct pci_device_id *);
1637 void hfi1_free_devdata(struct hfi1_devdata *);
1638 void cc_state_reclaim(struct rcu_head *rcu);
1639 struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra);
1641 /* LED beaconing functions */
1642 void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon,
1643 unsigned int timeoff);
1644 void shutdown_led_override(struct hfi1_pportdata *ppd);
1646 #define HFI1_CREDIT_RETURN_RATE (100)
1649 * The number of words for the KDETH protocol field. If this is
1650 * larger then the actual field used, then part of the payload
1651 * will be in the header.
1653 * Optimally, we want this sized so that a typical case will
1654 * use full cache lines. The typical local KDETH header would
1665 * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS
1667 #define DEFAULT_RCVHDRSIZE 9
1670 * Maximal header byte count:
1681 * We also want to maintain a cache line alignment to assist DMA'ing
1682 * of the header bytes. Round up to a good size.
1684 #define DEFAULT_RCVHDR_ENTSIZE 32
1686 bool hfi1_can_pin_pages(struct hfi1_devdata *, u32, u32);
1687 int hfi1_acquire_user_pages(unsigned long, size_t, bool, struct page **);
1688 void hfi1_release_user_pages(struct mm_struct *, struct page **, size_t, bool);
1690 static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1692 *((u64 *)rcd->rcvhdrtail_kvaddr) = 0ULL;
1695 static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1698 * volatile because it's a DMA target from the chip, routine is
1699 * inlined, and don't want register caching or reordering.
1701 return (u32)le64_to_cpu(*rcd->rcvhdrtail_kvaddr);
1708 extern const char ib_hfi1_version[];
1710 int hfi1_device_create(struct hfi1_devdata *);
1711 void hfi1_device_remove(struct hfi1_devdata *);
1713 int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num,
1714 struct kobject *kobj);
1715 int hfi1_verbs_register_sysfs(struct hfi1_devdata *);
1716 void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *);
1717 /* Hook for sysfs read of QSFP */
1718 int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len);
1720 int hfi1_pcie_init(struct pci_dev *, const struct pci_device_id *);
1721 void hfi1_pcie_cleanup(struct pci_dev *);
1722 int hfi1_pcie_ddinit(struct hfi1_devdata *, struct pci_dev *,
1723 const struct pci_device_id *);
1724 void hfi1_pcie_ddcleanup(struct hfi1_devdata *);
1725 void hfi1_pcie_flr(struct hfi1_devdata *);
1726 int pcie_speeds(struct hfi1_devdata *);
1727 void request_msix(struct hfi1_devdata *, u32 *, struct hfi1_msix_entry *);
1728 void hfi1_enable_intx(struct pci_dev *);
1729 void restore_pci_variables(struct hfi1_devdata *dd);
1730 int do_pcie_gen3_transition(struct hfi1_devdata *dd);
1731 int parse_platform_config(struct hfi1_devdata *dd);
1732 int get_platform_config_field(struct hfi1_devdata *dd,
1733 enum platform_config_table_type_encoding
1734 table_type, int table_index, int field_index,
1735 u32 *data, u32 len);
1737 const char *get_unit_name(int unit);
1738 const char *get_card_name(struct rvt_dev_info *rdi);
1739 struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi);
1742 * Flush write combining store buffers (if present) and perform a write
1745 static inline void flush_wc(void)
1747 asm volatile("sfence" : : : "memory");
1750 void handle_eflags(struct hfi1_packet *packet);
1751 int process_receive_ib(struct hfi1_packet *packet);
1752 int process_receive_bypass(struct hfi1_packet *packet);
1753 int process_receive_error(struct hfi1_packet *packet);
1754 int kdeth_process_expected(struct hfi1_packet *packet);
1755 int kdeth_process_eager(struct hfi1_packet *packet);
1756 int process_receive_invalid(struct hfi1_packet *packet);
1758 extern rhf_rcv_function_ptr snoop_rhf_rcv_functions[8];
1760 void update_sge(struct rvt_sge_state *ss, u32 length);
1762 /* global module parameter variables */
1763 extern unsigned int hfi1_max_mtu;
1764 extern unsigned int hfi1_cu;
1765 extern unsigned int user_credit_return_threshold;
1766 extern int num_user_contexts;
1767 extern unsigned n_krcvqs;
1768 extern uint krcvqs[];
1769 extern int krcvqsset;
1770 extern uint kdeth_qp;
1771 extern uint loopback;
1772 extern uint quick_linkup;
1773 extern uint rcv_intr_timeout;
1774 extern uint rcv_intr_count;
1775 extern uint rcv_intr_dynamic;
1776 extern ushort link_crc_mask;
1778 extern struct mutex hfi1_mutex;
1780 /* Number of seconds before our card status check... */
1781 #define STATUS_TIMEOUT 60
1783 #define DRIVER_NAME "hfi1"
1784 #define HFI1_USER_MINOR_BASE 0
1785 #define HFI1_TRACE_MINOR 127
1786 #define HFI1_DIAGPKT_MINOR 128
1787 #define HFI1_DIAG_MINOR_BASE 129
1788 #define HFI1_SNOOP_CAPTURE_BASE 200
1789 #define HFI1_NMINORS 255
1791 #define PCI_VENDOR_ID_INTEL 0x8086
1792 #define PCI_DEVICE_ID_INTEL0 0x24f0
1793 #define PCI_DEVICE_ID_INTEL1 0x24f1
1795 #define HFI1_PKT_USER_SC_INTEGRITY \
1796 (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \
1797 | SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK \
1798 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \
1799 | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK)
1801 #define HFI1_PKT_KERNEL_SC_INTEGRITY \
1802 (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK)
1804 static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd,
1807 u64 base_sc_integrity =
1808 SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
1809 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
1810 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
1811 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
1812 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
1813 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK
1814 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
1815 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
1816 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
1817 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK
1818 | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
1819 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
1820 | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK
1821 | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK
1822 | SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK
1823 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK
1824 | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK;
1826 if (ctxt_type == SC_USER)
1827 base_sc_integrity |= HFI1_PKT_USER_SC_INTEGRITY;
1829 base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY;
1832 /* turn off send-side job key checks - A0 */
1833 return base_sc_integrity &
1834 ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
1835 return base_sc_integrity;
1838 static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd)
1840 u64 base_sdma_integrity =
1841 SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
1842 | SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
1843 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
1844 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
1845 | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
1846 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
1847 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
1848 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
1849 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK
1850 | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
1851 | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
1852 | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK
1853 | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK
1854 | SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK
1855 | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK
1856 | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK;
1859 /* turn off send-side job key checks - A0 */
1860 return base_sdma_integrity &
1861 ~SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
1862 return base_sdma_integrity;
1866 * hfi1_early_err is used (only!) to print early errors before devdata is
1867 * allocated, or when dd->pcidev may not be valid, and at the tail end of
1868 * cleanup when devdata may have been freed, etc. hfi1_dev_porterr is
1869 * the same as dd_dev_err, but is used when the message really needs
1870 * the IB port# to be definitive as to what's happening..
1872 #define hfi1_early_err(dev, fmt, ...) \
1873 dev_err(dev, fmt, ##__VA_ARGS__)
1875 #define hfi1_early_info(dev, fmt, ...) \
1876 dev_info(dev, fmt, ##__VA_ARGS__)
1878 #define dd_dev_emerg(dd, fmt, ...) \
1879 dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \
1880 get_unit_name((dd)->unit), ##__VA_ARGS__)
1881 #define dd_dev_err(dd, fmt, ...) \
1882 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
1883 get_unit_name((dd)->unit), ##__VA_ARGS__)
1884 #define dd_dev_warn(dd, fmt, ...) \
1885 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \
1886 get_unit_name((dd)->unit), ##__VA_ARGS__)
1888 #define dd_dev_warn_ratelimited(dd, fmt, ...) \
1889 dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
1890 get_unit_name((dd)->unit), ##__VA_ARGS__)
1892 #define dd_dev_info(dd, fmt, ...) \
1893 dev_info(&(dd)->pcidev->dev, "%s: " fmt, \
1894 get_unit_name((dd)->unit), ##__VA_ARGS__)
1896 #define dd_dev_dbg(dd, fmt, ...) \
1897 dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \
1898 get_unit_name((dd)->unit), ##__VA_ARGS__)
1900 #define hfi1_dev_porterr(dd, port, fmt, ...) \
1901 dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \
1902 get_unit_name((dd)->unit), (port), ##__VA_ARGS__)
1905 * this is used for formatting hw error messages...
1907 struct hfi1_hwerror_msgs {
1914 void hfi1_format_hwerrors(u64 hwerrs,
1915 const struct hfi1_hwerror_msgs *hwerrmsgs,
1916 size_t nhwerrmsgs, char *msg, size_t lmsg);
1918 #define USER_OPCODE_CHECK_VAL 0xC0
1919 #define USER_OPCODE_CHECK_MASK 0xC0
1920 #define OPCODE_CHECK_VAL_DISABLED 0x0
1921 #define OPCODE_CHECK_MASK_DISABLED 0x0
1923 static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd)
1925 struct hfi1_pportdata *ppd;
1928 dd->z_int_counter = get_all_cpu_total(dd->int_counter);
1929 dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit);
1930 dd->z_send_schedule = get_all_cpu_total(dd->send_schedule);
1932 ppd = (struct hfi1_pportdata *)(dd + 1);
1933 for (i = 0; i < dd->num_pports; i++, ppd++) {
1934 ppd->ibport_data.rvp.z_rc_acks =
1935 get_all_cpu_total(ppd->ibport_data.rvp.rc_acks);
1936 ppd->ibport_data.rvp.z_rc_qacks =
1937 get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks);
1941 /* Control LED state */
1942 static inline void setextled(struct hfi1_devdata *dd, u32 on)
1945 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F);
1947 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10);
1950 /* return the i2c resource given the target */
1951 static inline u32 i2c_target(u32 target)
1953 return target ? CR_I2C2 : CR_I2C1;
1956 /* return the i2c chain chip resource that this HFI uses for QSFP */
1957 static inline u32 qsfp_resource(struct hfi1_devdata *dd)
1959 return i2c_target(dd->hfi1_id);
1962 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp);
1964 #define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev))
1965 #define DD_DEV_ASSIGN(dd) __assign_str(dev, dev_name(&(dd)->pcidev->dev))
1967 #define packettype_name(etype) { RHF_RCV_TYPE_##etype, #etype }
1968 #define show_packettype(etype) \
1969 __print_symbolic(etype, \
1970 packettype_name(EXPECTED), \
1971 packettype_name(EAGER), \
1972 packettype_name(IB), \
1973 packettype_name(ERROR), \
1974 packettype_name(BYPASS))
1976 #define ib_opcode_name(opcode) { IB_OPCODE_##opcode, #opcode }
1977 #define show_ib_opcode(opcode) \
1978 __print_symbolic(opcode, \
1979 ib_opcode_name(RC_SEND_FIRST), \
1980 ib_opcode_name(RC_SEND_MIDDLE), \
1981 ib_opcode_name(RC_SEND_LAST), \
1982 ib_opcode_name(RC_SEND_LAST_WITH_IMMEDIATE), \
1983 ib_opcode_name(RC_SEND_ONLY), \
1984 ib_opcode_name(RC_SEND_ONLY_WITH_IMMEDIATE), \
1985 ib_opcode_name(RC_RDMA_WRITE_FIRST), \
1986 ib_opcode_name(RC_RDMA_WRITE_MIDDLE), \
1987 ib_opcode_name(RC_RDMA_WRITE_LAST), \
1988 ib_opcode_name(RC_RDMA_WRITE_LAST_WITH_IMMEDIATE), \
1989 ib_opcode_name(RC_RDMA_WRITE_ONLY), \
1990 ib_opcode_name(RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE), \
1991 ib_opcode_name(RC_RDMA_READ_REQUEST), \
1992 ib_opcode_name(RC_RDMA_READ_RESPONSE_FIRST), \
1993 ib_opcode_name(RC_RDMA_READ_RESPONSE_MIDDLE), \
1994 ib_opcode_name(RC_RDMA_READ_RESPONSE_LAST), \
1995 ib_opcode_name(RC_RDMA_READ_RESPONSE_ONLY), \
1996 ib_opcode_name(RC_ACKNOWLEDGE), \
1997 ib_opcode_name(RC_ATOMIC_ACKNOWLEDGE), \
1998 ib_opcode_name(RC_COMPARE_SWAP), \
1999 ib_opcode_name(RC_FETCH_ADD), \
2000 ib_opcode_name(UC_SEND_FIRST), \
2001 ib_opcode_name(UC_SEND_MIDDLE), \
2002 ib_opcode_name(UC_SEND_LAST), \
2003 ib_opcode_name(UC_SEND_LAST_WITH_IMMEDIATE), \
2004 ib_opcode_name(UC_SEND_ONLY), \
2005 ib_opcode_name(UC_SEND_ONLY_WITH_IMMEDIATE), \
2006 ib_opcode_name(UC_RDMA_WRITE_FIRST), \
2007 ib_opcode_name(UC_RDMA_WRITE_MIDDLE), \
2008 ib_opcode_name(UC_RDMA_WRITE_LAST), \
2009 ib_opcode_name(UC_RDMA_WRITE_LAST_WITH_IMMEDIATE), \
2010 ib_opcode_name(UC_RDMA_WRITE_ONLY), \
2011 ib_opcode_name(UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE), \
2012 ib_opcode_name(UD_SEND_ONLY), \
2013 ib_opcode_name(UD_SEND_ONLY_WITH_IMMEDIATE), \
2014 ib_opcode_name(CNP))
2015 #endif /* _HFI1_KERNEL_H */