drivers/infiniband/hw/hfi1/init.c

   1 /*
   2  * Copyright(c) 2015, 2016 Intel Corporation.
   3  *
   4  * This file is provided under a dual BSD/GPLv2 license.  When using or
   5  * redistributing this file, you may do so under either license.
   6  *
   7  * GPL LICENSE SUMMARY
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * BSD LICENSE
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions
  22  * are met:
  23  *
  24  *  - Redistributions of source code must retain the above copyright
  25  *    notice, this list of conditions and the following disclaimer.
  26  *  - Redistributions in binary form must reproduce the above copyright
  27  *    notice, this list of conditions and the following disclaimer in
  28  *    the documentation and/or other materials provided with the
  29  *    distribution.
  30  *  - Neither the name of Intel Corporation nor the names of its
  31  *    contributors may be used to endorse or promote products derived
  32  *    from this software without specific prior written permission.
  33  *
  34  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  35  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  36  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  37  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  38  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  39  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  40  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  41  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  42  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  44  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  45  *
  46  */
  47
  48 #include <linux/pci.h>
  49 #include <linux/netdevice.h>
  50 #include <linux/vmalloc.h>
  51 #include <linux/delay.h>
  52 #include <linux/idr.h>
  53 #include <linux/module.h>
  54 #include <linux/printk.h>
  55 #include <linux/hrtimer.h>
  56 #include <rdma/rdma_vt.h>
  57
  58 #include "hfi.h"
  59 #include "device.h"
  60 #include "common.h"
  61 #include "trace.h"
  62 #include "mad.h"
  63 #include "sdma.h"
  64 #include "debugfs.h"
  65 #include "verbs.h"
  66 #include "aspm.h"
  67 #include "affinity.h"
  68
  69 #undef pr_fmt
  70 #define pr_fmt(fmt) DRIVER_NAME ": " fmt
  71
  72 /*
  73  * min buffers we want to have per context, after driver
  74  */
  75 #define HFI1_MIN_USER_CTXT_BUFCNT 7
  76
  77 #define HFI1_MIN_HDRQ_EGRBUF_CNT 2
  78 #define HFI1_MAX_HDRQ_EGRBUF_CNT 16352
  79 #define HFI1_MIN_EAGER_BUFFER_SIZE (4 * 1024) /* 4KB */
  80 #define HFI1_MAX_EAGER_BUFFER_SIZE (256 * 1024) /* 256KB */
  81
  82 /*
  83  * Number of user receive contexts we are configured to use (to allow for more
  84  * pio buffers per ctxt, etc.)  Zero means use one user context per CPU.
  85  */
  86 int num_user_contexts = -1;
  87 module_param_named(num_user_contexts, num_user_contexts, uint, S_IRUGO);
  88 MODULE_PARM_DESC(
  89         num_user_contexts, "Set max number of user contexts to use");
  90
  91 uint krcvqs[RXE_NUM_DATA_VL];
  92 int krcvqsset;
  93 module_param_array(krcvqs, uint, &krcvqsset, S_IRUGO);
  94 MODULE_PARM_DESC(krcvqs, "Array of the number of non-control kernel receive queues by VL");
  95
  96 /* computed based on above array */
  97 unsigned n_krcvqs;
  98
  99 static unsigned hfi1_rcvarr_split = 25;
 100 module_param_named(rcvarr_split, hfi1_rcvarr_split, uint, S_IRUGO);
 101 MODULE_PARM_DESC(rcvarr_split, "Percent of context's RcvArray entries used for Eager buffers");
 102
 103 static uint eager_buffer_size = (2 << 20); /* 2MB */
 104 module_param(eager_buffer_size, uint, S_IRUGO);
 105 MODULE_PARM_DESC(eager_buffer_size, "Size of the eager buffers, default: 2MB");
 106
 107 static uint rcvhdrcnt = 2048; /* 2x the max eager buffer count */
 108 module_param_named(rcvhdrcnt, rcvhdrcnt, uint, S_IRUGO);
 109 MODULE_PARM_DESC(rcvhdrcnt, "Receive header queue count (default 2048)");
 110
 111 static uint hfi1_hdrq_entsize = 32;
 112 module_param_named(hdrq_entsize, hfi1_hdrq_entsize, uint, S_IRUGO);
 113 MODULE_PARM_DESC(hdrq_entsize, "Size of header queue entries: 2 - 8B, 16 - 64B (default), 32 - 128B");
 114
 115 unsigned int user_credit_return_threshold = 33; /* default is 33% */
 116 module_param(user_credit_return_threshold, uint, S_IRUGO);
 117 MODULE_PARM_DESC(user_credit_return_threshold, "Credit return threshold for user send contexts, return when unreturned credits passes this many blocks (in percent of allocated blocks, 0 is off)");
 118
 119 static inline u64 encode_rcv_header_entry_size(u16);
 120
 121 static struct idr hfi1_unit_table;
 122 u32 hfi1_cpulist_count;
 123 unsigned long *hfi1_cpulist;
 124
 125 /*
 126  * Common code for creating the receive context array.
 127  */
 128 int hfi1_create_ctxts(struct hfi1_devdata *dd)
 129 {
 130         unsigned i;
 131         int ret;
 132
 133         /* Control context has to be always 0 */
 134         BUILD_BUG_ON(HFI1_CTRL_CTXT != 0);
 135
 136         dd->rcd = kzalloc_node(dd->num_rcv_contexts * sizeof(*dd->rcd),
 137                                GFP_KERNEL, dd->node);
 138         if (!dd->rcd)
 139                 goto nomem;
 140
 141         /* create one or more kernel contexts */
 142         for (i = 0; i < dd->first_user_ctxt; ++i) {
 143                 struct hfi1_pportdata *ppd;
 144                 struct hfi1_ctxtdata *rcd;
 145
 146                 ppd = dd->pport + (i % dd->num_pports);
 147                 rcd = hfi1_create_ctxtdata(ppd, i, dd->node);
 148                 if (!rcd) {
 149                         dd_dev_err(dd,
 150                                    "Unable to allocate kernel receive context, failing\n");
 151                         goto nomem;
 152                 }
 153                 /*
 154                  * Set up the kernel context flags here and now because they
 155                  * use default values for all receive side memories.  User
 156                  * contexts will be handled as they are created.
 157                  */
 158                 rcd->flags = HFI1_CAP_KGET(MULTI_PKT_EGR) |
 159                         HFI1_CAP_KGET(NODROP_RHQ_FULL) |
 160                         HFI1_CAP_KGET(NODROP_EGR_FULL) |
 161                         HFI1_CAP_KGET(DMA_RTAIL);
 162
 163                 /* Control context must use DMA_RTAIL */
 164                 if (rcd->ctxt == HFI1_CTRL_CTXT)
 165                         rcd->flags |= HFI1_CAP_DMA_RTAIL;
 166                 rcd->seq_cnt = 1;
 167
 168                 rcd->sc = sc_alloc(dd, SC_ACK, rcd->rcvhdrqentsize, dd->node);
 169                 if (!rcd->sc) {
 170                         dd_dev_err(dd,
 171                                    "Unable to allocate kernel send context, failing\n");
 172                         dd->rcd[rcd->ctxt] = NULL;
 173                         hfi1_free_ctxtdata(dd, rcd);
 174                         goto nomem;
 175                 }
 176
 177                 ret = hfi1_init_ctxt(rcd->sc);
 178                 if (ret < 0) {
 179                         dd_dev_err(dd,
 180                                    "Failed to setup kernel receive context, failing\n");
 181                         sc_free(rcd->sc);
 182                         dd->rcd[rcd->ctxt] = NULL;
 183                         hfi1_free_ctxtdata(dd, rcd);
 184                         ret = -EFAULT;
 185                         goto bail;
 186                 }
 187         }
 188
 189         /*
 190          * Initialize aspm, to be done after gen3 transition and setting up
 191          * contexts and before enabling interrupts
 192          */
 193         aspm_init(dd);
 194
 195         return 0;
 196 nomem:
 197         ret = -ENOMEM;
 198 bail:
 199         kfree(dd->rcd);
 200         dd->rcd = NULL;
 201         return ret;
 202 }
 203
 204 /*
 205  * Common code for user and kernel context setup.
 206  */
 207 struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, u32 ctxt,
 208                                            int numa)
 209 {
 210         struct hfi1_devdata *dd = ppd->dd;
 211         struct hfi1_ctxtdata *rcd;
 212         unsigned kctxt_ngroups = 0;
 213         u32 base;
 214
 215         if (dd->rcv_entries.nctxt_extra >
 216             dd->num_rcv_contexts - dd->first_user_ctxt)
 217                 kctxt_ngroups = (dd->rcv_entries.nctxt_extra -
 218                                  (dd->num_rcv_contexts - dd->first_user_ctxt));
 219         rcd = kzalloc(sizeof(*rcd), GFP_KERNEL);
 220         if (rcd) {
 221                 u32 rcvtids, max_entries;
 222
 223                 hfi1_cdbg(PROC, "setting up context %u\n", ctxt);
 224
 225                 INIT_LIST_HEAD(&rcd->qp_wait_list);
 226                 rcd->ppd = ppd;
 227                 rcd->dd = dd;
 228                 rcd->cnt = 1;
 229                 rcd->ctxt = ctxt;
 230                 dd->rcd[ctxt] = rcd;
 231                 rcd->numa_id = numa;
 232                 rcd->rcv_array_groups = dd->rcv_entries.ngroups;
 233
 234                 mutex_init(&rcd->exp_lock);
 235
 236                 /*
 237                  * Calculate the context's RcvArray entry starting point.
 238                  * We do this here because we have to take into account all
 239                  * the RcvArray entries that previous context would have
 240                  * taken and we have to account for any extra groups
 241                  * assigned to the kernel or user contexts.
 242                  */
 243                 if (ctxt < dd->first_user_ctxt) {
 244                         if (ctxt < kctxt_ngroups) {
 245                                 base = ctxt * (dd->rcv_entries.ngroups + 1);
 246                                 rcd->rcv_array_groups++;
 247                         } else
 248                                 base = kctxt_ngroups +
 249                                         (ctxt * dd->rcv_entries.ngroups);
 250                 } else {
 251                         u16 ct = ctxt - dd->first_user_ctxt;
 252
 253                         base = ((dd->n_krcv_queues * dd->rcv_entries.ngroups) +
 254                                 kctxt_ngroups);
 255                         if (ct < dd->rcv_entries.nctxt_extra) {
 256                                 base += ct * (dd->rcv_entries.ngroups + 1);
 257                                 rcd->rcv_array_groups++;
 258                         } else
 259                                 base += dd->rcv_entries.nctxt_extra +
 260                                         (ct * dd->rcv_entries.ngroups);
 261                 }
 262                 rcd->eager_base = base * dd->rcv_entries.group_size;
 263
 264                 /* Validate and initialize Rcv Hdr Q variables */
 265                 if (rcvhdrcnt % HDRQ_INCREMENT) {
 266                         dd_dev_err(dd,
 267                                    "ctxt%u: header queue count %d must be divisible by %lu\n",
 268                                    rcd->ctxt, rcvhdrcnt, HDRQ_INCREMENT);
 269                         goto bail;
 270                 }
 271                 rcd->rcvhdrq_cnt = rcvhdrcnt;
 272                 rcd->rcvhdrqentsize = hfi1_hdrq_entsize;
 273                 /*
 274                  * Simple Eager buffer allocation: we have already pre-allocated
 275                  * the number of RcvArray entry groups. Each ctxtdata structure
 276                  * holds the number of groups for that context.
 277                  *
 278                  * To follow CSR requirements and maintain cacheline alignment,
 279                  * make sure all sizes and bases are multiples of group_size.
 280                  *
 281                  * The expected entry count is what is left after assigning
 282                  * eager.
 283                  */
 284                 max_entries = rcd->rcv_array_groups *
 285                         dd->rcv_entries.group_size;
 286                 rcvtids = ((max_entries * hfi1_rcvarr_split) / 100);
 287                 rcd->egrbufs.count = round_down(rcvtids,
 288                                                 dd->rcv_entries.group_size);
 289                 if (rcd->egrbufs.count > MAX_EAGER_ENTRIES) {
 290                         dd_dev_err(dd, "ctxt%u: requested too many RcvArray entries.\n",
 291                                    rcd->ctxt);
 292                         rcd->egrbufs.count = MAX_EAGER_ENTRIES;
 293                 }
 294                 hfi1_cdbg(PROC,
 295                           "ctxt%u: max Eager buffer RcvArray entries: %u\n",
 296                           rcd->ctxt, rcd->egrbufs.count);
 297
 298                 /*
 299                  * Allocate array that will hold the eager buffer accounting
 300                  * data.
 301                  * This will allocate the maximum possible buffer count based
 302                  * on the value of the RcvArray split parameter.
 303                  * The resulting value will be rounded down to the closest
 304                  * multiple of dd->rcv_entries.group_size.
 305                  */
 306                 rcd->egrbufs.buffers = kcalloc(rcd->egrbufs.count,
 307                                                sizeof(*rcd->egrbufs.buffers),
 308                                                GFP_KERNEL);
 309                 if (!rcd->egrbufs.buffers)
 310                         goto bail;
 311                 rcd->egrbufs.rcvtids = kcalloc(rcd->egrbufs.count,
 312                                                sizeof(*rcd->egrbufs.rcvtids),
 313                                                GFP_KERNEL);
 314                 if (!rcd->egrbufs.rcvtids)
 315                         goto bail;
 316                 rcd->egrbufs.size = eager_buffer_size;
 317                 /*
 318                  * The size of the buffers programmed into the RcvArray
 319                  * entries needs to be big enough to handle the highest
 320                  * MTU supported.
 321                  */
 322                 if (rcd->egrbufs.size < hfi1_max_mtu) {
 323                         rcd->egrbufs.size = __roundup_pow_of_two(hfi1_max_mtu);
 324                         hfi1_cdbg(PROC,
 325                                   "ctxt%u: eager bufs size too small. Adjusting to %zu\n",
 326                                     rcd->ctxt, rcd->egrbufs.size);
 327                 }
 328                 rcd->egrbufs.rcvtid_size = HFI1_MAX_EAGER_BUFFER_SIZE;
 329
 330                 if (ctxt < dd->first_user_ctxt) { /* N/A for PSM contexts */
 331                         rcd->opstats = kzalloc(sizeof(*rcd->opstats),
 332                                 GFP_KERNEL);
 333                         if (!rcd->opstats)
 334                                 goto bail;
 335                 }
 336         }
 337         return rcd;
 338 bail:
 339         kfree(rcd->egrbufs.rcvtids);
 340         kfree(rcd->egrbufs.buffers);
 341         kfree(rcd);
 342         return NULL;
 343 }
 344
 345 /*
 346  * Convert a receive header entry size that to the encoding used in the CSR.
 347  *
 348  * Return a zero if the given size is invalid.
 349  */
 350 static inline u64 encode_rcv_header_entry_size(u16 size)
 351 {
 352         /* there are only 3 valid receive header entry sizes */
 353         if (size == 2)
 354                 return 1;
 355         if (size == 16)
 356                 return 2;
 357         else if (size == 32)
 358                 return 4;
 359         return 0; /* invalid */
 360 }
 361
 362 /*
 363  * Select the largest ccti value over all SLs to determine the intra-
 364  * packet gap for the link.
 365  *
 366  * called with cca_timer_lock held (to protect access to cca_timer
 367  * array), and rcu_read_lock() (to protect access to cc_state).
 368  */
 369 void set_link_ipg(struct hfi1_pportdata *ppd)
 370 {
 371         struct hfi1_devdata *dd = ppd->dd;
 372         struct cc_state *cc_state;
 373         int i;
 374         u16 cce, ccti_limit, max_ccti = 0;
 375         u16 shift, mult;
 376         u64 src;
 377         u32 current_egress_rate; /* Mbits /sec */
 378         u32 max_pkt_time;
 379         /*
 380          * max_pkt_time is the maximum packet egress time in units
 381          * of the fabric clock period 1/(805 MHz).
 382          */
 383
 384         cc_state = get_cc_state(ppd);
 385
 386         if (!cc_state)
 387                 /*
 388                  * This should _never_ happen - rcu_read_lock() is held,
 389                  * and set_link_ipg() should not be called if cc_state
 390                  * is NULL.
 391                  */
 392                 return;
 393
 394         for (i = 0; i < OPA_MAX_SLS; i++) {
 395                 u16 ccti = ppd->cca_timer[i].ccti;
 396
 397                 if (ccti > max_ccti)
 398                         max_ccti = ccti;
 399         }
 400
 401         ccti_limit = cc_state->cct.ccti_limit;
 402         if (max_ccti > ccti_limit)
 403                 max_ccti = ccti_limit;
 404
 405         cce = cc_state->cct.entries[max_ccti].entry;
 406         shift = (cce & 0xc000) >> 14;
 407         mult = (cce & 0x3fff);
 408
 409         current_egress_rate = active_egress_rate(ppd);
 410
 411         max_pkt_time = egress_cycles(ppd->ibmaxlen, current_egress_rate);
 412
 413         src = (max_pkt_time >> shift) * mult;
 414
 415         src &= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SMASK;
 416         src <<= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SHIFT;
 417
 418         write_csr(dd, SEND_STATIC_RATE_CONTROL, src);
 419 }
 420
 421 static enum hrtimer_restart cca_timer_fn(struct hrtimer *t)
 422 {
 423         struct cca_timer *cca_timer;
 424         struct hfi1_pportdata *ppd;
 425         int sl;
 426         u16 ccti_timer, ccti_min;
 427         struct cc_state *cc_state;
 428         unsigned long flags;
 429         enum hrtimer_restart ret = HRTIMER_NORESTART;
 430
 431         cca_timer = container_of(t, struct cca_timer, hrtimer);
 432         ppd = cca_timer->ppd;
 433         sl = cca_timer->sl;
 434
 435         rcu_read_lock();
 436
 437         cc_state = get_cc_state(ppd);
 438
 439         if (!cc_state) {
 440                 rcu_read_unlock();
 441                 return HRTIMER_NORESTART;
 442         }
 443
 444         /*
 445          * 1) decrement ccti for SL
 446          * 2) calculate IPG for link (set_link_ipg())
 447          * 3) restart timer, unless ccti is at min value
 448          */
 449
 450         ccti_min = cc_state->cong_setting.entries[sl].ccti_min;
 451         ccti_timer = cc_state->cong_setting.entries[sl].ccti_timer;
 452
 453         spin_lock_irqsave(&ppd->cca_timer_lock, flags);
 454
 455         if (cca_timer->ccti > ccti_min) {
 456                 cca_timer->ccti--;
 457                 set_link_ipg(ppd);
 458         }
 459
 460         if (cca_timer->ccti > ccti_min) {
 461                 unsigned long nsec = 1024 * ccti_timer;
 462                 /* ccti_timer is in units of 1.024 usec */
 463                 hrtimer_forward_now(t, ns_to_ktime(nsec));
 464                 ret = HRTIMER_RESTART;
 465         }
 466
 467         spin_unlock_irqrestore(&ppd->cca_timer_lock, flags);
 468         rcu_read_unlock();
 469         return ret;
 470 }
 471
 472 /*
 473  * Common code for initializing the physical port structure.
 474  */
 475 void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd,
 476                          struct hfi1_devdata *dd, u8 hw_pidx, u8 port)
 477 {
 478         int i, size;
 479         uint default_pkey_idx;
 480
 481         ppd->dd = dd;
 482         ppd->hw_pidx = hw_pidx;
 483         ppd->port = port; /* IB port number, not index */
 484
 485         default_pkey_idx = 1;
 486
 487         ppd->pkeys[default_pkey_idx] = DEFAULT_P_KEY;
 488         if (loopback) {
 489                 hfi1_early_err(&pdev->dev,
 490                                "Faking data partition 0x8001 in idx %u\n",
 491                                !default_pkey_idx);
 492                 ppd->pkeys[!default_pkey_idx] = 0x8001;
 493         }
 494
 495         INIT_WORK(&ppd->link_vc_work, handle_verify_cap);
 496         INIT_WORK(&ppd->link_up_work, handle_link_up);
 497         INIT_WORK(&ppd->link_down_work, handle_link_down);
 498         INIT_WORK(&ppd->freeze_work, handle_freeze);
 499         INIT_WORK(&ppd->link_downgrade_work, handle_link_downgrade);
 500         INIT_WORK(&ppd->sma_message_work, handle_sma_message);
 501         INIT_WORK(&ppd->link_bounce_work, handle_link_bounce);
 502         INIT_WORK(&ppd->linkstate_active_work, receive_interrupt_work);
 503         INIT_WORK(&ppd->qsfp_info.qsfp_work, qsfp_event);
 504
 505         mutex_init(&ppd->hls_lock);
 506         spin_lock_init(&ppd->sdma_alllock);
 507         spin_lock_init(&ppd->qsfp_info.qsfp_lock);
 508
 509         ppd->qsfp_info.ppd = ppd;
 510         ppd->sm_trap_qp = 0x0;
 511         ppd->sa_qp = 0x1;
 512
 513         ppd->hfi1_wq = NULL;
 514
 515         spin_lock_init(&ppd->cca_timer_lock);
 516
 517         for (i = 0; i < OPA_MAX_SLS; i++) {
 518                 hrtimer_init(&ppd->cca_timer[i].hrtimer, CLOCK_MONOTONIC,
 519                              HRTIMER_MODE_REL);
 520                 ppd->cca_timer[i].ppd = ppd;
 521                 ppd->cca_timer[i].sl = i;
 522                 ppd->cca_timer[i].ccti = 0;
 523                 ppd->cca_timer[i].hrtimer.function = cca_timer_fn;
 524         }
 525
 526         ppd->cc_max_table_entries = IB_CC_TABLE_CAP_DEFAULT;
 527
 528         spin_lock_init(&ppd->cc_state_lock);
 529         spin_lock_init(&ppd->cc_log_lock);
 530         size = sizeof(struct cc_state);
 531         RCU_INIT_POINTER(ppd->cc_state, kzalloc(size, GFP_KERNEL));
 532         if (!rcu_dereference(ppd->cc_state))
 533                 goto bail;
 534         return;
 535
 536 bail:
 537
 538         hfi1_early_err(&pdev->dev,
 539                        "Congestion Control Agent disabled for port %d\n", port);
 540 }
 541
 542 /*
 543  * Do initialization for device that is only needed on
 544  * first detect, not on resets.
 545  */
 546 static int loadtime_init(struct hfi1_devdata *dd)
 547 {
 548         return 0;
 549 }
 550
 551 /**
 552  * init_after_reset - re-initialize after a reset
 553  * @dd: the hfi1_ib device
 554  *
 555  * sanity check at least some of the values after reset, and
 556  * ensure no receive or transmit (explicitly, in case reset
 557  * failed
 558  */
 559 static int init_after_reset(struct hfi1_devdata *dd)
 560 {
 561         int i;
 562
 563         /*
 564          * Ensure chip does no sends or receives, tail updates, or
 565          * pioavail updates while we re-initialize.  This is mostly
 566          * for the driver data structures, not chip registers.
 567          */
 568         for (i = 0; i < dd->num_rcv_contexts; i++)
 569                 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS |
 570                                   HFI1_RCVCTRL_INTRAVAIL_DIS |
 571                                   HFI1_RCVCTRL_TAILUPD_DIS, i);
 572         pio_send_control(dd, PSC_GLOBAL_DISABLE);
 573         for (i = 0; i < dd->num_send_contexts; i++)
 574                 sc_disable(dd->send_contexts[i].sc);
 575
 576         return 0;
 577 }
 578
 579 static void enable_chip(struct hfi1_devdata *dd)
 580 {
 581         u32 rcvmask;
 582         u32 i;
 583
 584         /* enable PIO send */
 585         pio_send_control(dd, PSC_GLOBAL_ENABLE);
 586
 587         /*
 588          * Enable kernel ctxts' receive and receive interrupt.
 589          * Other ctxts done as user opens and initializes them.
 590          */
 591         for (i = 0; i < dd->first_user_ctxt; ++i) {
 592                 rcvmask = HFI1_RCVCTRL_CTXT_ENB | HFI1_RCVCTRL_INTRAVAIL_ENB;
 593                 rcvmask |= HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, DMA_RTAIL) ?
 594                         HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS;
 595                 if (!HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, MULTI_PKT_EGR))
 596                         rcvmask |= HFI1_RCVCTRL_ONE_PKT_EGR_ENB;
 597                 if (HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, NODROP_RHQ_FULL))
 598                         rcvmask |= HFI1_RCVCTRL_NO_RHQ_DROP_ENB;
 599                 if (HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, NODROP_EGR_FULL))
 600                         rcvmask |= HFI1_RCVCTRL_NO_EGR_DROP_ENB;
 601                 hfi1_rcvctrl(dd, rcvmask, i);
 602                 sc_enable(dd->rcd[i]->sc);
 603         }
 604 }
 605
 606 /**
 607  * create_workqueues - create per port workqueues
 608  * @dd: the hfi1_ib device
 609  */
 610 static int create_workqueues(struct hfi1_devdata *dd)
 611 {
 612         int pidx;
 613         struct hfi1_pportdata *ppd;
 614
 615         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 616                 ppd = dd->pport + pidx;
 617                 if (!ppd->hfi1_wq) {
 618                         ppd->hfi1_wq =
 619                                 alloc_workqueue(
 620                                     "hfi%d_%d",
 621                                     WQ_SYSFS | WQ_HIGHPRI | WQ_CPU_INTENSIVE,
 622                                     dd->num_sdma,
 623                                     dd->unit, pidx);
 624                         if (!ppd->hfi1_wq)
 625                                 goto wq_error;
 626                 }
 627         }
 628         return 0;
 629 wq_error:
 630         pr_err("alloc_workqueue failed for port %d\n", pidx + 1);
 631         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 632                 ppd = dd->pport + pidx;
 633                 if (ppd->hfi1_wq) {
 634                         destroy_workqueue(ppd->hfi1_wq);
 635                         ppd->hfi1_wq = NULL;
 636                 }
 637         }
 638         return -ENOMEM;
 639 }
 640
 641 /**
 642  * hfi1_init - do the actual initialization sequence on the chip
 643  * @dd: the hfi1_ib device
 644  * @reinit: re-initializing, so don't allocate new memory
 645  *
 646  * Do the actual initialization sequence on the chip.  This is done
 647  * both from the init routine called from the PCI infrastructure, and
 648  * when we reset the chip, or detect that it was reset internally,
 649  * or it's administratively re-enabled.
 650  *
 651  * Memory allocation here and in called routines is only done in
 652  * the first case (reinit == 0).  We have to be careful, because even
 653  * without memory allocation, we need to re-write all the chip registers
 654  * TIDs, etc. after the reset or enable has completed.
 655  */
 656 int hfi1_init(struct hfi1_devdata *dd, int reinit)
 657 {
 658         int ret = 0, pidx, lastfail = 0;
 659         unsigned i, len;
 660         struct hfi1_ctxtdata *rcd;
 661         struct hfi1_pportdata *ppd;
 662
 663         /* Set up recv low level handlers */
 664         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_EXPECTED] =
 665                                                 kdeth_process_expected;
 666         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_EAGER] =
 667                                                 kdeth_process_eager;
 668         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_IB] = process_receive_ib;
 669         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_ERROR] =
 670                                                 process_receive_error;
 671         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_BYPASS] =
 672                                                 process_receive_bypass;
 673         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID5] =
 674                                                 process_receive_invalid;
 675         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID6] =
 676                                                 process_receive_invalid;
 677         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID7] =
 678                                                 process_receive_invalid;
 679         dd->rhf_rcv_function_map = dd->normal_rhf_rcv_functions;
 680
 681         /* Set up send low level handlers */
 682         dd->process_pio_send = hfi1_verbs_send_pio;
 683         dd->process_dma_send = hfi1_verbs_send_dma;
 684         dd->pio_inline_send = pio_copy;
 685
 686         if (is_ax(dd)) {
 687                 atomic_set(&dd->drop_packet, DROP_PACKET_ON);
 688                 dd->do_drop = 1;
 689         } else {
 690                 atomic_set(&dd->drop_packet, DROP_PACKET_OFF);
 691                 dd->do_drop = 0;
 692         }
 693
 694         /* make sure the link is not "up" */
 695         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 696                 ppd = dd->pport + pidx;
 697                 ppd->linkup = 0;
 698         }
 699
 700         if (reinit)
 701                 ret = init_after_reset(dd);
 702         else
 703                 ret = loadtime_init(dd);
 704         if (ret)
 705                 goto done;
 706
 707         /* allocate dummy tail memory for all receive contexts */
 708         dd->rcvhdrtail_dummy_kvaddr = dma_zalloc_coherent(
 709                 &dd->pcidev->dev, sizeof(u64),
 710                 &dd->rcvhdrtail_dummy_physaddr,
 711                 GFP_KERNEL);
 712
 713         if (!dd->rcvhdrtail_dummy_kvaddr) {
 714                 dd_dev_err(dd, "cannot allocate dummy tail memory\n");
 715                 ret = -ENOMEM;
 716                 goto done;
 717         }
 718
 719         /* dd->rcd can be NULL if early initialization failed */
 720         for (i = 0; dd->rcd && i < dd->first_user_ctxt; ++i) {
 721                 /*
 722                  * Set up the (kernel) rcvhdr queue and egr TIDs.  If doing
 723                  * re-init, the simplest way to handle this is to free
 724                  * existing, and re-allocate.
 725                  * Need to re-create rest of ctxt 0 ctxtdata as well.
 726                  */
 727                 rcd = dd->rcd[i];
 728                 if (!rcd)
 729                         continue;
 730
 731                 rcd->do_interrupt = &handle_receive_interrupt;
 732
 733                 lastfail = hfi1_create_rcvhdrq(dd, rcd);
 734                 if (!lastfail)
 735                         lastfail = hfi1_setup_eagerbufs(rcd);
 736                 if (lastfail) {
 737                         dd_dev_err(dd,
 738                                    "failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n");
 739                         ret = lastfail;
 740                 }
 741         }
 742
 743         /* Allocate enough memory for user event notification. */
 744         len = PAGE_ALIGN(dd->chip_rcv_contexts * HFI1_MAX_SHARED_CTXTS *
 745                          sizeof(*dd->events));
 746         dd->events = vmalloc_user(len);
 747         if (!dd->events)
 748                 dd_dev_err(dd, "Failed to allocate user events page\n");
 749         /*
 750          * Allocate a page for device and port status.
 751          * Page will be shared amongst all user processes.
 752          */
 753         dd->status = vmalloc_user(PAGE_SIZE);
 754         if (!dd->status)
 755                 dd_dev_err(dd, "Failed to allocate dev status page\n");
 756         else
 757                 dd->freezelen = PAGE_SIZE - (sizeof(*dd->status) -
 758                                              sizeof(dd->status->freezemsg));
 759         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 760                 ppd = dd->pport + pidx;
 761                 if (dd->status)
 762                         /* Currently, we only have one port */
 763                         ppd->statusp = &dd->status->port;
 764
 765                 set_mtu(ppd);
 766         }
 767
 768         /* enable chip even if we have an error, so we can debug cause */
 769         enable_chip(dd);
 770
 771 done:
 772         /*
 773          * Set status even if port serdes is not initialized
 774          * so that diags will work.
 775          */
 776         if (dd->status)
 777                 dd->status->dev |= HFI1_STATUS_CHIP_PRESENT |
 778                         HFI1_STATUS_INITTED;
 779         if (!ret) {
 780                 /* enable all interrupts from the chip */
 781                 set_intr_state(dd, 1);
 782
 783                 /* chip is OK for user apps; mark it as initialized */
 784                 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 785                         ppd = dd->pport + pidx;
 786
 787                         /*
 788                          * start the serdes - must be after interrupts are
 789                          * enabled so we are notified when the link goes up
 790                          */
 791                         lastfail = bringup_serdes(ppd);
 792                         if (lastfail)
 793                                 dd_dev_info(dd,
 794                                             "Failed to bring up port %u\n",
 795                                             ppd->port);
 796
 797                         /*
 798                          * Set status even if port serdes is not initialized
 799                          * so that diags will work.
 800                          */
 801                         if (ppd->statusp)
 802                                 *ppd->statusp |= HFI1_STATUS_CHIP_PRESENT |
 803                                                         HFI1_STATUS_INITTED;
 804                         if (!ppd->link_speed_enabled)
 805                                 continue;
 806                 }
 807         }
 808
 809         /* if ret is non-zero, we probably should do some cleanup here... */
 810         return ret;
 811 }
 812
 813 static inline struct hfi1_devdata *__hfi1_lookup(int unit)
 814 {
 815         return idr_find(&hfi1_unit_table, unit);
 816 }
 817
 818 struct hfi1_devdata *hfi1_lookup(int unit)
 819 {
 820         struct hfi1_devdata *dd;
 821         unsigned long flags;
 822
 823         spin_lock_irqsave(&hfi1_devs_lock, flags);
 824         dd = __hfi1_lookup(unit);
 825         spin_unlock_irqrestore(&hfi1_devs_lock, flags);
 826
 827         return dd;
 828 }
 829
 830 /*
 831  * Stop the timers during unit shutdown, or after an error late
 832  * in initialization.
 833  */
 834 static void stop_timers(struct hfi1_devdata *dd)
 835 {
 836         struct hfi1_pportdata *ppd;
 837         int pidx;
 838
 839         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 840                 ppd = dd->pport + pidx;
 841                 if (ppd->led_override_timer.data) {
 842                         del_timer_sync(&ppd->led_override_timer);
 843                         atomic_set(&ppd->led_override_timer_active, 0);
 844                 }
 845         }
 846 }
 847
 848 /**
 849  * shutdown_device - shut down a device
 850  * @dd: the hfi1_ib device
 851  *
 852  * This is called to make the device quiet when we are about to
 853  * unload the driver, and also when the device is administratively
 854  * disabled.   It does not free any data structures.
 855  * Everything it does has to be setup again by hfi1_init(dd, 1)
 856  */
 857 static void shutdown_device(struct hfi1_devdata *dd)
 858 {
 859         struct hfi1_pportdata *ppd;
 860         unsigned pidx;
 861         int i;
 862
 863         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 864                 ppd = dd->pport + pidx;
 865
 866                 ppd->linkup = 0;
 867                 if (ppd->statusp)
 868                         *ppd->statusp &= ~(HFI1_STATUS_IB_CONF |
 869                                            HFI1_STATUS_IB_READY);
 870         }
 871         dd->flags &= ~HFI1_INITTED;
 872
 873         /* mask interrupts, but not errors */
 874         set_intr_state(dd, 0);
 875
 876         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 877                 ppd = dd->pport + pidx;
 878                 for (i = 0; i < dd->num_rcv_contexts; i++)
 879                         hfi1_rcvctrl(dd, HFI1_RCVCTRL_TAILUPD_DIS |
 880                                           HFI1_RCVCTRL_CTXT_DIS |
 881                                           HFI1_RCVCTRL_INTRAVAIL_DIS |
 882                                           HFI1_RCVCTRL_PKEY_DIS |
 883                                           HFI1_RCVCTRL_ONE_PKT_EGR_DIS, i);
 884                 /*
 885                  * Gracefully stop all sends allowing any in progress to
 886                  * trickle out first.
 887                  */
 888                 for (i = 0; i < dd->num_send_contexts; i++)
 889                         sc_flush(dd->send_contexts[i].sc);
 890         }
 891
 892         /*
 893          * Enough for anything that's going to trickle out to have actually
 894          * done so.
 895          */
 896         udelay(20);
 897
 898         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 899                 ppd = dd->pport + pidx;
 900
 901                 /* disable all contexts */
 902                 for (i = 0; i < dd->num_send_contexts; i++)
 903                         sc_disable(dd->send_contexts[i].sc);
 904                 /* disable the send device */
 905                 pio_send_control(dd, PSC_GLOBAL_DISABLE);
 906
 907                 shutdown_led_override(ppd);
 908
 909                 /*
 910                  * Clear SerdesEnable.
 911                  * We can't count on interrupts since we are stopping.
 912                  */
 913                 hfi1_quiet_serdes(ppd);
 914
 915                 if (ppd->hfi1_wq) {
 916                         destroy_workqueue(ppd->hfi1_wq);
 917                         ppd->hfi1_wq = NULL;
 918                 }
 919         }
 920         sdma_exit(dd);
 921 }
 922
 923 /**
 924  * hfi1_free_ctxtdata - free a context's allocated data
 925  * @dd: the hfi1_ib device
 926  * @rcd: the ctxtdata structure
 927  *
 928  * free up any allocated data for a context
 929  * This should not touch anything that would affect a simultaneous
 930  * re-allocation of context data, because it is called after hfi1_mutex
 931  * is released (and can be called from reinit as well).
 932  * It should never change any chip state, or global driver state.
 933  */
 934 void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
 935 {
 936         unsigned e;
 937
 938         if (!rcd)
 939                 return;
 940
 941         if (rcd->rcvhdrq) {
 942                 dma_free_coherent(&dd->pcidev->dev, rcd->rcvhdrq_size,
 943                                   rcd->rcvhdrq, rcd->rcvhdrq_phys);
 944                 rcd->rcvhdrq = NULL;
 945                 if (rcd->rcvhdrtail_kvaddr) {
 946                         dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
 947                                           (void *)rcd->rcvhdrtail_kvaddr,
 948                                           rcd->rcvhdrqtailaddr_phys);
 949                         rcd->rcvhdrtail_kvaddr = NULL;
 950                 }
 951         }
 952
 953         /* all the RcvArray entries should have been cleared by now */
 954         kfree(rcd->egrbufs.rcvtids);
 955
 956         for (e = 0; e < rcd->egrbufs.alloced; e++) {
 957                 if (rcd->egrbufs.buffers[e].phys)
 958                         dma_free_coherent(&dd->pcidev->dev,
 959                                           rcd->egrbufs.buffers[e].len,
 960                                           rcd->egrbufs.buffers[e].addr,
 961                                           rcd->egrbufs.buffers[e].phys);
 962         }
 963         kfree(rcd->egrbufs.buffers);
 964
 965         sc_free(rcd->sc);
 966         vfree(rcd->user_event_mask);
 967         vfree(rcd->subctxt_uregbase);
 968         vfree(rcd->subctxt_rcvegrbuf);
 969         vfree(rcd->subctxt_rcvhdr_base);
 970         kfree(rcd->opstats);
 971         kfree(rcd);
 972 }
 973
 974 /*
 975  * Release our hold on the shared asic data.  If we are the last one,
 976  * return the structure to be finalized outside the lock.  Must be
 977  * holding hfi1_devs_lock.
 978  */
 979 static struct hfi1_asic_data *release_asic_data(struct hfi1_devdata *dd)
 980 {
 981         struct hfi1_asic_data *ad;
 982         int other;
 983
 984         if (!dd->asic_data)
 985                 return NULL;
 986         dd->asic_data->dds[dd->hfi1_id] = NULL;
 987         other = dd->hfi1_id ? 0 : 1;
 988         ad = dd->asic_data;
 989         dd->asic_data = NULL;
 990         /* return NULL if the other dd still has a link */
 991         return ad->dds[other] ? NULL : ad;
 992 }
 993
 994 static void finalize_asic_data(struct hfi1_devdata *dd,
 995                                struct hfi1_asic_data *ad)
 996 {
 997         clean_up_i2c(dd, ad);
 998         kfree(ad);
 999 }
1000
1001 static void __hfi1_free_devdata(struct kobject *kobj)
1002 {
1003         struct hfi1_devdata *dd =
1004                 container_of(kobj, struct hfi1_devdata, kobj);
1005         struct hfi1_asic_data *ad;
1006         unsigned long flags;
1007
1008         spin_lock_irqsave(&hfi1_devs_lock, flags);
1009         idr_remove(&hfi1_unit_table, dd->unit);
1010         list_del(&dd->list);
1011         ad = release_asic_data(dd);
1012         spin_unlock_irqrestore(&hfi1_devs_lock, flags);
1013         if (ad)
1014                 finalize_asic_data(dd, ad);
1015         free_platform_config(dd);
1016         rcu_barrier(); /* wait for rcu callbacks to complete */
1017         free_percpu(dd->int_counter);
1018         free_percpu(dd->rcv_limit);
1019         free_percpu(dd->send_schedule);
1020         rvt_dealloc_device(&dd->verbs_dev.rdi);
1021 }
1022
1023 static struct kobj_type hfi1_devdata_type = {
1024         .release = __hfi1_free_devdata,
1025 };
1026
1027 void hfi1_free_devdata(struct hfi1_devdata *dd)
1028 {
1029         kobject_put(&dd->kobj);
1030 }
1031
1032 /*
1033  * Allocate our primary per-unit data structure.  Must be done via verbs
1034  * allocator, because the verbs cleanup process both does cleanup and
1035  * free of the data structure.
1036  * "extra" is for chip-specific data.
1037  *
1038  * Use the idr mechanism to get a unit number for this unit.
1039  */
1040 struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra)
1041 {
1042         unsigned long flags;
1043         struct hfi1_devdata *dd;
1044         int ret, nports;
1045
1046         /* extra is * number of ports */
1047         nports = extra / sizeof(struct hfi1_pportdata);
1048
1049         dd = (struct hfi1_devdata *)rvt_alloc_device(sizeof(*dd) + extra,
1050                                                      nports);
1051         if (!dd)
1052                 return ERR_PTR(-ENOMEM);
1053         dd->num_pports = nports;
1054         dd->pport = (struct hfi1_pportdata *)(dd + 1);
1055
1056         INIT_LIST_HEAD(&dd->list);
1057         idr_preload(GFP_KERNEL);
1058         spin_lock_irqsave(&hfi1_devs_lock, flags);
1059
1060         ret = idr_alloc(&hfi1_unit_table, dd, 0, 0, GFP_NOWAIT);
1061         if (ret >= 0) {
1062                 dd->unit = ret;
1063                 list_add(&dd->list, &hfi1_dev_list);
1064         }
1065
1066         spin_unlock_irqrestore(&hfi1_devs_lock, flags);
1067         idr_preload_end();
1068
1069         if (ret < 0) {
1070                 hfi1_early_err(&pdev->dev,
1071                                "Could not allocate unit ID: error %d\n", -ret);
1072                 goto bail;
1073         }
1074         /*
1075          * Initialize all locks for the device. This needs to be as early as
1076          * possible so locks are usable.
1077          */
1078         spin_lock_init(&dd->sc_lock);
1079         spin_lock_init(&dd->sendctrl_lock);
1080         spin_lock_init(&dd->rcvctrl_lock);
1081         spin_lock_init(&dd->uctxt_lock);
1082         spin_lock_init(&dd->hfi1_diag_trans_lock);
1083         spin_lock_init(&dd->sc_init_lock);
1084         spin_lock_init(&dd->dc8051_lock);
1085         spin_lock_init(&dd->dc8051_memlock);
1086         seqlock_init(&dd->sc2vl_lock);
1087         spin_lock_init(&dd->sde_map_lock);
1088         spin_lock_init(&dd->pio_map_lock);
1089         init_waitqueue_head(&dd->event_queue);
1090
1091         dd->int_counter = alloc_percpu(u64);
1092         if (!dd->int_counter) {
1093                 ret = -ENOMEM;
1094                 hfi1_early_err(&pdev->dev,
1095                                "Could not allocate per-cpu int_counter\n");
1096                 goto bail;
1097         }
1098
1099         dd->rcv_limit = alloc_percpu(u64);
1100         if (!dd->rcv_limit) {
1101                 ret = -ENOMEM;
1102                 hfi1_early_err(&pdev->dev,
1103                                "Could not allocate per-cpu rcv_limit\n");
1104                 goto bail;
1105         }
1106
1107         dd->send_schedule = alloc_percpu(u64);
1108         if (!dd->send_schedule) {
1109                 ret = -ENOMEM;
1110                 hfi1_early_err(&pdev->dev,
1111                                "Could not allocate per-cpu int_counter\n");
1112                 goto bail;
1113         }
1114
1115         if (!hfi1_cpulist_count) {
1116                 u32 count = num_online_cpus();
1117
1118                 hfi1_cpulist = kcalloc(BITS_TO_LONGS(count), sizeof(long),
1119                                        GFP_KERNEL);
1120                 if (hfi1_cpulist)
1121                         hfi1_cpulist_count = count;
1122                 else
1123                         hfi1_early_err(
1124                         &pdev->dev,
1125                         "Could not alloc cpulist info, cpu affinity might be wrong\n");
1126         }
1127         kobject_init(&dd->kobj, &hfi1_devdata_type);
1128         return dd;
1129
1130 bail:
1131         if (!list_empty(&dd->list))
1132                 list_del_init(&dd->list);
1133         rvt_dealloc_device(&dd->verbs_dev.rdi);
1134         return ERR_PTR(ret);
1135 }
1136
1137 /*
1138  * Called from freeze mode handlers, and from PCI error
1139  * reporting code.  Should be paranoid about state of
1140  * system and data structures.
1141  */
1142 void hfi1_disable_after_error(struct hfi1_devdata *dd)
1143 {
1144         if (dd->flags & HFI1_INITTED) {
1145                 u32 pidx;
1146
1147                 dd->flags &= ~HFI1_INITTED;
1148                 if (dd->pport)
1149                         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1150                                 struct hfi1_pportdata *ppd;
1151
1152                                 ppd = dd->pport + pidx;
1153                                 if (dd->flags & HFI1_PRESENT)
1154                                         set_link_state(ppd, HLS_DN_DISABLE);
1155
1156                                 if (ppd->statusp)
1157                                         *ppd->statusp &= ~HFI1_STATUS_IB_READY;
1158                         }
1159         }
1160
1161         /*
1162          * Mark as having had an error for driver, and also
1163          * for /sys and status word mapped to user programs.
1164          * This marks unit as not usable, until reset.
1165          */
1166         if (dd->status)
1167                 dd->status->dev |= HFI1_STATUS_HWERROR;
1168 }
1169
1170 static void remove_one(struct pci_dev *);
1171 static int init_one(struct pci_dev *, const struct pci_device_id *);
1172
1173 #define DRIVER_LOAD_MSG "Intel " DRIVER_NAME " loaded: "
1174 #define PFX DRIVER_NAME ": "
1175
1176 const struct pci_device_id hfi1_pci_tbl[] = {
1177         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL0) },
1178         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL1) },
1179         { 0, }
1180 };
1181
1182 MODULE_DEVICE_TABLE(pci, hfi1_pci_tbl);
1183
1184 static struct pci_driver hfi1_pci_driver = {
1185         .name = DRIVER_NAME,
1186         .probe = init_one,
1187         .remove = remove_one,
1188         .id_table = hfi1_pci_tbl,
1189         .err_handler = &hfi1_pci_err_handler,
1190 };
1191
1192 static void __init compute_krcvqs(void)
1193 {
1194         int i;
1195
1196         for (i = 0; i < krcvqsset; i++)
1197                 n_krcvqs += krcvqs[i];
1198 }
1199
1200 /*
1201  * Do all the generic driver unit- and chip-independent memory
1202  * allocation and initialization.
1203  */
1204 static int __init hfi1_mod_init(void)
1205 {
1206         int ret;
1207
1208         ret = dev_init();
1209         if (ret)
1210                 goto bail;
1211
1212         ret = node_affinity_init();
1213         if (ret)
1214                 goto bail;
1215
1216         /* validate max MTU before any devices start */
1217         if (!valid_opa_max_mtu(hfi1_max_mtu)) {
1218                 pr_err("Invalid max_mtu 0x%x, using 0x%x instead\n",
1219                        hfi1_max_mtu, HFI1_DEFAULT_MAX_MTU);
1220                 hfi1_max_mtu = HFI1_DEFAULT_MAX_MTU;
1221         }
1222         /* valid CUs run from 1-128 in powers of 2 */
1223         if (hfi1_cu > 128 || !is_power_of_2(hfi1_cu))
1224                 hfi1_cu = 1;
1225         /* valid credit return threshold is 0-100, variable is unsigned */
1226         if (user_credit_return_threshold > 100)
1227                 user_credit_return_threshold = 100;
1228
1229         compute_krcvqs();
1230         /*
1231          * sanitize receive interrupt count, time must wait until after
1232          * the hardware type is known
1233          */
1234         if (rcv_intr_count > RCV_HDR_HEAD_COUNTER_MASK)
1235                 rcv_intr_count = RCV_HDR_HEAD_COUNTER_MASK;
1236         /* reject invalid combinations */
1237         if (rcv_intr_count == 0 && rcv_intr_timeout == 0) {
1238                 pr_err("Invalid mode: both receive interrupt count and available timeout are zero - setting interrupt count to 1\n");
1239                 rcv_intr_count = 1;
1240         }
1241         if (rcv_intr_count > 1 && rcv_intr_timeout == 0) {
1242                 /*
1243                  * Avoid indefinite packet delivery by requiring a timeout
1244                  * if count is > 1.
1245                  */
1246                 pr_err("Invalid mode: receive interrupt count greater than 1 and available timeout is zero - setting available timeout to 1\n");
1247                 rcv_intr_timeout = 1;
1248         }
1249         if (rcv_intr_dynamic && !(rcv_intr_count > 1 && rcv_intr_timeout > 0)) {
1250                 /*
1251                  * The dynamic algorithm expects a non-zero timeout
1252                  * and a count > 1.
1253                  */
1254                 pr_err("Invalid mode: dynamic receive interrupt mitigation with invalid count and timeout - turning dynamic off\n");
1255                 rcv_intr_dynamic = 0;
1256         }
1257
1258         /* sanitize link CRC options */
1259         link_crc_mask &= SUPPORTED_CRCS;
1260
1261         /*
1262          * These must be called before the driver is registered with
1263          * the PCI subsystem.
1264          */
1265         idr_init(&hfi1_unit_table);
1266
1267         hfi1_dbg_init();
1268         ret = hfi1_wss_init();
1269         if (ret < 0)
1270                 goto bail_wss;
1271         ret = pci_register_driver(&hfi1_pci_driver);
1272         if (ret < 0) {
1273                 pr_err("Unable to register driver: error %d\n", -ret);
1274                 goto bail_dev;
1275         }
1276         goto bail; /* all OK */
1277
1278 bail_dev:
1279         hfi1_wss_exit();
1280 bail_wss:
1281         hfi1_dbg_exit();
1282         idr_destroy(&hfi1_unit_table);
1283         dev_cleanup();
1284 bail:
1285         return ret;
1286 }
1287
1288 module_init(hfi1_mod_init);
1289
1290 /*
1291  * Do the non-unit driver cleanup, memory free, etc. at unload.
1292  */
1293 static void __exit hfi1_mod_cleanup(void)
1294 {
1295         pci_unregister_driver(&hfi1_pci_driver);
1296         node_affinity_destroy();
1297         hfi1_wss_exit();
1298         hfi1_dbg_exit();
1299         hfi1_cpulist_count = 0;
1300         kfree(hfi1_cpulist);
1301
1302         idr_destroy(&hfi1_unit_table);
1303         dispose_firmware();     /* asymmetric with obtain_firmware() */
1304         dev_cleanup();
1305 }
1306
1307 module_exit(hfi1_mod_cleanup);
1308
1309 /* this can only be called after a successful initialization */
1310 static void cleanup_device_data(struct hfi1_devdata *dd)
1311 {
1312         int ctxt;
1313         int pidx;
1314         struct hfi1_ctxtdata **tmp;
1315         unsigned long flags;
1316
1317         /* users can't do anything more with chip */
1318         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1319                 struct hfi1_pportdata *ppd = &dd->pport[pidx];
1320                 struct cc_state *cc_state;
1321                 int i;
1322
1323                 if (ppd->statusp)
1324                         *ppd->statusp &= ~HFI1_STATUS_CHIP_PRESENT;
1325
1326                 for (i = 0; i < OPA_MAX_SLS; i++)
1327                         hrtimer_cancel(&ppd->cca_timer[i].hrtimer);
1328
1329                 spin_lock(&ppd->cc_state_lock);
1330                 cc_state = get_cc_state(ppd);
1331                 RCU_INIT_POINTER(ppd->cc_state, NULL);
1332                 spin_unlock(&ppd->cc_state_lock);
1333
1334                 if (cc_state)
1335                         call_rcu(&cc_state->rcu, cc_state_reclaim);
1336         }
1337
1338         free_credit_return(dd);
1339
1340         /*
1341          * Free any resources still in use (usually just kernel contexts)
1342          * at unload; we do for ctxtcnt, because that's what we allocate.
1343          * We acquire lock to be really paranoid that rcd isn't being
1344          * accessed from some interrupt-related code (that should not happen,
1345          * but best to be sure).
1346          */
1347         spin_lock_irqsave(&dd->uctxt_lock, flags);
1348         tmp = dd->rcd;
1349         dd->rcd = NULL;
1350         spin_unlock_irqrestore(&dd->uctxt_lock, flags);
1351
1352         if (dd->rcvhdrtail_dummy_kvaddr) {
1353                 dma_free_coherent(&dd->pcidev->dev, sizeof(u64),
1354                                   (void *)dd->rcvhdrtail_dummy_kvaddr,
1355                                   dd->rcvhdrtail_dummy_physaddr);
1356                 dd->rcvhdrtail_dummy_kvaddr = NULL;
1357         }
1358
1359         for (ctxt = 0; tmp && ctxt < dd->num_rcv_contexts; ctxt++) {
1360                 struct hfi1_ctxtdata *rcd = tmp[ctxt];
1361
1362                 tmp[ctxt] = NULL; /* debugging paranoia */
1363                 if (rcd) {
1364                         hfi1_clear_tids(rcd);
1365                         hfi1_free_ctxtdata(dd, rcd);
1366                 }
1367         }
1368         kfree(tmp);
1369         free_pio_map(dd);
1370         /* must follow rcv context free - need to remove rcv's hooks */
1371         for (ctxt = 0; ctxt < dd->num_send_contexts; ctxt++)
1372                 sc_free(dd->send_contexts[ctxt].sc);
1373         dd->num_send_contexts = 0;
1374         kfree(dd->send_contexts);
1375         dd->send_contexts = NULL;
1376         kfree(dd->hw_to_sw);
1377         dd->hw_to_sw = NULL;
1378         kfree(dd->boardname);
1379         vfree(dd->events);
1380         vfree(dd->status);
1381 }
1382
1383 /*
1384  * Clean up on unit shutdown, or error during unit load after
1385  * successful initialization.
1386  */
1387 static void postinit_cleanup(struct hfi1_devdata *dd)
1388 {
1389         hfi1_start_cleanup(dd);
1390
1391         hfi1_pcie_ddcleanup(dd);
1392         hfi1_pcie_cleanup(dd->pcidev);
1393
1394         cleanup_device_data(dd);
1395
1396         hfi1_free_devdata(dd);
1397 }
1398
1399 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1400 {
1401         int ret = 0, j, pidx, initfail;
1402         struct hfi1_devdata *dd = ERR_PTR(-EINVAL);
1403         struct hfi1_pportdata *ppd;
1404
1405         /* First, lock the non-writable module parameters */
1406         HFI1_CAP_LOCK();
1407
1408         /* Validate some global module parameters */
1409         if (rcvhdrcnt <= HFI1_MIN_HDRQ_EGRBUF_CNT) {
1410                 hfi1_early_err(&pdev->dev, "Header queue  count too small\n");
1411                 ret = -EINVAL;
1412                 goto bail;
1413         }
1414         if (rcvhdrcnt > HFI1_MAX_HDRQ_EGRBUF_CNT) {
1415                 hfi1_early_err(&pdev->dev,
1416                                "Receive header queue count cannot be greater than %u\n",
1417                                HFI1_MAX_HDRQ_EGRBUF_CNT);
1418                 ret = -EINVAL;
1419                 goto bail;
1420         }
1421         /* use the encoding function as a sanitization check */
1422         if (!encode_rcv_header_entry_size(hfi1_hdrq_entsize)) {
1423                 hfi1_early_err(&pdev->dev, "Invalid HdrQ Entry size %u\n",
1424                                hfi1_hdrq_entsize);
1425                 ret = -EINVAL;
1426                 goto bail;
1427         }
1428
1429         /* The receive eager buffer size must be set before the receive
1430          * contexts are created.
1431          *
1432          * Set the eager buffer size.  Validate that it falls in a range
1433          * allowed by the hardware - all powers of 2 between the min and
1434          * max.  The maximum valid MTU is within the eager buffer range
1435          * so we do not need to cap the max_mtu by an eager buffer size
1436          * setting.
1437          */
1438         if (eager_buffer_size) {
1439                 if (!is_power_of_2(eager_buffer_size))
1440                         eager_buffer_size =
1441                                 roundup_pow_of_two(eager_buffer_size);
1442                 eager_buffer_size =
1443                         clamp_val(eager_buffer_size,
1444                                   MIN_EAGER_BUFFER * 8,
1445                                   MAX_EAGER_BUFFER_TOTAL);
1446                 hfi1_early_info(&pdev->dev, "Eager buffer size %u\n",
1447                                 eager_buffer_size);
1448         } else {
1449                 hfi1_early_err(&pdev->dev, "Invalid Eager buffer size of 0\n");
1450                 ret = -EINVAL;
1451                 goto bail;
1452         }
1453
1454         /* restrict value of hfi1_rcvarr_split */
1455         hfi1_rcvarr_split = clamp_val(hfi1_rcvarr_split, 0, 100);
1456
1457         ret = hfi1_pcie_init(pdev, ent);
1458         if (ret)
1459                 goto bail;
1460
1461         /*
1462          * Do device-specific initialization, function table setup, dd
1463          * allocation, etc.
1464          */
1465         switch (ent->device) {
1466         case PCI_DEVICE_ID_INTEL0:
1467         case PCI_DEVICE_ID_INTEL1:
1468                 dd = hfi1_init_dd(pdev, ent);
1469                 break;
1470         default:
1471                 hfi1_early_err(&pdev->dev,
1472                                "Failing on unknown Intel deviceid 0x%x\n",
1473                                ent->device);
1474                 ret = -ENODEV;
1475         }
1476
1477         if (IS_ERR(dd))
1478                 ret = PTR_ERR(dd);
1479         if (ret)
1480                 goto clean_bail; /* error already printed */
1481
1482         ret = create_workqueues(dd);
1483         if (ret)
1484                 goto clean_bail;
1485
1486         /* do the generic initialization */
1487         initfail = hfi1_init(dd, 0);
1488
1489         ret = hfi1_register_ib_device(dd);
1490
1491         /*
1492          * Now ready for use.  this should be cleared whenever we
1493          * detect a reset, or initiate one.  If earlier failure,
1494          * we still create devices, so diags, etc. can be used
1495          * to determine cause of problem.
1496          */
1497         if (!initfail && !ret) {
1498                 dd->flags |= HFI1_INITTED;
1499                 /* create debufs files after init and ib register */
1500                 hfi1_dbg_ibdev_init(&dd->verbs_dev);
1501         }
1502
1503         j = hfi1_device_create(dd);
1504         if (j)
1505                 dd_dev_err(dd, "Failed to create /dev devices: %d\n", -j);
1506
1507         if (initfail || ret) {
1508                 stop_timers(dd);
1509                 flush_workqueue(ib_wq);
1510                 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1511                         hfi1_quiet_serdes(dd->pport + pidx);
1512                         ppd = dd->pport + pidx;
1513                         if (ppd->hfi1_wq) {
1514                                 destroy_workqueue(ppd->hfi1_wq);
1515                                 ppd->hfi1_wq = NULL;
1516                         }
1517                 }
1518                 if (!j)
1519                         hfi1_device_remove(dd);
1520                 if (!ret)
1521                         hfi1_unregister_ib_device(dd);
1522                 postinit_cleanup(dd);
1523                 if (initfail)
1524                         ret = initfail;
1525                 goto bail;      /* everything already cleaned */
1526         }
1527
1528         sdma_start(dd);
1529
1530         return 0;
1531
1532 clean_bail:
1533         hfi1_pcie_cleanup(pdev);
1534 bail:
1535         return ret;
1536 }
1537
1538 static void remove_one(struct pci_dev *pdev)
1539 {
1540         struct hfi1_devdata *dd = pci_get_drvdata(pdev);
1541
1542         /* close debugfs files before ib unregister */
1543         hfi1_dbg_ibdev_exit(&dd->verbs_dev);
1544         /* unregister from IB core */
1545         hfi1_unregister_ib_device(dd);
1546
1547         /*
1548          * Disable the IB link, disable interrupts on the device,
1549          * clear dma engines, etc.
1550          */
1551         shutdown_device(dd);
1552
1553         stop_timers(dd);
1554
1555         /* wait until all of our (qsfp) queue_work() calls complete */
1556         flush_workqueue(ib_wq);
1557
1558         hfi1_device_remove(dd);
1559
1560         postinit_cleanup(dd);
1561 }
1562
1563 /**
1564  * hfi1_create_rcvhdrq - create a receive header queue
1565  * @dd: the hfi1_ib device
1566  * @rcd: the context data
1567  *
1568  * This must be contiguous memory (from an i/o perspective), and must be
1569  * DMA'able (which means for some systems, it will go through an IOMMU,
1570  * or be forced into a low address range).
1571  */
1572 int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
1573 {
1574         unsigned amt;
1575         u64 reg;
1576
1577         if (!rcd->rcvhdrq) {
1578                 dma_addr_t phys_hdrqtail;
1579                 gfp_t gfp_flags;
1580
1581                 /*
1582                  * rcvhdrqentsize is in DWs, so we have to convert to bytes
1583                  * (* sizeof(u32)).
1584                  */
1585                 amt = PAGE_ALIGN(rcd->rcvhdrq_cnt * rcd->rcvhdrqentsize *
1586                                  sizeof(u32));
1587
1588                 gfp_flags = (rcd->ctxt >= dd->first_user_ctxt) ?
1589                         GFP_USER : GFP_KERNEL;
1590                 rcd->rcvhdrq = dma_zalloc_coherent(
1591                         &dd->pcidev->dev, amt, &rcd->rcvhdrq_phys,
1592                         gfp_flags | __GFP_COMP);
1593
1594                 if (!rcd->rcvhdrq) {
1595                         dd_dev_err(dd,
1596                                    "attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n",
1597                                    amt, rcd->ctxt);
1598                         goto bail;
1599                 }
1600
1601                 if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL)) {
1602                         rcd->rcvhdrtail_kvaddr = dma_zalloc_coherent(
1603                                 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail,
1604                                 gfp_flags);
1605                         if (!rcd->rcvhdrtail_kvaddr)
1606                                 goto bail_free;
1607                         rcd->rcvhdrqtailaddr_phys = phys_hdrqtail;
1608                 }
1609
1610                 rcd->rcvhdrq_size = amt;
1611         }
1612         /*
1613          * These values are per-context:
1614          *      RcvHdrCnt
1615          *      RcvHdrEntSize
1616          *      RcvHdrSize
1617          */
1618         reg = ((u64)(rcd->rcvhdrq_cnt >> HDRQ_SIZE_SHIFT)
1619                         & RCV_HDR_CNT_CNT_MASK)
1620                 << RCV_HDR_CNT_CNT_SHIFT;
1621         write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_CNT, reg);
1622         reg = (encode_rcv_header_entry_size(rcd->rcvhdrqentsize)
1623                         & RCV_HDR_ENT_SIZE_ENT_SIZE_MASK)
1624                 << RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT;
1625         write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_ENT_SIZE, reg);
1626         reg = (dd->rcvhdrsize & RCV_HDR_SIZE_HDR_SIZE_MASK)
1627                 << RCV_HDR_SIZE_HDR_SIZE_SHIFT;
1628         write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_SIZE, reg);
1629
1630         /*
1631          * Program dummy tail address for every receive context
1632          * before enabling any receive context
1633          */
1634         write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_TAIL_ADDR,
1635                         dd->rcvhdrtail_dummy_physaddr);
1636
1637         return 0;
1638
1639 bail_free:
1640         dd_dev_err(dd,
1641                    "attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n",
1642                    rcd->ctxt);
1643         vfree(rcd->user_event_mask);
1644         rcd->user_event_mask = NULL;
1645         dma_free_coherent(&dd->pcidev->dev, amt, rcd->rcvhdrq,
1646                           rcd->rcvhdrq_phys);
1647         rcd->rcvhdrq = NULL;
1648 bail:
1649         return -ENOMEM;
1650 }
1651
1652 /**
1653  * allocate eager buffers, both kernel and user contexts.
1654  * @rcd: the context we are setting up.
1655  *
1656  * Allocate the eager TID buffers and program them into hip.
1657  * They are no longer completely contiguous, we do multiple allocation
1658  * calls.  Otherwise we get the OOM code involved, by asking for too
1659  * much per call, with disastrous results on some kernels.
1660  */
1661 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd)
1662 {
1663         struct hfi1_devdata *dd = rcd->dd;
1664         u32 max_entries, egrtop, alloced_bytes = 0, idx = 0;
1665         gfp_t gfp_flags;
1666         u16 order;
1667         int ret = 0;
1668         u16 round_mtu = roundup_pow_of_two(hfi1_max_mtu);
1669
1670         /*
1671          * GFP_USER, but without GFP_FS, so buffer cache can be
1672          * coalesced (we hope); otherwise, even at order 4,
1673          * heavy filesystem activity makes these fail, and we can
1674          * use compound pages.
1675          */
1676         gfp_flags = __GFP_RECLAIM | __GFP_IO | __GFP_COMP;
1677
1678         /*
1679          * The minimum size of the eager buffers is a groups of MTU-sized
1680          * buffers.
1681          * The global eager_buffer_size parameter is checked against the
1682          * theoretical lower limit of the value. Here, we check against the
1683          * MTU.
1684          */
1685         if (rcd->egrbufs.size < (round_mtu * dd->rcv_entries.group_size))
1686                 rcd->egrbufs.size = round_mtu * dd->rcv_entries.group_size;
1687         /*
1688          * If using one-pkt-per-egr-buffer, lower the eager buffer
1689          * size to the max MTU (page-aligned).
1690          */
1691         if (!HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR))
1692                 rcd->egrbufs.rcvtid_size = round_mtu;
1693
1694         /*
1695          * Eager buffers sizes of 1MB or less require smaller TID sizes
1696          * to satisfy the "multiple of 8 RcvArray entries" requirement.
1697          */
1698         if (rcd->egrbufs.size <= (1 << 20))
1699                 rcd->egrbufs.rcvtid_size = max((unsigned long)round_mtu,
1700                         rounddown_pow_of_two(rcd->egrbufs.size / 8));
1701
1702         while (alloced_bytes < rcd->egrbufs.size &&
1703                rcd->egrbufs.alloced < rcd->egrbufs.count) {
1704                 rcd->egrbufs.buffers[idx].addr =
1705                         dma_zalloc_coherent(&dd->pcidev->dev,
1706                                             rcd->egrbufs.rcvtid_size,
1707                                             &rcd->egrbufs.buffers[idx].phys,
1708                                             gfp_flags);
1709                 if (rcd->egrbufs.buffers[idx].addr) {
1710                         rcd->egrbufs.buffers[idx].len =
1711                                 rcd->egrbufs.rcvtid_size;
1712                         rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].addr =
1713                                 rcd->egrbufs.buffers[idx].addr;
1714                         rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].phys =
1715                                 rcd->egrbufs.buffers[idx].phys;
1716                         rcd->egrbufs.alloced++;
1717                         alloced_bytes += rcd->egrbufs.rcvtid_size;
1718                         idx++;
1719                 } else {
1720                         u32 new_size, i, j;
1721                         u64 offset = 0;
1722
1723                         /*
1724                          * Fail the eager buffer allocation if:
1725                          *   - we are already using the lowest acceptable size
1726                          *   - we are using one-pkt-per-egr-buffer (this implies
1727                          *     that we are accepting only one size)
1728                          */
1729                         if (rcd->egrbufs.rcvtid_size == round_mtu ||
1730                             !HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR)) {
1731                                 dd_dev_err(dd, "ctxt%u: Failed to allocate eager buffers\n",
1732                                            rcd->ctxt);
1733                                 goto bail_rcvegrbuf_phys;
1734                         }
1735
1736                         new_size = rcd->egrbufs.rcvtid_size / 2;
1737
1738                         /*
1739                          * If the first attempt to allocate memory failed, don't
1740                          * fail everything but continue with the next lower
1741                          * size.
1742                          */
1743                         if (idx == 0) {
1744                                 rcd->egrbufs.rcvtid_size = new_size;
1745                                 continue;
1746                         }
1747
1748                         /*
1749                          * Re-partition already allocated buffers to a smaller
1750                          * size.
1751                          */
1752                         rcd->egrbufs.alloced = 0;
1753                         for (i = 0, j = 0, offset = 0; j < idx; i++) {
1754                                 if (i >= rcd->egrbufs.count)
1755                                         break;
1756                                 rcd->egrbufs.rcvtids[i].phys =
1757                                         rcd->egrbufs.buffers[j].phys + offset;
1758                                 rcd->egrbufs.rcvtids[i].addr =
1759                                         rcd->egrbufs.buffers[j].addr + offset;
1760                                 rcd->egrbufs.alloced++;
1761                                 if ((rcd->egrbufs.buffers[j].phys + offset +
1762                                      new_size) ==
1763                                     (rcd->egrbufs.buffers[j].phys +
1764                                      rcd->egrbufs.buffers[j].len)) {
1765                                         j++;
1766                                         offset = 0;
1767                                 } else {
1768                                         offset += new_size;
1769                                 }
1770                         }
1771                         rcd->egrbufs.rcvtid_size = new_size;
1772                 }
1773         }
1774         rcd->egrbufs.numbufs = idx;
1775         rcd->egrbufs.size = alloced_bytes;
1776
1777         hfi1_cdbg(PROC,
1778                   "ctxt%u: Alloced %u rcv tid entries @ %uKB, total %zuKB\n",
1779                   rcd->ctxt, rcd->egrbufs.alloced, rcd->egrbufs.rcvtid_size,
1780                   rcd->egrbufs.size);
1781
1782         /*
1783          * Set the contexts rcv array head update threshold to the closest
1784          * power of 2 (so we can use a mask instead of modulo) below half
1785          * the allocated entries.
1786          */
1787         rcd->egrbufs.threshold =
1788                 rounddown_pow_of_two(rcd->egrbufs.alloced / 2);
1789         /*
1790          * Compute the expected RcvArray entry base. This is done after
1791          * allocating the eager buffers in order to maximize the
1792          * expected RcvArray entries for the context.
1793          */
1794         max_entries = rcd->rcv_array_groups * dd->rcv_entries.group_size;
1795         egrtop = roundup(rcd->egrbufs.alloced, dd->rcv_entries.group_size);
1796         rcd->expected_count = max_entries - egrtop;
1797         if (rcd->expected_count > MAX_TID_PAIR_ENTRIES * 2)
1798                 rcd->expected_count = MAX_TID_PAIR_ENTRIES * 2;
1799
1800         rcd->expected_base = rcd->eager_base + egrtop;
1801         hfi1_cdbg(PROC, "ctxt%u: eager:%u, exp:%u, egrbase:%u, expbase:%u\n",
1802                   rcd->ctxt, rcd->egrbufs.alloced, rcd->expected_count,
1803                   rcd->eager_base, rcd->expected_base);
1804
1805         if (!hfi1_rcvbuf_validate(rcd->egrbufs.rcvtid_size, PT_EAGER, &order)) {
1806                 hfi1_cdbg(PROC,
1807                           "ctxt%u: current Eager buffer size is invalid %u\n",
1808                           rcd->ctxt, rcd->egrbufs.rcvtid_size);
1809                 ret = -EINVAL;
1810                 goto bail;
1811         }
1812
1813         for (idx = 0; idx < rcd->egrbufs.alloced; idx++) {
1814                 hfi1_put_tid(dd, rcd->eager_base + idx, PT_EAGER,
1815                              rcd->egrbufs.rcvtids[idx].phys, order);
1816                 cond_resched();
1817         }
1818         goto bail;
1819
1820 bail_rcvegrbuf_phys:
1821         for (idx = 0; idx < rcd->egrbufs.alloced &&
1822              rcd->egrbufs.buffers[idx].addr;
1823              idx++) {
1824                 dma_free_coherent(&dd->pcidev->dev,
1825                                   rcd->egrbufs.buffers[idx].len,
1826                                   rcd->egrbufs.buffers[idx].addr,
1827                                   rcd->egrbufs.buffers[idx].phys);
1828                 rcd->egrbufs.buffers[idx].addr = NULL;
1829                 rcd->egrbufs.buffers[idx].phys = 0;
1830                 rcd->egrbufs.buffers[idx].len = 0;
1831         }
1832 bail:
1833         return ret;
1834 }