drivers/infiniband/hw/i40iw/i40iw_osdep.h

   1 /*******************************************************************************
   2 *
   3 * Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
   4 *
   5 * This software is available to you under a choice of one of two
   6 * licenses.  You may choose to be licensed under the terms of the GNU
   7 * General Public License (GPL) Version 2, available from the file
   8 * COPYING in the main directory of this source tree, or the
   9 * OpenFabrics.org BSD license below:
  10 *
  11 *   Redistribution and use in source and binary forms, with or
  12 *   without modification, are permitted provided that the following
  13 *   conditions are met:
  14 *
  15 *    - Redistributions of source code must retain the above
  16 *       copyright notice, this list of conditions and the following
  17 *       disclaimer.
  18 *
  19 *    - Redistributions in binary form must reproduce the above
  20 *       copyright notice, this list of conditions and the following
  21 *       disclaimer in the documentation and/or other materials
  22 *       provided with the distribution.
  23 *
  24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31 * SOFTWARE.
  32 *
  33 *******************************************************************************/
  34
  35 #ifndef I40IW_OSDEP_H
  36 #define I40IW_OSDEP_H
  37
  38 #include <linux/kernel.h>
  39 #include <linux/string.h>
  40 #include <linux/bitops.h>
  41 #include <net/tcp.h>
  42 /* get readq/writeq support for 32 bit kernels, use the low-first version */
  43 #include <linux/io-64-nonatomic-lo-hi.h>
  44
  45 #define STATS_TIMER_DELAY 1000
  46
  47 static inline void set_64bit_val(u64 *wqe_words, u32 byte_index, u64 value)
  48 {
  49         wqe_words[byte_index >> 3] = value;
  50 }
  51
  52 /**
  53  * set_32bit_val - set 32 value to hw wqe
  54  * @wqe_words: wqe addr to write
  55  * @byte_index: index in wqe
  56  * @value: value to write
  57  **/
  58 static inline void set_32bit_val(u32 *wqe_words, u32 byte_index, u32 value)
  59 {
  60         wqe_words[byte_index >> 2] = value;
  61 }
  62
  63 /**
  64  * get_64bit_val - read 64 bit value from wqe
  65  * @wqe_words: wqe addr
  66  * @byte_index: index to read from
  67  * @value: read value
  68  **/
  69 static inline void get_64bit_val(u64 *wqe_words, u32 byte_index, u64 *value)
  70 {
  71         *value = wqe_words[byte_index >> 3];
  72 }
  73
  74 /**
  75  * get_32bit_val - read 32 bit value from wqe
  76  * @wqe_words: wqe addr
  77  * @byte_index: index to reaad from
  78  * @value: return 32 bit value
  79  **/
  80 static inline void get_32bit_val(u32 *wqe_words, u32 byte_index, u32 *value)
  81 {
  82         *value = wqe_words[byte_index >> 2];
  83 }
  84
  85 struct i40iw_dma_mem {
  86         void *va;
  87         dma_addr_t pa;
  88         u32 size;
  89 } __packed;
  90
  91 struct i40iw_virt_mem {
  92         void *va;
  93         u32 size;
  94 } __packed;
  95
  96 #define i40iw_debug(h, m, s, ...)                               \
  97 do {                                                            \
  98         if (((m) & (h)->debug_mask))                            \
  99                 pr_info("i40iw " s, ##__VA_ARGS__);             \
 100 } while (0)
 101
 102 #define i40iw_flush(a)          readl((a)->hw_addr + I40E_GLGEN_STAT)
 103
 104 #define I40E_GLHMC_VFSDCMD(_i)  (0x000C8000 + ((_i) * 4)) \
 105                                 /* _i=0...31 */
 106 #define I40E_GLHMC_VFSDCMD_MAX_INDEX    31
 107 #define I40E_GLHMC_VFSDCMD_PMSDIDX_SHIFT  0
 108 #define I40E_GLHMC_VFSDCMD_PMSDIDX_MASK  (0xFFF \
 109                                           << I40E_GLHMC_VFSDCMD_PMSDIDX_SHIFT)
 110 #define I40E_GLHMC_VFSDCMD_PF_SHIFT       16
 111 #define I40E_GLHMC_VFSDCMD_PF_MASK        (0xF << I40E_GLHMC_VFSDCMD_PF_SHIFT)
 112 #define I40E_GLHMC_VFSDCMD_VF_SHIFT       20
 113 #define I40E_GLHMC_VFSDCMD_VF_MASK        (0x1FF << I40E_GLHMC_VFSDCMD_VF_SHIFT)
 114 #define I40E_GLHMC_VFSDCMD_PMF_TYPE_SHIFT 29
 115 #define I40E_GLHMC_VFSDCMD_PMF_TYPE_MASK  (0x3 \
 116                                            << I40E_GLHMC_VFSDCMD_PMF_TYPE_SHIFT)
 117 #define I40E_GLHMC_VFSDCMD_PMSDWR_SHIFT   31
 118 #define I40E_GLHMC_VFSDCMD_PMSDWR_MASK  (0x1 << I40E_GLHMC_VFSDCMD_PMSDWR_SHIFT)
 119
 120 #define I40E_GLHMC_VFSDDATAHIGH(_i)     (0x000C8200 + ((_i) * 4)) \
 121                                 /* _i=0...31 */
 122 #define I40E_GLHMC_VFSDDATAHIGH_MAX_INDEX       31
 123 #define I40E_GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_SHIFT 0
 124 #define I40E_GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_MASK  (0xFFFFFFFF \
 125                         << I40E_GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_SHIFT)
 126
 127 #define I40E_GLHMC_VFSDDATALOW(_i)      (0x000C8100 + ((_i) * 4)) \
 128                                 /* _i=0...31 */
 129 #define I40E_GLHMC_VFSDDATALOW_MAX_INDEX        31
 130 #define I40E_GLHMC_VFSDDATALOW_PMSDVALID_SHIFT   0
 131 #define I40E_GLHMC_VFSDDATALOW_PMSDVALID_MASK  (0x1 \
 132                         << I40E_GLHMC_VFSDDATALOW_PMSDVALID_SHIFT)
 133 #define I40E_GLHMC_VFSDDATALOW_PMSDTYPE_SHIFT    1
 134 #define I40E_GLHMC_VFSDDATALOW_PMSDTYPE_MASK  (0x1 \
 135                         << I40E_GLHMC_VFSDDATALOW_PMSDTYPE_SHIFT)
 136 #define I40E_GLHMC_VFSDDATALOW_PMSDBPCOUNT_SHIFT 2
 137 #define I40E_GLHMC_VFSDDATALOW_PMSDBPCOUNT_MASK  (0x3FF \
 138                         << I40E_GLHMC_VFSDDATALOW_PMSDBPCOUNT_SHIFT)
 139 #define I40E_GLHMC_VFSDDATALOW_PMSDDATALOW_SHIFT 12
 140 #define I40E_GLHMC_VFSDDATALOW_PMSDDATALOW_MASK  (0xFFFFF \
 141                         << I40E_GLHMC_VFSDDATALOW_PMSDDATALOW_SHIFT)
 142
 143 #define I40E_GLPE_FWLDSTATUS                     0x0000D200
 144 #define I40E_GLPE_FWLDSTATUS_LOAD_REQUESTED_SHIFT 0
 145 #define I40E_GLPE_FWLDSTATUS_LOAD_REQUESTED_MASK  (0x1 \
 146                         << I40E_GLPE_FWLDSTATUS_LOAD_REQUESTED_SHIFT)
 147 #define I40E_GLPE_FWLDSTATUS_DONE_SHIFT           1
 148 #define I40E_GLPE_FWLDSTATUS_DONE_MASK  (0x1 << I40E_GLPE_FWLDSTATUS_DONE_SHIFT)
 149 #define I40E_GLPE_FWLDSTATUS_CQP_FAIL_SHIFT       2
 150 #define I40E_GLPE_FWLDSTATUS_CQP_FAIL_MASK  (0x1 \
 151                          << I40E_GLPE_FWLDSTATUS_CQP_FAIL_SHIFT)
 152 #define I40E_GLPE_FWLDSTATUS_TEP_FAIL_SHIFT       3
 153 #define I40E_GLPE_FWLDSTATUS_TEP_FAIL_MASK  (0x1 \
 154                          << I40E_GLPE_FWLDSTATUS_TEP_FAIL_SHIFT)
 155 #define I40E_GLPE_FWLDSTATUS_OOP_FAIL_SHIFT       4
 156 #define I40E_GLPE_FWLDSTATUS_OOP_FAIL_MASK  (0x1 \
 157                          << I40E_GLPE_FWLDSTATUS_OOP_FAIL_SHIFT)
 158
 159 struct i40iw_sc_dev;
 160 struct i40iw_sc_qp;
 161 struct i40iw_puda_buf;
 162 struct i40iw_puda_completion_info;
 163 struct i40iw_update_sds_info;
 164 struct i40iw_hmc_fcn_info;
 165 struct i40iw_virtchnl_work_info;
 166 struct i40iw_manage_vf_pble_info;
 167 struct i40iw_device;
 168 struct i40iw_hmc_info;
 169 struct i40iw_hw;
 170
 171 u8 __iomem *i40iw_get_hw_addr(void *dev);
 172 void i40iw_ieq_mpa_crc_ae(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp);
 173 enum i40iw_status_code i40iw_vf_wait_vchnl_resp(struct i40iw_sc_dev *dev);
 174 enum i40iw_status_code i40iw_ieq_check_mpacrc(struct hash_desc *desc, void *addr,
 175                                               u32 length, u32 value);
 176 struct i40iw_sc_qp *i40iw_ieq_get_qp(struct i40iw_sc_dev *dev, struct i40iw_puda_buf *buf);
 177 void i40iw_ieq_update_tcpip_info(struct i40iw_puda_buf *buf, u16 length, u32 seqnum);
 178 void i40iw_free_hash_desc(struct hash_desc *);
 179 enum i40iw_status_code i40iw_init_hash_desc(struct hash_desc *);
 180 enum i40iw_status_code i40iw_puda_get_tcpip_info(struct i40iw_puda_completion_info *info,
 181                                                  struct i40iw_puda_buf *buf);
 182 enum i40iw_status_code i40iw_cqp_sds_cmd(struct i40iw_sc_dev *dev,
 183                                          struct i40iw_update_sds_info *info);
 184 enum i40iw_status_code i40iw_cqp_manage_hmc_fcn_cmd(struct i40iw_sc_dev *dev,
 185                                                     struct i40iw_hmc_fcn_info *hmcfcninfo);
 186 enum i40iw_status_code i40iw_cqp_query_fpm_values_cmd(struct i40iw_sc_dev *dev,
 187                                                       struct i40iw_dma_mem *values_mem,
 188                                                       u8 hmc_fn_id);
 189 enum i40iw_status_code i40iw_cqp_commit_fpm_values_cmd(struct i40iw_sc_dev *dev,
 190                                                        struct i40iw_dma_mem *values_mem,
 191                                                        u8 hmc_fn_id);
 192 enum i40iw_status_code i40iw_alloc_query_fpm_buf(struct i40iw_sc_dev *dev,
 193                                                  struct i40iw_dma_mem *mem);
 194 enum i40iw_status_code i40iw_cqp_manage_vf_pble_bp(struct i40iw_sc_dev *dev,
 195                                                    struct i40iw_manage_vf_pble_info *info);
 196 void i40iw_cqp_spawn_worker(struct i40iw_sc_dev *dev,
 197                             struct i40iw_virtchnl_work_info *work_info, u32 iw_vf_idx);
 198 void *i40iw_remove_head(struct list_head *list);
 199
 200 void i40iw_term_modify_qp(struct i40iw_sc_qp *qp, u8 next_state, u8 term, u8 term_len);
 201 void i40iw_terminate_done(struct i40iw_sc_qp *qp, int timeout_occurred);
 202 void i40iw_terminate_start_timer(struct i40iw_sc_qp *qp);
 203 void i40iw_terminate_del_timer(struct i40iw_sc_qp *qp);
 204
 205 enum i40iw_status_code i40iw_hw_manage_vf_pble_bp(struct i40iw_device *iwdev,
 206                                                   struct i40iw_manage_vf_pble_info *info,
 207                                                   bool wait);
 208 struct i40iw_dev_pestat;
 209 void i40iw_hw_stats_start_timer(struct i40iw_sc_dev *);
 210 void i40iw_hw_stats_del_timer(struct i40iw_sc_dev *);
 211 #define i40iw_mmiowb() mmiowb()
 212 void i40iw_wr32(struct i40iw_hw *hw, u32 reg, u32 value);
 213 u32  i40iw_rd32(struct i40iw_hw *hw, u32 reg);
 214 #endif                          /* _I40IW_OSDEP_H_ */