drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/log2.h>
  35 #include <linux/slab.h>
  36 #include <linux/netdevice.h>
  37
  38 #include <rdma/ib_cache.h>
  39 #include <rdma/ib_pack.h>
  40 #include <rdma/ib_addr.h>
  41 #include <rdma/ib_mad.h>
  42
  43 #include <linux/mlx4/qp.h>
  44
  45 #include "mlx4_ib.h"
  46 #include "user.h"
  47
  48 enum {
  49         MLX4_IB_ACK_REQ_FREQ    = 8,
  50 };
  51
  52 enum {
  53         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  54         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  55         MLX4_IB_LINK_TYPE_IB            = 0,
  56         MLX4_IB_LINK_TYPE_ETH           = 1
  57 };
  58
  59 enum {
  60         /*
  61          * Largest possible UD header: send with GRH and immediate
  62          * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
  63          * tag.  (LRH would only use 8 bytes, so Ethernet is the
  64          * biggest case)
  65          */
  66         MLX4_IB_UD_HEADER_SIZE          = 82,
  67         MLX4_IB_LSO_HEADER_SPARE        = 128,
  68 };
  69
  70 enum {
  71         MLX4_IB_IBOE_ETHERTYPE          = 0x8915
  72 };
  73
  74 struct mlx4_ib_sqp {
  75         struct mlx4_ib_qp       qp;
  76         int                     pkey_index;
  77         u32                     qkey;
  78         u32                     send_psn;
  79         struct ib_ud_header     ud_header;
  80         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  81 };
  82
  83 enum {
  84         MLX4_IB_MIN_SQ_STRIDE   = 6,
  85         MLX4_IB_CACHE_LINE_SIZE = 64,
  86 };
  87
  88 enum {
  89         MLX4_RAW_QP_MTU         = 7,
  90         MLX4_RAW_QP_MSGMAX      = 31,
  91 };
  92
  93 static const __be32 mlx4_ib_opcode[] = {
  94         [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
  95         [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
  96         [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
  97         [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
  98         [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
  99         [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
 100         [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
 101         [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
 102         [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
 103         [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
 104         [IB_WR_FAST_REG_MR]                     = cpu_to_be32(MLX4_OPCODE_FMR),
 105         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
 106         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
 107         [IB_WR_BIND_MW]                         = cpu_to_be32(MLX4_OPCODE_BIND_MW),
 108 };
 109
 110 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
 111 {
 112         return container_of(mqp, struct mlx4_ib_sqp, qp);
 113 }
 114
 115 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 116 {
 117         if (!mlx4_is_master(dev->dev))
 118                 return 0;
 119
 120         return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
 121                qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
 122                 8 * MLX4_MFUNC_MAX;
 123 }
 124
 125 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 126 {
 127         int proxy_sqp = 0;
 128         int real_sqp = 0;
 129         int i;
 130         /* PPF or Native -- real SQP */
 131         real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 132                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 133                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
 134         if (real_sqp)
 135                 return 1;
 136         /* VF or PF -- proxy SQP */
 137         if (mlx4_is_mfunc(dev->dev)) {
 138                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 139                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
 140                             qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
 141                                 proxy_sqp = 1;
 142                                 break;
 143                         }
 144                 }
 145         }
 146         return proxy_sqp;
 147 }
 148
 149 /* used for INIT/CLOSE port logic */
 150 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 151 {
 152         int proxy_qp0 = 0;
 153         int real_qp0 = 0;
 154         int i;
 155         /* PPF or Native -- real QP0 */
 156         real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 157                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 158                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
 159         if (real_qp0)
 160                 return 1;
 161         /* VF or PF -- proxy QP0 */
 162         if (mlx4_is_mfunc(dev->dev)) {
 163                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 164                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
 165                                 proxy_qp0 = 1;
 166                                 break;
 167                         }
 168                 }
 169         }
 170         return proxy_qp0;
 171 }
 172
 173 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 174 {
 175         return mlx4_buf_offset(&qp->buf, offset);
 176 }
 177
 178 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 179 {
 180         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 181 }
 182
 183 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 184 {
 185         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 186 }
 187
 188 /*
 189  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 190  * first four bytes of every 64 byte chunk with
 191  *     0x7FFFFFF | (invalid_ownership_value << 31).
 192  *
 193  * When the max work request size is less than or equal to the WQE
 194  * basic block size, as an optimization, we can stamp all WQEs with
 195  * 0xffffffff, and skip the very first chunk of each WQE.
 196  */
 197 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 198 {
 199         __be32 *wqe;
 200         int i;
 201         int s;
 202         int ind;
 203         void *buf;
 204         __be32 stamp;
 205         struct mlx4_wqe_ctrl_seg *ctrl;
 206
 207         if (qp->sq_max_wqes_per_wr > 1) {
 208                 s = roundup(size, 1U << qp->sq.wqe_shift);
 209                 for (i = 0; i < s; i += 64) {
 210                         ind = (i >> qp->sq.wqe_shift) + n;
 211                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 212                                                        cpu_to_be32(0xffffffff);
 213                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 214                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 215                         *wqe = stamp;
 216                 }
 217         } else {
 218                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 219                 s = (ctrl->fence_size & 0x3f) << 4;
 220                 for (i = 64; i < s; i += 64) {
 221                         wqe = buf + i;
 222                         *wqe = cpu_to_be32(0xffffffff);
 223                 }
 224         }
 225 }
 226
 227 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 228 {
 229         struct mlx4_wqe_ctrl_seg *ctrl;
 230         struct mlx4_wqe_inline_seg *inl;
 231         void *wqe;
 232         int s;
 233
 234         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 235         s = sizeof(struct mlx4_wqe_ctrl_seg);
 236
 237         if (qp->ibqp.qp_type == IB_QPT_UD) {
 238                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 239                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 240                 memset(dgram, 0, sizeof *dgram);
 241                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 242                 s += sizeof(struct mlx4_wqe_datagram_seg);
 243         }
 244
 245         /* Pad the remainder of the WQE with an inline data segment. */
 246         if (size > s) {
 247                 inl = wqe + s;
 248                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 249         }
 250         ctrl->srcrb_flags = 0;
 251         ctrl->fence_size = size / 16;
 252         /*
 253          * Make sure descriptor is fully written before setting ownership bit
 254          * (because HW can start executing as soon as we do).
 255          */
 256         wmb();
 257
 258         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 259                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 260
 261         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 262 }
 263
 264 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 265 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 266 {
 267         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 268         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 269                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 270                 ind += s;
 271         }
 272         return ind;
 273 }
 274
 275 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 276 {
 277         struct ib_event event;
 278         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 279
 280         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 281                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 282
 283         if (ibqp->event_handler) {
 284                 event.device     = ibqp->device;
 285                 event.element.qp = ibqp;
 286                 switch (type) {
 287                 case MLX4_EVENT_TYPE_PATH_MIG:
 288                         event.event = IB_EVENT_PATH_MIG;
 289                         break;
 290                 case MLX4_EVENT_TYPE_COMM_EST:
 291                         event.event = IB_EVENT_COMM_EST;
 292                         break;
 293                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 294                         event.event = IB_EVENT_SQ_DRAINED;
 295                         break;
 296                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 297                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 298                         break;
 299                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 300                         event.event = IB_EVENT_QP_FATAL;
 301                         break;
 302                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 303                         event.event = IB_EVENT_PATH_MIG_ERR;
 304                         break;
 305                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 306                         event.event = IB_EVENT_QP_REQ_ERR;
 307                         break;
 308                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 309                         event.event = IB_EVENT_QP_ACCESS_ERR;
 310                         break;
 311                 default:
 312                         pr_warn("Unexpected event type %d "
 313                                "on QP %06x\n", type, qp->qpn);
 314                         return;
 315                 }
 316
 317                 ibqp->event_handler(&event, ibqp->qp_context);
 318         }
 319 }
 320
 321 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
 322 {
 323         /*
 324          * UD WQEs must have a datagram segment.
 325          * RC and UC WQEs might have a remote address segment.
 326          * MLX WQEs need two extra inline data segments (for the UD
 327          * header and space for the ICRC).
 328          */
 329         switch (type) {
 330         case MLX4_IB_QPT_UD:
 331                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 332                         sizeof (struct mlx4_wqe_datagram_seg) +
 333                         ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
 334         case MLX4_IB_QPT_PROXY_SMI_OWNER:
 335         case MLX4_IB_QPT_PROXY_SMI:
 336         case MLX4_IB_QPT_PROXY_GSI:
 337                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 338                         sizeof (struct mlx4_wqe_datagram_seg) + 64;
 339         case MLX4_IB_QPT_TUN_SMI_OWNER:
 340         case MLX4_IB_QPT_TUN_GSI:
 341                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 342                         sizeof (struct mlx4_wqe_datagram_seg);
 343
 344         case MLX4_IB_QPT_UC:
 345                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 346                         sizeof (struct mlx4_wqe_raddr_seg);
 347         case MLX4_IB_QPT_RC:
 348                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 349                         sizeof (struct mlx4_wqe_atomic_seg) +
 350                         sizeof (struct mlx4_wqe_raddr_seg);
 351         case MLX4_IB_QPT_SMI:
 352         case MLX4_IB_QPT_GSI:
 353                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 354                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 355                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 356                                            MLX4_INLINE_ALIGN) *
 357                               sizeof (struct mlx4_wqe_inline_seg),
 358                               sizeof (struct mlx4_wqe_data_seg)) +
 359                         ALIGN(4 +
 360                               sizeof (struct mlx4_wqe_inline_seg),
 361                               sizeof (struct mlx4_wqe_data_seg));
 362         default:
 363                 return sizeof (struct mlx4_wqe_ctrl_seg);
 364         }
 365 }
 366
 367 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 368                        int is_user, int has_rq, struct mlx4_ib_qp *qp)
 369 {
 370         /* Sanity check RQ size before proceeding */
 371         if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
 372             cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
 373                 return -EINVAL;
 374
 375         if (!has_rq) {
 376                 if (cap->max_recv_wr)
 377                         return -EINVAL;
 378
 379                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 380         } else {
 381                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 382                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 383                         return -EINVAL;
 384
 385                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 386                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 387                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 388         }
 389
 390         /* leave userspace return values as they were, so as not to break ABI */
 391         if (is_user) {
 392                 cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 393                 cap->max_recv_sge = qp->rq.max_gs;
 394         } else {
 395                 cap->max_recv_wr  = qp->rq.max_post =
 396                         min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
 397                 cap->max_recv_sge = min(qp->rq.max_gs,
 398                                         min(dev->dev->caps.max_sq_sg,
 399                                             dev->dev->caps.max_rq_sg));
 400         }
 401
 402         return 0;
 403 }
 404
 405 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 406                               enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
 407 {
 408         int s;
 409
 410         /* Sanity check SQ size before proceeding */
 411         if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
 412             cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
 413             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 414             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 415                 return -EINVAL;
 416
 417         /*
 418          * For MLX transport we need 2 extra S/G entries:
 419          * one for the header and one for the checksum at the end
 420          */
 421         if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
 422              type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
 423             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 424                 return -EINVAL;
 425
 426         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 427                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 428                 send_wqe_overhead(type, qp->flags);
 429
 430         if (s > dev->dev->caps.max_sq_desc_sz)
 431                 return -EINVAL;
 432
 433         /*
 434          * Hermon supports shrinking WQEs, such that a single work
 435          * request can include multiple units of 1 << wqe_shift.  This
 436          * way, work requests can differ in size, and do not have to
 437          * be a power of 2 in size, saving memory and speeding up send
 438          * WR posting.  Unfortunately, if we do this then the
 439          * wqe_index field in CQEs can't be used to look up the WR ID
 440          * anymore, so we do this only if selective signaling is off.
 441          *
 442          * Further, on 32-bit platforms, we can't use vmap() to make
 443          * the QP buffer virtually contiguous.  Thus we have to use
 444          * constant-sized WRs to make sure a WR is always fully within
 445          * a single page-sized chunk.
 446          *
 447          * Finally, we use NOP work requests to pad the end of the
 448          * work queue, to avoid wrap-around in the middle of WR.  We
 449          * set NEC bit to avoid getting completions with error for
 450          * these NOP WRs, but since NEC is only supported starting
 451          * with firmware 2.2.232, we use constant-sized WRs for older
 452          * firmware.
 453          *
 454          * And, since MLX QPs only support SEND, we use constant-sized
 455          * WRs in this case.
 456          *
 457          * We look for the smallest value of wqe_shift such that the
 458          * resulting number of wqes does not exceed device
 459          * capabilities.
 460          *
 461          * We set WQE size to at least 64 bytes, this way stamping
 462          * invalidates each WQE.
 463          */
 464         if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 465             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 466             type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
 467             !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
 468                       MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
 469                 qp->sq.wqe_shift = ilog2(64);
 470         else
 471                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 472
 473         for (;;) {
 474                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 475
 476                 /*
 477                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 478                  * allow HW to prefetch.
 479                  */
 480                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 481                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 482                                                     qp->sq_max_wqes_per_wr +
 483                                                     qp->sq_spare_wqes);
 484
 485                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 486                         break;
 487
 488                 if (qp->sq_max_wqes_per_wr <= 1)
 489                         return -EINVAL;
 490
 491                 ++qp->sq.wqe_shift;
 492         }
 493
 494         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 495                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 496                          send_wqe_overhead(type, qp->flags)) /
 497                 sizeof (struct mlx4_wqe_data_seg);
 498
 499         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 500                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 501         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 502                 qp->rq.offset = 0;
 503                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 504         } else {
 505                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 506                 qp->sq.offset = 0;
 507         }
 508
 509         cap->max_send_wr  = qp->sq.max_post =
 510                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 511         cap->max_send_sge = min(qp->sq.max_gs,
 512                                 min(dev->dev->caps.max_sq_sg,
 513                                     dev->dev->caps.max_rq_sg));
 514         /* We don't support inline sends for kernel QPs (yet) */
 515         cap->max_inline_data = 0;
 516
 517         return 0;
 518 }
 519
 520 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 521                             struct mlx4_ib_qp *qp,
 522                             struct mlx4_ib_create_qp *ucmd)
 523 {
 524         /* Sanity check SQ size before proceeding */
 525         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 526             ucmd->log_sq_stride >
 527                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 528             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 529                 return -EINVAL;
 530
 531         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 532         qp->sq.wqe_shift = ucmd->log_sq_stride;
 533
 534         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 535                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 536
 537         return 0;
 538 }
 539
 540 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 541 {
 542         int i;
 543
 544         qp->sqp_proxy_rcv =
 545                 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
 546                         GFP_KERNEL);
 547         if (!qp->sqp_proxy_rcv)
 548                 return -ENOMEM;
 549         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 550                 qp->sqp_proxy_rcv[i].addr =
 551                         kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
 552                                 GFP_KERNEL);
 553                 if (!qp->sqp_proxy_rcv[i].addr)
 554                         goto err;
 555                 qp->sqp_proxy_rcv[i].map =
 556                         ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
 557                                           sizeof (struct mlx4_ib_proxy_sqp_hdr),
 558                                           DMA_FROM_DEVICE);
 559         }
 560         return 0;
 561
 562 err:
 563         while (i > 0) {
 564                 --i;
 565                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 566                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 567                                     DMA_FROM_DEVICE);
 568                 kfree(qp->sqp_proxy_rcv[i].addr);
 569         }
 570         kfree(qp->sqp_proxy_rcv);
 571         qp->sqp_proxy_rcv = NULL;
 572         return -ENOMEM;
 573 }
 574
 575 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 576 {
 577         int i;
 578
 579         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 580                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 581                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 582                                     DMA_FROM_DEVICE);
 583                 kfree(qp->sqp_proxy_rcv[i].addr);
 584         }
 585         kfree(qp->sqp_proxy_rcv);
 586 }
 587
 588 static int qp_has_rq(struct ib_qp_init_attr *attr)
 589 {
 590         if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
 591                 return 0;
 592
 593         return !attr->srq;
 594 }
 595
 596 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 597                             struct ib_qp_init_attr *init_attr,
 598                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp)
 599 {
 600         int qpn;
 601         int err;
 602         struct mlx4_ib_sqp *sqp;
 603         struct mlx4_ib_qp *qp;
 604         enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
 605
 606         /* When tunneling special qps, we use a plain UD qp */
 607         if (sqpn) {
 608                 if (mlx4_is_mfunc(dev->dev) &&
 609                     (!mlx4_is_master(dev->dev) ||
 610                      !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
 611                         if (init_attr->qp_type == IB_QPT_GSI)
 612                                 qp_type = MLX4_IB_QPT_PROXY_GSI;
 613                         else if (mlx4_is_master(dev->dev))
 614                                 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
 615                         else
 616                                 qp_type = MLX4_IB_QPT_PROXY_SMI;
 617                 }
 618                 qpn = sqpn;
 619                 /* add extra sg entry for tunneling */
 620                 init_attr->cap.max_recv_sge++;
 621         } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
 622                 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
 623                         container_of(init_attr,
 624                                      struct mlx4_ib_qp_tunnel_init_attr, init_attr);
 625                 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
 626                      tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
 627                     !mlx4_is_master(dev->dev))
 628                         return -EINVAL;
 629                 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
 630                         qp_type = MLX4_IB_QPT_TUN_GSI;
 631                 else if (tnl_init->slave == mlx4_master_func_num(dev->dev))
 632                         qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
 633                 else
 634                         qp_type = MLX4_IB_QPT_TUN_SMI;
 635                 /* we are definitely in the PPF here, since we are creating
 636                  * tunnel QPs. base_tunnel_sqpn is therefore valid. */
 637                 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
 638                         + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
 639                 sqpn = qpn;
 640         }
 641
 642         if (!*caller_qp) {
 643                 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
 644                     (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
 645                                 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
 646                         sqp = kzalloc(sizeof (struct mlx4_ib_sqp), GFP_KERNEL);
 647                         if (!sqp)
 648                                 return -ENOMEM;
 649                         qp = &sqp->qp;
 650                 } else {
 651                         qp = kzalloc(sizeof (struct mlx4_ib_qp), GFP_KERNEL);
 652                         if (!qp)
 653                                 return -ENOMEM;
 654                 }
 655         } else
 656                 qp = *caller_qp;
 657
 658         qp->mlx4_ib_qp_type = qp_type;
 659
 660         mutex_init(&qp->mutex);
 661         spin_lock_init(&qp->sq.lock);
 662         spin_lock_init(&qp->rq.lock);
 663         INIT_LIST_HEAD(&qp->gid_list);
 664         INIT_LIST_HEAD(&qp->steering_rules);
 665
 666         qp->state        = IB_QPS_RESET;
 667         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 668                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 669
 670         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
 671         if (err)
 672                 goto err;
 673
 674         if (pd->uobject) {
 675                 struct mlx4_ib_create_qp ucmd;
 676
 677                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 678                         err = -EFAULT;
 679                         goto err;
 680                 }
 681
 682                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 683
 684                 err = set_user_sq_size(dev, qp, &ucmd);
 685                 if (err)
 686                         goto err;
 687
 688                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 689                                        qp->buf_size, 0, 0);
 690                 if (IS_ERR(qp->umem)) {
 691                         err = PTR_ERR(qp->umem);
 692                         goto err;
 693                 }
 694
 695                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 696                                     ilog2(qp->umem->page_size), &qp->mtt);
 697                 if (err)
 698                         goto err_buf;
 699
 700                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 701                 if (err)
 702                         goto err_mtt;
 703
 704                 if (qp_has_rq(init_attr)) {
 705                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 706                                                   ucmd.db_addr, &qp->db);
 707                         if (err)
 708                                 goto err_mtt;
 709                 }
 710         } else {
 711                 qp->sq_no_prefetch = 0;
 712
 713                 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
 714                         qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 715
 716                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 717                         qp->flags |= MLX4_IB_QP_LSO;
 718
 719                 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
 720                         if (dev->steering_support ==
 721                             MLX4_STEERING_MODE_DEVICE_MANAGED)
 722                                 qp->flags |= MLX4_IB_QP_NETIF;
 723                         else
 724                                 goto err;
 725                 }
 726
 727                 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
 728                 if (err)
 729                         goto err;
 730
 731                 if (qp_has_rq(init_attr)) {
 732                         err = mlx4_db_alloc(dev->dev, &qp->db, 0);
 733                         if (err)
 734                                 goto err;
 735
 736                         *qp->db.db = 0;
 737                 }
 738
 739                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
 740                         err = -ENOMEM;
 741                         goto err_db;
 742                 }
 743
 744                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 745                                     &qp->mtt);
 746                 if (err)
 747                         goto err_buf;
 748
 749                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
 750                 if (err)
 751                         goto err_mtt;
 752
 753                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 754                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 755
 756                 if (!qp->sq.wrid || !qp->rq.wrid) {
 757                         err = -ENOMEM;
 758                         goto err_wrid;
 759                 }
 760         }
 761
 762         if (sqpn) {
 763                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
 764                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
 765                         if (alloc_proxy_bufs(pd->device, qp)) {
 766                                 err = -ENOMEM;
 767                                 goto err_wrid;
 768                         }
 769                 }
 770         } else {
 771                 /* Raw packet QPNs must be aligned to 8 bits. If not, the WQE
 772                  * BlueFlame setup flow wrongly causes VLAN insertion. */
 773                 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
 774                         err = mlx4_qp_reserve_range(dev->dev, 1, 1 << 8, &qpn);
 775                 else
 776                         if (qp->flags & MLX4_IB_QP_NETIF)
 777                                 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
 778                         else
 779                                 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
 780                                                             &qpn);
 781                 if (err)
 782                         goto err_proxy;
 783         }
 784
 785         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
 786         if (err)
 787                 goto err_qpn;
 788
 789         if (init_attr->qp_type == IB_QPT_XRC_TGT)
 790                 qp->mqp.qpn |= (1 << 23);
 791
 792         /*
 793          * Hardware wants QPN written in big-endian order (after
 794          * shifting) for send doorbell.  Precompute this value to save
 795          * a little bit when posting sends.
 796          */
 797         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 798
 799         qp->mqp.event = mlx4_ib_qp_event;
 800         if (!*caller_qp)
 801                 *caller_qp = qp;
 802         return 0;
 803
 804 err_qpn:
 805         if (!sqpn) {
 806                 if (qp->flags & MLX4_IB_QP_NETIF)
 807                         mlx4_ib_steer_qp_free(dev, qpn, 1);
 808                 else
 809                         mlx4_qp_release_range(dev->dev, qpn, 1);
 810         }
 811 err_proxy:
 812         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
 813                 free_proxy_bufs(pd->device, qp);
 814 err_wrid:
 815         if (pd->uobject) {
 816                 if (qp_has_rq(init_attr))
 817                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
 818         } else {
 819                 kfree(qp->sq.wrid);
 820                 kfree(qp->rq.wrid);
 821         }
 822
 823 err_mtt:
 824         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 825
 826 err_buf:
 827         if (pd->uobject)
 828                 ib_umem_release(qp->umem);
 829         else
 830                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 831
 832 err_db:
 833         if (!pd->uobject && qp_has_rq(init_attr))
 834                 mlx4_db_free(dev->dev, &qp->db);
 835
 836 err:
 837         if (!*caller_qp)
 838                 kfree(qp);
 839         return err;
 840 }
 841
 842 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 843 {
 844         switch (state) {
 845         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 846         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 847         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 848         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 849         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 850         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 851         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 852         default:                return -1;
 853         }
 854 }
 855
 856 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 857         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
 858 {
 859         if (send_cq == recv_cq) {
 860                 spin_lock_irq(&send_cq->lock);
 861                 __acquire(&recv_cq->lock);
 862         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 863                 spin_lock_irq(&send_cq->lock);
 864                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 865         } else {
 866                 spin_lock_irq(&recv_cq->lock);
 867                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 868         }
 869 }
 870
 871 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 872         __releases(&send_cq->lock) __releases(&recv_cq->lock)
 873 {
 874         if (send_cq == recv_cq) {
 875                 __release(&recv_cq->lock);
 876                 spin_unlock_irq(&send_cq->lock);
 877         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 878                 spin_unlock(&recv_cq->lock);
 879                 spin_unlock_irq(&send_cq->lock);
 880         } else {
 881                 spin_unlock(&send_cq->lock);
 882                 spin_unlock_irq(&recv_cq->lock);
 883         }
 884 }
 885
 886 static void del_gid_entries(struct mlx4_ib_qp *qp)
 887 {
 888         struct mlx4_ib_gid_entry *ge, *tmp;
 889
 890         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
 891                 list_del(&ge->list);
 892                 kfree(ge);
 893         }
 894 }
 895
 896 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
 897 {
 898         if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
 899                 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
 900         else
 901                 return to_mpd(qp->ibqp.pd);
 902 }
 903
 904 static void get_cqs(struct mlx4_ib_qp *qp,
 905                     struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
 906 {
 907         switch (qp->ibqp.qp_type) {
 908         case IB_QPT_XRC_TGT:
 909                 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
 910                 *recv_cq = *send_cq;
 911                 break;
 912         case IB_QPT_XRC_INI:
 913                 *send_cq = to_mcq(qp->ibqp.send_cq);
 914                 *recv_cq = *send_cq;
 915                 break;
 916         default:
 917                 *send_cq = to_mcq(qp->ibqp.send_cq);
 918                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
 919                 break;
 920         }
 921 }
 922
 923 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 924                               int is_user)
 925 {
 926         struct mlx4_ib_cq *send_cq, *recv_cq;
 927
 928         if (qp->state != IB_QPS_RESET)
 929                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
 930                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
 931                         pr_warn("modify QP %06x to RESET failed.\n",
 932                                qp->mqp.qpn);
 933
 934         get_cqs(qp, &send_cq, &recv_cq);
 935
 936         mlx4_ib_lock_cqs(send_cq, recv_cq);
 937
 938         if (!is_user) {
 939                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
 940                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
 941                 if (send_cq != recv_cq)
 942                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
 943         }
 944
 945         mlx4_qp_remove(dev->dev, &qp->mqp);
 946
 947         mlx4_ib_unlock_cqs(send_cq, recv_cq);
 948
 949         mlx4_qp_free(dev->dev, &qp->mqp);
 950
 951         if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
 952                 if (qp->flags & MLX4_IB_QP_NETIF)
 953                         mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
 954                 else
 955                         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
 956         }
 957
 958         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 959
 960         if (is_user) {
 961                 if (qp->rq.wqe_cnt)
 962                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
 963                                               &qp->db);
 964                 ib_umem_release(qp->umem);
 965         } else {
 966                 kfree(qp->sq.wrid);
 967                 kfree(qp->rq.wrid);
 968                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
 969                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
 970                         free_proxy_bufs(&dev->ib_dev, qp);
 971                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 972                 if (qp->rq.wqe_cnt)
 973                         mlx4_db_free(dev->dev, &qp->db);
 974         }
 975
 976         del_gid_entries(qp);
 977 }
 978
 979 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
 980 {
 981         /* Native or PPF */
 982         if (!mlx4_is_mfunc(dev->dev) ||
 983             (mlx4_is_master(dev->dev) &&
 984              attr->create_flags & MLX4_IB_SRIOV_SQP)) {
 985                 return  dev->dev->phys_caps.base_sqpn +
 986                         (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
 987                         attr->port_num - 1;
 988         }
 989         /* PF or VF -- creating proxies */
 990         if (attr->qp_type == IB_QPT_SMI)
 991                 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
 992         else
 993                 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
 994 }
 995
 996 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
 997                                 struct ib_qp_init_attr *init_attr,
 998                                 struct ib_udata *udata)
 999 {
1000         struct mlx4_ib_qp *qp = NULL;
1001         int err;
1002         u16 xrcdn = 0;
1003
1004         /*
1005          * We only support LSO, vendor flag1, and multicast loopback blocking,
1006          * and only for kernel UD QPs.
1007          */
1008         if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1009                                         MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1010                                         MLX4_IB_SRIOV_TUNNEL_QP |
1011                                         MLX4_IB_SRIOV_SQP |
1012                                         MLX4_IB_QP_NETIF))
1013                 return ERR_PTR(-EINVAL);
1014
1015         if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1016                 if (init_attr->qp_type != IB_QPT_UD)
1017                         return ERR_PTR(-EINVAL);
1018         }
1019
1020         if (init_attr->create_flags &&
1021             (udata ||
1022              ((init_attr->create_flags & ~MLX4_IB_SRIOV_SQP) &&
1023               init_attr->qp_type != IB_QPT_UD) ||
1024              ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1025               init_attr->qp_type > IB_QPT_GSI)))
1026                 return ERR_PTR(-EINVAL);
1027
1028         switch (init_attr->qp_type) {
1029         case IB_QPT_XRC_TGT:
1030                 pd = to_mxrcd(init_attr->xrcd)->pd;
1031                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1032                 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1033                 /* fall through */
1034         case IB_QPT_XRC_INI:
1035                 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1036                         return ERR_PTR(-ENOSYS);
1037                 init_attr->recv_cq = init_attr->send_cq;
1038                 /* fall through */
1039         case IB_QPT_RC:
1040         case IB_QPT_UC:
1041         case IB_QPT_RAW_PACKET:
1042                 qp = kzalloc(sizeof *qp, GFP_KERNEL);
1043                 if (!qp)
1044                         return ERR_PTR(-ENOMEM);
1045                 /* fall through */
1046         case IB_QPT_UD:
1047         {
1048                 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
1049                                        udata, 0, &qp);
1050                 if (err)
1051                         return ERR_PTR(err);
1052
1053                 qp->ibqp.qp_num = qp->mqp.qpn;
1054                 qp->xrcdn = xrcdn;
1055
1056                 break;
1057         }
1058         case IB_QPT_SMI:
1059         case IB_QPT_GSI:
1060         {
1061                 /* Userspace is not allowed to create special QPs: */
1062                 if (udata)
1063                         return ERR_PTR(-EINVAL);
1064
1065                 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
1066                                        get_sqp_num(to_mdev(pd->device), init_attr),
1067                                        &qp);
1068                 if (err)
1069                         return ERR_PTR(err);
1070
1071                 qp->port        = init_attr->port_num;
1072                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1073
1074                 break;
1075         }
1076         default:
1077                 /* Don't support raw QPs */
1078                 return ERR_PTR(-EINVAL);
1079         }
1080
1081         return &qp->ibqp;
1082 }
1083
1084 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1085 {
1086         struct mlx4_ib_dev *dev = to_mdev(qp->device);
1087         struct mlx4_ib_qp *mqp = to_mqp(qp);
1088         struct mlx4_ib_pd *pd;
1089
1090         if (is_qp0(dev, mqp))
1091                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1092
1093         pd = get_pd(mqp);
1094         destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
1095
1096         if (is_sqp(dev, mqp))
1097                 kfree(to_msqp(mqp));
1098         else
1099                 kfree(mqp);
1100
1101         return 0;
1102 }
1103
1104 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1105 {
1106         switch (type) {
1107         case MLX4_IB_QPT_RC:            return MLX4_QP_ST_RC;
1108         case MLX4_IB_QPT_UC:            return MLX4_QP_ST_UC;
1109         case MLX4_IB_QPT_UD:            return MLX4_QP_ST_UD;
1110         case MLX4_IB_QPT_XRC_INI:
1111         case MLX4_IB_QPT_XRC_TGT:       return MLX4_QP_ST_XRC;
1112         case MLX4_IB_QPT_SMI:
1113         case MLX4_IB_QPT_GSI:
1114         case MLX4_IB_QPT_RAW_PACKET:    return MLX4_QP_ST_MLX;
1115
1116         case MLX4_IB_QPT_PROXY_SMI_OWNER:
1117         case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1118                                                 MLX4_QP_ST_MLX : -1);
1119         case MLX4_IB_QPT_PROXY_SMI:
1120         case MLX4_IB_QPT_TUN_SMI:
1121         case MLX4_IB_QPT_PROXY_GSI:
1122         case MLX4_IB_QPT_TUN_GSI:       return (mlx4_is_mfunc(dev->dev) ?
1123                                                 MLX4_QP_ST_UD : -1);
1124         default:                        return -1;
1125         }
1126 }
1127
1128 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1129                                    int attr_mask)
1130 {
1131         u8 dest_rd_atomic;
1132         u32 access_flags;
1133         u32 hw_access_flags = 0;
1134
1135         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1136                 dest_rd_atomic = attr->max_dest_rd_atomic;
1137         else
1138                 dest_rd_atomic = qp->resp_depth;
1139
1140         if (attr_mask & IB_QP_ACCESS_FLAGS)
1141                 access_flags = attr->qp_access_flags;
1142         else
1143                 access_flags = qp->atomic_rd_en;
1144
1145         if (!dest_rd_atomic)
1146                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1147
1148         if (access_flags & IB_ACCESS_REMOTE_READ)
1149                 hw_access_flags |= MLX4_QP_BIT_RRE;
1150         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1151                 hw_access_flags |= MLX4_QP_BIT_RAE;
1152         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1153                 hw_access_flags |= MLX4_QP_BIT_RWE;
1154
1155         return cpu_to_be32(hw_access_flags);
1156 }
1157
1158 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1159                             int attr_mask)
1160 {
1161         if (attr_mask & IB_QP_PKEY_INDEX)
1162                 sqp->pkey_index = attr->pkey_index;
1163         if (attr_mask & IB_QP_QKEY)
1164                 sqp->qkey = attr->qkey;
1165         if (attr_mask & IB_QP_SQ_PSN)
1166                 sqp->send_psn = attr->sq_psn;
1167 }
1168
1169 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1170 {
1171         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1172 }
1173
1174 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1175                          struct mlx4_qp_path *path, u8 port)
1176 {
1177         int err;
1178         int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1179                 IB_LINK_LAYER_ETHERNET;
1180         u8 mac[6];
1181         int is_mcast;
1182         u16 vlan_tag;
1183         int vidx;
1184
1185         path->grh_mylmc     = ah->src_path_bits & 0x7f;
1186         path->rlid          = cpu_to_be16(ah->dlid);
1187         if (ah->static_rate) {
1188                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1189                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1190                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1191                         --path->static_rate;
1192         } else
1193                 path->static_rate = 0;
1194
1195         if (ah->ah_flags & IB_AH_GRH) {
1196                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
1197                         pr_err("sgid_index (%u) too large. max is %d\n",
1198                                ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1199                         return -1;
1200                 }
1201
1202                 path->grh_mylmc |= 1 << 7;
1203                 path->mgid_index = ah->grh.sgid_index;
1204                 path->hop_limit  = ah->grh.hop_limit;
1205                 path->tclass_flowlabel =
1206                         cpu_to_be32((ah->grh.traffic_class << 20) |
1207                                     (ah->grh.flow_label));
1208                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1209         }
1210
1211         if (is_eth) {
1212                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1213                         ((port - 1) << 6) | ((ah->sl & 7) << 3);
1214
1215                 if (!(ah->ah_flags & IB_AH_GRH))
1216                         return -1;
1217
1218                 err = mlx4_ib_resolve_grh(dev, ah, mac, &is_mcast, port);
1219                 if (err)
1220                         return err;
1221
1222                 memcpy(path->dmac, mac, 6);
1223                 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1224                 /* use index 0 into MAC table for IBoE */
1225                 path->grh_mylmc &= 0x80;
1226
1227                 vlan_tag = rdma_get_vlan_id(&dev->iboe.gid_table[port - 1][ah->grh.sgid_index]);
1228                 if (vlan_tag < 0x1000) {
1229                         if (mlx4_find_cached_vlan(dev->dev, port, vlan_tag, &vidx))
1230                                 return -ENOENT;
1231
1232                         path->vlan_index = vidx;
1233                         path->fl = 1 << 6;
1234                 }
1235         } else
1236                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1237                         ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
1238
1239         return 0;
1240 }
1241
1242 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1243 {
1244         struct mlx4_ib_gid_entry *ge, *tmp;
1245
1246         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1247                 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1248                         ge->added = 1;
1249                         ge->port = qp->port;
1250                 }
1251         }
1252 }
1253
1254 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1255                                const struct ib_qp_attr *attr, int attr_mask,
1256                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
1257 {
1258         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1259         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1260         struct mlx4_ib_pd *pd;
1261         struct mlx4_ib_cq *send_cq, *recv_cq;
1262         struct mlx4_qp_context *context;
1263         enum mlx4_qp_optpar optpar = 0;
1264         int sqd_event;
1265         int steer_qp = 0;
1266         int err = -EINVAL;
1267
1268         context = kzalloc(sizeof *context, GFP_KERNEL);
1269         if (!context)
1270                 return -ENOMEM;
1271
1272         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1273                                      (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
1274
1275         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1276                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1277         else {
1278                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1279                 switch (attr->path_mig_state) {
1280                 case IB_MIG_MIGRATED:
1281                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1282                         break;
1283                 case IB_MIG_REARM:
1284                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1285                         break;
1286                 case IB_MIG_ARMED:
1287                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1288                         break;
1289                 }
1290         }
1291
1292         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1293                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1294         else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1295                 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
1296         else if (ibqp->qp_type == IB_QPT_UD) {
1297                 if (qp->flags & MLX4_IB_QP_LSO)
1298                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
1299                                               ilog2(dev->dev->caps.max_gso_sz);
1300                 else
1301                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1302         } else if (attr_mask & IB_QP_PATH_MTU) {
1303                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1304                         pr_err("path MTU (%u) is invalid\n",
1305                                attr->path_mtu);
1306                         goto out;
1307                 }
1308                 context->mtu_msgmax = (attr->path_mtu << 5) |
1309                         ilog2(dev->dev->caps.max_msg_sz);
1310         }
1311
1312         if (qp->rq.wqe_cnt)
1313                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1314         context->rq_size_stride |= qp->rq.wqe_shift - 4;
1315
1316         if (qp->sq.wqe_cnt)
1317                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1318         context->sq_size_stride |= qp->sq.wqe_shift - 4;
1319
1320         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1321                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1322                 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1323                 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1324                         context->param3 |= cpu_to_be32(1 << 30);
1325         }
1326
1327         if (qp->ibqp.uobject)
1328                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1329         else
1330                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1331
1332         if (attr_mask & IB_QP_DEST_QPN)
1333                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1334
1335         if (attr_mask & IB_QP_PORT) {
1336                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1337                     !(attr_mask & IB_QP_AV)) {
1338                         mlx4_set_sched(&context->pri_path, attr->port_num);
1339                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1340                 }
1341         }
1342
1343         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1344                 if (dev->counters[qp->port - 1] != -1) {
1345                         context->pri_path.counter_index =
1346                                                 dev->counters[qp->port - 1];
1347                         optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1348                 } else
1349                         context->pri_path.counter_index = 0xff;
1350
1351                 if (qp->flags & MLX4_IB_QP_NETIF) {
1352                         mlx4_ib_steer_qp_reg(dev, qp, 1);
1353                         steer_qp = 1;
1354                 }
1355         }
1356
1357         if (attr_mask & IB_QP_PKEY_INDEX) {
1358                 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1359                         context->pri_path.disable_pkey_check = 0x40;
1360                 context->pri_path.pkey_index = attr->pkey_index;
1361                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1362         }
1363
1364         if (attr_mask & IB_QP_AV) {
1365                 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
1366                                   attr_mask & IB_QP_PORT ?
1367                                   attr->port_num : qp->port))
1368                         goto out;
1369
1370                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1371                            MLX4_QP_OPTPAR_SCHED_QUEUE);
1372         }
1373
1374         if (attr_mask & IB_QP_TIMEOUT) {
1375                 context->pri_path.ackto |= attr->timeout << 3;
1376                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1377         }
1378
1379         if (attr_mask & IB_QP_ALT_PATH) {
1380                 if (attr->alt_port_num == 0 ||
1381                     attr->alt_port_num > dev->dev->caps.num_ports)
1382                         goto out;
1383
1384                 if (attr->alt_pkey_index >=
1385                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
1386                         goto out;
1387
1388                 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
1389                                   attr->alt_port_num))
1390                         goto out;
1391
1392                 context->alt_path.pkey_index = attr->alt_pkey_index;
1393                 context->alt_path.ackto = attr->alt_timeout << 3;
1394                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1395         }
1396
1397         pd = get_pd(qp);
1398         get_cqs(qp, &send_cq, &recv_cq);
1399         context->pd       = cpu_to_be32(pd->pdn);
1400         context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1401         context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1402         context->params1  = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1403
1404         /* Set "fast registration enabled" for all kernel QPs */
1405         if (!qp->ibqp.uobject)
1406                 context->params1 |= cpu_to_be32(1 << 11);
1407
1408         if (attr_mask & IB_QP_RNR_RETRY) {
1409                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1410                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1411         }
1412
1413         if (attr_mask & IB_QP_RETRY_CNT) {
1414                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1415                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1416         }
1417
1418         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1419                 if (attr->max_rd_atomic)
1420                         context->params1 |=
1421                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1422                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1423         }
1424
1425         if (attr_mask & IB_QP_SQ_PSN)
1426                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1427
1428         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1429                 if (attr->max_dest_rd_atomic)
1430                         context->params2 |=
1431                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1432                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1433         }
1434
1435         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1436                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1437                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1438         }
1439
1440         if (ibqp->srq)
1441                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1442
1443         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1444                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1445                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1446         }
1447         if (attr_mask & IB_QP_RQ_PSN)
1448                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1449
1450         /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
1451         if (attr_mask & IB_QP_QKEY) {
1452                 if (qp->mlx4_ib_qp_type &
1453                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1454                         context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1455                 else {
1456                         if (mlx4_is_mfunc(dev->dev) &&
1457                             !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1458                             (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1459                             MLX4_RESERVED_QKEY_BASE) {
1460                                 pr_err("Cannot use reserved QKEY"
1461                                        " 0x%x (range 0xffff0000..0xffffffff"
1462                                        " is reserved)\n", attr->qkey);
1463                                 err = -EINVAL;
1464                                 goto out;
1465                         }
1466                         context->qkey = cpu_to_be32(attr->qkey);
1467                 }
1468                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1469         }
1470
1471         if (ibqp->srq)
1472                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1473
1474         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1475                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1476
1477         if (cur_state == IB_QPS_INIT &&
1478             new_state == IB_QPS_RTR  &&
1479             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1480              ibqp->qp_type == IB_QPT_UD ||
1481              ibqp->qp_type == IB_QPT_RAW_PACKET)) {
1482                 context->pri_path.sched_queue = (qp->port - 1) << 6;
1483                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1484                     qp->mlx4_ib_qp_type &
1485                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
1486                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1487                         if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1488                                 context->pri_path.fl = 0x80;
1489                 } else {
1490                         if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1491                                 context->pri_path.fl = 0x80;
1492                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1493                 }
1494         }
1495
1496         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET)
1497                 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1498                                         MLX4_IB_LINK_TYPE_ETH;
1499
1500         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1501             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1502                 sqd_event = 1;
1503         else
1504                 sqd_event = 0;
1505
1506         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1507                 context->rlkey |= (1 << 4);
1508
1509         /*
1510          * Before passing a kernel QP to the HW, make sure that the
1511          * ownership bits of the send queue are set and the SQ
1512          * headroom is stamped so that the hardware doesn't start
1513          * processing stale work requests.
1514          */
1515         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1516                 struct mlx4_wqe_ctrl_seg *ctrl;
1517                 int i;
1518
1519                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1520                         ctrl = get_send_wqe(qp, i);
1521                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
1522                         if (qp->sq_max_wqes_per_wr == 1)
1523                                 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1524
1525                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1526                 }
1527         }
1528
1529         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1530                              to_mlx4_state(new_state), context, optpar,
1531                              sqd_event, &qp->mqp);
1532         if (err)
1533                 goto out;
1534
1535         qp->state = new_state;
1536
1537         if (attr_mask & IB_QP_ACCESS_FLAGS)
1538                 qp->atomic_rd_en = attr->qp_access_flags;
1539         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1540                 qp->resp_depth = attr->max_dest_rd_atomic;
1541         if (attr_mask & IB_QP_PORT) {
1542                 qp->port = attr->port_num;
1543                 update_mcg_macs(dev, qp);
1544         }
1545         if (attr_mask & IB_QP_ALT_PATH)
1546                 qp->alt_port = attr->alt_port_num;
1547
1548         if (is_sqp(dev, qp))
1549                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1550
1551         /*
1552          * If we moved QP0 to RTR, bring the IB link up; if we moved
1553          * QP0 to RESET or ERROR, bring the link back down.
1554          */
1555         if (is_qp0(dev, qp)) {
1556                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1557                         if (mlx4_INIT_PORT(dev->dev, qp->port))
1558                                 pr_warn("INIT_PORT failed for port %d\n",
1559                                        qp->port);
1560
1561                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1562                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1563                         mlx4_CLOSE_PORT(dev->dev, qp->port);
1564         }
1565
1566         /*
1567          * If we moved a kernel QP to RESET, clean up all old CQ
1568          * entries and reinitialize the QP.
1569          */
1570         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1571                 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1572                                  ibqp->srq ? to_msrq(ibqp->srq): NULL);
1573                 if (send_cq != recv_cq)
1574                         mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1575
1576                 qp->rq.head = 0;
1577                 qp->rq.tail = 0;
1578                 qp->sq.head = 0;
1579                 qp->sq.tail = 0;
1580                 qp->sq_next_wqe = 0;
1581                 if (qp->rq.wqe_cnt)
1582                         *qp->db.db  = 0;
1583
1584                 if (qp->flags & MLX4_IB_QP_NETIF)
1585                         mlx4_ib_steer_qp_reg(dev, qp, 0);
1586         }
1587
1588 out:
1589         if (err && steer_qp)
1590                 mlx4_ib_steer_qp_reg(dev, qp, 0);
1591         kfree(context);
1592         return err;
1593 }
1594
1595 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1596                       int attr_mask, struct ib_udata *udata)
1597 {
1598         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1599         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1600         enum ib_qp_state cur_state, new_state;
1601         int err = -EINVAL;
1602
1603         mutex_lock(&qp->mutex);
1604
1605         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1606         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1607
1608         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
1609                 pr_debug("qpn 0x%x: invalid attribute mask specified "
1610                          "for transition %d to %d. qp_type %d,"
1611                          " attr_mask 0x%x\n",
1612                          ibqp->qp_num, cur_state, new_state,
1613                          ibqp->qp_type, attr_mask);
1614                 goto out;
1615         }
1616
1617         if ((attr_mask & IB_QP_PORT) &&
1618             (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
1619                 pr_debug("qpn 0x%x: invalid port number (%d) specified "
1620                          "for transition %d to %d. qp_type %d\n",
1621                          ibqp->qp_num, attr->port_num, cur_state,
1622                          new_state, ibqp->qp_type);
1623                 goto out;
1624         }
1625
1626         if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
1627             (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
1628              IB_LINK_LAYER_ETHERNET))
1629                 goto out;
1630
1631         if (attr_mask & IB_QP_PKEY_INDEX) {
1632                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1633                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
1634                         pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
1635                                  "for transition %d to %d. qp_type %d\n",
1636                                  ibqp->qp_num, attr->pkey_index, cur_state,
1637                                  new_state, ibqp->qp_type);
1638                         goto out;
1639                 }
1640         }
1641
1642         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1643             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1644                 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
1645                          "Transition %d to %d. qp_type %d\n",
1646                          ibqp->qp_num, attr->max_rd_atomic, cur_state,
1647                          new_state, ibqp->qp_type);
1648                 goto out;
1649         }
1650
1651         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1652             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1653                 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
1654                          "Transition %d to %d. qp_type %d\n",
1655                          ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
1656                          new_state, ibqp->qp_type);
1657                 goto out;
1658         }
1659
1660         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1661                 err = 0;
1662                 goto out;
1663         }
1664
1665         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1666
1667 out:
1668         mutex_unlock(&qp->mutex);
1669         return err;
1670 }
1671
1672 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
1673                                   struct ib_send_wr *wr,
1674                                   void *wqe, unsigned *mlx_seg_len)
1675 {
1676         struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
1677         struct ib_device *ib_dev = &mdev->ib_dev;
1678         struct mlx4_wqe_mlx_seg *mlx = wqe;
1679         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1680         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1681         u16 pkey;
1682         u32 qkey;
1683         int send_size;
1684         int header_size;
1685         int spc;
1686         int i;
1687
1688         if (wr->opcode != IB_WR_SEND)
1689                 return -EINVAL;
1690
1691         send_size = 0;
1692
1693         for (i = 0; i < wr->num_sge; ++i)
1694                 send_size += wr->sg_list[i].length;
1695
1696         /* for proxy-qp0 sends, need to add in size of tunnel header */
1697         /* for tunnel-qp0 sends, tunnel header is already in s/g list */
1698         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
1699                 send_size += sizeof (struct mlx4_ib_tunnel_header);
1700
1701         ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
1702
1703         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
1704                 sqp->ud_header.lrh.service_level =
1705                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
1706                 sqp->ud_header.lrh.destination_lid =
1707                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1708                 sqp->ud_header.lrh.source_lid =
1709                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1710         }
1711
1712         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1713
1714         /* force loopback */
1715         mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
1716         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1717
1718         sqp->ud_header.lrh.virtual_lane    = 0;
1719         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1720         ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
1721         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1722         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
1723                 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1724         else
1725                 sqp->ud_header.bth.destination_qpn =
1726                         cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
1727
1728         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1729         if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
1730                 return -EINVAL;
1731         sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
1732         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
1733
1734         sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
1735         sqp->ud_header.immediate_present = 0;
1736
1737         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1738
1739         /*
1740          * Inline data segments may not cross a 64 byte boundary.  If
1741          * our UD header is bigger than the space available up to the
1742          * next 64 byte boundary in the WQE, use two inline data
1743          * segments to hold the UD header.
1744          */
1745         spc = MLX4_INLINE_ALIGN -
1746               ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1747         if (header_size <= spc) {
1748                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1749                 memcpy(inl + 1, sqp->header_buf, header_size);
1750                 i = 1;
1751         } else {
1752                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1753                 memcpy(inl + 1, sqp->header_buf, spc);
1754
1755                 inl = (void *) (inl + 1) + spc;
1756                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1757                 /*
1758                  * Need a barrier here to make sure all the data is
1759                  * visible before the byte_count field is set.
1760                  * Otherwise the HCA prefetcher could grab the 64-byte
1761                  * chunk with this inline segment and get a valid (!=
1762                  * 0xffffffff) byte count but stale data, and end up
1763                  * generating a packet with bad headers.
1764                  *
1765                  * The first inline segment's byte_count field doesn't
1766                  * need a barrier, because it comes after a
1767                  * control/MLX segment and therefore is at an offset
1768                  * of 16 mod 64.
1769                  */
1770                 wmb();
1771                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1772                 i = 2;
1773         }
1774
1775         *mlx_seg_len =
1776         ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1777         return 0;
1778 }
1779
1780 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1781                             void *wqe, unsigned *mlx_seg_len)
1782 {
1783         struct ib_device *ib_dev = sqp->qp.ibqp.device;
1784         struct mlx4_wqe_mlx_seg *mlx = wqe;
1785         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1786         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1787         struct net_device *ndev;
1788         union ib_gid sgid;
1789         u16 pkey;
1790         int send_size;
1791         int header_size;
1792         int spc;
1793         int i;
1794         int err = 0;
1795         u16 vlan = 0xffff;
1796         bool is_eth;
1797         bool is_vlan = false;
1798         bool is_grh;
1799
1800         send_size = 0;
1801         for (i = 0; i < wr->num_sge; ++i)
1802                 send_size += wr->sg_list[i].length;
1803
1804         is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
1805         is_grh = mlx4_ib_ah_grh_present(ah);
1806         if (is_eth) {
1807                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
1808                         /* When multi-function is enabled, the ib_core gid
1809                          * indexes don't necessarily match the hw ones, so
1810                          * we must use our own cache */
1811                         sgid.global.subnet_prefix =
1812                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
1813                                 subnet_prefix;
1814                         sgid.global.interface_id =
1815                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
1816                                 guid_cache[ah->av.ib.gid_index];
1817                 } else  {
1818                         err = ib_get_cached_gid(ib_dev,
1819                                                 be32_to_cpu(ah->av.ib.port_pd) >> 24,
1820                                                 ah->av.ib.gid_index, &sgid);
1821                         if (err)
1822                                 return err;
1823                 }
1824
1825                 vlan = rdma_get_vlan_id(&sgid);
1826                 is_vlan = vlan < 0x1000;
1827         }
1828         ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
1829
1830         if (!is_eth) {
1831                 sqp->ud_header.lrh.service_level =
1832                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
1833                 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
1834                 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1835         }
1836
1837         if (is_grh) {
1838                 sqp->ud_header.grh.traffic_class =
1839                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
1840                 sqp->ud_header.grh.flow_label    =
1841                         ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1842                 sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
1843                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
1844                         /* When multi-function is enabled, the ib_core gid
1845                          * indexes don't necessarily match the hw ones, so
1846                          * we must use our own cache */
1847                         sqp->ud_header.grh.source_gid.global.subnet_prefix =
1848                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
1849                                                        subnet_prefix;
1850                         sqp->ud_header.grh.source_gid.global.interface_id =
1851                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
1852                                                guid_cache[ah->av.ib.gid_index];
1853                 } else
1854                         ib_get_cached_gid(ib_dev,
1855                                           be32_to_cpu(ah->av.ib.port_pd) >> 24,
1856                                           ah->av.ib.gid_index,
1857                                           &sqp->ud_header.grh.source_gid);
1858                 memcpy(sqp->ud_header.grh.destination_gid.raw,
1859                        ah->av.ib.dgid, 16);
1860         }
1861
1862         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1863
1864         if (!is_eth) {
1865                 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1866                                           (sqp->ud_header.lrh.destination_lid ==
1867                                            IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1868                                           (sqp->ud_header.lrh.service_level << 8));
1869                 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
1870                         mlx->flags |= cpu_to_be32(0x1); /* force loopback */
1871                 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1872         }
1873
1874         switch (wr->opcode) {
1875         case IB_WR_SEND:
1876                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
1877                 sqp->ud_header.immediate_present = 0;
1878                 break;
1879         case IB_WR_SEND_WITH_IMM:
1880                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1881                 sqp->ud_header.immediate_present = 1;
1882                 sqp->ud_header.immediate_data    = wr->ex.imm_data;
1883                 break;
1884         default:
1885                 return -EINVAL;
1886         }
1887
1888         if (is_eth) {
1889                 u8 *smac;
1890                 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
1891
1892                 mlx->sched_prio = cpu_to_be16(pcp);
1893
1894                 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
1895                 /* FIXME: cache smac value? */
1896                 ndev = to_mdev(sqp->qp.ibqp.device)->iboe.netdevs[sqp->qp.port - 1];
1897                 if (!ndev)
1898                         return -ENODEV;
1899                 smac = ndev->dev_addr;
1900                 memcpy(sqp->ud_header.eth.smac_h, smac, 6);
1901                 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
1902                         mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
1903                 if (!is_vlan) {
1904                         sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
1905                 } else {
1906                         sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
1907                         sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
1908                 }
1909         } else {
1910                 sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1911                 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1912                         sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1913         }
1914         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1915         if (!sqp->qp.ibqp.qp_num)
1916                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1917         else
1918                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1919         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1920         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1921         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1922         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1923                                                sqp->qkey : wr->wr.ud.remote_qkey);
1924         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1925
1926         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1927
1928         if (0) {
1929                 pr_err("built UD header of size %d:\n", header_size);
1930                 for (i = 0; i < header_size / 4; ++i) {
1931                         if (i % 8 == 0)
1932                                 pr_err("  [%02x] ", i * 4);
1933                         pr_cont(" %08x",
1934                                 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1935                         if ((i + 1) % 8 == 0)
1936                                 pr_cont("\n");
1937                 }
1938                 pr_err("\n");
1939         }
1940
1941         /*
1942          * Inline data segments may not cross a 64 byte boundary.  If
1943          * our UD header is bigger than the space available up to the
1944          * next 64 byte boundary in the WQE, use two inline data
1945          * segments to hold the UD header.
1946          */
1947         spc = MLX4_INLINE_ALIGN -
1948                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1949         if (header_size <= spc) {
1950                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1951                 memcpy(inl + 1, sqp->header_buf, header_size);
1952                 i = 1;
1953         } else {
1954                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1955                 memcpy(inl + 1, sqp->header_buf, spc);
1956
1957                 inl = (void *) (inl + 1) + spc;
1958                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1959                 /*
1960                  * Need a barrier here to make sure all the data is
1961                  * visible before the byte_count field is set.
1962                  * Otherwise the HCA prefetcher could grab the 64-byte
1963                  * chunk with this inline segment and get a valid (!=
1964                  * 0xffffffff) byte count but stale data, and end up
1965                  * generating a packet with bad headers.
1966                  *
1967                  * The first inline segment's byte_count field doesn't
1968                  * need a barrier, because it comes after a
1969                  * control/MLX segment and therefore is at an offset
1970                  * of 16 mod 64.
1971                  */
1972                 wmb();
1973                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1974                 i = 2;
1975         }
1976
1977         *mlx_seg_len =
1978                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1979         return 0;
1980 }
1981
1982 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1983 {
1984         unsigned cur;
1985         struct mlx4_ib_cq *cq;
1986
1987         cur = wq->head - wq->tail;
1988         if (likely(cur + nreq < wq->max_post))
1989                 return 0;
1990
1991         cq = to_mcq(ib_cq);
1992         spin_lock(&cq->lock);
1993         cur = wq->head - wq->tail;
1994         spin_unlock(&cq->lock);
1995
1996         return cur + nreq >= wq->max_post;
1997 }
1998
1999 static __be32 convert_access(int acc)
2000 {
2001         return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2002                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC)       : 0) |
2003                (acc & IB_ACCESS_REMOTE_WRITE  ?
2004                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2005                (acc & IB_ACCESS_REMOTE_READ   ?
2006                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ)  : 0) |
2007                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
2008                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2009 }
2010
2011 static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
2012 {
2013         struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
2014         int i;
2015
2016         for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
2017                 mfrpl->mapped_page_list[i] =
2018                         cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
2019                                     MLX4_MTT_FLAG_PRESENT);
2020
2021         fseg->flags             = convert_access(wr->wr.fast_reg.access_flags);
2022         fseg->mem_key           = cpu_to_be32(wr->wr.fast_reg.rkey);
2023         fseg->buf_list          = cpu_to_be64(mfrpl->map);
2024         fseg->start_addr        = cpu_to_be64(wr->wr.fast_reg.iova_start);
2025         fseg->reg_len           = cpu_to_be64(wr->wr.fast_reg.length);
2026         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
2027         fseg->page_size         = cpu_to_be32(wr->wr.fast_reg.page_shift);
2028         fseg->reserved[0]       = 0;
2029         fseg->reserved[1]       = 0;
2030 }
2031
2032 static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg, struct ib_send_wr *wr)
2033 {
2034         bseg->flags1 =
2035                 convert_access(wr->wr.bind_mw.bind_info.mw_access_flags) &
2036                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ  |
2037                             MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE |
2038                             MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC);
2039         bseg->flags2 = 0;
2040         if (wr->wr.bind_mw.mw->type == IB_MW_TYPE_2)
2041                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2);
2042         if (wr->wr.bind_mw.bind_info.mw_access_flags & IB_ZERO_BASED)
2043                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED);
2044         bseg->new_rkey = cpu_to_be32(wr->wr.bind_mw.rkey);
2045         bseg->lkey = cpu_to_be32(wr->wr.bind_mw.bind_info.mr->lkey);
2046         bseg->addr = cpu_to_be64(wr->wr.bind_mw.bind_info.addr);
2047         bseg->length = cpu_to_be64(wr->wr.bind_mw.bind_info.length);
2048 }
2049
2050 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2051 {
2052         memset(iseg, 0, sizeof(*iseg));
2053         iseg->mem_key = cpu_to_be32(rkey);
2054 }
2055
2056 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2057                                           u64 remote_addr, u32 rkey)
2058 {
2059         rseg->raddr    = cpu_to_be64(remote_addr);
2060         rseg->rkey     = cpu_to_be32(rkey);
2061         rseg->reserved = 0;
2062 }
2063
2064 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
2065 {
2066         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2067                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2068                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add);
2069         } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2070                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2071                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2072         } else {
2073                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2074                 aseg->compare  = 0;
2075         }
2076
2077 }
2078
2079 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2080                                   struct ib_send_wr *wr)
2081 {
2082         aseg->swap_add          = cpu_to_be64(wr->wr.atomic.swap);
2083         aseg->swap_add_mask     = cpu_to_be64(wr->wr.atomic.swap_mask);
2084         aseg->compare           = cpu_to_be64(wr->wr.atomic.compare_add);
2085         aseg->compare_mask      = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2086 }
2087
2088 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
2089                              struct ib_send_wr *wr)
2090 {
2091         memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
2092         dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2093         dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2094         dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan;
2095         memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6);
2096 }
2097
2098 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2099                                     struct mlx4_wqe_datagram_seg *dseg,
2100                                     struct ib_send_wr *wr, enum ib_qp_type qpt)
2101 {
2102         union mlx4_ext_av *av = &to_mah(wr->wr.ud.ah)->av;
2103         struct mlx4_av sqp_av = {0};
2104         int port = *((u8 *) &av->ib.port_pd) & 0x3;
2105
2106         /* force loopback */
2107         sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2108         sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2109         sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2110                         cpu_to_be32(0xf0000000);
2111
2112         memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
2113         /* This function used only for sending on QP1 proxies */
2114         dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2115         /* Use QKEY from the QP context, which is set by master */
2116         dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2117 }
2118
2119 static void build_tunnel_header(struct ib_send_wr *wr, void *wqe, unsigned *mlx_seg_len)
2120 {
2121         struct mlx4_wqe_inline_seg *inl = wqe;
2122         struct mlx4_ib_tunnel_header hdr;
2123         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2124         int spc;
2125         int i;
2126
2127         memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2128         hdr.remote_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2129         hdr.pkey_index = cpu_to_be16(wr->wr.ud.pkey_index);
2130         hdr.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2131
2132         spc = MLX4_INLINE_ALIGN -
2133                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2134         if (sizeof (hdr) <= spc) {
2135                 memcpy(inl + 1, &hdr, sizeof (hdr));
2136                 wmb();
2137                 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2138                 i = 1;
2139         } else {
2140                 memcpy(inl + 1, &hdr, spc);
2141                 wmb();
2142                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2143
2144                 inl = (void *) (inl + 1) + spc;
2145                 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2146                 wmb();
2147                 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2148                 i = 2;
2149         }
2150
2151         *mlx_seg_len =
2152                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2153 }
2154
2155 static void set_mlx_icrc_seg(void *dseg)
2156 {
2157         u32 *t = dseg;
2158         struct mlx4_wqe_inline_seg *iseg = dseg;
2159
2160         t[1] = 0;
2161
2162         /*
2163          * Need a barrier here before writing the byte_count field to
2164          * make sure that all the data is visible before the
2165          * byte_count field is set.  Otherwise, if the segment begins
2166          * a new cacheline, the HCA prefetcher could grab the 64-byte
2167          * chunk and get a valid (!= * 0xffffffff) byte count but
2168          * stale data, and end up sending the wrong data.
2169          */
2170         wmb();
2171
2172         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2173 }
2174
2175 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2176 {
2177         dseg->lkey       = cpu_to_be32(sg->lkey);
2178         dseg->addr       = cpu_to_be64(sg->addr);
2179
2180         /*
2181          * Need a barrier here before writing the byte_count field to
2182          * make sure that all the data is visible before the
2183          * byte_count field is set.  Otherwise, if the segment begins
2184          * a new cacheline, the HCA prefetcher could grab the 64-byte
2185          * chunk and get a valid (!= * 0xffffffff) byte count but
2186          * stale data, and end up sending the wrong data.
2187          */
2188         wmb();
2189
2190         dseg->byte_count = cpu_to_be32(sg->length);
2191 }
2192
2193 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2194 {
2195         dseg->byte_count = cpu_to_be32(sg->length);
2196         dseg->lkey       = cpu_to_be32(sg->lkey);
2197         dseg->addr       = cpu_to_be64(sg->addr);
2198 }
2199
2200 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
2201                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
2202                          __be32 *lso_hdr_sz, __be32 *blh)
2203 {
2204         unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
2205
2206         if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2207                 *blh = cpu_to_be32(1 << 6);
2208
2209         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2210                      wr->num_sge > qp->sq.max_gs - (halign >> 4)))
2211                 return -EINVAL;
2212
2213         memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
2214
2215         *lso_hdr_sz  = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
2216                                    wr->wr.ud.hlen);
2217         *lso_seg_len = halign;
2218         return 0;
2219 }
2220
2221 static __be32 send_ieth(struct ib_send_wr *wr)
2222 {
2223         switch (wr->opcode) {
2224         case IB_WR_SEND_WITH_IMM:
2225         case IB_WR_RDMA_WRITE_WITH_IMM:
2226                 return wr->ex.imm_data;
2227
2228         case IB_WR_SEND_WITH_INV:
2229                 return cpu_to_be32(wr->ex.invalidate_rkey);
2230
2231         default:
2232                 return 0;
2233         }
2234 }
2235
2236 static void add_zero_len_inline(void *wqe)
2237 {
2238         struct mlx4_wqe_inline_seg *inl = wqe;
2239         memset(wqe, 0, 16);
2240         inl->byte_count = cpu_to_be32(1 << 31);
2241 }
2242
2243 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2244                       struct ib_send_wr **bad_wr)
2245 {
2246         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2247         void *wqe;
2248         struct mlx4_wqe_ctrl_seg *ctrl;
2249         struct mlx4_wqe_data_seg *dseg;
2250         unsigned long flags;
2251         int nreq;
2252         int err = 0;
2253         unsigned ind;
2254         int uninitialized_var(stamp);
2255         int uninitialized_var(size);
2256         unsigned uninitialized_var(seglen);
2257         __be32 dummy;
2258         __be32 *lso_wqe;
2259         __be32 uninitialized_var(lso_hdr_sz);
2260         __be32 blh;
2261         int i;
2262
2263         spin_lock_irqsave(&qp->sq.lock, flags);
2264
2265         ind = qp->sq_next_wqe;
2266
2267         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2268                 lso_wqe = &dummy;
2269                 blh = 0;
2270
2271                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2272                         err = -ENOMEM;
2273                         *bad_wr = wr;
2274                         goto out;
2275                 }
2276
2277                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2278                         err = -EINVAL;
2279                         *bad_wr = wr;
2280                         goto out;
2281                 }
2282
2283                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
2284                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
2285
2286                 ctrl->srcrb_flags =
2287                         (wr->send_flags & IB_SEND_SIGNALED ?
2288                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2289                         (wr->send_flags & IB_SEND_SOLICITED ?
2290                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
2291                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
2292                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2293                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
2294                         qp->sq_signal_bits;
2295
2296                 ctrl->imm = send_ieth(wr);
2297
2298                 wqe += sizeof *ctrl;
2299                 size = sizeof *ctrl / 16;
2300
2301                 switch (qp->mlx4_ib_qp_type) {
2302                 case MLX4_IB_QPT_RC:
2303                 case MLX4_IB_QPT_UC:
2304                         switch (wr->opcode) {
2305                         case IB_WR_ATOMIC_CMP_AND_SWP:
2306                         case IB_WR_ATOMIC_FETCH_AND_ADD:
2307                         case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
2308                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2309                                               wr->wr.atomic.rkey);
2310                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2311
2312                                 set_atomic_seg(wqe, wr);
2313                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
2314
2315                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2316                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
2317
2318                                 break;
2319
2320                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2321                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2322                                               wr->wr.atomic.rkey);
2323                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2324
2325                                 set_masked_atomic_seg(wqe, wr);
2326                                 wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
2327
2328                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2329                                          sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
2330
2331                                 break;
2332
2333                         case IB_WR_RDMA_READ:
2334                         case IB_WR_RDMA_WRITE:
2335                         case IB_WR_RDMA_WRITE_WITH_IMM:
2336                                 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2337                                               wr->wr.rdma.rkey);
2338                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2339                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
2340                                 break;
2341
2342                         case IB_WR_LOCAL_INV:
2343                                 ctrl->srcrb_flags |=
2344                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2345                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2346                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
2347                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2348                                 break;
2349
2350                         case IB_WR_FAST_REG_MR:
2351                                 ctrl->srcrb_flags |=
2352                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2353                                 set_fmr_seg(wqe, wr);
2354                                 wqe  += sizeof (struct mlx4_wqe_fmr_seg);
2355                                 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
2356                                 break;
2357
2358                         case IB_WR_BIND_MW:
2359                                 ctrl->srcrb_flags |=
2360                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2361                                 set_bind_seg(wqe, wr);
2362                                 wqe  += sizeof(struct mlx4_wqe_bind_seg);
2363                                 size += sizeof(struct mlx4_wqe_bind_seg) / 16;
2364                                 break;
2365                         default:
2366                                 /* No extra segments required for sends */
2367                                 break;
2368                         }
2369                         break;
2370
2371                 case MLX4_IB_QPT_TUN_SMI_OWNER:
2372                         err =  build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2373                         if (unlikely(err)) {
2374                                 *bad_wr = wr;
2375                                 goto out;
2376                         }
2377                         wqe  += seglen;
2378                         size += seglen / 16;
2379                         break;
2380                 case MLX4_IB_QPT_TUN_SMI:
2381                 case MLX4_IB_QPT_TUN_GSI:
2382                         /* this is a UD qp used in MAD responses to slaves. */
2383                         set_datagram_seg(wqe, wr);
2384                         /* set the forced-loopback bit in the data seg av */
2385                         *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2386                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2387                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2388                         break;
2389                 case MLX4_IB_QPT_UD:
2390                         set_datagram_seg(wqe, wr);
2391                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2392                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2393
2394                         if (wr->opcode == IB_WR_LSO) {
2395                                 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
2396                                 if (unlikely(err)) {
2397                                         *bad_wr = wr;
2398                                         goto out;
2399                                 }
2400                                 lso_wqe = (__be32 *) wqe;
2401                                 wqe  += seglen;
2402                                 size += seglen / 16;
2403                         }
2404                         break;
2405
2406                 case MLX4_IB_QPT_PROXY_SMI_OWNER:
2407                         if (unlikely(!mlx4_is_master(to_mdev(ibqp->device)->dev))) {
2408                                 err = -ENOSYS;
2409                                 *bad_wr = wr;
2410                                 goto out;
2411                         }
2412                         err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2413                         if (unlikely(err)) {
2414                                 *bad_wr = wr;
2415                                 goto out;
2416                         }
2417                         wqe  += seglen;
2418                         size += seglen / 16;
2419                         /* to start tunnel header on a cache-line boundary */
2420                         add_zero_len_inline(wqe);
2421                         wqe += 16;
2422                         size++;
2423                         build_tunnel_header(wr, wqe, &seglen);
2424                         wqe  += seglen;
2425                         size += seglen / 16;
2426                         break;
2427                 case MLX4_IB_QPT_PROXY_SMI:
2428                         /* don't allow QP0 sends on guests */
2429                         err = -ENOSYS;
2430                         *bad_wr = wr;
2431                         goto out;
2432                 case MLX4_IB_QPT_PROXY_GSI:
2433                         /* If we are tunneling special qps, this is a UD qp.
2434                          * In this case we first add a UD segment targeting
2435                          * the tunnel qp, and then add a header with address
2436                          * information */
2437                         set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, wr, ibqp->qp_type);
2438                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2439                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2440                         build_tunnel_header(wr, wqe, &seglen);
2441                         wqe  += seglen;
2442                         size += seglen / 16;
2443                         break;
2444
2445                 case MLX4_IB_QPT_SMI:
2446                 case MLX4_IB_QPT_GSI:
2447                         err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
2448                         if (unlikely(err)) {
2449                                 *bad_wr = wr;
2450                                 goto out;
2451                         }
2452                         wqe  += seglen;
2453                         size += seglen / 16;
2454                         break;
2455
2456                 default:
2457                         break;
2458                 }
2459
2460                 /*
2461                  * Write data segments in reverse order, so as to
2462                  * overwrite cacheline stamp last within each
2463                  * cacheline.  This avoids issues with WQE
2464                  * prefetching.
2465                  */
2466
2467                 dseg = wqe;
2468                 dseg += wr->num_sge - 1;
2469                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
2470
2471                 /* Add one more inline data segment for ICRC for MLX sends */
2472                 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2473                              qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2474                              qp->mlx4_ib_qp_type &
2475                              (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
2476                         set_mlx_icrc_seg(dseg + 1);
2477                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
2478                 }
2479
2480                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2481                         set_data_seg(dseg, wr->sg_list + i);
2482
2483                 /*
2484                  * Possibly overwrite stamping in cacheline with LSO
2485                  * segment only after making sure all data segments
2486                  * are written.
2487                  */
2488                 wmb();
2489                 *lso_wqe = lso_hdr_sz;
2490
2491                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2492                                     MLX4_WQE_CTRL_FENCE : 0) | size;
2493
2494                 /*
2495                  * Make sure descriptor is fully written before
2496                  * setting ownership bit (because HW can start
2497                  * executing as soon as we do).
2498                  */
2499                 wmb();
2500
2501                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
2502                         *bad_wr = wr;
2503                         err = -EINVAL;
2504                         goto out;
2505                 }
2506
2507                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
2508                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
2509
2510                 stamp = ind + qp->sq_spare_wqes;
2511                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
2512
2513                 /*
2514                  * We can improve latency by not stamping the last
2515                  * send queue WQE until after ringing the doorbell, so
2516                  * only stamp here if there are still more WQEs to post.
2517                  *
2518                  * Same optimization applies to padding with NOP wqe
2519                  * in case of WQE shrinking (used to prevent wrap-around
2520                  * in the middle of WR).
2521                  */
2522                 if (wr->next) {
2523                         stamp_send_wqe(qp, stamp, size * 16);
2524                         ind = pad_wraparound(qp, ind);
2525                 }
2526         }
2527
2528 out:
2529         if (likely(nreq)) {
2530                 qp->sq.head += nreq;
2531
2532                 /*
2533                  * Make sure that descriptors are written before
2534                  * doorbell record.
2535                  */
2536                 wmb();
2537
2538                 writel(qp->doorbell_qpn,
2539                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
2540
2541                 /*
2542                  * Make sure doorbells don't leak out of SQ spinlock
2543                  * and reach the HCA out of order.
2544                  */
2545                 mmiowb();
2546
2547                 stamp_send_wqe(qp, stamp, size * 16);
2548
2549                 ind = pad_wraparound(qp, ind);
2550                 qp->sq_next_wqe = ind;
2551         }
2552
2553         spin_unlock_irqrestore(&qp->sq.lock, flags);
2554
2555         return err;
2556 }
2557
2558 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2559                       struct ib_recv_wr **bad_wr)
2560 {
2561         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2562         struct mlx4_wqe_data_seg *scat;
2563         unsigned long flags;
2564         int err = 0;
2565         int nreq;
2566         int ind;
2567         int max_gs;
2568         int i;
2569
2570         max_gs = qp->rq.max_gs;
2571         spin_lock_irqsave(&qp->rq.lock, flags);
2572
2573         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
2574
2575         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2576                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2577                         err = -ENOMEM;
2578                         *bad_wr = wr;
2579                         goto out;
2580                 }
2581
2582                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2583                         err = -EINVAL;
2584                         *bad_wr = wr;
2585                         goto out;
2586                 }
2587
2588                 scat = get_recv_wqe(qp, ind);
2589
2590                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
2591                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
2592                         ib_dma_sync_single_for_device(ibqp->device,
2593                                                       qp->sqp_proxy_rcv[ind].map,
2594                                                       sizeof (struct mlx4_ib_proxy_sqp_hdr),
2595                                                       DMA_FROM_DEVICE);
2596                         scat->byte_count =
2597                                 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
2598                         /* use dma lkey from upper layer entry */
2599                         scat->lkey = cpu_to_be32(wr->sg_list->lkey);
2600                         scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
2601                         scat++;
2602                         max_gs--;
2603                 }
2604
2605                 for (i = 0; i < wr->num_sge; ++i)
2606                         __set_data_seg(scat + i, wr->sg_list + i);
2607
2608                 if (i < max_gs) {
2609                         scat[i].byte_count = 0;
2610                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
2611                         scat[i].addr       = 0;
2612                 }
2613
2614                 qp->rq.wrid[ind] = wr->wr_id;
2615
2616                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
2617         }
2618
2619 out:
2620         if (likely(nreq)) {
2621                 qp->rq.head += nreq;
2622
2623                 /*
2624                  * Make sure that descriptors are written before
2625                  * doorbell record.
2626                  */
2627                 wmb();
2628
2629                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2630         }
2631
2632         spin_unlock_irqrestore(&qp->rq.lock, flags);
2633
2634         return err;
2635 }
2636
2637 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
2638 {
2639         switch (mlx4_state) {
2640         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
2641         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
2642         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
2643         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
2644         case MLX4_QP_STATE_SQ_DRAINING:
2645         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
2646         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
2647         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
2648         default:                     return -1;
2649         }
2650 }
2651
2652 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
2653 {
2654         switch (mlx4_mig_state) {
2655         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
2656         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
2657         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
2658         default: return -1;
2659         }
2660 }
2661
2662 static int to_ib_qp_access_flags(int mlx4_flags)
2663 {
2664         int ib_flags = 0;
2665
2666         if (mlx4_flags & MLX4_QP_BIT_RRE)
2667                 ib_flags |= IB_ACCESS_REMOTE_READ;
2668         if (mlx4_flags & MLX4_QP_BIT_RWE)
2669                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
2670         if (mlx4_flags & MLX4_QP_BIT_RAE)
2671                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
2672
2673         return ib_flags;
2674 }
2675
2676 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
2677                                 struct mlx4_qp_path *path)
2678 {
2679         struct mlx4_dev *dev = ibdev->dev;
2680         int is_eth;
2681
2682         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
2683         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
2684
2685         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
2686                 return;
2687
2688         is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
2689                 IB_LINK_LAYER_ETHERNET;
2690         if (is_eth)
2691                 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
2692                 ((path->sched_queue & 4) << 1);
2693         else
2694                 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
2695
2696         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
2697         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
2698         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
2699         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
2700         if (ib_ah_attr->ah_flags) {
2701                 ib_ah_attr->grh.sgid_index = path->mgid_index;
2702                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
2703                 ib_ah_attr->grh.traffic_class =
2704                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
2705                 ib_ah_attr->grh.flow_label =
2706                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
2707                 memcpy(ib_ah_attr->grh.dgid.raw,
2708                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
2709         }
2710 }
2711
2712 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
2713                      struct ib_qp_init_attr *qp_init_attr)
2714 {
2715         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2716         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2717         struct mlx4_qp_context context;
2718         int mlx4_state;
2719         int err = 0;
2720
2721         mutex_lock(&qp->mutex);
2722
2723         if (qp->state == IB_QPS_RESET) {
2724                 qp_attr->qp_state = IB_QPS_RESET;
2725                 goto done;
2726         }
2727
2728         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
2729         if (err) {
2730                 err = -EINVAL;
2731                 goto out;
2732         }
2733
2734         mlx4_state = be32_to_cpu(context.flags) >> 28;
2735
2736         qp->state                    = to_ib_qp_state(mlx4_state);
2737         qp_attr->qp_state            = qp->state;
2738         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
2739         qp_attr->path_mig_state      =
2740                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
2741         qp_attr->qkey                = be32_to_cpu(context.qkey);
2742         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
2743         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
2744         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
2745         qp_attr->qp_access_flags     =
2746                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
2747
2748         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
2749                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
2750                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
2751                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
2752                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
2753         }
2754
2755         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
2756         if (qp_attr->qp_state == IB_QPS_INIT)
2757                 qp_attr->port_num = qp->port;
2758         else
2759                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
2760
2761         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
2762         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
2763
2764         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
2765
2766         qp_attr->max_dest_rd_atomic =
2767                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
2768         qp_attr->min_rnr_timer      =
2769                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
2770         qp_attr->timeout            = context.pri_path.ackto >> 3;
2771         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
2772         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
2773         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
2774
2775 done:
2776         qp_attr->cur_qp_state        = qp_attr->qp_state;
2777         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
2778         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
2779
2780         if (!ibqp->uobject) {
2781                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
2782                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
2783         } else {
2784                 qp_attr->cap.max_send_wr  = 0;
2785                 qp_attr->cap.max_send_sge = 0;
2786         }
2787
2788         /*
2789          * We don't support inline sends for kernel QPs (yet), and we
2790          * don't know what userspace's value should be.
2791          */
2792         qp_attr->cap.max_inline_data = 0;
2793
2794         qp_init_attr->cap            = qp_attr->cap;
2795
2796         qp_init_attr->create_flags = 0;
2797         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2798                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
2799
2800         if (qp->flags & MLX4_IB_QP_LSO)
2801                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
2802
2803         if (qp->flags & MLX4_IB_QP_NETIF)
2804                 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
2805
2806         qp_init_attr->sq_sig_type =
2807                 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
2808                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
2809
2810 out:
2811         mutex_unlock(&qp->mutex);
2812         return err;
2813 }
2814