2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/kref.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_user_verbs.h>
36 #include <rdma/ib_cache.h>
40 static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq)
42 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
44 ibcq->comp_handler(ibcq, ibcq->cq_context);
47 static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type)
49 struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq);
50 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
51 struct ib_cq *ibcq = &cq->ibcq;
52 struct ib_event event;
54 if (type != MLX5_EVENT_TYPE_CQ_ERROR) {
55 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n",
60 if (ibcq->event_handler) {
61 event.device = &dev->ib_dev;
62 event.event = IB_EVENT_CQ_ERR;
63 event.element.cq = ibcq;
64 ibcq->event_handler(&event, ibcq->cq_context);
68 static void *get_cqe_from_buf(struct mlx5_ib_cq_buf *buf, int n, int size)
70 return mlx5_buf_offset(&buf->buf, n * size);
73 static void *get_cqe(struct mlx5_ib_cq *cq, int n)
75 return get_cqe_from_buf(&cq->buf, n, cq->mcq.cqe_sz);
78 static u8 sw_ownership_bit(int n, int nent)
80 return (n & nent) ? 1 : 0;
83 static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n)
85 void *cqe = get_cqe(cq, n & cq->ibcq.cqe);
86 struct mlx5_cqe64 *cqe64;
88 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
90 if (likely((cqe64->op_own) >> 4 != MLX5_CQE_INVALID) &&
91 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) {
98 static void *next_cqe_sw(struct mlx5_ib_cq *cq)
100 return get_sw_cqe(cq, cq->mcq.cons_index);
103 static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx)
105 switch (wq->wr_data[idx]) {
109 case IB_WR_LOCAL_INV:
110 return IB_WC_LOCAL_INV;
116 pr_warn("unknown completion status\n");
121 static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
122 struct mlx5_ib_wq *wq, int idx)
125 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {
126 case MLX5_OPCODE_RDMA_WRITE_IMM:
127 wc->wc_flags |= IB_WC_WITH_IMM;
128 case MLX5_OPCODE_RDMA_WRITE:
129 wc->opcode = IB_WC_RDMA_WRITE;
131 case MLX5_OPCODE_SEND_IMM:
132 wc->wc_flags |= IB_WC_WITH_IMM;
133 case MLX5_OPCODE_SEND:
134 case MLX5_OPCODE_SEND_INVAL:
135 wc->opcode = IB_WC_SEND;
137 case MLX5_OPCODE_RDMA_READ:
138 wc->opcode = IB_WC_RDMA_READ;
139 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
141 case MLX5_OPCODE_ATOMIC_CS:
142 wc->opcode = IB_WC_COMP_SWAP;
145 case MLX5_OPCODE_ATOMIC_FA:
146 wc->opcode = IB_WC_FETCH_ADD;
149 case MLX5_OPCODE_ATOMIC_MASKED_CS:
150 wc->opcode = IB_WC_MASKED_COMP_SWAP;
153 case MLX5_OPCODE_ATOMIC_MASKED_FA:
154 wc->opcode = IB_WC_MASKED_FETCH_ADD;
157 case MLX5_OPCODE_UMR:
158 wc->opcode = get_umr_comp(wq, idx);
164 MLX5_GRH_IN_BUFFER = 1,
168 static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
169 struct mlx5_ib_qp *qp)
171 enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1);
172 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
173 struct mlx5_ib_srq *srq;
174 struct mlx5_ib_wq *wq;
178 if (qp->ibqp.srq || qp->ibqp.xrcd) {
179 struct mlx5_core_srq *msrq = NULL;
182 msrq = mlx5_core_get_srq(dev->mdev,
183 be32_to_cpu(cqe->srqn));
184 srq = to_mibsrq(msrq);
186 srq = to_msrq(qp->ibqp.srq);
189 wqe_ctr = be16_to_cpu(cqe->wqe_counter);
190 wc->wr_id = srq->wrid[wqe_ctr];
191 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
192 if (msrq && atomic_dec_and_test(&msrq->refcount))
193 complete(&msrq->free);
197 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
200 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
202 switch (cqe->op_own >> 4) {
203 case MLX5_CQE_RESP_WR_IMM:
204 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
205 wc->wc_flags = IB_WC_WITH_IMM;
206 wc->ex.imm_data = cqe->imm_inval_pkey;
208 case MLX5_CQE_RESP_SEND:
209 wc->opcode = IB_WC_RECV;
210 wc->wc_flags = IB_WC_IP_CSUM_OK;
211 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) &&
212 (cqe->hds_ip_ext & CQE_L4_OK))))
215 case MLX5_CQE_RESP_SEND_IMM:
216 wc->opcode = IB_WC_RECV;
217 wc->wc_flags = IB_WC_WITH_IMM;
218 wc->ex.imm_data = cqe->imm_inval_pkey;
220 case MLX5_CQE_RESP_SEND_INV:
221 wc->opcode = IB_WC_RECV;
222 wc->wc_flags = IB_WC_WITH_INVALIDATE;
223 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey);
226 wc->slid = be16_to_cpu(cqe->slid);
227 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf;
228 wc->src_qp = be32_to_cpu(cqe->flags_rqpn) & 0xffffff;
229 wc->dlid_path_bits = cqe->ml_path;
230 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
231 wc->wc_flags |= g ? IB_WC_GRH : 0;
232 if (unlikely(is_qp1(qp->ibqp.qp_type))) {
233 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff;
235 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey,
241 if (ll != IB_LINK_LAYER_ETHERNET)
244 switch (wc->sl & 0x3) {
245 case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH:
246 wc->network_hdr_type = RDMA_NETWORK_IB;
248 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6:
249 wc->network_hdr_type = RDMA_NETWORK_IPV6;
251 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4:
252 wc->network_hdr_type = RDMA_NETWORK_IPV4;
255 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
258 static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe)
260 __be32 *p = (__be32 *)cqe;
263 mlx5_ib_warn(dev, "dump error cqe\n");
264 for (i = 0; i < sizeof(*cqe) / 16; i++, p += 4)
265 pr_info("%08x %08x %08x %08x\n", be32_to_cpu(p[0]),
266 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
270 static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev,
271 struct mlx5_err_cqe *cqe,
276 switch (cqe->syndrome) {
277 case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR:
278 wc->status = IB_WC_LOC_LEN_ERR;
280 case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR:
281 wc->status = IB_WC_LOC_QP_OP_ERR;
283 case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR:
284 wc->status = IB_WC_LOC_PROT_ERR;
286 case MLX5_CQE_SYNDROME_WR_FLUSH_ERR:
288 wc->status = IB_WC_WR_FLUSH_ERR;
290 case MLX5_CQE_SYNDROME_MW_BIND_ERR:
291 wc->status = IB_WC_MW_BIND_ERR;
293 case MLX5_CQE_SYNDROME_BAD_RESP_ERR:
294 wc->status = IB_WC_BAD_RESP_ERR;
296 case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR:
297 wc->status = IB_WC_LOC_ACCESS_ERR;
299 case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
300 wc->status = IB_WC_REM_INV_REQ_ERR;
302 case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR:
303 wc->status = IB_WC_REM_ACCESS_ERR;
305 case MLX5_CQE_SYNDROME_REMOTE_OP_ERR:
306 wc->status = IB_WC_REM_OP_ERR;
308 case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
309 wc->status = IB_WC_RETRY_EXC_ERR;
312 case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
313 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
316 case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR:
317 wc->status = IB_WC_REM_ABORT_ERR;
320 wc->status = IB_WC_GENERAL_ERR;
324 wc->vendor_err = cqe->vendor_err_synd;
329 static int is_atomic_response(struct mlx5_ib_qp *qp, uint16_t idx)
331 /* TBD: waiting decision
336 static void *mlx5_get_atomic_laddr(struct mlx5_ib_qp *qp, uint16_t idx)
338 struct mlx5_wqe_data_seg *dpseg;
341 dpseg = mlx5_get_send_wqe(qp, idx) + sizeof(struct mlx5_wqe_ctrl_seg) +
342 sizeof(struct mlx5_wqe_raddr_seg) +
343 sizeof(struct mlx5_wqe_atomic_seg);
344 addr = (void *)(unsigned long)be64_to_cpu(dpseg->addr);
348 static void handle_atomic(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
355 if (!is_atomic_response(qp, idx))
358 byte_count = be32_to_cpu(cqe64->byte_cnt);
359 addr = mlx5_get_atomic_laddr(qp, idx);
361 if (byte_count == 4) {
362 *(uint32_t *)addr = be32_to_cpu(*((__be32 *)addr));
364 for (i = 0; i < byte_count; i += 8) {
365 *(uint64_t *)addr = be64_to_cpu(*((__be64 *)addr));
373 static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
379 idx = tail & (qp->sq.wqe_cnt - 1);
380 handle_atomic(qp, cqe64, idx);
384 tail = qp->sq.w_list[idx].next;
386 tail = qp->sq.w_list[idx].next;
387 qp->sq.last_poll = tail;
390 static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf)
392 mlx5_buf_free(dev->mdev, &buf->buf);
395 static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe,
396 struct ib_sig_err *item)
398 u16 syndrome = be16_to_cpu(cqe->syndrome);
400 #define GUARD_ERR (1 << 13)
401 #define APPTAG_ERR (1 << 12)
402 #define REFTAG_ERR (1 << 11)
404 if (syndrome & GUARD_ERR) {
405 item->err_type = IB_SIG_BAD_GUARD;
406 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16;
407 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16;
409 if (syndrome & REFTAG_ERR) {
410 item->err_type = IB_SIG_BAD_REFTAG;
411 item->expected = be32_to_cpu(cqe->expected_reftag);
412 item->actual = be32_to_cpu(cqe->actual_reftag);
414 if (syndrome & APPTAG_ERR) {
415 item->err_type = IB_SIG_BAD_APPTAG;
416 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff;
417 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff;
419 pr_err("Got signature completion error with bad syndrome %04x\n",
423 item->sig_err_offset = be64_to_cpu(cqe->err_offset);
424 item->key = be32_to_cpu(cqe->mkey);
427 static void sw_send_comp(struct mlx5_ib_qp *qp, int num_entries,
428 struct ib_wc *wc, int *npolled)
430 struct mlx5_ib_wq *wq;
437 cur = wq->head - wq->tail;
443 for (i = 0; i < cur && np < num_entries; i++) {
444 idx = wq->last_poll & (wq->wqe_cnt - 1);
445 wc->wr_id = wq->wrid[idx];
446 wc->status = IB_WC_WR_FLUSH_ERR;
447 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
452 wq->last_poll = wq->w_list[idx].next;
457 static void sw_recv_comp(struct mlx5_ib_qp *qp, int num_entries,
458 struct ib_wc *wc, int *npolled)
460 struct mlx5_ib_wq *wq;
466 cur = wq->head - wq->tail;
472 for (i = 0; i < cur && np < num_entries; i++) {
473 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
474 wc->status = IB_WC_WR_FLUSH_ERR;
475 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
484 static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries,
485 struct ib_wc *wc, int *npolled)
487 struct mlx5_ib_qp *qp;
490 /* Find uncompleted WQEs belonging to that cq and retrun mmics ones */
491 list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) {
492 sw_send_comp(qp, num_entries, wc + *npolled, npolled);
493 if (*npolled >= num_entries)
497 list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) {
498 sw_recv_comp(qp, num_entries, wc + *npolled, npolled);
499 if (*npolled >= num_entries)
504 static int mlx5_poll_one(struct mlx5_ib_cq *cq,
505 struct mlx5_ib_qp **cur_qp,
508 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
509 struct mlx5_err_cqe *err_cqe;
510 struct mlx5_cqe64 *cqe64;
511 struct mlx5_core_qp *mqp;
512 struct mlx5_ib_wq *wq;
513 struct mlx5_sig_err_cqe *sig_err_cqe;
514 struct mlx5_core_mkey *mmkey;
515 struct mlx5_ib_mr *mr;
523 cqe = next_cqe_sw(cq);
527 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
529 ++cq->mcq.cons_index;
531 /* Make sure we read CQ entry contents after we've checked the
536 opcode = cqe64->op_own >> 4;
537 if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) {
538 if (likely(cq->resize_buf)) {
539 free_cq_buf(dev, &cq->buf);
540 cq->buf = *cq->resize_buf;
541 kfree(cq->resize_buf);
542 cq->resize_buf = NULL;
545 mlx5_ib_warn(dev, "unexpected resize cqe\n");
549 qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff;
550 if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) {
551 /* We do not have to take the QP table lock here,
552 * because CQs will be locked while QPs are removed
555 mqp = __mlx5_qp_lookup(dev->mdev, qpn);
556 *cur_qp = to_mibqp(mqp);
559 wc->qp = &(*cur_qp)->ibqp;
563 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
564 idx = wqe_ctr & (wq->wqe_cnt - 1);
565 handle_good_req(wc, cqe64, wq, idx);
566 handle_atomics(*cur_qp, cqe64, wq->last_poll, idx);
567 wc->wr_id = wq->wrid[idx];
568 wq->tail = wq->wqe_head[idx] + 1;
569 wc->status = IB_WC_SUCCESS;
571 case MLX5_CQE_RESP_WR_IMM:
572 case MLX5_CQE_RESP_SEND:
573 case MLX5_CQE_RESP_SEND_IMM:
574 case MLX5_CQE_RESP_SEND_INV:
575 handle_responder(wc, cqe64, *cur_qp);
576 wc->status = IB_WC_SUCCESS;
578 case MLX5_CQE_RESIZE_CQ:
580 case MLX5_CQE_REQ_ERR:
581 case MLX5_CQE_RESP_ERR:
582 err_cqe = (struct mlx5_err_cqe *)cqe64;
583 mlx5_handle_error_cqe(dev, err_cqe, wc);
584 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n",
585 opcode == MLX5_CQE_REQ_ERR ?
586 "Requestor" : "Responder", cq->mcq.cqn);
587 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n",
588 err_cqe->syndrome, err_cqe->vendor_err_synd);
589 if (opcode == MLX5_CQE_REQ_ERR) {
591 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
592 idx = wqe_ctr & (wq->wqe_cnt - 1);
593 wc->wr_id = wq->wrid[idx];
594 wq->tail = wq->wqe_head[idx] + 1;
596 struct mlx5_ib_srq *srq;
598 if ((*cur_qp)->ibqp.srq) {
599 srq = to_msrq((*cur_qp)->ibqp.srq);
600 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
601 wc->wr_id = srq->wrid[wqe_ctr];
602 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
605 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
610 case MLX5_CQE_SIG_ERR:
611 sig_err_cqe = (struct mlx5_sig_err_cqe *)cqe64;
613 read_lock(&dev->mdev->priv.mkey_table.lock);
614 mmkey = __mlx5_mr_lookup(dev->mdev,
615 mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey)));
616 mr = to_mibmr(mmkey);
617 get_sig_err_item(sig_err_cqe, &mr->sig->err_item);
618 mr->sig->sig_err_exists = true;
619 mr->sig->sigerr_count++;
621 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n",
622 cq->mcq.cqn, mr->sig->err_item.key,
623 mr->sig->err_item.err_type,
624 mr->sig->err_item.sig_err_offset,
625 mr->sig->err_item.expected,
626 mr->sig->err_item.actual);
628 read_unlock(&dev->mdev->priv.mkey_table.lock);
635 static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries,
638 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
639 struct mlx5_ib_wc *soft_wc, *next;
642 list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) {
643 if (npolled >= num_entries)
646 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n",
649 wc[npolled++] = soft_wc->wc;
650 list_del(&soft_wc->list);
657 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
659 struct mlx5_ib_cq *cq = to_mcq(ibcq);
660 struct mlx5_ib_qp *cur_qp = NULL;
661 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
662 struct mlx5_core_dev *mdev = dev->mdev;
667 spin_lock_irqsave(&cq->lock, flags);
668 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
669 mlx5_ib_poll_sw_comp(cq, num_entries, wc, &npolled);
673 if (unlikely(!list_empty(&cq->wc_list)))
674 soft_polled = poll_soft_wc(cq, num_entries, wc);
676 for (npolled = 0; npolled < num_entries - soft_polled; npolled++) {
677 if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled))
682 mlx5_cq_set_ci(&cq->mcq);
684 spin_unlock_irqrestore(&cq->lock, flags);
686 return soft_polled + npolled;
689 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
691 struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev;
692 struct mlx5_ib_cq *cq = to_mcq(ibcq);
693 void __iomem *uar_page = mdev->priv.uuari.uars[0].map;
694 unsigned long irq_flags;
697 spin_lock_irqsave(&cq->lock, irq_flags);
698 if (cq->notify_flags != IB_CQ_NEXT_COMP)
699 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK;
701 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list))
703 spin_unlock_irqrestore(&cq->lock, irq_flags);
705 mlx5_cq_arm(&cq->mcq,
706 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
707 MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT,
709 MLX5_GET_DOORBELL_LOCK(&mdev->priv.cq_uar_lock),
710 to_mcq(ibcq)->mcq.cons_index);
715 static int alloc_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf,
716 int nent, int cqe_size)
720 err = mlx5_buf_alloc(dev->mdev, nent * cqe_size, &buf->buf);
724 buf->cqe_size = cqe_size;
730 static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
731 struct ib_ucontext *context, struct mlx5_ib_cq *cq,
732 int entries, u32 **cqb,
733 int *cqe_size, int *index, int *inlen)
735 struct mlx5_ib_create_cq ucmd;
745 (udata->inlen - sizeof(struct ib_uverbs_cmd_hdr) <
746 sizeof(ucmd)) ? (sizeof(ucmd) -
747 sizeof(ucmd.reserved)) : sizeof(ucmd);
749 if (ib_copy_from_udata(&ucmd, udata, ucmdlen))
752 if (ucmdlen == sizeof(ucmd) &&
756 if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128)
759 *cqe_size = ucmd.cqe_size;
761 cq->buf.umem = ib_umem_get(context, ucmd.buf_addr,
762 entries * ucmd.cqe_size,
763 IB_ACCESS_LOCAL_WRITE, 1);
764 if (IS_ERR(cq->buf.umem)) {
765 err = PTR_ERR(cq->buf.umem);
769 err = mlx5_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
774 mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, &npages, &page_shift,
776 mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n",
777 ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont);
779 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
780 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * ncont;
781 *cqb = mlx5_vzalloc(*inlen);
787 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
788 mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, pas, 0);
790 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
791 MLX5_SET(cqc, cqc, log_page_size,
792 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
794 *index = to_mucontext(context)->uuari.uars[0].index;
799 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
802 ib_umem_release(cq->buf.umem);
806 static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_ucontext *context)
808 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
809 ib_umem_release(cq->buf.umem);
812 static void init_cq_buf(struct mlx5_ib_cq *cq, struct mlx5_ib_cq_buf *buf)
816 struct mlx5_cqe64 *cqe64;
818 for (i = 0; i < buf->nent; i++) {
819 cqe = get_cqe_from_buf(buf, i, buf->cqe_size);
820 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64;
821 cqe64->op_own = MLX5_CQE_INVALID << 4;
825 static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
826 int entries, int cqe_size,
827 u32 **cqb, int *index, int *inlen)
833 err = mlx5_db_alloc(dev->mdev, &cq->db);
837 cq->mcq.set_ci_db = cq->db.db;
838 cq->mcq.arm_db = cq->db.db + 1;
839 cq->mcq.cqe_sz = cqe_size;
841 err = alloc_cq_buf(dev, &cq->buf, entries, cqe_size);
845 init_cq_buf(cq, &cq->buf);
847 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
848 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * cq->buf.buf.npages;
849 *cqb = mlx5_vzalloc(*inlen);
855 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
856 mlx5_fill_page_array(&cq->buf.buf, pas);
858 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
859 MLX5_SET(cqc, cqc, log_page_size,
860 cq->buf.buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
862 *index = dev->mdev->priv.uuari.uars[0].index;
867 free_cq_buf(dev, &cq->buf);
870 mlx5_db_free(dev->mdev, &cq->db);
874 static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
876 free_cq_buf(dev, &cq->buf);
877 mlx5_db_free(dev->mdev, &cq->db);
880 static void notify_soft_wc_handler(struct work_struct *work)
882 struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq,
885 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
888 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
889 const struct ib_cq_init_attr *attr,
890 struct ib_ucontext *context,
891 struct ib_udata *udata)
893 int entries = attr->cqe;
894 int vector = attr->comp_vector;
895 struct mlx5_ib_dev *dev = to_mdev(ibdev);
896 struct mlx5_ib_cq *cq;
897 int uninitialized_var(index);
898 int uninitialized_var(inlen);
907 (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))))
908 return ERR_PTR(-EINVAL);
910 if (check_cq_create_flags(attr->flags))
911 return ERR_PTR(-EOPNOTSUPP);
913 entries = roundup_pow_of_two(entries + 1);
914 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))
915 return ERR_PTR(-EINVAL);
917 cq = kzalloc(sizeof(*cq), GFP_KERNEL);
919 return ERR_PTR(-ENOMEM);
921 cq->ibcq.cqe = entries - 1;
922 mutex_init(&cq->resize_mutex);
923 spin_lock_init(&cq->lock);
924 cq->resize_buf = NULL;
925 cq->resize_umem = NULL;
926 cq->create_flags = attr->flags;
927 INIT_LIST_HEAD(&cq->list_send_qp);
928 INIT_LIST_HEAD(&cq->list_recv_qp);
931 err = create_cq_user(dev, udata, context, cq, entries,
932 &cqb, &cqe_size, &index, &inlen);
936 /* for now choose 64 bytes till we have a proper interface */
938 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb,
943 INIT_WORK(&cq->notify_work, notify_soft_wc_handler);
946 err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn);
950 cq->cqe_size = cqe_size;
952 cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context);
953 MLX5_SET(cqc, cqc, cqe_sz, cqe_sz_to_mlx_sz(cqe_size));
954 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
955 MLX5_SET(cqc, cqc, uar_page, index);
956 MLX5_SET(cqc, cqc, c_eqn, eqn);
957 MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma);
958 if (cq->create_flags & IB_CQ_FLAGS_IGNORE_OVERRUN)
959 MLX5_SET(cqc, cqc, oi, 1);
961 err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen);
965 mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn);
968 cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp;
970 cq->mcq.comp = mlx5_ib_cq_comp;
971 cq->mcq.event = mlx5_ib_cq_event;
973 INIT_LIST_HEAD(&cq->wc_list);
976 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) {
986 mlx5_core_destroy_cq(dev->mdev, &cq->mcq);
991 destroy_cq_user(cq, context);
993 destroy_cq_kernel(dev, cq);
1002 int mlx5_ib_destroy_cq(struct ib_cq *cq)
1004 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1005 struct mlx5_ib_cq *mcq = to_mcq(cq);
1006 struct ib_ucontext *context = NULL;
1009 context = cq->uobject->context;
1011 mlx5_core_destroy_cq(dev->mdev, &mcq->mcq);
1013 destroy_cq_user(mcq, context);
1015 destroy_cq_kernel(dev, mcq);
1022 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn)
1024 return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff);
1027 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq)
1029 struct mlx5_cqe64 *cqe64, *dest64;
1038 /* First we need to find the current producer index, so we
1039 * know where to start cleaning from. It doesn't matter if HW
1040 * adds new entries after this loop -- the QP we're worried
1041 * about is already in RESET, so the new entries won't come
1042 * from our QP and therefore don't need to be checked.
1044 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++)
1045 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
1048 /* Now sweep backwards through the CQ, removing CQ entries
1049 * that match our QP by copying older entries on top of them.
1051 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
1052 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
1053 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
1054 if (is_equal_rsn(cqe64, rsn)) {
1055 if (srq && (ntohl(cqe64->srqn) & 0xffffff))
1056 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter));
1058 } else if (nfreed) {
1059 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
1060 dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64;
1061 owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK;
1062 memcpy(dest, cqe, cq->mcq.cqe_sz);
1063 dest64->op_own = owner_bit |
1064 (dest64->op_own & ~MLX5_CQE_OWNER_MASK);
1069 cq->mcq.cons_index += nfreed;
1070 /* Make sure update of buffer contents is done before
1071 * updating consumer index.
1074 mlx5_cq_set_ci(&cq->mcq);
1078 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq)
1083 spin_lock_irq(&cq->lock);
1084 __mlx5_ib_cq_clean(cq, qpn, srq);
1085 spin_unlock_irq(&cq->lock);
1088 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
1090 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1091 struct mlx5_ib_cq *mcq = to_mcq(cq);
1094 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation))
1097 err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq,
1098 cq_period, cq_count);
1100 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn);
1105 static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1106 int entries, struct ib_udata *udata, int *npas,
1107 int *page_shift, int *cqe_size)
1109 struct mlx5_ib_resize_cq ucmd;
1110 struct ib_umem *umem;
1113 struct ib_ucontext *context = cq->buf.umem->context;
1115 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
1119 if (ucmd.reserved0 || ucmd.reserved1)
1122 umem = ib_umem_get(context, ucmd.buf_addr, entries * ucmd.cqe_size,
1123 IB_ACCESS_LOCAL_WRITE, 1);
1125 err = PTR_ERR(umem);
1129 mlx5_ib_cont_pages(umem, ucmd.buf_addr, &npages, page_shift,
1132 cq->resize_umem = umem;
1133 *cqe_size = ucmd.cqe_size;
1138 static void un_resize_user(struct mlx5_ib_cq *cq)
1140 ib_umem_release(cq->resize_umem);
1143 static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1144 int entries, int cqe_size)
1148 cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL);
1149 if (!cq->resize_buf)
1152 err = alloc_cq_buf(dev, cq->resize_buf, entries, cqe_size);
1156 init_cq_buf(cq, cq->resize_buf);
1161 kfree(cq->resize_buf);
1165 static void un_resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
1167 free_cq_buf(dev, cq->resize_buf);
1168 cq->resize_buf = NULL;
1171 static int copy_resize_cqes(struct mlx5_ib_cq *cq)
1173 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
1174 struct mlx5_cqe64 *scqe64;
1175 struct mlx5_cqe64 *dcqe64;
1184 ssize = cq->buf.cqe_size;
1185 dsize = cq->resize_buf->cqe_size;
1186 if (ssize != dsize) {
1187 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n");
1191 i = cq->mcq.cons_index;
1192 scqe = get_sw_cqe(cq, i);
1193 scqe64 = ssize == 64 ? scqe : scqe + 64;
1196 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1200 while ((scqe64->op_own >> 4) != MLX5_CQE_RESIZE_CQ) {
1201 dcqe = get_cqe_from_buf(cq->resize_buf,
1202 (i + 1) & (cq->resize_buf->nent),
1204 dcqe64 = dsize == 64 ? dcqe : dcqe + 64;
1205 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent);
1206 memcpy(dcqe, scqe, dsize);
1207 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own;
1210 scqe = get_sw_cqe(cq, i);
1211 scqe64 = ssize == 64 ? scqe : scqe + 64;
1213 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1217 if (scqe == start_cqe) {
1218 pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n",
1223 ++cq->mcq.cons_index;
1227 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
1229 struct mlx5_ib_dev *dev = to_mdev(ibcq->device);
1230 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1238 int uninitialized_var(cqe_size);
1239 unsigned long flags;
1241 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) {
1242 pr_info("Firmware does not support resize CQ\n");
1247 entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) {
1248 mlx5_ib_warn(dev, "wrong entries number %d, max %d\n",
1250 1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz));
1254 entries = roundup_pow_of_two(entries + 1);
1255 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1)
1258 if (entries == ibcq->cqe + 1)
1261 mutex_lock(&cq->resize_mutex);
1263 err = resize_user(dev, cq, entries, udata, &npas, &page_shift,
1267 err = resize_kernel(dev, cq, entries, cqe_size);
1269 npas = cq->resize_buf->buf.npages;
1270 page_shift = cq->resize_buf->buf.page_shift;
1277 inlen = MLX5_ST_SZ_BYTES(modify_cq_in) +
1278 MLX5_FLD_SZ_BYTES(modify_cq_in, pas[0]) * npas;
1280 in = mlx5_vzalloc(inlen);
1286 pas = (__be64 *)MLX5_ADDR_OF(modify_cq_in, in, pas);
1288 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift,
1291 mlx5_fill_page_array(&cq->resize_buf->buf, pas);
1293 MLX5_SET(modify_cq_in, in,
1294 modify_field_select_resize_field_select.resize_field_select.resize_field_select,
1295 MLX5_MODIFY_CQ_MASK_LOG_SIZE |
1296 MLX5_MODIFY_CQ_MASK_PG_OFFSET |
1297 MLX5_MODIFY_CQ_MASK_PG_SIZE);
1299 cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context);
1301 MLX5_SET(cqc, cqc, log_page_size,
1302 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1303 MLX5_SET(cqc, cqc, cqe_sz, cqe_sz_to_mlx_sz(cqe_size));
1304 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1306 MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE);
1307 MLX5_SET(modify_cq_in, in, cqn, cq->mcq.cqn);
1309 err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen);
1314 cq->ibcq.cqe = entries - 1;
1315 ib_umem_release(cq->buf.umem);
1316 cq->buf.umem = cq->resize_umem;
1317 cq->resize_umem = NULL;
1319 struct mlx5_ib_cq_buf tbuf;
1322 spin_lock_irqsave(&cq->lock, flags);
1323 if (cq->resize_buf) {
1324 err = copy_resize_cqes(cq);
1327 cq->buf = *cq->resize_buf;
1328 kfree(cq->resize_buf);
1329 cq->resize_buf = NULL;
1333 cq->ibcq.cqe = entries - 1;
1334 spin_unlock_irqrestore(&cq->lock, flags);
1336 free_cq_buf(dev, &tbuf);
1338 mutex_unlock(&cq->resize_mutex);
1350 un_resize_kernel(dev, cq);
1352 mutex_unlock(&cq->resize_mutex);
1356 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq)
1358 struct mlx5_ib_cq *cq;
1364 return cq->cqe_size;
1367 /* Called from atomic context */
1368 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc)
1370 struct mlx5_ib_wc *soft_wc;
1371 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1372 unsigned long flags;
1374 soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC);
1379 spin_lock_irqsave(&cq->lock, flags);
1380 list_add_tail(&soft_wc->list, &cq->wc_list);
1381 if (cq->notify_flags == IB_CQ_NEXT_COMP ||
1382 wc->status != IB_WC_SUCCESS) {
1383 cq->notify_flags = 0;
1384 schedule_work(&cq->notify_work);
1386 spin_unlock_irqrestore(&cq->lock, flags);