drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/init.h>
  36 #include <linux/errno.h>
  37 #include <linux/pci.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/slab.h>
  40 #include <linux/io-mapping.h>
  41 #include <linux/sched.h>
  42 #include <rdma/ib_user_verbs.h>
  43 #include <rdma/ib_addr.h>
  44 #include <rdma/ib_cache.h>
  45 #include <linux/mlx5/vport.h>
  46 #include <rdma/ib_smi.h>
  47 #include <rdma/ib_umem.h>
  48 #include <linux/in.h>
  49 #include <linux/etherdevice.h>
  50 #include <linux/mlx5/fs.h>
  51 #include "user.h"
  52 #include "mlx5_ib.h"
  53
  54 #define DRIVER_NAME "mlx5_ib"
  55 #define DRIVER_VERSION "2.2-1"
  56 #define DRIVER_RELDATE  "Feb 2014"
  57
  58 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  59 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  60 MODULE_LICENSE("Dual BSD/GPL");
  61 MODULE_VERSION(DRIVER_VERSION);
  62
  63 static int deprecated_prof_sel = 2;
  64 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
  65 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
  66
  67 static char mlx5_version[] =
  68         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  69         DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  70
  71 enum {
  72         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  73 };
  74
  75 static enum rdma_link_layer
  76 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  77 {
  78         switch (port_type_cap) {
  79         case MLX5_CAP_PORT_TYPE_IB:
  80                 return IB_LINK_LAYER_INFINIBAND;
  81         case MLX5_CAP_PORT_TYPE_ETH:
  82                 return IB_LINK_LAYER_ETHERNET;
  83         default:
  84                 return IB_LINK_LAYER_UNSPECIFIED;
  85         }
  86 }
  87
  88 static enum rdma_link_layer
  89 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
  90 {
  91         struct mlx5_ib_dev *dev = to_mdev(device);
  92         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
  93
  94         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
  95 }
  96
  97 static int mlx5_netdev_event(struct notifier_block *this,
  98                              unsigned long event, void *ptr)
  99 {
 100         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 101         struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
 102                                                  roce.nb);
 103
 104         if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER))
 105                 return NOTIFY_DONE;
 106
 107         write_lock(&ibdev->roce.netdev_lock);
 108         if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
 109                 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev;
 110         write_unlock(&ibdev->roce.netdev_lock);
 111
 112         return NOTIFY_DONE;
 113 }
 114
 115 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 116                                              u8 port_num)
 117 {
 118         struct mlx5_ib_dev *ibdev = to_mdev(device);
 119         struct net_device *ndev;
 120
 121         /* Ensure ndev does not disappear before we invoke dev_hold()
 122          */
 123         read_lock(&ibdev->roce.netdev_lock);
 124         ndev = ibdev->roce.netdev;
 125         if (ndev)
 126                 dev_hold(ndev);
 127         read_unlock(&ibdev->roce.netdev_lock);
 128
 129         return ndev;
 130 }
 131
 132 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 133                                 struct ib_port_attr *props)
 134 {
 135         struct mlx5_ib_dev *dev = to_mdev(device);
 136         struct net_device *ndev;
 137         enum ib_mtu ndev_ib_mtu;
 138         u16 qkey_viol_cntr;
 139
 140         memset(props, 0, sizeof(*props));
 141
 142         props->port_cap_flags  |= IB_PORT_CM_SUP;
 143         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 144
 145         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 146                                                 roce_address_table_size);
 147         props->max_mtu          = IB_MTU_4096;
 148         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 149         props->pkey_tbl_len     = 1;
 150         props->state            = IB_PORT_DOWN;
 151         props->phys_state       = 3;
 152
 153         mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
 154         props->qkey_viol_cntr = qkey_viol_cntr;
 155
 156         ndev = mlx5_ib_get_netdev(device, port_num);
 157         if (!ndev)
 158                 return 0;
 159
 160         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 161                 props->state      = IB_PORT_ACTIVE;
 162                 props->phys_state = 5;
 163         }
 164
 165         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 166
 167         dev_put(ndev);
 168
 169         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 170
 171         props->active_width     = IB_WIDTH_4X;  /* TODO */
 172         props->active_speed     = IB_SPEED_QDR; /* TODO */
 173
 174         return 0;
 175 }
 176
 177 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
 178                                      const struct ib_gid_attr *attr,
 179                                      void *mlx5_addr)
 180 {
 181 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
 182         char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 183                                                source_l3_address);
 184         void *mlx5_addr_mac     = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 185                                                source_mac_47_32);
 186
 187         if (!gid)
 188                 return;
 189
 190         ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
 191
 192         if (is_vlan_dev(attr->ndev)) {
 193                 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
 194                 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
 195         }
 196
 197         switch (attr->gid_type) {
 198         case IB_GID_TYPE_IB:
 199                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
 200                 break;
 201         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 202                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
 203                 break;
 204
 205         default:
 206                 WARN_ON(true);
 207         }
 208
 209         if (attr->gid_type != IB_GID_TYPE_IB) {
 210                 if (ipv6_addr_v4mapped((void *)gid))
 211                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 212                                     MLX5_ROCE_L3_TYPE_IPV4);
 213                 else
 214                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 215                                     MLX5_ROCE_L3_TYPE_IPV6);
 216         }
 217
 218         if ((attr->gid_type == IB_GID_TYPE_IB) ||
 219             !ipv6_addr_v4mapped((void *)gid))
 220                 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
 221         else
 222                 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
 223 }
 224
 225 static int set_roce_addr(struct ib_device *device, u8 port_num,
 226                          unsigned int index,
 227                          const union ib_gid *gid,
 228                          const struct ib_gid_attr *attr)
 229 {
 230         struct mlx5_ib_dev *dev = to_mdev(device);
 231         u32  in[MLX5_ST_SZ_DW(set_roce_address_in)];
 232         u32 out[MLX5_ST_SZ_DW(set_roce_address_out)];
 233         void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
 234         enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
 235
 236         if (ll != IB_LINK_LAYER_ETHERNET)
 237                 return -EINVAL;
 238
 239         memset(in, 0, sizeof(in));
 240
 241         ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
 242
 243         MLX5_SET(set_roce_address_in, in, roce_address_index, index);
 244         MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
 245
 246         memset(out, 0, sizeof(out));
 247         return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
 248 }
 249
 250 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
 251                            unsigned int index, const union ib_gid *gid,
 252                            const struct ib_gid_attr *attr,
 253                            __always_unused void **context)
 254 {
 255         return set_roce_addr(device, port_num, index, gid, attr);
 256 }
 257
 258 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
 259                            unsigned int index, __always_unused void **context)
 260 {
 261         return set_roce_addr(device, port_num, index, NULL, NULL);
 262 }
 263
 264 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 265                                int index)
 266 {
 267         struct ib_gid_attr attr;
 268         union ib_gid gid;
 269
 270         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 271                 return 0;
 272
 273         if (!attr.ndev)
 274                 return 0;
 275
 276         dev_put(attr.ndev);
 277
 278         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 279                 return 0;
 280
 281         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 282 }
 283
 284 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 285 {
 286         return !dev->mdev->issi;
 287 }
 288
 289 enum {
 290         MLX5_VPORT_ACCESS_METHOD_MAD,
 291         MLX5_VPORT_ACCESS_METHOD_HCA,
 292         MLX5_VPORT_ACCESS_METHOD_NIC,
 293 };
 294
 295 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 296 {
 297         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 298                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 299
 300         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 301             IB_LINK_LAYER_ETHERNET)
 302                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 303
 304         return MLX5_VPORT_ACCESS_METHOD_HCA;
 305 }
 306
 307 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 308                             struct ib_device_attr *props)
 309 {
 310         u8 tmp;
 311         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 312         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 313         u8 atomic_req_8B_endianness_mode =
 314                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
 315
 316         /* Check if HW supports 8 bytes standard atomic operations and capable
 317          * of host endianness respond
 318          */
 319         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 320         if (((atomic_operations & tmp) == tmp) &&
 321             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 322             (atomic_req_8B_endianness_mode)) {
 323                 props->atomic_cap = IB_ATOMIC_HCA;
 324         } else {
 325                 props->atomic_cap = IB_ATOMIC_NONE;
 326         }
 327 }
 328
 329 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 330                                         __be64 *sys_image_guid)
 331 {
 332         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 333         struct mlx5_core_dev *mdev = dev->mdev;
 334         u64 tmp;
 335         int err;
 336
 337         switch (mlx5_get_vport_access_method(ibdev)) {
 338         case MLX5_VPORT_ACCESS_METHOD_MAD:
 339                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 340                                                             sys_image_guid);
 341
 342         case MLX5_VPORT_ACCESS_METHOD_HCA:
 343                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 344                 break;
 345
 346         case MLX5_VPORT_ACCESS_METHOD_NIC:
 347                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 348                 break;
 349
 350         default:
 351                 return -EINVAL;
 352         }
 353
 354         if (!err)
 355                 *sys_image_guid = cpu_to_be64(tmp);
 356
 357         return err;
 358
 359 }
 360
 361 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 362                                 u16 *max_pkeys)
 363 {
 364         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 365         struct mlx5_core_dev *mdev = dev->mdev;
 366
 367         switch (mlx5_get_vport_access_method(ibdev)) {
 368         case MLX5_VPORT_ACCESS_METHOD_MAD:
 369                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 370
 371         case MLX5_VPORT_ACCESS_METHOD_HCA:
 372         case MLX5_VPORT_ACCESS_METHOD_NIC:
 373                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 374                                                 pkey_table_size));
 375                 return 0;
 376
 377         default:
 378                 return -EINVAL;
 379         }
 380 }
 381
 382 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 383                                 u32 *vendor_id)
 384 {
 385         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 386
 387         switch (mlx5_get_vport_access_method(ibdev)) {
 388         case MLX5_VPORT_ACCESS_METHOD_MAD:
 389                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 390
 391         case MLX5_VPORT_ACCESS_METHOD_HCA:
 392         case MLX5_VPORT_ACCESS_METHOD_NIC:
 393                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 394
 395         default:
 396                 return -EINVAL;
 397         }
 398 }
 399
 400 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 401                                 __be64 *node_guid)
 402 {
 403         u64 tmp;
 404         int err;
 405
 406         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 407         case MLX5_VPORT_ACCESS_METHOD_MAD:
 408                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 409
 410         case MLX5_VPORT_ACCESS_METHOD_HCA:
 411                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 412                 break;
 413
 414         case MLX5_VPORT_ACCESS_METHOD_NIC:
 415                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 416                 break;
 417
 418         default:
 419                 return -EINVAL;
 420         }
 421
 422         if (!err)
 423                 *node_guid = cpu_to_be64(tmp);
 424
 425         return err;
 426 }
 427
 428 struct mlx5_reg_node_desc {
 429         u8      desc[64];
 430 };
 431
 432 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 433 {
 434         struct mlx5_reg_node_desc in;
 435
 436         if (mlx5_use_mad_ifc(dev))
 437                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 438
 439         memset(&in, 0, sizeof(in));
 440
 441         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 442                                     sizeof(struct mlx5_reg_node_desc),
 443                                     MLX5_REG_NODE_DESC, 0, 0);
 444 }
 445
 446 static int mlx5_ib_query_device(struct ib_device *ibdev,
 447                                 struct ib_device_attr *props,
 448                                 struct ib_udata *uhw)
 449 {
 450         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 451         struct mlx5_core_dev *mdev = dev->mdev;
 452         int err = -ENOMEM;
 453         int max_rq_sg;
 454         int max_sq_sg;
 455         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 456
 457         if (uhw->inlen || uhw->outlen)
 458                 return -EINVAL;
 459
 460         memset(props, 0, sizeof(*props));
 461         err = mlx5_query_system_image_guid(ibdev,
 462                                            &props->sys_image_guid);
 463         if (err)
 464                 return err;
 465
 466         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 467         if (err)
 468                 return err;
 469
 470         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 471         if (err)
 472                 return err;
 473
 474         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 475                 (fw_rev_min(dev->mdev) << 16) |
 476                 fw_rev_sub(dev->mdev);
 477         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 478                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 479                 IB_DEVICE_SYS_IMAGE_GUID                |
 480                 IB_DEVICE_RC_RNR_NAK_GEN;
 481
 482         if (MLX5_CAP_GEN(mdev, pkv))
 483                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 484         if (MLX5_CAP_GEN(mdev, qkv))
 485                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 486         if (MLX5_CAP_GEN(mdev, apm))
 487                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 488         if (MLX5_CAP_GEN(mdev, xrc))
 489                 props->device_cap_flags |= IB_DEVICE_XRC;
 490         if (MLX5_CAP_GEN(mdev, imaicl)) {
 491                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 492                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 493                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 494                 /* We support 'Gappy' memory registration too */
 495                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 496         }
 497         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 498         if (MLX5_CAP_GEN(mdev, sho)) {
 499                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 500                 /* At this stage no support for signature handover */
 501                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 502                                       IB_PROT_T10DIF_TYPE_2 |
 503                                       IB_PROT_T10DIF_TYPE_3;
 504                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 505                                        IB_GUARD_T10DIF_CSUM;
 506         }
 507         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 508                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 509
 510         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 511             (MLX5_CAP_ETH(dev->mdev, csum_cap)))
 512                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 513
 514         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 515                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 516                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 517         }
 518
 519         props->vendor_part_id      = mdev->pdev->device;
 520         props->hw_ver              = mdev->pdev->revision;
 521
 522         props->max_mr_size         = ~0ull;
 523         props->page_size_cap       = ~(min_page_size - 1);
 524         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 525         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 526         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 527                      sizeof(struct mlx5_wqe_data_seg);
 528         max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
 529                      sizeof(struct mlx5_wqe_ctrl_seg)) /
 530                      sizeof(struct mlx5_wqe_data_seg);
 531         props->max_sge = min(max_rq_sg, max_sq_sg);
 532         props->max_sge_rd = props->max_sge;
 533         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 534         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 535         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 536         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 537         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 538         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 539         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 540         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 541         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 542         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 543         props->max_srq_sge         = max_rq_sg - 1;
 544         props->max_fast_reg_page_list_len =
 545                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 546         get_atomic_caps(dev, props);
 547         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 548         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 549         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 550         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 551                                            props->max_mcast_grp;
 552         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 553         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 554         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 555
 556 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 557         if (MLX5_CAP_GEN(mdev, pg))
 558                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 559         props->odp_caps = dev->odp_caps;
 560 #endif
 561
 562         if (MLX5_CAP_GEN(mdev, cd))
 563                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 564
 565         return 0;
 566 }
 567
 568 enum mlx5_ib_width {
 569         MLX5_IB_WIDTH_1X        = 1 << 0,
 570         MLX5_IB_WIDTH_2X        = 1 << 1,
 571         MLX5_IB_WIDTH_4X        = 1 << 2,
 572         MLX5_IB_WIDTH_8X        = 1 << 3,
 573         MLX5_IB_WIDTH_12X       = 1 << 4
 574 };
 575
 576 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
 577                                   u8 *ib_width)
 578 {
 579         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 580         int err = 0;
 581
 582         if (active_width & MLX5_IB_WIDTH_1X) {
 583                 *ib_width = IB_WIDTH_1X;
 584         } else if (active_width & MLX5_IB_WIDTH_2X) {
 585                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
 586                             (int)active_width);
 587                 err = -EINVAL;
 588         } else if (active_width & MLX5_IB_WIDTH_4X) {
 589                 *ib_width = IB_WIDTH_4X;
 590         } else if (active_width & MLX5_IB_WIDTH_8X) {
 591                 *ib_width = IB_WIDTH_8X;
 592         } else if (active_width & MLX5_IB_WIDTH_12X) {
 593                 *ib_width = IB_WIDTH_12X;
 594         } else {
 595                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
 596                             (int)active_width);
 597                 err = -EINVAL;
 598         }
 599
 600         return err;
 601 }
 602
 603 static int mlx5_mtu_to_ib_mtu(int mtu)
 604 {
 605         switch (mtu) {
 606         case 256: return 1;
 607         case 512: return 2;
 608         case 1024: return 3;
 609         case 2048: return 4;
 610         case 4096: return 5;
 611         default:
 612                 pr_warn("invalid mtu\n");
 613                 return -1;
 614         }
 615 }
 616
 617 enum ib_max_vl_num {
 618         __IB_MAX_VL_0           = 1,
 619         __IB_MAX_VL_0_1         = 2,
 620         __IB_MAX_VL_0_3         = 3,
 621         __IB_MAX_VL_0_7         = 4,
 622         __IB_MAX_VL_0_14        = 5,
 623 };
 624
 625 enum mlx5_vl_hw_cap {
 626         MLX5_VL_HW_0    = 1,
 627         MLX5_VL_HW_0_1  = 2,
 628         MLX5_VL_HW_0_2  = 3,
 629         MLX5_VL_HW_0_3  = 4,
 630         MLX5_VL_HW_0_4  = 5,
 631         MLX5_VL_HW_0_5  = 6,
 632         MLX5_VL_HW_0_6  = 7,
 633         MLX5_VL_HW_0_7  = 8,
 634         MLX5_VL_HW_0_14 = 15
 635 };
 636
 637 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
 638                                 u8 *max_vl_num)
 639 {
 640         switch (vl_hw_cap) {
 641         case MLX5_VL_HW_0:
 642                 *max_vl_num = __IB_MAX_VL_0;
 643                 break;
 644         case MLX5_VL_HW_0_1:
 645                 *max_vl_num = __IB_MAX_VL_0_1;
 646                 break;
 647         case MLX5_VL_HW_0_3:
 648                 *max_vl_num = __IB_MAX_VL_0_3;
 649                 break;
 650         case MLX5_VL_HW_0_7:
 651                 *max_vl_num = __IB_MAX_VL_0_7;
 652                 break;
 653         case MLX5_VL_HW_0_14:
 654                 *max_vl_num = __IB_MAX_VL_0_14;
 655                 break;
 656
 657         default:
 658                 return -EINVAL;
 659         }
 660
 661         return 0;
 662 }
 663
 664 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
 665                                struct ib_port_attr *props)
 666 {
 667         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 668         struct mlx5_core_dev *mdev = dev->mdev;
 669         struct mlx5_hca_vport_context *rep;
 670         int max_mtu;
 671         int oper_mtu;
 672         int err;
 673         u8 ib_link_width_oper;
 674         u8 vl_hw_cap;
 675
 676         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
 677         if (!rep) {
 678                 err = -ENOMEM;
 679                 goto out;
 680         }
 681
 682         memset(props, 0, sizeof(*props));
 683
 684         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
 685         if (err)
 686                 goto out;
 687
 688         props->lid              = rep->lid;
 689         props->lmc              = rep->lmc;
 690         props->sm_lid           = rep->sm_lid;
 691         props->sm_sl            = rep->sm_sl;
 692         props->state            = rep->vport_state;
 693         props->phys_state       = rep->port_physical_state;
 694         props->port_cap_flags   = rep->cap_mask1;
 695         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
 696         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
 697         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
 698         props->bad_pkey_cntr    = rep->pkey_violation_counter;
 699         props->qkey_viol_cntr   = rep->qkey_violation_counter;
 700         props->subnet_timeout   = rep->subnet_timeout;
 701         props->init_type_reply  = rep->init_type_reply;
 702
 703         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
 704         if (err)
 705                 goto out;
 706
 707         err = translate_active_width(ibdev, ib_link_width_oper,
 708                                      &props->active_width);
 709         if (err)
 710                 goto out;
 711         err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB,
 712                                          port);
 713         if (err)
 714                 goto out;
 715
 716         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
 717
 718         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
 719
 720         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
 721
 722         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
 723
 724         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
 725         if (err)
 726                 goto out;
 727
 728         err = translate_max_vl_num(ibdev, vl_hw_cap,
 729                                    &props->max_vl_num);
 730 out:
 731         kfree(rep);
 732         return err;
 733 }
 734
 735 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
 736                        struct ib_port_attr *props)
 737 {
 738         switch (mlx5_get_vport_access_method(ibdev)) {
 739         case MLX5_VPORT_ACCESS_METHOD_MAD:
 740                 return mlx5_query_mad_ifc_port(ibdev, port, props);
 741
 742         case MLX5_VPORT_ACCESS_METHOD_HCA:
 743                 return mlx5_query_hca_port(ibdev, port, props);
 744
 745         case MLX5_VPORT_ACCESS_METHOD_NIC:
 746                 return mlx5_query_port_roce(ibdev, port, props);
 747
 748         default:
 749                 return -EINVAL;
 750         }
 751 }
 752
 753 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
 754                              union ib_gid *gid)
 755 {
 756         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 757         struct mlx5_core_dev *mdev = dev->mdev;
 758
 759         switch (mlx5_get_vport_access_method(ibdev)) {
 760         case MLX5_VPORT_ACCESS_METHOD_MAD:
 761                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
 762
 763         case MLX5_VPORT_ACCESS_METHOD_HCA:
 764                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
 765
 766         default:
 767                 return -EINVAL;
 768         }
 769
 770 }
 771
 772 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
 773                               u16 *pkey)
 774 {
 775         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 776         struct mlx5_core_dev *mdev = dev->mdev;
 777
 778         switch (mlx5_get_vport_access_method(ibdev)) {
 779         case MLX5_VPORT_ACCESS_METHOD_MAD:
 780                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
 781
 782         case MLX5_VPORT_ACCESS_METHOD_HCA:
 783         case MLX5_VPORT_ACCESS_METHOD_NIC:
 784                 return mlx5_query_hca_vport_pkey(mdev, 0, port,  0, index,
 785                                                  pkey);
 786         default:
 787                 return -EINVAL;
 788         }
 789 }
 790
 791 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
 792                                  struct ib_device_modify *props)
 793 {
 794         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 795         struct mlx5_reg_node_desc in;
 796         struct mlx5_reg_node_desc out;
 797         int err;
 798
 799         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
 800                 return -EOPNOTSUPP;
 801
 802         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
 803                 return 0;
 804
 805         /*
 806          * If possible, pass node desc to FW, so it can generate
 807          * a 144 trap.  If cmd fails, just ignore.
 808          */
 809         memcpy(&in, props->node_desc, 64);
 810         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
 811                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
 812         if (err)
 813                 return err;
 814
 815         memcpy(ibdev->node_desc, props->node_desc, 64);
 816
 817         return err;
 818 }
 819
 820 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
 821                                struct ib_port_modify *props)
 822 {
 823         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 824         struct ib_port_attr attr;
 825         u32 tmp;
 826         int err;
 827
 828         mutex_lock(&dev->cap_mask_mutex);
 829
 830         err = mlx5_ib_query_port(ibdev, port, &attr);
 831         if (err)
 832                 goto out;
 833
 834         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
 835                 ~props->clr_port_cap_mask;
 836
 837         err = mlx5_set_port_caps(dev->mdev, port, tmp);
 838
 839 out:
 840         mutex_unlock(&dev->cap_mask_mutex);
 841         return err;
 842 }
 843
 844 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
 845                                                   struct ib_udata *udata)
 846 {
 847         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 848         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
 849         struct mlx5_ib_alloc_ucontext_resp resp = {};
 850         struct mlx5_ib_ucontext *context;
 851         struct mlx5_uuar_info *uuari;
 852         struct mlx5_uar *uars;
 853         int gross_uuars;
 854         int num_uars;
 855         int ver;
 856         int uuarn;
 857         int err;
 858         int i;
 859         size_t reqlen;
 860         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
 861                                      max_cqe_version);
 862
 863         if (!dev->ib_active)
 864                 return ERR_PTR(-EAGAIN);
 865
 866         if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
 867                 return ERR_PTR(-EINVAL);
 868
 869         reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
 870         if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
 871                 ver = 0;
 872         else if (reqlen >= min_req_v2)
 873                 ver = 2;
 874         else
 875                 return ERR_PTR(-EINVAL);
 876
 877         err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
 878         if (err)
 879                 return ERR_PTR(err);
 880
 881         if (req.flags)
 882                 return ERR_PTR(-EINVAL);
 883
 884         if (req.total_num_uuars > MLX5_MAX_UUARS)
 885                 return ERR_PTR(-ENOMEM);
 886
 887         if (req.total_num_uuars == 0)
 888                 return ERR_PTR(-EINVAL);
 889
 890         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
 891                 return ERR_PTR(-EOPNOTSUPP);
 892
 893         if (reqlen > sizeof(req) &&
 894             !ib_is_udata_cleared(udata, sizeof(req),
 895                                  reqlen - sizeof(req)))
 896                 return ERR_PTR(-EOPNOTSUPP);
 897
 898         req.total_num_uuars = ALIGN(req.total_num_uuars,
 899                                     MLX5_NON_FP_BF_REGS_PER_PAGE);
 900         if (req.num_low_latency_uuars > req.total_num_uuars - 1)
 901                 return ERR_PTR(-EINVAL);
 902
 903         num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
 904         gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
 905         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
 906         resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
 907         resp.cache_line_size = L1_CACHE_BYTES;
 908         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
 909         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
 910         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
 911         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
 912         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
 913         resp.cqe_version = min_t(__u8,
 914                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
 915                                  req.max_cqe_version);
 916         resp.response_length = min(offsetof(typeof(resp), response_length) +
 917                                    sizeof(resp.response_length), udata->outlen);
 918
 919         context = kzalloc(sizeof(*context), GFP_KERNEL);
 920         if (!context)
 921                 return ERR_PTR(-ENOMEM);
 922
 923         uuari = &context->uuari;
 924         mutex_init(&uuari->lock);
 925         uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
 926         if (!uars) {
 927                 err = -ENOMEM;
 928                 goto out_ctx;
 929         }
 930
 931         uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
 932                                 sizeof(*uuari->bitmap),
 933                                 GFP_KERNEL);
 934         if (!uuari->bitmap) {
 935                 err = -ENOMEM;
 936                 goto out_uar_ctx;
 937         }
 938         /*
 939          * clear all fast path uuars
 940          */
 941         for (i = 0; i < gross_uuars; i++) {
 942                 uuarn = i & 3;
 943                 if (uuarn == 2 || uuarn == 3)
 944                         set_bit(i, uuari->bitmap);
 945         }
 946
 947         uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
 948         if (!uuari->count) {
 949                 err = -ENOMEM;
 950                 goto out_bitmap;
 951         }
 952
 953         for (i = 0; i < num_uars; i++) {
 954                 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
 955                 if (err)
 956                         goto out_count;
 957         }
 958
 959 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 960         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
 961 #endif
 962
 963         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
 964                 err = mlx5_core_alloc_transport_domain(dev->mdev,
 965                                                        &context->tdn);
 966                 if (err)
 967                         goto out_uars;
 968         }
 969
 970         INIT_LIST_HEAD(&context->db_page_list);
 971         mutex_init(&context->db_page_mutex);
 972
 973         resp.tot_uuars = req.total_num_uuars;
 974         resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
 975
 976         if (field_avail(typeof(resp), cqe_version, udata->outlen))
 977                 resp.response_length += sizeof(resp.cqe_version);
 978
 979         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
 980                 resp.comp_mask |=
 981                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
 982                 resp.hca_core_clock_offset =
 983                         offsetof(struct mlx5_init_seg, internal_timer_h) %
 984                         PAGE_SIZE;
 985                 resp.response_length += sizeof(resp.hca_core_clock_offset) +
 986                                         sizeof(resp.reserved2) +
 987                                         sizeof(resp.reserved3);
 988         }
 989
 990         err = ib_copy_to_udata(udata, &resp, resp.response_length);
 991         if (err)
 992                 goto out_td;
 993
 994         uuari->ver = ver;
 995         uuari->num_low_latency_uuars = req.num_low_latency_uuars;
 996         uuari->uars = uars;
 997         uuari->num_uars = num_uars;
 998         context->cqe_version = resp.cqe_version;
 999
1000         return &context->ibucontext;
1001
1002 out_td:
1003         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1004                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1005
1006 out_uars:
1007         for (i--; i >= 0; i--)
1008                 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
1009 out_count:
1010         kfree(uuari->count);
1011
1012 out_bitmap:
1013         kfree(uuari->bitmap);
1014
1015 out_uar_ctx:
1016         kfree(uars);
1017
1018 out_ctx:
1019         kfree(context);
1020         return ERR_PTR(err);
1021 }
1022
1023 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1024 {
1025         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1026         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1027         struct mlx5_uuar_info *uuari = &context->uuari;
1028         int i;
1029
1030         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1031                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1032
1033         for (i = 0; i < uuari->num_uars; i++) {
1034                 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
1035                         mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1036         }
1037
1038         kfree(uuari->count);
1039         kfree(uuari->bitmap);
1040         kfree(uuari->uars);
1041         kfree(context);
1042
1043         return 0;
1044 }
1045
1046 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1047 {
1048         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1049 }
1050
1051 static int get_command(unsigned long offset)
1052 {
1053         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1054 }
1055
1056 static int get_arg(unsigned long offset)
1057 {
1058         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1059 }
1060
1061 static int get_index(unsigned long offset)
1062 {
1063         return get_arg(offset);
1064 }
1065
1066 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1067 {
1068         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1069         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1070         struct mlx5_uuar_info *uuari = &context->uuari;
1071         unsigned long command;
1072         unsigned long idx;
1073         phys_addr_t pfn;
1074
1075         command = get_command(vma->vm_pgoff);
1076         switch (command) {
1077         case MLX5_IB_MMAP_REGULAR_PAGE:
1078                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1079                         return -EINVAL;
1080
1081                 idx = get_index(vma->vm_pgoff);
1082                 if (idx >= uuari->num_uars)
1083                         return -EINVAL;
1084
1085                 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1086                 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx,
1087                             (unsigned long long)pfn);
1088
1089                 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1090                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1091                                        PAGE_SIZE, vma->vm_page_prot))
1092                         return -EAGAIN;
1093
1094                 mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n",
1095                             vma->vm_start,
1096                             (unsigned long long)pfn << PAGE_SHIFT);
1097                 break;
1098
1099         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1100                 return -ENOSYS;
1101
1102         case MLX5_IB_MMAP_CORE_CLOCK:
1103                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1104                         return -EINVAL;
1105
1106                 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
1107                         return -EPERM;
1108
1109                 /* Don't expose to user-space information it shouldn't have */
1110                 if (PAGE_SIZE > 4096)
1111                         return -EOPNOTSUPP;
1112
1113                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1114                 pfn = (dev->mdev->iseg_base +
1115                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1116                         PAGE_SHIFT;
1117                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1118                                        PAGE_SIZE, vma->vm_page_prot))
1119                         return -EAGAIN;
1120
1121                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1122                             vma->vm_start,
1123                             (unsigned long long)pfn << PAGE_SHIFT);
1124                 break;
1125
1126         default:
1127                 return -EINVAL;
1128         }
1129
1130         return 0;
1131 }
1132
1133 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1134                                       struct ib_ucontext *context,
1135                                       struct ib_udata *udata)
1136 {
1137         struct mlx5_ib_alloc_pd_resp resp;
1138         struct mlx5_ib_pd *pd;
1139         int err;
1140
1141         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1142         if (!pd)
1143                 return ERR_PTR(-ENOMEM);
1144
1145         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1146         if (err) {
1147                 kfree(pd);
1148                 return ERR_PTR(err);
1149         }
1150
1151         if (context) {
1152                 resp.pdn = pd->pdn;
1153                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1154                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1155                         kfree(pd);
1156                         return ERR_PTR(-EFAULT);
1157                 }
1158         }
1159
1160         return &pd->ibpd;
1161 }
1162
1163 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1164 {
1165         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1166         struct mlx5_ib_pd *mpd = to_mpd(pd);
1167
1168         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1169         kfree(mpd);
1170
1171         return 0;
1172 }
1173
1174 static bool outer_header_zero(u32 *match_criteria)
1175 {
1176         int size = MLX5_ST_SZ_BYTES(fte_match_param);
1177         char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria,
1178                                              outer_headers);
1179
1180         return outer_headers_c[0] == 0 && !memcmp(outer_headers_c,
1181                                                   outer_headers_c + 1,
1182                                                   size - 1);
1183 }
1184
1185 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1186                            union ib_flow_spec *ib_spec)
1187 {
1188         void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1189                                              outer_headers);
1190         void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1191                                              outer_headers);
1192         switch (ib_spec->type) {
1193         case IB_FLOW_SPEC_ETH:
1194                 if (ib_spec->size != sizeof(ib_spec->eth))
1195                         return -EINVAL;
1196
1197                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1198                                              dmac_47_16),
1199                                 ib_spec->eth.mask.dst_mac);
1200                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1201                                              dmac_47_16),
1202                                 ib_spec->eth.val.dst_mac);
1203
1204                 if (ib_spec->eth.mask.vlan_tag) {
1205                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1206                                  vlan_tag, 1);
1207                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1208                                  vlan_tag, 1);
1209
1210                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1211                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1212                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1213                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1214
1215                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1216                                  first_cfi,
1217                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1218                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1219                                  first_cfi,
1220                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1221
1222                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1223                                  first_prio,
1224                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1225                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1226                                  first_prio,
1227                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1228                 }
1229                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1230                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
1231                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1232                          ethertype, ntohs(ib_spec->eth.val.ether_type));
1233                 break;
1234         case IB_FLOW_SPEC_IPV4:
1235                 if (ib_spec->size != sizeof(ib_spec->ipv4))
1236                         return -EINVAL;
1237
1238                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1239                          ethertype, 0xffff);
1240                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1241                          ethertype, ETH_P_IP);
1242
1243                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1244                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1245                        &ib_spec->ipv4.mask.src_ip,
1246                        sizeof(ib_spec->ipv4.mask.src_ip));
1247                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1248                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1249                        &ib_spec->ipv4.val.src_ip,
1250                        sizeof(ib_spec->ipv4.val.src_ip));
1251                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1252                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1253                        &ib_spec->ipv4.mask.dst_ip,
1254                        sizeof(ib_spec->ipv4.mask.dst_ip));
1255                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1256                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1257                        &ib_spec->ipv4.val.dst_ip,
1258                        sizeof(ib_spec->ipv4.val.dst_ip));
1259                 break;
1260         case IB_FLOW_SPEC_TCP:
1261                 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1262                         return -EINVAL;
1263
1264                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1265                          0xff);
1266                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1267                          IPPROTO_TCP);
1268
1269                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1270                          ntohs(ib_spec->tcp_udp.mask.src_port));
1271                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1272                          ntohs(ib_spec->tcp_udp.val.src_port));
1273
1274                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1275                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1276                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1277                          ntohs(ib_spec->tcp_udp.val.dst_port));
1278                 break;
1279         case IB_FLOW_SPEC_UDP:
1280                 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1281                         return -EINVAL;
1282
1283                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1284                          0xff);
1285                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1286                          IPPROTO_UDP);
1287
1288                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1289                          ntohs(ib_spec->tcp_udp.mask.src_port));
1290                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1291                          ntohs(ib_spec->tcp_udp.val.src_port));
1292
1293                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1294                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1295                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1296                          ntohs(ib_spec->tcp_udp.val.dst_port));
1297                 break;
1298         default:
1299                 return -EINVAL;
1300         }
1301
1302         return 0;
1303 }
1304
1305 /* If a flow could catch both multicast and unicast packets,
1306  * it won't fall into the multicast flow steering table and this rule
1307  * could steal other multicast packets.
1308  */
1309 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1310 {
1311         struct ib_flow_spec_eth *eth_spec;
1312
1313         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1314             ib_attr->size < sizeof(struct ib_flow_attr) +
1315             sizeof(struct ib_flow_spec_eth) ||
1316             ib_attr->num_of_specs < 1)
1317                 return false;
1318
1319         eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1320         if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1321             eth_spec->size != sizeof(*eth_spec))
1322                 return false;
1323
1324         return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1325                is_multicast_ether_addr(eth_spec->val.dst_mac);
1326 }
1327
1328 static bool is_valid_attr(struct ib_flow_attr *flow_attr)
1329 {
1330         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1331         bool has_ipv4_spec = false;
1332         bool eth_type_ipv4 = true;
1333         unsigned int spec_index;
1334
1335         /* Validate that ethertype is correct */
1336         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1337                 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1338                     ib_spec->eth.mask.ether_type) {
1339                         if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1340                               ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1341                                 eth_type_ipv4 = false;
1342                 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1343                         has_ipv4_spec = true;
1344                 }
1345                 ib_spec = (void *)ib_spec + ib_spec->size;
1346         }
1347         return !has_ipv4_spec || eth_type_ipv4;
1348 }
1349
1350 static void put_flow_table(struct mlx5_ib_dev *dev,
1351                            struct mlx5_ib_flow_prio *prio, bool ft_added)
1352 {
1353         prio->refcount -= !!ft_added;
1354         if (!prio->refcount) {
1355                 mlx5_destroy_flow_table(prio->flow_table);
1356                 prio->flow_table = NULL;
1357         }
1358 }
1359
1360 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1361 {
1362         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1363         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1364                                                           struct mlx5_ib_flow_handler,
1365                                                           ibflow);
1366         struct mlx5_ib_flow_handler *iter, *tmp;
1367
1368         mutex_lock(&dev->flow_db.lock);
1369
1370         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1371                 mlx5_del_flow_rule(iter->rule);
1372                 list_del(&iter->list);
1373                 kfree(iter);
1374         }
1375
1376         mlx5_del_flow_rule(handler->rule);
1377         put_flow_table(dev, &dev->flow_db.prios[handler->prio], true);
1378         mutex_unlock(&dev->flow_db.lock);
1379
1380         kfree(handler);
1381
1382         return 0;
1383 }
1384
1385 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1386 {
1387         priority *= 2;
1388         if (!dont_trap)
1389                 priority++;
1390         return priority;
1391 }
1392
1393 #define MLX5_FS_MAX_TYPES        10
1394 #define MLX5_FS_MAX_ENTRIES      32000UL
1395 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1396                                                 struct ib_flow_attr *flow_attr)
1397 {
1398         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1399         struct mlx5_flow_namespace *ns = NULL;
1400         struct mlx5_ib_flow_prio *prio;
1401         struct mlx5_flow_table *ft;
1402         int num_entries;
1403         int num_groups;
1404         int priority;
1405         int err = 0;
1406
1407         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1408                 if (flow_is_multicast_only(flow_attr) &&
1409                     !dont_trap)
1410                         priority = MLX5_IB_FLOW_MCAST_PRIO;
1411                 else
1412                         priority = ib_prio_to_core_prio(flow_attr->priority,
1413                                                         dont_trap);
1414                 ns = mlx5_get_flow_namespace(dev->mdev,
1415                                              MLX5_FLOW_NAMESPACE_BYPASS);
1416                 num_entries = MLX5_FS_MAX_ENTRIES;
1417                 num_groups = MLX5_FS_MAX_TYPES;
1418                 prio = &dev->flow_db.prios[priority];
1419         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1420                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1421                 ns = mlx5_get_flow_namespace(dev->mdev,
1422                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
1423                 build_leftovers_ft_param(&priority,
1424                                          &num_entries,
1425                                          &num_groups);
1426                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1427         }
1428
1429         if (!ns)
1430                 return ERR_PTR(-ENOTSUPP);
1431
1432         ft = prio->flow_table;
1433         if (!ft) {
1434                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1435                                                          num_entries,
1436                                                          num_groups);
1437
1438                 if (!IS_ERR(ft)) {
1439                         prio->refcount = 0;
1440                         prio->flow_table = ft;
1441                 } else {
1442                         err = PTR_ERR(ft);
1443                 }
1444         }
1445
1446         return err ? ERR_PTR(err) : prio;
1447 }
1448
1449 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1450                                                      struct mlx5_ib_flow_prio *ft_prio,
1451                                                      struct ib_flow_attr *flow_attr,
1452                                                      struct mlx5_flow_destination *dst)
1453 {
1454         struct mlx5_flow_table  *ft = ft_prio->flow_table;
1455         struct mlx5_ib_flow_handler *handler;
1456         void *ib_flow = flow_attr + 1;
1457         u8 match_criteria_enable = 0;
1458         unsigned int spec_index;
1459         u32 *match_c;
1460         u32 *match_v;
1461         u32 action;
1462         int err = 0;
1463
1464         if (!is_valid_attr(flow_attr))
1465                 return ERR_PTR(-EINVAL);
1466
1467         match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1468         match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1469         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1470         if (!handler || !match_c || !match_v) {
1471                 err = -ENOMEM;
1472                 goto free;
1473         }
1474
1475         INIT_LIST_HEAD(&handler->list);
1476
1477         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1478                 err = parse_flow_attr(match_c, match_v, ib_flow);
1479                 if (err < 0)
1480                         goto free;
1481
1482                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1483         }
1484
1485         /* Outer header support only */
1486         match_criteria_enable = (!outer_header_zero(match_c)) << 0;
1487         action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1488                 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
1489         handler->rule = mlx5_add_flow_rule(ft, match_criteria_enable,
1490                                            match_c, match_v,
1491                                            action,
1492                                            MLX5_FS_DEFAULT_FLOW_TAG,
1493                                            dst);
1494
1495         if (IS_ERR(handler->rule)) {
1496                 err = PTR_ERR(handler->rule);
1497                 goto free;
1498         }
1499
1500         handler->prio = ft_prio - dev->flow_db.prios;
1501
1502         ft_prio->flow_table = ft;
1503 free:
1504         if (err)
1505                 kfree(handler);
1506         kfree(match_c);
1507         kfree(match_v);
1508         return err ? ERR_PTR(err) : handler;
1509 }
1510
1511 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1512                                                           struct mlx5_ib_flow_prio *ft_prio,
1513                                                           struct ib_flow_attr *flow_attr,
1514                                                           struct mlx5_flow_destination *dst)
1515 {
1516         struct mlx5_ib_flow_handler *handler_dst = NULL;
1517         struct mlx5_ib_flow_handler *handler = NULL;
1518
1519         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1520         if (!IS_ERR(handler)) {
1521                 handler_dst = create_flow_rule(dev, ft_prio,
1522                                                flow_attr, dst);
1523                 if (IS_ERR(handler_dst)) {
1524                         mlx5_del_flow_rule(handler->rule);
1525                         kfree(handler);
1526                         handler = handler_dst;
1527                 } else {
1528                         list_add(&handler_dst->list, &handler->list);
1529                 }
1530         }
1531
1532         return handler;
1533 }
1534 enum {
1535         LEFTOVERS_MC,
1536         LEFTOVERS_UC,
1537 };
1538
1539 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1540                                                           struct mlx5_ib_flow_prio *ft_prio,
1541                                                           struct ib_flow_attr *flow_attr,
1542                                                           struct mlx5_flow_destination *dst)
1543 {
1544         struct mlx5_ib_flow_handler *handler_ucast = NULL;
1545         struct mlx5_ib_flow_handler *handler = NULL;
1546
1547         static struct {
1548                 struct ib_flow_attr     flow_attr;
1549                 struct ib_flow_spec_eth eth_flow;
1550         } leftovers_specs[] = {
1551                 [LEFTOVERS_MC] = {
1552                         .flow_attr = {
1553                                 .num_of_specs = 1,
1554                                 .size = sizeof(leftovers_specs[0])
1555                         },
1556                         .eth_flow = {
1557                                 .type = IB_FLOW_SPEC_ETH,
1558                                 .size = sizeof(struct ib_flow_spec_eth),
1559                                 .mask = {.dst_mac = {0x1} },
1560                                 .val =  {.dst_mac = {0x1} }
1561                         }
1562                 },
1563                 [LEFTOVERS_UC] = {
1564                         .flow_attr = {
1565                                 .num_of_specs = 1,
1566                                 .size = sizeof(leftovers_specs[0])
1567                         },
1568                         .eth_flow = {
1569                                 .type = IB_FLOW_SPEC_ETH,
1570                                 .size = sizeof(struct ib_flow_spec_eth),
1571                                 .mask = {.dst_mac = {0x1} },
1572                                 .val = {.dst_mac = {} }
1573                         }
1574                 }
1575         };
1576
1577         handler = create_flow_rule(dev, ft_prio,
1578                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
1579                                    dst);
1580         if (!IS_ERR(handler) &&
1581             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
1582                 handler_ucast = create_flow_rule(dev, ft_prio,
1583                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
1584                                                  dst);
1585                 if (IS_ERR(handler_ucast)) {
1586                         kfree(handler);
1587                         handler = handler_ucast;
1588                 } else {
1589                         list_add(&handler_ucast->list, &handler->list);
1590                 }
1591         }
1592
1593         return handler;
1594 }
1595
1596 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
1597                                            struct ib_flow_attr *flow_attr,
1598                                            int domain)
1599 {
1600         struct mlx5_ib_dev *dev = to_mdev(qp->device);
1601         struct mlx5_ib_flow_handler *handler = NULL;
1602         struct mlx5_flow_destination *dst = NULL;
1603         struct mlx5_ib_flow_prio *ft_prio;
1604         int err;
1605
1606         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
1607                 return ERR_PTR(-ENOSPC);
1608
1609         if (domain != IB_FLOW_DOMAIN_USER ||
1610             flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
1611             (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
1612                 return ERR_PTR(-EINVAL);
1613
1614         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
1615         if (!dst)
1616                 return ERR_PTR(-ENOMEM);
1617
1618         mutex_lock(&dev->flow_db.lock);
1619
1620         ft_prio = get_flow_table(dev, flow_attr);
1621         if (IS_ERR(ft_prio)) {
1622                 err = PTR_ERR(ft_prio);
1623                 goto unlock;
1624         }
1625
1626         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1627         dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn;
1628
1629         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1630                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
1631                         handler = create_dont_trap_rule(dev, ft_prio,
1632                                                         flow_attr, dst);
1633                 } else {
1634                         handler = create_flow_rule(dev, ft_prio, flow_attr,
1635                                                    dst);
1636                 }
1637         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1638                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1639                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
1640                                                 dst);
1641         } else {
1642                 err = -EINVAL;
1643                 goto destroy_ft;
1644         }
1645
1646         if (IS_ERR(handler)) {
1647                 err = PTR_ERR(handler);
1648                 handler = NULL;
1649                 goto destroy_ft;
1650         }
1651
1652         ft_prio->refcount++;
1653         mutex_unlock(&dev->flow_db.lock);
1654         kfree(dst);
1655
1656         return &handler->ibflow;
1657
1658 destroy_ft:
1659         put_flow_table(dev, ft_prio, false);
1660 unlock:
1661         mutex_unlock(&dev->flow_db.lock);
1662         kfree(dst);
1663         kfree(handler);
1664         return ERR_PTR(err);
1665 }
1666
1667 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1668 {
1669         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1670         int err;
1671
1672         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
1673         if (err)
1674                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
1675                              ibqp->qp_num, gid->raw);
1676
1677         return err;
1678 }
1679
1680 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1681 {
1682         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1683         int err;
1684
1685         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
1686         if (err)
1687                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
1688                              ibqp->qp_num, gid->raw);
1689
1690         return err;
1691 }
1692
1693 static int init_node_data(struct mlx5_ib_dev *dev)
1694 {
1695         int err;
1696
1697         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
1698         if (err)
1699                 return err;
1700
1701         dev->mdev->rev_id = dev->mdev->pdev->revision;
1702
1703         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
1704 }
1705
1706 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
1707                              char *buf)
1708 {
1709         struct mlx5_ib_dev *dev =
1710                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1711
1712         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
1713 }
1714
1715 static ssize_t show_reg_pages(struct device *device,
1716                               struct device_attribute *attr, char *buf)
1717 {
1718         struct mlx5_ib_dev *dev =
1719                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1720
1721         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
1722 }
1723
1724 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
1725                         char *buf)
1726 {
1727         struct mlx5_ib_dev *dev =
1728                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1729         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
1730 }
1731
1732 static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
1733                            char *buf)
1734 {
1735         struct mlx5_ib_dev *dev =
1736                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1737         return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev),
1738                        fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
1739 }
1740
1741 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
1742                         char *buf)
1743 {
1744         struct mlx5_ib_dev *dev =
1745                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1746         return sprintf(buf, "%x\n", dev->mdev->rev_id);
1747 }
1748
1749 static ssize_t show_board(struct device *device, struct device_attribute *attr,
1750                           char *buf)
1751 {
1752         struct mlx5_ib_dev *dev =
1753                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1754         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
1755                        dev->mdev->board_id);
1756 }
1757
1758 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
1759 static DEVICE_ATTR(fw_ver,   S_IRUGO, show_fw_ver, NULL);
1760 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
1761 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
1762 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
1763 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
1764
1765 static struct device_attribute *mlx5_class_attributes[] = {
1766         &dev_attr_hw_rev,
1767         &dev_attr_fw_ver,
1768         &dev_attr_hca_type,
1769         &dev_attr_board_id,
1770         &dev_attr_fw_pages,
1771         &dev_attr_reg_pages,
1772 };
1773
1774 static void pkey_change_handler(struct work_struct *work)
1775 {
1776         struct mlx5_ib_port_resources *ports =
1777                 container_of(work, struct mlx5_ib_port_resources,
1778                              pkey_change_work);
1779
1780         mutex_lock(&ports->devr->mutex);
1781         mlx5_ib_gsi_pkey_change(ports->gsi);
1782         mutex_unlock(&ports->devr->mutex);
1783 }
1784
1785 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
1786                           enum mlx5_dev_event event, unsigned long param)
1787 {
1788         struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
1789         struct ib_event ibev;
1790
1791         u8 port = 0;
1792
1793         switch (event) {
1794         case MLX5_DEV_EVENT_SYS_ERROR:
1795                 ibdev->ib_active = false;
1796                 ibev.event = IB_EVENT_DEVICE_FATAL;
1797                 break;
1798
1799         case MLX5_DEV_EVENT_PORT_UP:
1800                 ibev.event = IB_EVENT_PORT_ACTIVE;
1801                 port = (u8)param;
1802                 break;
1803
1804         case MLX5_DEV_EVENT_PORT_DOWN:
1805                 ibev.event = IB_EVENT_PORT_ERR;
1806                 port = (u8)param;
1807                 break;
1808
1809         case MLX5_DEV_EVENT_PORT_INITIALIZED:
1810                 /* not used by ULPs */
1811                 return;
1812
1813         case MLX5_DEV_EVENT_LID_CHANGE:
1814                 ibev.event = IB_EVENT_LID_CHANGE;
1815                 port = (u8)param;
1816                 break;
1817
1818         case MLX5_DEV_EVENT_PKEY_CHANGE:
1819                 ibev.event = IB_EVENT_PKEY_CHANGE;
1820                 port = (u8)param;
1821
1822                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
1823                 break;
1824
1825         case MLX5_DEV_EVENT_GUID_CHANGE:
1826                 ibev.event = IB_EVENT_GID_CHANGE;
1827                 port = (u8)param;
1828                 break;
1829
1830         case MLX5_DEV_EVENT_CLIENT_REREG:
1831                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
1832                 port = (u8)param;
1833                 break;
1834         }
1835
1836         ibev.device           = &ibdev->ib_dev;
1837         ibev.element.port_num = port;
1838
1839         if (port < 1 || port > ibdev->num_ports) {
1840                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
1841                 return;
1842         }
1843
1844         if (ibdev->ib_active)
1845                 ib_dispatch_event(&ibev);
1846 }
1847
1848 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
1849 {
1850         int port;
1851
1852         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
1853                 mlx5_query_ext_port_caps(dev, port);
1854 }
1855
1856 static int get_port_caps(struct mlx5_ib_dev *dev)
1857 {
1858         struct ib_device_attr *dprops = NULL;
1859         struct ib_port_attr *pprops = NULL;
1860         int err = -ENOMEM;
1861         int port;
1862         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
1863
1864         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
1865         if (!pprops)
1866                 goto out;
1867
1868         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
1869         if (!dprops)
1870                 goto out;
1871
1872         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
1873         if (err) {
1874                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
1875                 goto out;
1876         }
1877
1878         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
1879                 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
1880                 if (err) {
1881                         mlx5_ib_warn(dev, "query_port %d failed %d\n",
1882                                      port, err);
1883                         break;
1884                 }
1885                 dev->mdev->port_caps[port - 1].pkey_table_len =
1886                                                 dprops->max_pkeys;
1887                 dev->mdev->port_caps[port - 1].gid_table_len =
1888                                                 pprops->gid_tbl_len;
1889                 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
1890                             dprops->max_pkeys, pprops->gid_tbl_len);
1891         }
1892
1893 out:
1894         kfree(pprops);
1895         kfree(dprops);
1896
1897         return err;
1898 }
1899
1900 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
1901 {
1902         int err;
1903
1904         err = mlx5_mr_cache_cleanup(dev);
1905         if (err)
1906                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
1907
1908         mlx5_ib_destroy_qp(dev->umrc.qp);
1909         ib_free_cq(dev->umrc.cq);
1910         ib_dealloc_pd(dev->umrc.pd);
1911 }
1912
1913 enum {
1914         MAX_UMR_WR = 128,
1915 };
1916
1917 static int create_umr_res(struct mlx5_ib_dev *dev)
1918 {
1919         struct ib_qp_init_attr *init_attr = NULL;
1920         struct ib_qp_attr *attr = NULL;
1921         struct ib_pd *pd;
1922         struct ib_cq *cq;
1923         struct ib_qp *qp;
1924         int ret;
1925
1926         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
1927         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
1928         if (!attr || !init_attr) {
1929                 ret = -ENOMEM;
1930                 goto error_0;
1931         }
1932
1933         pd = ib_alloc_pd(&dev->ib_dev);
1934         if (IS_ERR(pd)) {
1935                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
1936                 ret = PTR_ERR(pd);
1937                 goto error_0;
1938         }
1939
1940         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
1941         if (IS_ERR(cq)) {
1942                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
1943                 ret = PTR_ERR(cq);
1944                 goto error_2;
1945         }
1946
1947         init_attr->send_cq = cq;
1948         init_attr->recv_cq = cq;
1949         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
1950         init_attr->cap.max_send_wr = MAX_UMR_WR;
1951         init_attr->cap.max_send_sge = 1;
1952         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
1953         init_attr->port_num = 1;
1954         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
1955         if (IS_ERR(qp)) {
1956                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
1957                 ret = PTR_ERR(qp);
1958                 goto error_3;
1959         }
1960         qp->device     = &dev->ib_dev;
1961         qp->real_qp    = qp;
1962         qp->uobject    = NULL;
1963         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
1964
1965         attr->qp_state = IB_QPS_INIT;
1966         attr->port_num = 1;
1967         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
1968                                 IB_QP_PORT, NULL);
1969         if (ret) {
1970                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
1971                 goto error_4;
1972         }
1973
1974         memset(attr, 0, sizeof(*attr));
1975         attr->qp_state = IB_QPS_RTR;
1976         attr->path_mtu = IB_MTU_256;
1977
1978         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1979         if (ret) {
1980                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
1981                 goto error_4;
1982         }
1983
1984         memset(attr, 0, sizeof(*attr));
1985         attr->qp_state = IB_QPS_RTS;
1986         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1987         if (ret) {
1988                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
1989                 goto error_4;
1990         }
1991
1992         dev->umrc.qp = qp;
1993         dev->umrc.cq = cq;
1994         dev->umrc.pd = pd;
1995
1996         sema_init(&dev->umrc.sem, MAX_UMR_WR);
1997         ret = mlx5_mr_cache_init(dev);
1998         if (ret) {
1999                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2000                 goto error_4;
2001         }
2002
2003         kfree(attr);
2004         kfree(init_attr);
2005
2006         return 0;
2007
2008 error_4:
2009         mlx5_ib_destroy_qp(qp);
2010
2011 error_3:
2012         ib_free_cq(cq);
2013
2014 error_2:
2015         ib_dealloc_pd(pd);
2016
2017 error_0:
2018         kfree(attr);
2019         kfree(init_attr);
2020         return ret;
2021 }
2022
2023 static int create_dev_resources(struct mlx5_ib_resources *devr)
2024 {
2025         struct ib_srq_init_attr attr;
2026         struct mlx5_ib_dev *dev;
2027         struct ib_cq_init_attr cq_attr = {.cqe = 1};
2028         int port;
2029         int ret = 0;
2030
2031         dev = container_of(devr, struct mlx5_ib_dev, devr);
2032
2033         mutex_init(&devr->mutex);
2034
2035         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2036         if (IS_ERR(devr->p0)) {
2037                 ret = PTR_ERR(devr->p0);
2038                 goto error0;
2039         }
2040         devr->p0->device  = &dev->ib_dev;
2041         devr->p0->uobject = NULL;
2042         atomic_set(&devr->p0->usecnt, 0);
2043
2044         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2045         if (IS_ERR(devr->c0)) {
2046                 ret = PTR_ERR(devr->c0);
2047                 goto error1;
2048         }
2049         devr->c0->device        = &dev->ib_dev;
2050         devr->c0->uobject       = NULL;
2051         devr->c0->comp_handler  = NULL;
2052         devr->c0->event_handler = NULL;
2053         devr->c0->cq_context    = NULL;
2054         atomic_set(&devr->c0->usecnt, 0);
2055
2056         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2057         if (IS_ERR(devr->x0)) {
2058                 ret = PTR_ERR(devr->x0);
2059                 goto error2;
2060         }
2061         devr->x0->device = &dev->ib_dev;
2062         devr->x0->inode = NULL;
2063         atomic_set(&devr->x0->usecnt, 0);
2064         mutex_init(&devr->x0->tgt_qp_mutex);
2065         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2066
2067         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2068         if (IS_ERR(devr->x1)) {
2069                 ret = PTR_ERR(devr->x1);
2070                 goto error3;
2071         }
2072         devr->x1->device = &dev->ib_dev;
2073         devr->x1->inode = NULL;
2074         atomic_set(&devr->x1->usecnt, 0);
2075         mutex_init(&devr->x1->tgt_qp_mutex);
2076         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2077
2078         memset(&attr, 0, sizeof(attr));
2079         attr.attr.max_sge = 1;
2080         attr.attr.max_wr = 1;
2081         attr.srq_type = IB_SRQT_XRC;
2082         attr.ext.xrc.cq = devr->c0;
2083         attr.ext.xrc.xrcd = devr->x0;
2084
2085         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2086         if (IS_ERR(devr->s0)) {
2087                 ret = PTR_ERR(devr->s0);
2088                 goto error4;
2089         }
2090         devr->s0->device        = &dev->ib_dev;
2091         devr->s0->pd            = devr->p0;
2092         devr->s0->uobject       = NULL;
2093         devr->s0->event_handler = NULL;
2094         devr->s0->srq_context   = NULL;
2095         devr->s0->srq_type      = IB_SRQT_XRC;
2096         devr->s0->ext.xrc.xrcd  = devr->x0;
2097         devr->s0->ext.xrc.cq    = devr->c0;
2098         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2099         atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2100         atomic_inc(&devr->p0->usecnt);
2101         atomic_set(&devr->s0->usecnt, 0);
2102
2103         memset(&attr, 0, sizeof(attr));
2104         attr.attr.max_sge = 1;
2105         attr.attr.max_wr = 1;
2106         attr.srq_type = IB_SRQT_BASIC;
2107         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2108         if (IS_ERR(devr->s1)) {
2109                 ret = PTR_ERR(devr->s1);
2110                 goto error5;
2111         }
2112         devr->s1->device        = &dev->ib_dev;
2113         devr->s1->pd            = devr->p0;
2114         devr->s1->uobject       = NULL;
2115         devr->s1->event_handler = NULL;
2116         devr->s1->srq_context   = NULL;
2117         devr->s1->srq_type      = IB_SRQT_BASIC;
2118         devr->s1->ext.xrc.cq    = devr->c0;
2119         atomic_inc(&devr->p0->usecnt);
2120         atomic_set(&devr->s0->usecnt, 0);
2121
2122         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2123                 INIT_WORK(&devr->ports[port].pkey_change_work,
2124                           pkey_change_handler);
2125                 devr->ports[port].devr = devr;
2126         }
2127
2128         return 0;
2129
2130 error5:
2131         mlx5_ib_destroy_srq(devr->s0);
2132 error4:
2133         mlx5_ib_dealloc_xrcd(devr->x1);
2134 error3:
2135         mlx5_ib_dealloc_xrcd(devr->x0);
2136 error2:
2137         mlx5_ib_destroy_cq(devr->c0);
2138 error1:
2139         mlx5_ib_dealloc_pd(devr->p0);
2140 error0:
2141         return ret;
2142 }
2143
2144 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2145 {
2146         struct mlx5_ib_dev *dev =
2147                 container_of(devr, struct mlx5_ib_dev, devr);
2148         int port;
2149
2150         mlx5_ib_destroy_srq(devr->s1);
2151         mlx5_ib_destroy_srq(devr->s0);
2152         mlx5_ib_dealloc_xrcd(devr->x0);
2153         mlx5_ib_dealloc_xrcd(devr->x1);
2154         mlx5_ib_destroy_cq(devr->c0);
2155         mlx5_ib_dealloc_pd(devr->p0);
2156
2157         /* Make sure no change P_Key work items are still executing */
2158         for (port = 0; port < dev->num_ports; ++port)
2159                 cancel_work_sync(&devr->ports[port].pkey_change_work);
2160 }
2161
2162 static u32 get_core_cap_flags(struct ib_device *ibdev)
2163 {
2164         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2165         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2166         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2167         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2168         u32 ret = 0;
2169
2170         if (ll == IB_LINK_LAYER_INFINIBAND)
2171                 return RDMA_CORE_PORT_IBA_IB;
2172
2173         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2174                 return 0;
2175
2176         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2177                 return 0;
2178
2179         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2180                 ret |= RDMA_CORE_PORT_IBA_ROCE;
2181
2182         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2183                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2184
2185         return ret;
2186 }
2187
2188 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2189                                struct ib_port_immutable *immutable)
2190 {
2191         struct ib_port_attr attr;
2192         int err;
2193
2194         err = mlx5_ib_query_port(ibdev, port_num, &attr);
2195         if (err)
2196                 return err;
2197
2198         immutable->pkey_tbl_len = attr.pkey_tbl_len;
2199         immutable->gid_tbl_len = attr.gid_tbl_len;
2200         immutable->core_cap_flags = get_core_cap_flags(ibdev);
2201         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2202
2203         return 0;
2204 }
2205
2206 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2207 {
2208         int err;
2209
2210         dev->roce.nb.notifier_call = mlx5_netdev_event;
2211         err = register_netdevice_notifier(&dev->roce.nb);
2212         if (err)
2213                 return err;
2214
2215         err = mlx5_nic_vport_enable_roce(dev->mdev);
2216         if (err)
2217                 goto err_unregister_netdevice_notifier;
2218
2219         return 0;
2220
2221 err_unregister_netdevice_notifier:
2222         unregister_netdevice_notifier(&dev->roce.nb);
2223         return err;
2224 }
2225
2226 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2227 {
2228         mlx5_nic_vport_disable_roce(dev->mdev);
2229         unregister_netdevice_notifier(&dev->roce.nb);
2230 }
2231
2232 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
2233 {
2234         struct mlx5_ib_dev *dev;
2235         enum rdma_link_layer ll;
2236         int port_type_cap;
2237         int err;
2238         int i;
2239
2240         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2241         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2242
2243         if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
2244                 return NULL;
2245
2246         printk_once(KERN_INFO "%s", mlx5_version);
2247
2248         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2249         if (!dev)
2250                 return NULL;
2251
2252         dev->mdev = mdev;
2253
2254         rwlock_init(&dev->roce.netdev_lock);
2255         err = get_port_caps(dev);
2256         if (err)
2257                 goto err_dealloc;
2258
2259         if (mlx5_use_mad_ifc(dev))
2260                 get_ext_port_caps(dev);
2261
2262         MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2263
2264         strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
2265         dev->ib_dev.owner               = THIS_MODULE;
2266         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
2267         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
2268         dev->num_ports          = MLX5_CAP_GEN(mdev, num_ports);
2269         dev->ib_dev.phys_port_cnt     = dev->num_ports;
2270         dev->ib_dev.num_comp_vectors    =
2271                 dev->mdev->priv.eq_table.num_comp_vectors;
2272         dev->ib_dev.dma_device  = &mdev->pdev->dev;
2273
2274         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
2275         dev->ib_dev.uverbs_cmd_mask     =
2276                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
2277                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
2278                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
2279                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
2280                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
2281                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
2282                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
2283                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
2284                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2285                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
2286                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
2287                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
2288                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
2289                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
2290                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
2291                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
2292                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
2293                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
2294                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
2295                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
2296                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
2297                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
2298                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
2299                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
2300         dev->ib_dev.uverbs_ex_cmd_mask =
2301                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
2302                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
2303                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
2304
2305         dev->ib_dev.query_device        = mlx5_ib_query_device;
2306         dev->ib_dev.query_port          = mlx5_ib_query_port;
2307         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
2308         if (ll == IB_LINK_LAYER_ETHERNET)
2309                 dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
2310         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
2311         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
2312         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
2313         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
2314         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
2315         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
2316         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
2317         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
2318         dev->ib_dev.mmap                = mlx5_ib_mmap;
2319         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
2320         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
2321         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
2322         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
2323         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
2324         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
2325         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
2326         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
2327         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
2328         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
2329         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
2330         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
2331         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
2332         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
2333         dev->ib_dev.post_send           = mlx5_ib_post_send;
2334         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
2335         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
2336         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
2337         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
2338         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
2339         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
2340         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
2341         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
2342         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
2343         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
2344         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
2345         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
2346         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
2347         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
2348         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
2349         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
2350         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
2351         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
2352
2353         mlx5_ib_internal_fill_odp_caps(dev);
2354
2355         if (MLX5_CAP_GEN(mdev, imaicl)) {
2356                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
2357                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
2358                 dev->ib_dev.uverbs_cmd_mask |=
2359                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
2360                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2361         }
2362
2363         if (MLX5_CAP_GEN(mdev, xrc)) {
2364                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
2365                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
2366                 dev->ib_dev.uverbs_cmd_mask |=
2367                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2368                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2369         }
2370
2371         if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
2372             IB_LINK_LAYER_ETHERNET) {
2373                 dev->ib_dev.create_flow = mlx5_ib_create_flow;
2374                 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
2375                 dev->ib_dev.uverbs_ex_cmd_mask |=
2376                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2377                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
2378         }
2379         err = init_node_data(dev);
2380         if (err)
2381                 goto err_dealloc;
2382
2383         mutex_init(&dev->flow_db.lock);
2384         mutex_init(&dev->cap_mask_mutex);
2385
2386         if (ll == IB_LINK_LAYER_ETHERNET) {
2387                 err = mlx5_enable_roce(dev);
2388                 if (err)
2389                         goto err_dealloc;
2390         }
2391
2392         err = create_dev_resources(&dev->devr);
2393         if (err)
2394                 goto err_disable_roce;
2395
2396         err = mlx5_ib_odp_init_one(dev);
2397         if (err)
2398                 goto err_rsrc;
2399
2400         err = ib_register_device(&dev->ib_dev, NULL);
2401         if (err)
2402                 goto err_odp;
2403
2404         err = create_umr_res(dev);
2405         if (err)
2406                 goto err_dev;
2407
2408         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
2409                 err = device_create_file(&dev->ib_dev.dev,
2410                                          mlx5_class_attributes[i]);
2411                 if (err)
2412                         goto err_umrc;
2413         }
2414
2415         dev->ib_active = true;
2416
2417         return dev;
2418
2419 err_umrc:
2420         destroy_umrc_res(dev);
2421
2422 err_dev:
2423         ib_unregister_device(&dev->ib_dev);
2424
2425 err_odp:
2426         mlx5_ib_odp_remove_one(dev);
2427
2428 err_rsrc:
2429         destroy_dev_resources(&dev->devr);
2430
2431 err_disable_roce:
2432         if (ll == IB_LINK_LAYER_ETHERNET)
2433                 mlx5_disable_roce(dev);
2434
2435 err_dealloc:
2436         ib_dealloc_device((struct ib_device *)dev);
2437
2438         return NULL;
2439 }
2440
2441 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
2442 {
2443         struct mlx5_ib_dev *dev = context;
2444         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
2445
2446         ib_unregister_device(&dev->ib_dev);
2447         destroy_umrc_res(dev);
2448         mlx5_ib_odp_remove_one(dev);
2449         destroy_dev_resources(&dev->devr);
2450         if (ll == IB_LINK_LAYER_ETHERNET)
2451                 mlx5_disable_roce(dev);
2452         ib_dealloc_device(&dev->ib_dev);
2453 }
2454
2455 static struct mlx5_interface mlx5_ib_interface = {
2456         .add            = mlx5_ib_add,
2457         .remove         = mlx5_ib_remove,
2458         .event          = mlx5_ib_event,
2459         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
2460 };
2461
2462 static int __init mlx5_ib_init(void)
2463 {
2464         int err;
2465
2466         if (deprecated_prof_sel != 2)
2467                 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
2468
2469         err = mlx5_ib_odp_init();
2470         if (err)
2471                 return err;
2472
2473         err = mlx5_register_interface(&mlx5_ib_interface);
2474         if (err)
2475                 goto clean_odp;
2476
2477         return err;
2478
2479 clean_odp:
2480         mlx5_ib_odp_cleanup();
2481         return err;
2482 }
2483
2484 static void __exit mlx5_ib_cleanup(void)
2485 {
2486         mlx5_unregister_interface(&mlx5_ib_interface);
2487         mlx5_ib_odp_cleanup();
2488 }
2489
2490 module_init(mlx5_ib_init);
2491 module_exit(mlx5_ib_cleanup);