2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/sched.h>
38 #include <rdma/ib_verbs.h>
39 #include <rdma/ib_smi.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/cq.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/srq.h>
44 #include <linux/types.h>
46 #define mlx5_ib_dbg(dev, format, arg...) \
47 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
48 __LINE__, current->pid, ##arg)
50 #define mlx5_ib_err(dev, format, arg...) \
51 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
52 __LINE__, current->pid, ##arg)
54 #define mlx5_ib_warn(dev, format, arg...) \
55 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
56 __LINE__, current->pid, ##arg)
59 MLX5_IB_MMAP_CMD_SHIFT = 8,
60 MLX5_IB_MMAP_CMD_MASK = 0xff,
63 enum mlx5_ib_mmap_cmd {
64 MLX5_IB_MMAP_REGULAR_PAGE = 0,
65 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, /* always last */
69 MLX5_RES_SCAT_DATA32_CQE = 0x1,
70 MLX5_RES_SCAT_DATA64_CQE = 0x2,
71 MLX5_REQ_SCAT_DATA32_CQE = 0x11,
72 MLX5_REQ_SCAT_DATA64_CQE = 0x22,
75 enum mlx5_ib_latency_class {
76 MLX5_IB_LATENCY_CLASS_LOW,
77 MLX5_IB_LATENCY_CLASS_MEDIUM,
78 MLX5_IB_LATENCY_CLASS_HIGH,
79 MLX5_IB_LATENCY_CLASS_FAST_PATH
82 enum mlx5_ib_mad_ifc_flags {
83 MLX5_MAD_IFC_IGNORE_MKEY = 1,
84 MLX5_MAD_IFC_IGNORE_BKEY = 2,
85 MLX5_MAD_IFC_NET_VIEW = 4,
88 struct mlx5_ib_ucontext {
89 struct ib_ucontext ibucontext;
90 struct list_head db_page_list;
92 /* protect doorbell record alloc/free
94 struct mutex db_page_mutex;
95 struct mlx5_uuar_info uuari;
98 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
100 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
109 /* Use macros here so that don't have to duplicate
110 * enum ib_send_flags and enum ib_qp_type for low-level driver
113 #define MLX5_IB_SEND_UMR_UNREG IB_SEND_RESERVED_START
114 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 1)
115 #define MLX5_IB_SEND_UMR_UPDATE_MTT (IB_SEND_RESERVED_START << 2)
116 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
117 #define MLX5_IB_WR_UMR IB_WR_RESERVED1
127 struct wr_list *w_list;
131 /* serialize post to the work queue
154 struct mlx5_core_qp mqp;
158 struct mlx5_ib_wq rq;
163 int sq_max_wqes_per_wr;
165 struct mlx5_ib_wq sq;
167 struct ib_umem *umem;
170 /* serialize qp state modifications
187 /* only for user space QPs. For kernel
188 * we have it from the bf object
195 /* Store signature errors */
199 struct mlx5_ib_cq_buf {
201 struct ib_umem *umem;
206 enum mlx5_ib_qp_flags {
207 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = 1 << 0,
208 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 1,
217 unsigned int page_shift;
224 struct mlx5_shared_mr_info {
226 struct ib_umem *umem;
231 struct mlx5_core_cq mcq;
232 struct mlx5_ib_cq_buf buf;
235 /* serialize access to the CQ
241 struct mutex resize_mutex;
242 struct mlx5_ib_cq_buf *resize_buf;
243 struct ib_umem *resize_umem;
249 struct mlx5_core_srq msrq;
253 /* protect SRQ hanlding
259 struct ib_umem *umem;
260 /* serialize arming a SRQ
266 struct mlx5_ib_xrcd {
267 struct ib_xrcd ibxrcd;
271 enum mlx5_ib_mtt_access_flags {
272 MLX5_IB_MTT_READ = (1 << 0),
273 MLX5_IB_MTT_WRITE = (1 << 1),
276 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
280 struct mlx5_core_mr mmr;
281 struct ib_umem *umem;
282 struct mlx5_shared_mr_info *smr_info;
283 struct list_head list;
287 struct mlx5_ib_dev *dev;
288 struct mlx5_create_mkey_mbox_out out;
289 struct mlx5_core_sig_ctx *sig;
292 struct mlx5_ib_fast_reg_page_list {
293 struct ib_fast_reg_page_list ibfrpl;
294 __be64 *mapped_page_list;
298 struct mlx5_ib_umr_context {
299 enum ib_wc_status status;
300 struct completion done;
303 static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context)
305 context->status = -1;
306 init_completion(&context->done);
314 /* control access to UMR QP
316 struct semaphore sem;
327 struct mlx5_core_mr mr;
334 struct ib_send_wr wr[2];
336 struct ib_fast_reg_page_list page_list;
339 struct mlx5_cache_ent {
340 struct list_head head;
341 /* sync access to the cahce entry
354 struct dentry *fsize;
356 struct dentry *fmiss;
357 struct dentry *flimit;
359 struct mlx5_ib_dev *dev;
360 struct work_struct work;
361 struct delayed_work dwork;
365 struct mlx5_mr_cache {
366 struct workqueue_struct *wq;
367 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES];
370 unsigned long last_add;
373 struct mlx5_ib_resources {
382 struct ib_device ib_dev;
383 struct mlx5_core_dev *mdev;
384 MLX5_DECLARE_DOORBELL_LOCK(uar_lock);
385 struct list_head eqs_list;
387 int num_comp_vectors;
388 /* serialize update of capability mask
390 struct mutex cap_mask_mutex;
392 struct umr_common umrc;
393 /* sync used page count stats
396 struct mlx5_ib_resources devr;
397 struct mlx5_mr_cache cache;
398 struct timer_list delay_timer;
400 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
401 struct ib_odp_caps odp_caps;
405 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
407 return container_of(mcq, struct mlx5_ib_cq, mcq);
410 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
412 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
415 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
417 return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
420 static inline struct mlx5_ib_fmr *to_mfmr(struct ib_fmr *ibfmr)
422 return container_of(ibfmr, struct mlx5_ib_fmr, ibfmr);
425 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
427 return container_of(ibcq, struct mlx5_ib_cq, ibcq);
430 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
432 return container_of(mqp, struct mlx5_ib_qp, mqp);
435 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mr *mmr)
437 return container_of(mmr, struct mlx5_ib_mr, mmr);
440 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
442 return container_of(ibpd, struct mlx5_ib_pd, ibpd);
445 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
447 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
450 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
452 return container_of(ibqp, struct mlx5_ib_qp, ibqp);
455 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
457 return container_of(msrq, struct mlx5_ib_srq, msrq);
460 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
462 return container_of(ibmr, struct mlx5_ib_mr, ibmr);
465 static inline struct mlx5_ib_fast_reg_page_list *to_mfrpl(struct ib_fast_reg_page_list *ibfrpl)
467 return container_of(ibfrpl, struct mlx5_ib_fast_reg_page_list, ibfrpl);
475 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah)
477 return container_of(ibah, struct mlx5_ib_ah, ibah);
480 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt,
482 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
483 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
484 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
485 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
486 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey,
487 u8 port, struct ib_wc *in_wc, struct ib_grh *in_grh,
488 void *in_mad, void *response_mad);
489 struct ib_ah *create_ib_ah(struct ib_ah_attr *ah_attr,
490 struct mlx5_ib_ah *ah);
491 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr);
492 int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr);
493 int mlx5_ib_destroy_ah(struct ib_ah *ah);
494 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd,
495 struct ib_srq_init_attr *init_attr,
496 struct ib_udata *udata);
497 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
498 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
499 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
500 int mlx5_ib_destroy_srq(struct ib_srq *srq);
501 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
502 struct ib_recv_wr **bad_wr);
503 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
504 struct ib_qp_init_attr *init_attr,
505 struct ib_udata *udata);
506 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
507 int attr_mask, struct ib_udata *udata);
508 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
509 struct ib_qp_init_attr *qp_init_attr);
510 int mlx5_ib_destroy_qp(struct ib_qp *qp);
511 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
512 struct ib_send_wr **bad_wr);
513 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
514 struct ib_recv_wr **bad_wr);
515 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n);
516 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
517 void *buffer, u32 length);
518 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, int entries,
519 int vector, struct ib_ucontext *context,
520 struct ib_udata *udata);
521 int mlx5_ib_destroy_cq(struct ib_cq *cq);
522 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
523 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
524 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
525 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
526 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
527 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
528 u64 virt_addr, int access_flags,
529 struct ib_udata *udata);
530 int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index,
531 int npages, int zap);
532 int mlx5_ib_dereg_mr(struct ib_mr *ibmr);
533 int mlx5_ib_destroy_mr(struct ib_mr *ibmr);
534 struct ib_mr *mlx5_ib_create_mr(struct ib_pd *pd,
535 struct ib_mr_init_attr *mr_init_attr);
536 struct ib_mr *mlx5_ib_alloc_fast_reg_mr(struct ib_pd *pd,
537 int max_page_list_len);
538 struct ib_fast_reg_page_list *mlx5_ib_alloc_fast_reg_page_list(struct ib_device *ibdev,
540 void mlx5_ib_free_fast_reg_page_list(struct ib_fast_reg_page_list *page_list);
541 struct ib_fmr *mlx5_ib_fmr_alloc(struct ib_pd *pd, int acc,
542 struct ib_fmr_attr *fmr_attr);
543 int mlx5_ib_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
544 int npages, u64 iova);
545 int mlx5_ib_unmap_fmr(struct list_head *fmr_list);
546 int mlx5_ib_fmr_dealloc(struct ib_fmr *ibfmr);
547 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
548 struct ib_wc *in_wc, struct ib_grh *in_grh,
549 struct ib_mad *in_mad, struct ib_mad *out_mad);
550 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
551 struct ib_ucontext *context,
552 struct ib_udata *udata);
553 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd);
554 int mlx5_vector2eqn(struct mlx5_ib_dev *dev, int vector, int *eqn, int *irqn);
555 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset);
556 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port);
557 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
558 struct ib_port_attr *props);
559 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev);
560 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev);
561 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift,
562 int *ncont, int *order);
563 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
564 int page_shift, size_t offset, size_t num_pages,
565 __be64 *pas, int access_flags);
566 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
567 int page_shift, __be64 *pas, int access_flags);
568 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
569 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq);
570 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
571 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
572 int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift);
573 void mlx5_umr_cq_handler(struct ib_cq *cq, void *cq_context);
574 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
575 struct ib_mr_status *mr_status);
577 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
578 int mlx5_ib_internal_query_odp_caps(struct mlx5_ib_dev *dev);
580 static inline int mlx5_ib_internal_query_odp_caps(struct mlx5_ib_dev *dev)
584 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
586 static inline void init_query_mad(struct ib_smp *mad)
588 mad->base_version = 1;
589 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
590 mad->class_version = 1;
591 mad->method = IB_MGMT_METHOD_GET;
594 static inline u8 convert_access(int acc)
596 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
597 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
598 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
599 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
600 MLX5_PERM_LOCAL_READ;
603 #define MLX5_MAX_UMR_SHIFT 16
604 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
606 #endif /* MLX5_IB_H */