2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/sched.h>
38 #include <rdma/ib_verbs.h>
39 #include <rdma/ib_smi.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/cq.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/srq.h>
44 #include <linux/types.h>
45 #include <linux/mlx5/transobj.h>
47 #define mlx5_ib_dbg(dev, format, arg...) \
48 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
49 __LINE__, current->pid, ##arg)
51 #define mlx5_ib_err(dev, format, arg...) \
52 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
53 __LINE__, current->pid, ##arg)
55 #define mlx5_ib_warn(dev, format, arg...) \
56 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
57 __LINE__, current->pid, ##arg)
59 #define field_avail(type, fld, sz) (offsetof(type, fld) + \
60 sizeof(((type *)0)->fld) <= (sz))
61 #define MLX5_IB_DEFAULT_UIDX 0xffffff
62 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
65 MLX5_IB_MMAP_CMD_SHIFT = 8,
66 MLX5_IB_MMAP_CMD_MASK = 0xff,
69 enum mlx5_ib_mmap_cmd {
70 MLX5_IB_MMAP_REGULAR_PAGE = 0,
71 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
72 /* 5 is chosen in order to be compatible with old versions of libmlx5 */
73 MLX5_IB_MMAP_CORE_CLOCK = 5,
77 MLX5_RES_SCAT_DATA32_CQE = 0x1,
78 MLX5_RES_SCAT_DATA64_CQE = 0x2,
79 MLX5_REQ_SCAT_DATA32_CQE = 0x11,
80 MLX5_REQ_SCAT_DATA64_CQE = 0x22,
83 enum mlx5_ib_latency_class {
84 MLX5_IB_LATENCY_CLASS_LOW,
85 MLX5_IB_LATENCY_CLASS_MEDIUM,
86 MLX5_IB_LATENCY_CLASS_HIGH,
87 MLX5_IB_LATENCY_CLASS_FAST_PATH
90 enum mlx5_ib_mad_ifc_flags {
91 MLX5_MAD_IFC_IGNORE_MKEY = 1,
92 MLX5_MAD_IFC_IGNORE_BKEY = 2,
93 MLX5_MAD_IFC_NET_VIEW = 4,
97 MLX5_CROSS_CHANNEL_UUAR = 0,
105 struct mlx5_ib_ucontext {
106 struct ib_ucontext ibucontext;
107 struct list_head db_page_list;
109 /* protect doorbell record alloc/free
111 struct mutex db_page_mutex;
112 struct mlx5_uuar_info uuari;
114 /* Transport Domain number */
118 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
120 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
128 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1)
129 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_IB_FLOW_MCAST_PRIO - 1)
130 #if (MLX5_IB_FLOW_LAST_PRIO <= 0)
131 #error "Invalid number of bypass priorities"
133 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1)
135 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
136 struct mlx5_ib_flow_prio {
137 struct mlx5_flow_table *flow_table;
138 unsigned int refcount;
141 struct mlx5_ib_flow_handler {
142 struct list_head list;
143 struct ib_flow ibflow;
145 struct mlx5_flow_rule *rule;
148 struct mlx5_ib_flow_db {
149 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT];
150 /* Protect flow steering bypass flow tables
151 * when add/del flow rules.
152 * only single add/removal of flow steering rule could be done
158 /* Use macros here so that don't have to duplicate
159 * enum ib_send_flags and enum ib_qp_type for low-level driver
162 #define MLX5_IB_SEND_UMR_UNREG IB_SEND_RESERVED_START
163 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 1)
164 #define MLX5_IB_SEND_UMR_UPDATE_MTT (IB_SEND_RESERVED_START << 2)
165 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
166 #define MLX5_IB_WR_UMR IB_WR_RESERVED1
176 struct wr_list *w_list;
180 /* serialize post to the work queue
202 * Connect-IB can trigger up to four concurrent pagefaults
205 enum mlx5_ib_pagefault_context {
206 MLX5_IB_PAGEFAULT_RESPONDER_READ,
207 MLX5_IB_PAGEFAULT_REQUESTOR_READ,
208 MLX5_IB_PAGEFAULT_RESPONDER_WRITE,
209 MLX5_IB_PAGEFAULT_REQUESTOR_WRITE,
210 MLX5_IB_PAGEFAULT_CONTEXTS
213 static inline enum mlx5_ib_pagefault_context
214 mlx5_ib_get_pagefault_context(struct mlx5_pagefault *pagefault)
216 return pagefault->flags & (MLX5_PFAULT_REQUESTOR | MLX5_PFAULT_WRITE);
219 struct mlx5_ib_pfault {
220 struct work_struct work;
221 struct mlx5_pagefault mpfault;
224 struct mlx5_ib_ubuffer {
225 struct ib_umem *umem;
230 struct mlx5_ib_qp_base {
231 struct mlx5_ib_qp *container_mibqp;
232 struct mlx5_core_qp mqp;
233 struct mlx5_ib_ubuffer ubuffer;
236 struct mlx5_ib_qp_trans {
237 struct mlx5_ib_qp_base base;
245 struct mlx5_ib_qp_base base;
246 struct mlx5_ib_wq *rq;
247 struct mlx5_ib_ubuffer ubuffer;
248 struct mlx5_db *doorbell;
254 struct mlx5_ib_qp_base base;
255 struct mlx5_ib_wq *sq;
256 struct mlx5_ib_ubuffer ubuffer;
257 struct mlx5_db *doorbell;
262 struct mlx5_ib_raw_packet_qp {
263 struct mlx5_ib_sq sq;
264 struct mlx5_ib_rq rq;
270 struct mlx5_ib_qp_trans trans_qp;
271 struct mlx5_ib_raw_packet_qp raw_packet_qp;
276 struct mlx5_ib_wq rq;
280 struct mlx5_ib_wq sq;
282 /* serialize qp state modifications
294 /* only for user space QPs. For kernel
295 * we have it from the bf object
301 /* Store signature errors */
304 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
306 * A flag that is true for QP's that are in a state that doesn't
307 * allow page faults, and shouldn't schedule any more faults.
309 int disable_page_faults;
311 * The disable_page_faults_lock protects a QP's disable_page_faults
312 * field, allowing for a thread to atomically check whether the QP
313 * allows page faults, and if so schedule a page fault.
315 spinlock_t disable_page_faults_lock;
316 struct mlx5_ib_pfault pagefaults[MLX5_IB_PAGEFAULT_CONTEXTS];
320 struct mlx5_ib_cq_buf {
322 struct ib_umem *umem;
327 enum mlx5_ib_qp_flags {
328 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = 1 << 0,
329 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 1,
330 MLX5_IB_QP_CROSS_CHANNEL = 1 << 2,
331 MLX5_IB_QP_MANAGED_SEND = 1 << 3,
332 MLX5_IB_QP_MANAGED_RECV = 1 << 4,
336 struct ib_send_wr wr;
342 unsigned int page_shift;
349 static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr)
351 return container_of(wr, struct mlx5_umr_wr, wr);
354 struct mlx5_shared_mr_info {
356 struct ib_umem *umem;
361 struct mlx5_core_cq mcq;
362 struct mlx5_ib_cq_buf buf;
365 /* serialize access to the CQ
371 struct mutex resize_mutex;
372 struct mlx5_ib_cq_buf *resize_buf;
373 struct ib_umem *resize_umem;
380 struct mlx5_core_srq msrq;
384 /* protect SRQ hanlding
390 struct ib_umem *umem;
391 /* serialize arming a SRQ
397 struct mlx5_ib_xrcd {
398 struct ib_xrcd ibxrcd;
402 enum mlx5_ib_mtt_access_flags {
403 MLX5_IB_MTT_READ = (1 << 0),
404 MLX5_IB_MTT_WRITE = (1 << 1),
407 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
416 struct mlx5_core_mr mmr;
417 struct ib_umem *umem;
418 struct mlx5_shared_mr_info *smr_info;
419 struct list_head list;
423 struct mlx5_ib_dev *dev;
424 struct mlx5_create_mkey_mbox_out out;
425 struct mlx5_core_sig_ctx *sig;
430 struct mlx5_ib_umr_context {
431 enum ib_wc_status status;
432 struct completion done;
435 static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context)
437 context->status = -1;
438 init_completion(&context->done);
445 /* control access to UMR QP
447 struct semaphore sem;
456 struct mlx5_cache_ent {
457 struct list_head head;
458 /* sync access to the cahce entry
471 struct dentry *fsize;
473 struct dentry *fmiss;
474 struct dentry *flimit;
476 struct mlx5_ib_dev *dev;
477 struct work_struct work;
478 struct delayed_work dwork;
482 struct mlx5_mr_cache {
483 struct workqueue_struct *wq;
484 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES];
487 unsigned long last_add;
490 struct mlx5_ib_resources {
500 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL
503 rwlock_t netdev_lock;
504 struct net_device *netdev;
505 struct notifier_block nb;
509 struct ib_device ib_dev;
510 struct mlx5_core_dev *mdev;
511 struct mlx5_roce roce;
512 MLX5_DECLARE_DOORBELL_LOCK(uar_lock);
514 /* serialize update of capability mask
516 struct mutex cap_mask_mutex;
518 struct umr_common umrc;
519 /* sync used page count stats
521 struct mlx5_ib_resources devr;
522 struct mlx5_mr_cache cache;
523 struct timer_list delay_timer;
525 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
526 struct ib_odp_caps odp_caps;
528 * Sleepable RCU that prevents destruction of MRs while they are still
529 * being used by a page fault handler.
531 struct srcu_struct mr_srcu;
533 struct mlx5_ib_flow_db flow_db;
536 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
538 return container_of(mcq, struct mlx5_ib_cq, mcq);
541 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
543 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
546 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
548 return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
551 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
553 return container_of(ibcq, struct mlx5_ib_cq, ibcq);
556 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
558 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp;
561 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mr *mmr)
563 return container_of(mmr, struct mlx5_ib_mr, mmr);
566 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
568 return container_of(ibpd, struct mlx5_ib_pd, ibpd);
571 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
573 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
576 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
578 return container_of(ibqp, struct mlx5_ib_qp, ibqp);
581 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
583 return container_of(msrq, struct mlx5_ib_srq, msrq);
586 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
588 return container_of(ibmr, struct mlx5_ib_mr, ibmr);
596 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah)
598 return container_of(ibah, struct mlx5_ib_ah, ibah);
601 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt,
603 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
604 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
605 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
606 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
607 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey,
608 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh,
609 const void *in_mad, void *response_mad);
610 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr);
611 int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr);
612 int mlx5_ib_destroy_ah(struct ib_ah *ah);
613 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd,
614 struct ib_srq_init_attr *init_attr,
615 struct ib_udata *udata);
616 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
617 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
618 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
619 int mlx5_ib_destroy_srq(struct ib_srq *srq);
620 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
621 struct ib_recv_wr **bad_wr);
622 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
623 struct ib_qp_init_attr *init_attr,
624 struct ib_udata *udata);
625 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
626 int attr_mask, struct ib_udata *udata);
627 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
628 struct ib_qp_init_attr *qp_init_attr);
629 int mlx5_ib_destroy_qp(struct ib_qp *qp);
630 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
631 struct ib_send_wr **bad_wr);
632 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
633 struct ib_recv_wr **bad_wr);
634 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n);
635 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
636 void *buffer, u32 length,
637 struct mlx5_ib_qp_base *base);
638 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
639 const struct ib_cq_init_attr *attr,
640 struct ib_ucontext *context,
641 struct ib_udata *udata);
642 int mlx5_ib_destroy_cq(struct ib_cq *cq);
643 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
644 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
645 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
646 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
647 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
648 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
649 u64 virt_addr, int access_flags,
650 struct ib_udata *udata);
651 int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index,
652 int npages, int zap);
653 int mlx5_ib_dereg_mr(struct ib_mr *ibmr);
654 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd,
655 enum ib_mr_type mr_type,
657 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr,
658 struct scatterlist *sg,
660 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
661 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
662 const struct ib_mad_hdr *in, size_t in_mad_size,
663 struct ib_mad_hdr *out, size_t *out_mad_size,
664 u16 *out_mad_pkey_index);
665 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
666 struct ib_ucontext *context,
667 struct ib_udata *udata);
668 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd);
669 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset);
670 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port);
671 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev,
672 struct ib_smp *out_mad);
673 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
674 __be64 *sys_image_guid);
675 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
677 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
679 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
680 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
681 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index,
683 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index,
685 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port,
686 struct ib_port_attr *props);
687 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
688 struct ib_port_attr *props);
689 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev);
690 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev);
691 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift,
692 int *ncont, int *order);
693 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
694 int page_shift, size_t offset, size_t num_pages,
695 __be64 *pas, int access_flags);
696 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
697 int page_shift, __be64 *pas, int access_flags);
698 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
699 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq);
700 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
701 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
702 int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift);
703 void mlx5_umr_cq_handler(struct ib_cq *cq, void *cq_context);
704 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
705 struct ib_mr_status *mr_status);
707 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
708 extern struct workqueue_struct *mlx5_ib_page_fault_wq;
710 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev);
711 void mlx5_ib_mr_pfault_handler(struct mlx5_ib_qp *qp,
712 struct mlx5_ib_pfault *pfault);
713 void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp);
714 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev);
715 void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev);
716 int __init mlx5_ib_odp_init(void);
717 void mlx5_ib_odp_cleanup(void);
718 void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp);
719 void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp);
720 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start,
723 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
724 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev)
729 static inline void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp) {}
730 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; }
731 static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev) {}
732 static inline int mlx5_ib_odp_init(void) { return 0; }
733 static inline void mlx5_ib_odp_cleanup(void) {}
734 static inline void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp) {}
735 static inline void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp) {}
737 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
739 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
742 static inline void init_query_mad(struct ib_smp *mad)
744 mad->base_version = 1;
745 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
746 mad->class_version = 1;
747 mad->method = IB_MGMT_METHOD_GET;
750 static inline u8 convert_access(int acc)
752 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
753 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
754 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
755 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
756 MLX5_PERM_LOCAL_READ;
759 static inline int is_qp1(enum ib_qp_type qp_type)
761 return qp_type == IB_QPT_GSI;
764 #define MLX5_MAX_UMR_SHIFT 16
765 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
767 static inline u32 check_cq_create_flags(u32 flags)
770 * It returns non-zero value for unsupported CQ
771 * create flags, otherwise it returns zero.
773 return (flags & ~(IB_CQ_FLAGS_IGNORE_OVERRUN |
774 IB_CQ_FLAGS_TIMESTAMP_COMPLETION));
777 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx,
781 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) ||
782 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK))
784 *user_index = cmd_uidx;
786 *user_index = MLX5_IB_DEFAULT_UIDX;
791 #endif /* MLX5_IB_H */