drivers/infiniband/hw/ocrdma/ocrdma_hw.c

   1 /*******************************************************************
   2  * This file is part of the Emulex RoCE Device Driver for          *
   3  * RoCE (RDMA over Converged Ethernet) CNA Adapters.              *
   4  * Copyright (C) 2008-2012 Emulex. All rights reserved.            *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *
  20  * Contact Information:
  21  * linux-drivers@emulex.com
  22  *
  23  * Emulex
  24  * 3333 Susan Street
  25  * Costa Mesa, CA 92626
  26  *******************************************************************/
  27
  28 #include <linux/sched.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/log2.h>
  31 #include <linux/dma-mapping.h>
  32
  33 #include <rdma/ib_verbs.h>
  34 #include <rdma/ib_user_verbs.h>
  35
  36 #include "ocrdma.h"
  37 #include "ocrdma_hw.h"
  38 #include "ocrdma_verbs.h"
  39 #include "ocrdma_ah.h"
  40
  41 enum mbx_status {
  42         OCRDMA_MBX_STATUS_FAILED                = 1,
  43         OCRDMA_MBX_STATUS_ILLEGAL_FIELD         = 3,
  44         OCRDMA_MBX_STATUS_OOR                   = 100,
  45         OCRDMA_MBX_STATUS_INVALID_PD            = 101,
  46         OCRDMA_MBX_STATUS_PD_INUSE              = 102,
  47         OCRDMA_MBX_STATUS_INVALID_CQ            = 103,
  48         OCRDMA_MBX_STATUS_INVALID_QP            = 104,
  49         OCRDMA_MBX_STATUS_INVALID_LKEY          = 105,
  50         OCRDMA_MBX_STATUS_ORD_EXCEEDS           = 106,
  51         OCRDMA_MBX_STATUS_IRD_EXCEEDS           = 107,
  52         OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS     = 108,
  53         OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS     = 109,
  54         OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS      = 110,
  55         OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS     = 111,
  56         OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS      = 112,
  57         OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE  = 113,
  58         OCRDMA_MBX_STATUS_MW_BOUND              = 114,
  59         OCRDMA_MBX_STATUS_INVALID_VA            = 115,
  60         OCRDMA_MBX_STATUS_INVALID_LENGTH        = 116,
  61         OCRDMA_MBX_STATUS_INVALID_FBO           = 117,
  62         OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS    = 118,
  63         OCRDMA_MBX_STATUS_INVALID_PBE_SIZE      = 119,
  64         OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY     = 120,
  65         OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT     = 121,
  66         OCRDMA_MBX_STATUS_INVALID_SRQ_ID        = 129,
  67         OCRDMA_MBX_STATUS_SRQ_ERROR             = 133,
  68         OCRDMA_MBX_STATUS_RQE_EXCEEDS           = 134,
  69         OCRDMA_MBX_STATUS_MTU_EXCEEDS           = 135,
  70         OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS        = 136,
  71         OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS     = 137,
  72         OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS     = 138,
  73         OCRDMA_MBX_STATUS_QP_BOUND              = 130,
  74         OCRDMA_MBX_STATUS_INVALID_CHANGE        = 139,
  75         OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP      = 140,
  76         OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
  77         OCRDMA_MBX_STATUS_MW_STILL_BOUND        = 142,
  78         OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID    = 143,
  79         OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS    = 144
  80 };
  81
  82 enum additional_status {
  83         OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
  84 };
  85
  86 enum cqe_status {
  87         OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES  = 1,
  88         OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER         = 2,
  89         OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES    = 3,
  90         OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING            = 4,
  91         OCRDMA_MBX_CQE_STATUS_DMA_FAILED                = 5
  92 };
  93
  94 static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
  95 {
  96         return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
  97 }
  98
  99 static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
 100 {
 101         eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
 102 }
 103
 104 static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
 105 {
 106         struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
 107             (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
 108
 109         if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
 110                 return NULL;
 111         return cqe;
 112 }
 113
 114 static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
 115 {
 116         dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
 117 }
 118
 119 static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
 120 {
 121         return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
 122 }
 123
 124 static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
 125 {
 126         dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
 127 }
 128
 129 static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
 130 {
 131         return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
 132 }
 133
 134 enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
 135 {
 136         switch (qps) {
 137         case OCRDMA_QPS_RST:
 138                 return IB_QPS_RESET;
 139         case OCRDMA_QPS_INIT:
 140                 return IB_QPS_INIT;
 141         case OCRDMA_QPS_RTR:
 142                 return IB_QPS_RTR;
 143         case OCRDMA_QPS_RTS:
 144                 return IB_QPS_RTS;
 145         case OCRDMA_QPS_SQD:
 146         case OCRDMA_QPS_SQ_DRAINING:
 147                 return IB_QPS_SQD;
 148         case OCRDMA_QPS_SQE:
 149                 return IB_QPS_SQE;
 150         case OCRDMA_QPS_ERR:
 151                 return IB_QPS_ERR;
 152         }
 153         return IB_QPS_ERR;
 154 }
 155
 156 static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
 157 {
 158         switch (qps) {
 159         case IB_QPS_RESET:
 160                 return OCRDMA_QPS_RST;
 161         case IB_QPS_INIT:
 162                 return OCRDMA_QPS_INIT;
 163         case IB_QPS_RTR:
 164                 return OCRDMA_QPS_RTR;
 165         case IB_QPS_RTS:
 166                 return OCRDMA_QPS_RTS;
 167         case IB_QPS_SQD:
 168                 return OCRDMA_QPS_SQD;
 169         case IB_QPS_SQE:
 170                 return OCRDMA_QPS_SQE;
 171         case IB_QPS_ERR:
 172                 return OCRDMA_QPS_ERR;
 173         }
 174         return OCRDMA_QPS_ERR;
 175 }
 176
 177 static int ocrdma_get_mbx_errno(u32 status)
 178 {
 179         int err_num;
 180         u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
 181                                         OCRDMA_MBX_RSP_STATUS_SHIFT;
 182         u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
 183                                         OCRDMA_MBX_RSP_ASTATUS_SHIFT;
 184
 185         switch (mbox_status) {
 186         case OCRDMA_MBX_STATUS_OOR:
 187         case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
 188                 err_num = -EAGAIN;
 189                 break;
 190
 191         case OCRDMA_MBX_STATUS_INVALID_PD:
 192         case OCRDMA_MBX_STATUS_INVALID_CQ:
 193         case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
 194         case OCRDMA_MBX_STATUS_INVALID_QP:
 195         case OCRDMA_MBX_STATUS_INVALID_CHANGE:
 196         case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
 197         case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
 198         case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
 199         case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
 200         case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
 201         case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
 202         case OCRDMA_MBX_STATUS_INVALID_LKEY:
 203         case OCRDMA_MBX_STATUS_INVALID_VA:
 204         case OCRDMA_MBX_STATUS_INVALID_LENGTH:
 205         case OCRDMA_MBX_STATUS_INVALID_FBO:
 206         case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
 207         case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
 208         case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
 209         case OCRDMA_MBX_STATUS_SRQ_ERROR:
 210         case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
 211                 err_num = -EINVAL;
 212                 break;
 213
 214         case OCRDMA_MBX_STATUS_PD_INUSE:
 215         case OCRDMA_MBX_STATUS_QP_BOUND:
 216         case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
 217         case OCRDMA_MBX_STATUS_MW_BOUND:
 218                 err_num = -EBUSY;
 219                 break;
 220
 221         case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
 222         case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
 223         case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
 224         case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
 225         case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
 226         case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
 227         case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
 228         case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
 229         case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
 230                 err_num = -ENOBUFS;
 231                 break;
 232
 233         case OCRDMA_MBX_STATUS_FAILED:
 234                 switch (add_status) {
 235                 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
 236                         err_num = -EAGAIN;
 237                         break;
 238                 }
 239         default:
 240                 err_num = -EFAULT;
 241         }
 242         return err_num;
 243 }
 244
 245 char *port_speed_string(struct ocrdma_dev *dev)
 246 {
 247         char *str = "";
 248         u16 speeds_supported;
 249
 250         speeds_supported = dev->phy.fixed_speeds_supported |
 251                                 dev->phy.auto_speeds_supported;
 252         if (speeds_supported & OCRDMA_PHY_SPEED_40GBPS)
 253                 str = "40Gbps ";
 254         else if (speeds_supported & OCRDMA_PHY_SPEED_10GBPS)
 255                 str = "10Gbps ";
 256         else if (speeds_supported & OCRDMA_PHY_SPEED_1GBPS)
 257                 str = "1Gbps ";
 258
 259         return str;
 260 }
 261
 262 static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
 263 {
 264         int err_num = -EINVAL;
 265
 266         switch (cqe_status) {
 267         case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
 268                 err_num = -EPERM;
 269                 break;
 270         case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
 271                 err_num = -EINVAL;
 272                 break;
 273         case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
 274         case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
 275                 err_num = -EINVAL;
 276                 break;
 277         case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
 278         default:
 279                 err_num = -EINVAL;
 280                 break;
 281         }
 282         return err_num;
 283 }
 284
 285 void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
 286                        bool solicited, u16 cqe_popped)
 287 {
 288         u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
 289
 290         val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
 291              OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
 292
 293         if (armed)
 294                 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
 295         if (solicited)
 296                 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
 297         val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
 298         iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
 299 }
 300
 301 static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
 302 {
 303         u32 val = 0;
 304
 305         val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
 306         val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
 307         iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
 308 }
 309
 310 static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
 311                               bool arm, bool clear_int, u16 num_eqe)
 312 {
 313         u32 val = 0;
 314
 315         val |= eq_id & OCRDMA_EQ_ID_MASK;
 316         val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
 317         if (arm)
 318                 val |= (1 << OCRDMA_REARM_SHIFT);
 319         if (clear_int)
 320                 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
 321         val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
 322         val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
 323         iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
 324 }
 325
 326 static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
 327                             u8 opcode, u8 subsys, u32 cmd_len)
 328 {
 329         cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
 330         cmd_hdr->timeout = 20; /* seconds */
 331         cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
 332 }
 333
 334 static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
 335 {
 336         struct ocrdma_mqe *mqe;
 337
 338         mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
 339         if (!mqe)
 340                 return NULL;
 341         mqe->hdr.spcl_sge_cnt_emb |=
 342                 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
 343                                         OCRDMA_MQE_HDR_EMB_MASK;
 344         mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
 345
 346         ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
 347                         mqe->hdr.pyld_len);
 348         return mqe;
 349 }
 350
 351 static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
 352 {
 353         dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
 354 }
 355
 356 static int ocrdma_alloc_q(struct ocrdma_dev *dev,
 357                           struct ocrdma_queue_info *q, u16 len, u16 entry_size)
 358 {
 359         memset(q, 0, sizeof(*q));
 360         q->len = len;
 361         q->entry_size = entry_size;
 362         q->size = len * entry_size;
 363         q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
 364                                    &q->dma, GFP_KERNEL);
 365         if (!q->va)
 366                 return -ENOMEM;
 367         memset(q->va, 0, q->size);
 368         return 0;
 369 }
 370
 371 static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
 372                                         dma_addr_t host_pa, int hw_page_size)
 373 {
 374         int i;
 375
 376         for (i = 0; i < cnt; i++) {
 377                 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
 378                 q_pa[i].hi = (u32) upper_32_bits(host_pa);
 379                 host_pa += hw_page_size;
 380         }
 381 }
 382
 383 static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev,
 384                                struct ocrdma_queue_info *q, int queue_type)
 385 {
 386         u8 opcode = 0;
 387         int status;
 388         struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
 389
 390         switch (queue_type) {
 391         case QTYPE_MCCQ:
 392                 opcode = OCRDMA_CMD_DELETE_MQ;
 393                 break;
 394         case QTYPE_CQ:
 395                 opcode = OCRDMA_CMD_DELETE_CQ;
 396                 break;
 397         case QTYPE_EQ:
 398                 opcode = OCRDMA_CMD_DELETE_EQ;
 399                 break;
 400         default:
 401                 BUG();
 402         }
 403         memset(cmd, 0, sizeof(*cmd));
 404         ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 405         cmd->id = q->id;
 406
 407         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 408                                  cmd, sizeof(*cmd), NULL, NULL);
 409         if (!status)
 410                 q->created = false;
 411         return status;
 412 }
 413
 414 static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 415 {
 416         int status;
 417         struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
 418         struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
 419
 420         memset(cmd, 0, sizeof(*cmd));
 421         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
 422                         sizeof(*cmd));
 423
 424         cmd->req.rsvd_version = 2;
 425         cmd->num_pages = 4;
 426         cmd->valid = OCRDMA_CREATE_EQ_VALID;
 427         cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
 428
 429         ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
 430                              PAGE_SIZE_4K);
 431         status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
 432                                  NULL);
 433         if (!status) {
 434                 eq->q.id = rsp->vector_eqid & 0xffff;
 435                 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
 436                 eq->q.created = true;
 437         }
 438         return status;
 439 }
 440
 441 static int ocrdma_create_eq(struct ocrdma_dev *dev,
 442                             struct ocrdma_eq *eq, u16 q_len)
 443 {
 444         int status;
 445
 446         status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
 447                                 sizeof(struct ocrdma_eqe));
 448         if (status)
 449                 return status;
 450
 451         status = ocrdma_mbx_create_eq(dev, eq);
 452         if (status)
 453                 goto mbx_err;
 454         eq->dev = dev;
 455         ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
 456
 457         return 0;
 458 mbx_err:
 459         ocrdma_free_q(dev, &eq->q);
 460         return status;
 461 }
 462
 463 int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 464 {
 465         int irq;
 466
 467         if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
 468                 irq = dev->nic_info.pdev->irq;
 469         else
 470                 irq = dev->nic_info.msix.vector_list[eq->vector];
 471         return irq;
 472 }
 473
 474 static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 475 {
 476         if (eq->q.created) {
 477                 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
 478                 ocrdma_free_q(dev, &eq->q);
 479         }
 480 }
 481
 482 static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 483 {
 484         int irq;
 485
 486         /* disarm EQ so that interrupts are not generated
 487          * during freeing and EQ delete is in progress.
 488          */
 489         ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
 490
 491         irq = ocrdma_get_irq(dev, eq);
 492         free_irq(irq, eq);
 493         _ocrdma_destroy_eq(dev, eq);
 494 }
 495
 496 static void ocrdma_destroy_eqs(struct ocrdma_dev *dev)
 497 {
 498         int i;
 499
 500         for (i = 0; i < dev->eq_cnt; i++)
 501                 ocrdma_destroy_eq(dev, &dev->eq_tbl[i]);
 502 }
 503
 504 static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
 505                                    struct ocrdma_queue_info *cq,
 506                                    struct ocrdma_queue_info *eq)
 507 {
 508         struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
 509         struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
 510         int status;
 511
 512         memset(cmd, 0, sizeof(*cmd));
 513         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
 514                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 515
 516         cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
 517         cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
 518                 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
 519         cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
 520
 521         cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
 522         cmd->eqn = eq->id;
 523         cmd->pdid_cqecnt = cq->size / sizeof(struct ocrdma_mcqe);
 524
 525         ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
 526                              cq->dma, PAGE_SIZE_4K);
 527         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 528                                  cmd, sizeof(*cmd), NULL, NULL);
 529         if (!status) {
 530                 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
 531                 cq->created = true;
 532         }
 533         return status;
 534 }
 535
 536 static u32 ocrdma_encoded_q_len(int q_len)
 537 {
 538         u32 len_encoded = fls(q_len);   /* log2(len) + 1 */
 539
 540         if (len_encoded == 16)
 541                 len_encoded = 0;
 542         return len_encoded;
 543 }
 544
 545 static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
 546                                 struct ocrdma_queue_info *mq,
 547                                 struct ocrdma_queue_info *cq)
 548 {
 549         int num_pages, status;
 550         struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
 551         struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
 552         struct ocrdma_pa *pa;
 553
 554         memset(cmd, 0, sizeof(*cmd));
 555         num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
 556
 557         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
 558                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 559         cmd->req.rsvd_version = 1;
 560         cmd->cqid_pages = num_pages;
 561         cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
 562         cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
 563
 564         cmd->async_event_bitmap = BIT(OCRDMA_ASYNC_GRP5_EVE_CODE);
 565         cmd->async_event_bitmap |= BIT(OCRDMA_ASYNC_RDMA_EVE_CODE);
 566
 567         cmd->async_cqid_ringsize = cq->id;
 568         cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
 569                                 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
 570         cmd->valid = OCRDMA_CREATE_MQ_VALID;
 571         pa = &cmd->pa[0];
 572
 573         ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
 574         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 575                                  cmd, sizeof(*cmd), NULL, NULL);
 576         if (!status) {
 577                 mq->id = rsp->id;
 578                 mq->created = true;
 579         }
 580         return status;
 581 }
 582
 583 static int ocrdma_create_mq(struct ocrdma_dev *dev)
 584 {
 585         int status;
 586
 587         /* Alloc completion queue for Mailbox queue */
 588         status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
 589                                 sizeof(struct ocrdma_mcqe));
 590         if (status)
 591                 goto alloc_err;
 592
 593         dev->eq_tbl[0].cq_cnt++;
 594         status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q);
 595         if (status)
 596                 goto mbx_cq_free;
 597
 598         memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
 599         init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
 600         mutex_init(&dev->mqe_ctx.lock);
 601
 602         /* Alloc Mailbox queue */
 603         status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
 604                                 sizeof(struct ocrdma_mqe));
 605         if (status)
 606                 goto mbx_cq_destroy;
 607         status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
 608         if (status)
 609                 goto mbx_q_free;
 610         ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
 611         return 0;
 612
 613 mbx_q_free:
 614         ocrdma_free_q(dev, &dev->mq.sq);
 615 mbx_cq_destroy:
 616         ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
 617 mbx_cq_free:
 618         ocrdma_free_q(dev, &dev->mq.cq);
 619 alloc_err:
 620         return status;
 621 }
 622
 623 static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
 624 {
 625         struct ocrdma_queue_info *mbxq, *cq;
 626
 627         /* mqe_ctx lock synchronizes with any other pending cmds. */
 628         mutex_lock(&dev->mqe_ctx.lock);
 629         mbxq = &dev->mq.sq;
 630         if (mbxq->created) {
 631                 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
 632                 ocrdma_free_q(dev, mbxq);
 633         }
 634         mutex_unlock(&dev->mqe_ctx.lock);
 635
 636         cq = &dev->mq.cq;
 637         if (cq->created) {
 638                 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
 639                 ocrdma_free_q(dev, cq);
 640         }
 641 }
 642
 643 static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
 644                                        struct ocrdma_qp *qp)
 645 {
 646         enum ib_qp_state new_ib_qps = IB_QPS_ERR;
 647         enum ib_qp_state old_ib_qps;
 648
 649         if (qp == NULL)
 650                 BUG();
 651         ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
 652 }
 653
 654 static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
 655                                     struct ocrdma_ae_mcqe *cqe)
 656 {
 657         struct ocrdma_qp *qp = NULL;
 658         struct ocrdma_cq *cq = NULL;
 659         struct ib_event ib_evt;
 660         int cq_event = 0;
 661         int qp_event = 1;
 662         int srq_event = 0;
 663         int dev_event = 0;
 664         int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
 665             OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
 666
 667         if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID)
 668                 qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK];
 669         if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID)
 670                 cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK];
 671
 672         memset(&ib_evt, 0, sizeof(ib_evt));
 673
 674         ib_evt.device = &dev->ibdev;
 675
 676         switch (type) {
 677         case OCRDMA_CQ_ERROR:
 678                 ib_evt.element.cq = &cq->ibcq;
 679                 ib_evt.event = IB_EVENT_CQ_ERR;
 680                 cq_event = 1;
 681                 qp_event = 0;
 682                 break;
 683         case OCRDMA_CQ_OVERRUN_ERROR:
 684                 ib_evt.element.cq = &cq->ibcq;
 685                 ib_evt.event = IB_EVENT_CQ_ERR;
 686                 cq_event = 1;
 687                 qp_event = 0;
 688                 break;
 689         case OCRDMA_CQ_QPCAT_ERROR:
 690                 ib_evt.element.qp = &qp->ibqp;
 691                 ib_evt.event = IB_EVENT_QP_FATAL;
 692                 ocrdma_process_qpcat_error(dev, qp);
 693                 break;
 694         case OCRDMA_QP_ACCESS_ERROR:
 695                 ib_evt.element.qp = &qp->ibqp;
 696                 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
 697                 break;
 698         case OCRDMA_QP_COMM_EST_EVENT:
 699                 ib_evt.element.qp = &qp->ibqp;
 700                 ib_evt.event = IB_EVENT_COMM_EST;
 701                 break;
 702         case OCRDMA_SQ_DRAINED_EVENT:
 703                 ib_evt.element.qp = &qp->ibqp;
 704                 ib_evt.event = IB_EVENT_SQ_DRAINED;
 705                 break;
 706         case OCRDMA_DEVICE_FATAL_EVENT:
 707                 ib_evt.element.port_num = 1;
 708                 ib_evt.event = IB_EVENT_DEVICE_FATAL;
 709                 qp_event = 0;
 710                 dev_event = 1;
 711                 break;
 712         case OCRDMA_SRQCAT_ERROR:
 713                 ib_evt.element.srq = &qp->srq->ibsrq;
 714                 ib_evt.event = IB_EVENT_SRQ_ERR;
 715                 srq_event = 1;
 716                 qp_event = 0;
 717                 break;
 718         case OCRDMA_SRQ_LIMIT_EVENT:
 719                 ib_evt.element.srq = &qp->srq->ibsrq;
 720                 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
 721                 srq_event = 1;
 722                 qp_event = 0;
 723                 break;
 724         case OCRDMA_QP_LAST_WQE_EVENT:
 725                 ib_evt.element.qp = &qp->ibqp;
 726                 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
 727                 break;
 728         default:
 729                 cq_event = 0;
 730                 qp_event = 0;
 731                 srq_event = 0;
 732                 dev_event = 0;
 733                 pr_err("%s() unknown type=0x%x\n", __func__, type);
 734                 break;
 735         }
 736
 737         if (qp_event) {
 738                 if (qp->ibqp.event_handler)
 739                         qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
 740         } else if (cq_event) {
 741                 if (cq->ibcq.event_handler)
 742                         cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
 743         } else if (srq_event) {
 744                 if (qp->srq->ibsrq.event_handler)
 745                         qp->srq->ibsrq.event_handler(&ib_evt,
 746                                                      qp->srq->ibsrq.
 747                                                      srq_context);
 748         } else if (dev_event) {
 749                 pr_err("%s: Fatal event received\n", dev->ibdev.name);
 750                 ib_dispatch_event(&ib_evt);
 751         }
 752
 753 }
 754
 755 static void ocrdma_process_grp5_aync(struct ocrdma_dev *dev,
 756                                         struct ocrdma_ae_mcqe *cqe)
 757 {
 758         struct ocrdma_ae_pvid_mcqe *evt;
 759         int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
 760                         OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
 761
 762         switch (type) {
 763         case OCRDMA_ASYNC_EVENT_PVID_STATE:
 764                 evt = (struct ocrdma_ae_pvid_mcqe *)cqe;
 765                 if ((evt->tag_enabled & OCRDMA_AE_PVID_MCQE_ENABLED_MASK) >>
 766                         OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT)
 767                         dev->pvid = ((evt->tag_enabled &
 768                                         OCRDMA_AE_PVID_MCQE_TAG_MASK) >>
 769                                         OCRDMA_AE_PVID_MCQE_TAG_SHIFT);
 770                 break;
 771
 772         case OCRDMA_ASYNC_EVENT_COS_VALUE:
 773                 atomic_set(&dev->update_sl, 1);
 774                 break;
 775         default:
 776                 /* Not interested evts. */
 777                 break;
 778         }
 779 }
 780
 781 static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
 782 {
 783         /* async CQE processing */
 784         struct ocrdma_ae_mcqe *cqe = ae_cqe;
 785         u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
 786                         OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
 787
 788         if (evt_code == OCRDMA_ASYNC_RDMA_EVE_CODE)
 789                 ocrdma_dispatch_ibevent(dev, cqe);
 790         else if (evt_code == OCRDMA_ASYNC_GRP5_EVE_CODE)
 791                 ocrdma_process_grp5_aync(dev, cqe);
 792         else
 793                 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
 794                        dev->id, evt_code);
 795 }
 796
 797 static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
 798 {
 799         if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
 800                 dev->mqe_ctx.cqe_status = (cqe->status &
 801                      OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
 802                 dev->mqe_ctx.ext_status =
 803                     (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
 804                     >> OCRDMA_MCQE_ESTATUS_SHIFT;
 805                 dev->mqe_ctx.cmd_done = true;
 806                 wake_up(&dev->mqe_ctx.cmd_wait);
 807         } else
 808                 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
 809                        __func__, cqe->tag_lo, dev->mqe_ctx.tag);
 810 }
 811
 812 static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
 813 {
 814         u16 cqe_popped = 0;
 815         struct ocrdma_mcqe *cqe;
 816
 817         while (1) {
 818                 cqe = ocrdma_get_mcqe(dev);
 819                 if (cqe == NULL)
 820                         break;
 821                 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
 822                 cqe_popped += 1;
 823                 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
 824                         ocrdma_process_acqe(dev, cqe);
 825                 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
 826                         ocrdma_process_mcqe(dev, cqe);
 827                 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
 828                 ocrdma_mcq_inc_tail(dev);
 829         }
 830         ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
 831         return 0;
 832 }
 833
 834 static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
 835                                        struct ocrdma_cq *cq)
 836 {
 837         unsigned long flags;
 838         struct ocrdma_qp *qp;
 839         bool buddy_cq_found = false;
 840         /* Go through list of QPs in error state which are using this CQ
 841          * and invoke its callback handler to trigger CQE processing for
 842          * error/flushed CQE. It is rare to find more than few entries in
 843          * this list as most consumers stops after getting error CQE.
 844          * List is traversed only once when a matching buddy cq found for a QP.
 845          */
 846         spin_lock_irqsave(&dev->flush_q_lock, flags);
 847         list_for_each_entry(qp, &cq->sq_head, sq_entry) {
 848                 if (qp->srq)
 849                         continue;
 850                 /* if wq and rq share the same cq, than comp_handler
 851                  * is already invoked.
 852                  */
 853                 if (qp->sq_cq == qp->rq_cq)
 854                         continue;
 855                 /* if completion came on sq, rq's cq is buddy cq.
 856                  * if completion came on rq, sq's cq is buddy cq.
 857                  */
 858                 if (qp->sq_cq == cq)
 859                         cq = qp->rq_cq;
 860                 else
 861                         cq = qp->sq_cq;
 862                 buddy_cq_found = true;
 863                 break;
 864         }
 865         spin_unlock_irqrestore(&dev->flush_q_lock, flags);
 866         if (buddy_cq_found == false)
 867                 return;
 868         if (cq->ibcq.comp_handler) {
 869                 spin_lock_irqsave(&cq->comp_handler_lock, flags);
 870                 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
 871                 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
 872         }
 873 }
 874
 875 static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
 876 {
 877         unsigned long flags;
 878         struct ocrdma_cq *cq;
 879
 880         if (cq_idx >= OCRDMA_MAX_CQ)
 881                 BUG();
 882
 883         cq = dev->cq_tbl[cq_idx];
 884         if (cq == NULL)
 885                 return;
 886
 887         if (cq->ibcq.comp_handler) {
 888                 spin_lock_irqsave(&cq->comp_handler_lock, flags);
 889                 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
 890                 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
 891         }
 892         ocrdma_qp_buddy_cq_handler(dev, cq);
 893 }
 894
 895 static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
 896 {
 897         /* process the MQ-CQE. */
 898         if (cq_id == dev->mq.cq.id)
 899                 ocrdma_mq_cq_handler(dev, cq_id);
 900         else
 901                 ocrdma_qp_cq_handler(dev, cq_id);
 902 }
 903
 904 static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
 905 {
 906         struct ocrdma_eq *eq = handle;
 907         struct ocrdma_dev *dev = eq->dev;
 908         struct ocrdma_eqe eqe;
 909         struct ocrdma_eqe *ptr;
 910         u16 cq_id;
 911         int budget = eq->cq_cnt;
 912
 913         do {
 914                 ptr = ocrdma_get_eqe(eq);
 915                 eqe = *ptr;
 916                 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
 917                 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
 918                         break;
 919
 920                 ptr->id_valid = 0;
 921                 /* ring eq doorbell as soon as its consumed. */
 922                 ocrdma_ring_eq_db(dev, eq->q.id, false, true, 1);
 923                 /* check whether its CQE or not. */
 924                 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
 925                         cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
 926                         ocrdma_cq_handler(dev, cq_id);
 927                 }
 928                 ocrdma_eq_inc_tail(eq);
 929
 930                 /* There can be a stale EQE after the last bound CQ is
 931                  * destroyed. EQE valid and budget == 0 implies this.
 932                  */
 933                 if (budget)
 934                         budget--;
 935
 936         } while (budget);
 937
 938         ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
 939         return IRQ_HANDLED;
 940 }
 941
 942 static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
 943 {
 944         struct ocrdma_mqe *mqe;
 945
 946         dev->mqe_ctx.tag = dev->mq.sq.head;
 947         dev->mqe_ctx.cmd_done = false;
 948         mqe = ocrdma_get_mqe(dev);
 949         cmd->hdr.tag_lo = dev->mq.sq.head;
 950         ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
 951         /* make sure descriptor is written before ringing doorbell */
 952         wmb();
 953         ocrdma_mq_inc_head(dev);
 954         ocrdma_ring_mq_db(dev);
 955 }
 956
 957 static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
 958 {
 959         long status;
 960         /* 30 sec timeout */
 961         status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
 962                                     (dev->mqe_ctx.cmd_done != false),
 963                                     msecs_to_jiffies(30000));
 964         if (status)
 965                 return 0;
 966         else {
 967                 dev->mqe_ctx.fw_error_state = true;
 968                 pr_err("%s(%d) mailbox timeout: fw not responding\n",
 969                        __func__, dev->id);
 970                 return -1;
 971         }
 972 }
 973
 974 /* issue a mailbox command on the MQ */
 975 static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
 976 {
 977         int status = 0;
 978         u16 cqe_status, ext_status;
 979         struct ocrdma_mqe *rsp_mqe;
 980         struct ocrdma_mbx_rsp *rsp = NULL;
 981
 982         mutex_lock(&dev->mqe_ctx.lock);
 983         if (dev->mqe_ctx.fw_error_state)
 984                 goto mbx_err;
 985         ocrdma_post_mqe(dev, mqe);
 986         status = ocrdma_wait_mqe_cmpl(dev);
 987         if (status)
 988                 goto mbx_err;
 989         cqe_status = dev->mqe_ctx.cqe_status;
 990         ext_status = dev->mqe_ctx.ext_status;
 991         rsp_mqe = ocrdma_get_mqe_rsp(dev);
 992         ocrdma_copy_le32_to_cpu(mqe, rsp_mqe, (sizeof(*mqe)));
 993         if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
 994                                 OCRDMA_MQE_HDR_EMB_SHIFT)
 995                 rsp = &mqe->u.rsp;
 996
 997         if (cqe_status || ext_status) {
 998                 pr_err("%s() cqe_status=0x%x, ext_status=0x%x,",
 999                        __func__, cqe_status, ext_status);
1000                 if (rsp) {
1001                         /* This is for embedded cmds. */
1002                         pr_err("opcode=0x%x, subsystem=0x%x\n",
1003                                (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1004                                 OCRDMA_MBX_RSP_OPCODE_SHIFT,
1005                                 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1006                                 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1007                 }
1008                 status = ocrdma_get_mbx_cqe_errno(cqe_status);
1009                 goto mbx_err;
1010         }
1011         /* For non embedded, rsp errors are handled in ocrdma_nonemb_mbx_cmd */
1012         if (rsp && (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK))
1013                 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
1014 mbx_err:
1015         mutex_unlock(&dev->mqe_ctx.lock);
1016         return status;
1017 }
1018
1019 static int ocrdma_nonemb_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe,
1020                                  void *payload_va)
1021 {
1022         int status = 0;
1023         struct ocrdma_mbx_rsp *rsp = payload_va;
1024
1025         if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1026                                 OCRDMA_MQE_HDR_EMB_SHIFT)
1027                 BUG();
1028
1029         status = ocrdma_mbx_cmd(dev, mqe);
1030         if (!status)
1031                 /* For non embedded, only CQE failures are handled in
1032                  * ocrdma_mbx_cmd. We need to check for RSP errors.
1033                  */
1034                 if (rsp->status & OCRDMA_MBX_RSP_STATUS_MASK)
1035                         status = ocrdma_get_mbx_errno(rsp->status);
1036
1037         if (status)
1038                 pr_err("opcode=0x%x, subsystem=0x%x\n",
1039                        (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1040                         OCRDMA_MBX_RSP_OPCODE_SHIFT,
1041                         (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1042                         OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1043         return status;
1044 }
1045
1046 static void ocrdma_get_attr(struct ocrdma_dev *dev,
1047                               struct ocrdma_dev_attr *attr,
1048                               struct ocrdma_mbx_query_config *rsp)
1049 {
1050         attr->max_pd =
1051             (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
1052             OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
1053         attr->max_dpp_pds =
1054            (rsp->max_dpp_pds_credits & OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK) >>
1055             OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET;
1056         attr->max_qp =
1057             (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
1058             OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
1059         attr->max_srq =
1060                 (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >>
1061                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET;
1062         attr->max_send_sge = ((rsp->max_write_send_sge &
1063                                OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1064                               OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
1065         attr->max_recv_sge = (rsp->max_write_send_sge &
1066                               OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1067             OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
1068         attr->max_srq_sge = (rsp->max_srq_rqe_sge &
1069                               OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
1070             OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
1071         attr->max_rdma_sge = (rsp->max_write_send_sge &
1072                               OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK) >>
1073             OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT;
1074         attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1075                                 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1076             OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
1077         attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1078                                 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1079             OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1080         attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1081                                     OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1082             OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1083         attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1084                                OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1085             OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1086         attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1087                                     OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1088             OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
1089         attr->max_mw = rsp->max_mw;
1090         attr->max_mr = rsp->max_mr;
1091         attr->max_mr_size = ((u64)rsp->max_mr_size_hi << 32) |
1092                               rsp->max_mr_size_lo;
1093         attr->max_fmr = 0;
1094         attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1095         attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1096         attr->max_cqe = rsp->max_cq_cqes_per_cq &
1097                         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
1098         attr->max_cq = (rsp->max_cq_cqes_per_cq &
1099                         OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK) >>
1100                         OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET;
1101         attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1102                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1103                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1104                 OCRDMA_WQE_STRIDE;
1105         attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1106                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1107                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1108                 OCRDMA_WQE_STRIDE;
1109         attr->max_inline_data =
1110             attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1111                               sizeof(struct ocrdma_sge));
1112         if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1113                 attr->ird = 1;
1114                 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1115                 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
1116         }
1117         dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1118                  OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1119         dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1120                 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
1121 }
1122
1123 static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1124                                    struct ocrdma_fw_conf_rsp *conf)
1125 {
1126         u32 fn_mode;
1127
1128         fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1129         if (fn_mode != OCRDMA_FN_MODE_RDMA)
1130                 return -EINVAL;
1131         dev->base_eqid = conf->base_eqid;
1132         dev->max_eq = conf->max_eq;
1133         return 0;
1134 }
1135
1136 /* can be issued only during init time. */
1137 static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1138 {
1139         int status = -ENOMEM;
1140         struct ocrdma_mqe *cmd;
1141         struct ocrdma_fw_ver_rsp *rsp;
1142
1143         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1144         if (!cmd)
1145                 return -ENOMEM;
1146         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1147                         OCRDMA_CMD_GET_FW_VER,
1148                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1149
1150         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1151         if (status)
1152                 goto mbx_err;
1153         rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1154         memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1155         memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1156                sizeof(rsp->running_ver));
1157         ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1158 mbx_err:
1159         kfree(cmd);
1160         return status;
1161 }
1162
1163 /* can be issued only during init time. */
1164 static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1165 {
1166         int status = -ENOMEM;
1167         struct ocrdma_mqe *cmd;
1168         struct ocrdma_fw_conf_rsp *rsp;
1169
1170         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1171         if (!cmd)
1172                 return -ENOMEM;
1173         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1174                         OCRDMA_CMD_GET_FW_CONFIG,
1175                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1176         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1177         if (status)
1178                 goto mbx_err;
1179         rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1180         status = ocrdma_check_fw_config(dev, rsp);
1181 mbx_err:
1182         kfree(cmd);
1183         return status;
1184 }
1185
1186 int ocrdma_mbx_rdma_stats(struct ocrdma_dev *dev, bool reset)
1187 {
1188         struct ocrdma_rdma_stats_req *req = dev->stats_mem.va;
1189         struct ocrdma_mqe *mqe = &dev->stats_mem.mqe;
1190         struct ocrdma_rdma_stats_resp *old_stats;
1191         int status;
1192
1193         old_stats = kmalloc(sizeof(*old_stats), GFP_KERNEL);
1194         if (old_stats == NULL)
1195                 return -ENOMEM;
1196
1197         memset(mqe, 0, sizeof(*mqe));
1198         mqe->hdr.pyld_len = dev->stats_mem.size;
1199         mqe->hdr.spcl_sge_cnt_emb |=
1200                         (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1201                                 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1202         mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dev->stats_mem.pa & 0xffffffff);
1203         mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dev->stats_mem.pa);
1204         mqe->u.nonemb_req.sge[0].len = dev->stats_mem.size;
1205
1206         /* Cache the old stats */
1207         memcpy(old_stats, req, sizeof(struct ocrdma_rdma_stats_resp));
1208         memset(req, 0, dev->stats_mem.size);
1209
1210         ocrdma_init_mch((struct ocrdma_mbx_hdr *)req,
1211                         OCRDMA_CMD_GET_RDMA_STATS,
1212                         OCRDMA_SUBSYS_ROCE,
1213                         dev->stats_mem.size);
1214         if (reset)
1215                 req->reset_stats = reset;
1216
1217         status = ocrdma_nonemb_mbx_cmd(dev, mqe, dev->stats_mem.va);
1218         if (status)
1219                 /* Copy from cache, if mbox fails */
1220                 memcpy(req, old_stats, sizeof(struct ocrdma_rdma_stats_resp));
1221         else
1222                 ocrdma_le32_to_cpu(req, dev->stats_mem.size);
1223
1224         kfree(old_stats);
1225         return status;
1226 }
1227
1228 static int ocrdma_mbx_get_ctrl_attribs(struct ocrdma_dev *dev)
1229 {
1230         int status = -ENOMEM;
1231         struct ocrdma_dma_mem dma;
1232         struct ocrdma_mqe *mqe;
1233         struct ocrdma_get_ctrl_attribs_rsp *ctrl_attr_rsp;
1234         struct mgmt_hba_attribs *hba_attribs;
1235
1236         mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
1237         if (!mqe)
1238                 return status;
1239
1240         dma.size = sizeof(struct ocrdma_get_ctrl_attribs_rsp);
1241         dma.va   = dma_alloc_coherent(&dev->nic_info.pdev->dev,
1242                                         dma.size, &dma.pa, GFP_KERNEL);
1243         if (!dma.va)
1244                 goto free_mqe;
1245
1246         mqe->hdr.pyld_len = dma.size;
1247         mqe->hdr.spcl_sge_cnt_emb |=
1248                         (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1249                         OCRDMA_MQE_HDR_SGE_CNT_MASK;
1250         mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dma.pa & 0xffffffff);
1251         mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dma.pa);
1252         mqe->u.nonemb_req.sge[0].len = dma.size;
1253
1254         memset(dma.va, 0, dma.size);
1255         ocrdma_init_mch((struct ocrdma_mbx_hdr *)dma.va,
1256                         OCRDMA_CMD_GET_CTRL_ATTRIBUTES,
1257                         OCRDMA_SUBSYS_COMMON,
1258                         dma.size);
1259
1260         status = ocrdma_nonemb_mbx_cmd(dev, mqe, dma.va);
1261         if (!status) {
1262                 ctrl_attr_rsp = (struct ocrdma_get_ctrl_attribs_rsp *)dma.va;
1263                 hba_attribs = &ctrl_attr_rsp->ctrl_attribs.hba_attribs;
1264
1265                 dev->hba_port_num = (hba_attribs->ptpnum_maxdoms_hbast_cv &
1266                                         OCRDMA_HBA_ATTRB_PTNUM_MASK)
1267                                         >> OCRDMA_HBA_ATTRB_PTNUM_SHIFT;
1268                 strncpy(dev->model_number,
1269                         hba_attribs->controller_model_number, 31);
1270         }
1271         dma_free_coherent(&dev->nic_info.pdev->dev, dma.size, dma.va, dma.pa);
1272 free_mqe:
1273         kfree(mqe);
1274         return status;
1275 }
1276
1277 static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1278 {
1279         int status = -ENOMEM;
1280         struct ocrdma_mbx_query_config *rsp;
1281         struct ocrdma_mqe *cmd;
1282
1283         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1284         if (!cmd)
1285                 return status;
1286         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1287         if (status)
1288                 goto mbx_err;
1289         rsp = (struct ocrdma_mbx_query_config *)cmd;
1290         ocrdma_get_attr(dev, &dev->attr, rsp);
1291 mbx_err:
1292         kfree(cmd);
1293         return status;
1294 }
1295
1296 int ocrdma_mbx_get_link_speed(struct ocrdma_dev *dev, u8 *lnk_speed)
1297 {
1298         int status = -ENOMEM;
1299         struct ocrdma_get_link_speed_rsp *rsp;
1300         struct ocrdma_mqe *cmd;
1301
1302         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1303                                   sizeof(*cmd));
1304         if (!cmd)
1305                 return status;
1306         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1307                         OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1308                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1309
1310         ((struct ocrdma_mbx_hdr *)cmd->u.cmd)->rsvd_version = 0x1;
1311
1312         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1313         if (status)
1314                 goto mbx_err;
1315
1316         rsp = (struct ocrdma_get_link_speed_rsp *)cmd;
1317         *lnk_speed = (rsp->pflt_pps_ld_pnum & OCRDMA_PHY_PS_MASK)
1318                         >> OCRDMA_PHY_PS_SHIFT;
1319
1320 mbx_err:
1321         kfree(cmd);
1322         return status;
1323 }
1324
1325 static int ocrdma_mbx_get_phy_info(struct ocrdma_dev *dev)
1326 {
1327         int status = -ENOMEM;
1328         struct ocrdma_mqe *cmd;
1329         struct ocrdma_get_phy_info_rsp *rsp;
1330
1331         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_PHY_DETAILS, sizeof(*cmd));
1332         if (!cmd)
1333                 return status;
1334
1335         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1336                         OCRDMA_CMD_PHY_DETAILS, OCRDMA_SUBSYS_COMMON,
1337                         sizeof(*cmd));
1338
1339         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1340         if (status)
1341                 goto mbx_err;
1342
1343         rsp = (struct ocrdma_get_phy_info_rsp *)cmd;
1344         dev->phy.phy_type =
1345                         (rsp->ityp_ptyp & OCRDMA_PHY_TYPE_MASK);
1346         dev->phy.interface_type =
1347                         (rsp->ityp_ptyp & OCRDMA_IF_TYPE_MASK)
1348                                 >> OCRDMA_IF_TYPE_SHIFT;
1349         dev->phy.auto_speeds_supported  =
1350                         (rsp->fspeed_aspeed & OCRDMA_ASPEED_SUPP_MASK);
1351         dev->phy.fixed_speeds_supported =
1352                         (rsp->fspeed_aspeed & OCRDMA_FSPEED_SUPP_MASK)
1353                                 >> OCRDMA_FSPEED_SUPP_SHIFT;
1354 mbx_err:
1355         kfree(cmd);
1356         return status;
1357 }
1358
1359 int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1360 {
1361         int status = -ENOMEM;
1362         struct ocrdma_alloc_pd *cmd;
1363         struct ocrdma_alloc_pd_rsp *rsp;
1364
1365         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1366         if (!cmd)
1367                 return status;
1368         if (pd->dpp_enabled)
1369                 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1370         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1371         if (status)
1372                 goto mbx_err;
1373         rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1374         pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1375         if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1376                 pd->dpp_enabled = true;
1377                 pd->dpp_page = rsp->dpp_page_pdid >>
1378                                 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1379         } else {
1380                 pd->dpp_enabled = false;
1381                 pd->num_dpp_qp = 0;
1382         }
1383 mbx_err:
1384         kfree(cmd);
1385         return status;
1386 }
1387
1388 int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1389 {
1390         int status = -ENOMEM;
1391         struct ocrdma_dealloc_pd *cmd;
1392
1393         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1394         if (!cmd)
1395                 return status;
1396         cmd->id = pd->id;
1397         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1398         kfree(cmd);
1399         return status;
1400 }
1401
1402
1403 static int ocrdma_mbx_alloc_pd_range(struct ocrdma_dev *dev)
1404 {
1405         int status = -ENOMEM;
1406         size_t pd_bitmap_size;
1407         struct ocrdma_alloc_pd_range *cmd;
1408         struct ocrdma_alloc_pd_range_rsp *rsp;
1409
1410         /* Pre allocate the DPP PDs */
1411         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE, sizeof(*cmd));
1412         if (!cmd)
1413                 return -ENOMEM;
1414         cmd->pd_count = dev->attr.max_dpp_pds;
1415         cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1416         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1417         if (status)
1418                 goto mbx_err;
1419         rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd;
1420
1421         if ((rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) && rsp->pd_count) {
1422                 dev->pd_mgr->dpp_page_index = rsp->dpp_page_pdid >>
1423                                 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1424                 dev->pd_mgr->pd_dpp_start = rsp->dpp_page_pdid &
1425                                 OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK;
1426                 dev->pd_mgr->max_dpp_pd = rsp->pd_count;
1427                 pd_bitmap_size = BITS_TO_LONGS(rsp->pd_count) * sizeof(long);
1428                 dev->pd_mgr->pd_dpp_bitmap = kzalloc(pd_bitmap_size,
1429                                                      GFP_KERNEL);
1430         }
1431         kfree(cmd);
1432
1433         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE, sizeof(*cmd));
1434         if (!cmd)
1435                 return -ENOMEM;
1436
1437         cmd->pd_count = dev->attr.max_pd - dev->attr.max_dpp_pds;
1438         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1439         if (status)
1440                 goto mbx_err;
1441         rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd;
1442         if (rsp->pd_count) {
1443                 dev->pd_mgr->pd_norm_start = rsp->dpp_page_pdid &
1444                                         OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK;
1445                 dev->pd_mgr->max_normal_pd = rsp->pd_count;
1446                 pd_bitmap_size = BITS_TO_LONGS(rsp->pd_count) * sizeof(long);
1447                 dev->pd_mgr->pd_norm_bitmap = kzalloc(pd_bitmap_size,
1448                                                       GFP_KERNEL);
1449         }
1450
1451         if (dev->pd_mgr->pd_norm_bitmap || dev->pd_mgr->pd_dpp_bitmap) {
1452                 /* Enable PD resource manager */
1453                 dev->pd_mgr->pd_prealloc_valid = true;
1454         } else {
1455                 return -ENOMEM;
1456         }
1457 mbx_err:
1458         kfree(cmd);
1459         return status;
1460 }
1461
1462 static void ocrdma_mbx_dealloc_pd_range(struct ocrdma_dev *dev)
1463 {
1464         struct ocrdma_dealloc_pd_range *cmd;
1465
1466         /* return normal PDs to firmware */
1467         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE, sizeof(*cmd));
1468         if (!cmd)
1469                 goto mbx_err;
1470
1471         if (dev->pd_mgr->max_normal_pd) {
1472                 cmd->start_pd_id = dev->pd_mgr->pd_norm_start;
1473                 cmd->pd_count = dev->pd_mgr->max_normal_pd;
1474                 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1475         }
1476
1477         if (dev->pd_mgr->max_dpp_pd) {
1478                 kfree(cmd);
1479                 /* return DPP PDs to firmware */
1480                 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE,
1481                                           sizeof(*cmd));
1482                 if (!cmd)
1483                         goto mbx_err;
1484
1485                 cmd->start_pd_id = dev->pd_mgr->pd_dpp_start;
1486                 cmd->pd_count = dev->pd_mgr->max_dpp_pd;
1487                 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1488         }
1489 mbx_err:
1490         kfree(cmd);
1491 }
1492
1493 void ocrdma_alloc_pd_pool(struct ocrdma_dev *dev)
1494 {
1495         int status;
1496
1497         dev->pd_mgr = kzalloc(sizeof(struct ocrdma_pd_resource_mgr),
1498                               GFP_KERNEL);
1499         if (!dev->pd_mgr) {
1500                 pr_err("%s(%d)Memory allocation failure.\n", __func__, dev->id);
1501                 return;
1502         }
1503         status = ocrdma_mbx_alloc_pd_range(dev);
1504         if (status) {
1505                 pr_err("%s(%d) Unable to initialize PD pool, using default.\n",
1506                          __func__, dev->id);
1507         }
1508 }
1509
1510 static void ocrdma_free_pd_pool(struct ocrdma_dev *dev)
1511 {
1512         ocrdma_mbx_dealloc_pd_range(dev);
1513         kfree(dev->pd_mgr->pd_norm_bitmap);
1514         kfree(dev->pd_mgr->pd_dpp_bitmap);
1515         kfree(dev->pd_mgr);
1516 }
1517
1518 static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1519                                int *num_pages, int *page_size)
1520 {
1521         int i;
1522         int mem_size;
1523
1524         *num_entries = roundup_pow_of_two(*num_entries);
1525         mem_size = *num_entries * entry_size;
1526         /* find the possible lowest possible multiplier */
1527         for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1528                 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1529                         break;
1530         }
1531         if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1532                 return -EINVAL;
1533         mem_size = roundup(mem_size,
1534                        ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1535         *num_pages =
1536             mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1537         *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1538         *num_entries = mem_size / entry_size;
1539         return 0;
1540 }
1541
1542 static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1543 {
1544         int i;
1545         int status = 0;
1546         int max_ah;
1547         struct ocrdma_create_ah_tbl *cmd;
1548         struct ocrdma_create_ah_tbl_rsp *rsp;
1549         struct pci_dev *pdev = dev->nic_info.pdev;
1550         dma_addr_t pa;
1551         struct ocrdma_pbe *pbes;
1552
1553         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1554         if (!cmd)
1555                 return status;
1556
1557         max_ah = OCRDMA_MAX_AH;
1558         dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1559
1560         /* number of PBEs in PBL */
1561         cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1562                                 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1563                                 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1564
1565         /* page size */
1566         for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1567                 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1568                         break;
1569         }
1570         cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1571                                 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1572
1573         /* ah_entry size */
1574         cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1575                                 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1576                                 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1577
1578         dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1579                                                 &dev->av_tbl.pbl.pa,
1580                                                 GFP_KERNEL);
1581         if (dev->av_tbl.pbl.va == NULL)
1582                 goto mem_err;
1583
1584         dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1585                                             &pa, GFP_KERNEL);
1586         if (dev->av_tbl.va == NULL)
1587                 goto mem_err_ah;
1588         dev->av_tbl.pa = pa;
1589         dev->av_tbl.num_ah = max_ah;
1590         memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1591
1592         pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1593         for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1594                 pbes[i].pa_lo = (u32)cpu_to_le32(pa & 0xffffffff);
1595                 pbes[i].pa_hi = (u32)cpu_to_le32(upper_32_bits(pa));
1596                 pa += PAGE_SIZE;
1597         }
1598         cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1599         cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1600         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1601         if (status)
1602                 goto mbx_err;
1603         rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1604         dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1605         kfree(cmd);
1606         return 0;
1607
1608 mbx_err:
1609         dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1610                           dev->av_tbl.pa);
1611         dev->av_tbl.va = NULL;
1612 mem_err_ah:
1613         dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1614                           dev->av_tbl.pbl.pa);
1615         dev->av_tbl.pbl.va = NULL;
1616         dev->av_tbl.size = 0;
1617 mem_err:
1618         kfree(cmd);
1619         return status;
1620 }
1621
1622 static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1623 {
1624         struct ocrdma_delete_ah_tbl *cmd;
1625         struct pci_dev *pdev = dev->nic_info.pdev;
1626
1627         if (dev->av_tbl.va == NULL)
1628                 return;
1629
1630         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1631         if (!cmd)
1632                 return;
1633         cmd->ahid = dev->av_tbl.ahid;
1634
1635         ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1636         dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1637                           dev->av_tbl.pa);
1638         dev->av_tbl.va = NULL;
1639         dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1640                           dev->av_tbl.pbl.pa);
1641         kfree(cmd);
1642 }
1643
1644 /* Multiple CQs uses the EQ. This routine returns least used
1645  * EQ to associate with CQ. This will distributes the interrupt
1646  * processing and CPU load to associated EQ, vector and so to that CPU.
1647  */
1648 static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1649 {
1650         int i, selected_eq = 0, cq_cnt = 0;
1651         u16 eq_id;
1652
1653         mutex_lock(&dev->dev_lock);
1654         cq_cnt = dev->eq_tbl[0].cq_cnt;
1655         eq_id = dev->eq_tbl[0].q.id;
1656         /* find the EQ which is has the least number of
1657          * CQs associated with it.
1658          */
1659         for (i = 0; i < dev->eq_cnt; i++) {
1660                 if (dev->eq_tbl[i].cq_cnt < cq_cnt) {
1661                         cq_cnt = dev->eq_tbl[i].cq_cnt;
1662                         eq_id = dev->eq_tbl[i].q.id;
1663                         selected_eq = i;
1664                 }
1665         }
1666         dev->eq_tbl[selected_eq].cq_cnt += 1;
1667         mutex_unlock(&dev->dev_lock);
1668         return eq_id;
1669 }
1670
1671 static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1672 {
1673         int i;
1674
1675         mutex_lock(&dev->dev_lock);
1676         i = ocrdma_get_eq_table_index(dev, eq_id);
1677         if (i == -EINVAL)
1678                 BUG();
1679         dev->eq_tbl[i].cq_cnt -= 1;
1680         mutex_unlock(&dev->dev_lock);
1681 }
1682
1683 int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
1684                          int entries, int dpp_cq, u16 pd_id)
1685 {
1686         int status = -ENOMEM; int max_hw_cqe;
1687         struct pci_dev *pdev = dev->nic_info.pdev;
1688         struct ocrdma_create_cq *cmd;
1689         struct ocrdma_create_cq_rsp *rsp;
1690         u32 hw_pages, cqe_size, page_size, cqe_count;
1691
1692         if (entries > dev->attr.max_cqe) {
1693                 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1694                        __func__, dev->id, dev->attr.max_cqe, entries);
1695                 return -EINVAL;
1696         }
1697         if (dpp_cq && (ocrdma_get_asic_type(dev) != OCRDMA_ASIC_GEN_SKH_R))
1698                 return -EINVAL;
1699
1700         if (dpp_cq) {
1701                 cq->max_hw_cqe = 1;
1702                 max_hw_cqe = 1;
1703                 cqe_size = OCRDMA_DPP_CQE_SIZE;
1704                 hw_pages = 1;
1705         } else {
1706                 cq->max_hw_cqe = dev->attr.max_cqe;
1707                 max_hw_cqe = dev->attr.max_cqe;
1708                 cqe_size = sizeof(struct ocrdma_cqe);
1709                 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1710         }
1711
1712         cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1713
1714         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1715         if (!cmd)
1716                 return -ENOMEM;
1717         ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1718                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1719         cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1720         if (!cq->va) {
1721                 status = -ENOMEM;
1722                 goto mem_err;
1723         }
1724         memset(cq->va, 0, cq->len);
1725         page_size = cq->len / hw_pages;
1726         cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1727                                         OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1728         cmd->cmd.pgsz_pgcnt |= hw_pages;
1729         cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1730
1731         cq->eqn = ocrdma_bind_eq(dev);
1732         cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER3;
1733         cqe_count = cq->len / cqe_size;
1734         cq->cqe_cnt = cqe_count;
1735         if (cqe_count > 1024) {
1736                 /* Set cnt to 3 to indicate more than 1024 cq entries */
1737                 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
1738         } else {
1739                 u8 count = 0;
1740                 switch (cqe_count) {
1741                 case 256:
1742                         count = 0;
1743                         break;
1744                 case 512:
1745                         count = 1;
1746                         break;
1747                 case 1024:
1748                         count = 2;
1749                         break;
1750                 default:
1751                         goto mbx_err;
1752                 }
1753                 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1754         }
1755         /* shared eq between all the consumer cqs. */
1756         cmd->cmd.eqn = cq->eqn;
1757         if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1758                 if (dpp_cq)
1759                         cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1760                                 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1761                 cq->phase_change = false;
1762                 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size);
1763         } else {
1764                 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size) - 1;
1765                 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1766                 cq->phase_change = true;
1767         }
1768
1769         /* pd_id valid only for v3 */
1770         cmd->cmd.pdid_cqecnt |= (pd_id <<
1771                 OCRDMA_CREATE_CQ_CMD_PDID_SHIFT);
1772         ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1773         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1774         if (status)
1775                 goto mbx_err;
1776
1777         rsp = (struct ocrdma_create_cq_rsp *)cmd;
1778         cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1779         kfree(cmd);
1780         return 0;
1781 mbx_err:
1782         ocrdma_unbind_eq(dev, cq->eqn);
1783         dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1784 mem_err:
1785         kfree(cmd);
1786         return status;
1787 }
1788
1789 int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1790 {
1791         int status = -ENOMEM;
1792         struct ocrdma_destroy_cq *cmd;
1793
1794         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1795         if (!cmd)
1796                 return status;
1797         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1798                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1799
1800         cmd->bypass_flush_qid |=
1801             (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1802             OCRDMA_DESTROY_CQ_QID_MASK;
1803
1804         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1805         ocrdma_unbind_eq(dev, cq->eqn);
1806         dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
1807         kfree(cmd);
1808         return status;
1809 }
1810
1811 int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1812                           u32 pdid, int addr_check)
1813 {
1814         int status = -ENOMEM;
1815         struct ocrdma_alloc_lkey *cmd;
1816         struct ocrdma_alloc_lkey_rsp *rsp;
1817
1818         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1819         if (!cmd)
1820                 return status;
1821         cmd->pdid = pdid;
1822         cmd->pbl_sz_flags |= addr_check;
1823         cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1824         cmd->pbl_sz_flags |=
1825             (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1826         cmd->pbl_sz_flags |=
1827             (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1828         cmd->pbl_sz_flags |=
1829             (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1830         cmd->pbl_sz_flags |=
1831             (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1832         cmd->pbl_sz_flags |=
1833             (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1834
1835         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1836         if (status)
1837                 goto mbx_err;
1838         rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1839         hwmr->lkey = rsp->lrkey;
1840 mbx_err:
1841         kfree(cmd);
1842         return status;
1843 }
1844
1845 int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1846 {
1847         int status = -ENOMEM;
1848         struct ocrdma_dealloc_lkey *cmd;
1849
1850         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1851         if (!cmd)
1852                 return -ENOMEM;
1853         cmd->lkey = lkey;
1854         cmd->rsvd_frmr = fr_mr ? 1 : 0;
1855         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1856         if (status)
1857                 goto mbx_err;
1858 mbx_err:
1859         kfree(cmd);
1860         return status;
1861 }
1862
1863 static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1864                              u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1865 {
1866         int status = -ENOMEM;
1867         int i;
1868         struct ocrdma_reg_nsmr *cmd;
1869         struct ocrdma_reg_nsmr_rsp *rsp;
1870
1871         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1872         if (!cmd)
1873                 return -ENOMEM;
1874         cmd->num_pbl_pdid =
1875             pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
1876         cmd->fr_mr = hwmr->fr_mr;
1877
1878         cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1879                                     OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1880         cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1881                                     OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1882         cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1883                                     OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1884         cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1885                                     OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1886         cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1887                                     OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1888         cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1889
1890         cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1891         cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1892                                         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1893         cmd->totlen_low = hwmr->len;
1894         cmd->totlen_high = upper_32_bits(hwmr->len);
1895         cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1896         cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1897         cmd->va_loaddr = (u32) hwmr->va;
1898         cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1899
1900         for (i = 0; i < pbl_cnt; i++) {
1901                 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1902                 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
1903         }
1904         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1905         if (status)
1906                 goto mbx_err;
1907         rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
1908         hwmr->lkey = rsp->lrkey;
1909 mbx_err:
1910         kfree(cmd);
1911         return status;
1912 }
1913
1914 static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
1915                                   struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
1916                                   u32 pbl_offset, u32 last)
1917 {
1918         int status = -ENOMEM;
1919         int i;
1920         struct ocrdma_reg_nsmr_cont *cmd;
1921
1922         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
1923         if (!cmd)
1924                 return -ENOMEM;
1925         cmd->lrkey = hwmr->lkey;
1926         cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
1927             (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
1928         cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
1929
1930         for (i = 0; i < pbl_cnt; i++) {
1931                 cmd->pbl[i].lo =
1932                     (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
1933                 cmd->pbl[i].hi =
1934                     upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
1935         }
1936         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1937         if (status)
1938                 goto mbx_err;
1939 mbx_err:
1940         kfree(cmd);
1941         return status;
1942 }
1943
1944 int ocrdma_reg_mr(struct ocrdma_dev *dev,
1945                   struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
1946 {
1947         int status;
1948         u32 last = 0;
1949         u32 cur_pbl_cnt, pbl_offset;
1950         u32 pending_pbl_cnt = hwmr->num_pbls;
1951
1952         pbl_offset = 0;
1953         cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1954         if (cur_pbl_cnt == pending_pbl_cnt)
1955                 last = 1;
1956
1957         status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
1958                                    cur_pbl_cnt, hwmr->pbe_size, last);
1959         if (status) {
1960                 pr_err("%s() status=%d\n", __func__, status);
1961                 return status;
1962         }
1963         /* if there is no more pbls to register then exit. */
1964         if (last)
1965                 return 0;
1966
1967         while (!last) {
1968                 pbl_offset += cur_pbl_cnt;
1969                 pending_pbl_cnt -= cur_pbl_cnt;
1970                 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1971                 /* if we reach the end of the pbls, then need to set the last
1972                  * bit, indicating no more pbls to register for this memory key.
1973                  */
1974                 if (cur_pbl_cnt == pending_pbl_cnt)
1975                         last = 1;
1976
1977                 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
1978                                                 pbl_offset, last);
1979                 if (status)
1980                         break;
1981         }
1982         if (status)
1983                 pr_err("%s() err. status=%d\n", __func__, status);
1984
1985         return status;
1986 }
1987
1988 bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1989 {
1990         struct ocrdma_qp *tmp;
1991         bool found = false;
1992         list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
1993                 if (qp == tmp) {
1994                         found = true;
1995                         break;
1996                 }
1997         }
1998         return found;
1999 }
2000
2001 bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
2002 {
2003         struct ocrdma_qp *tmp;
2004         bool found = false;
2005         list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
2006                 if (qp == tmp) {
2007                         found = true;
2008                         break;
2009                 }
2010         }
2011         return found;
2012 }
2013
2014 void ocrdma_flush_qp(struct ocrdma_qp *qp)
2015 {
2016         bool found;
2017         unsigned long flags;
2018
2019         spin_lock_irqsave(&qp->dev->flush_q_lock, flags);
2020         found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
2021         if (!found)
2022                 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
2023         if (!qp->srq) {
2024                 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
2025                 if (!found)
2026                         list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
2027         }
2028         spin_unlock_irqrestore(&qp->dev->flush_q_lock, flags);
2029 }
2030
2031 static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp)
2032 {
2033         qp->sq.head = 0;
2034         qp->sq.tail = 0;
2035         qp->rq.head = 0;
2036         qp->rq.tail = 0;
2037 }
2038
2039 int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
2040                            enum ib_qp_state *old_ib_state)
2041 {
2042         unsigned long flags;
2043         int status = 0;
2044         enum ocrdma_qp_state new_state;
2045         new_state = get_ocrdma_qp_state(new_ib_state);
2046
2047         /* sync with wqe and rqe posting */
2048         spin_lock_irqsave(&qp->q_lock, flags);
2049
2050         if (old_ib_state)
2051                 *old_ib_state = get_ibqp_state(qp->state);
2052         if (new_state == qp->state) {
2053                 spin_unlock_irqrestore(&qp->q_lock, flags);
2054                 return 1;
2055         }
2056
2057
2058         if (new_state == OCRDMA_QPS_INIT) {
2059                 ocrdma_init_hwq_ptr(qp);
2060                 ocrdma_del_flush_qp(qp);
2061         } else if (new_state == OCRDMA_QPS_ERR) {
2062                 ocrdma_flush_qp(qp);
2063         }
2064
2065         qp->state = new_state;
2066
2067         spin_unlock_irqrestore(&qp->q_lock, flags);
2068         return status;
2069 }
2070
2071 static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
2072 {
2073         u32 flags = 0;
2074         if (qp->cap_flags & OCRDMA_QP_INB_RD)
2075                 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
2076         if (qp->cap_flags & OCRDMA_QP_INB_WR)
2077                 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
2078         if (qp->cap_flags & OCRDMA_QP_MW_BIND)
2079                 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
2080         if (qp->cap_flags & OCRDMA_QP_LKEY0)
2081                 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
2082         if (qp->cap_flags & OCRDMA_QP_FAST_REG)
2083                 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
2084         return flags;
2085 }
2086
2087 static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
2088                                         struct ib_qp_init_attr *attrs,
2089                                         struct ocrdma_qp *qp)
2090 {
2091         int status;
2092         u32 len, hw_pages, hw_page_size;
2093         dma_addr_t pa;
2094         struct ocrdma_dev *dev = qp->dev;
2095         struct pci_dev *pdev = dev->nic_info.pdev;
2096         u32 max_wqe_allocated;
2097         u32 max_sges = attrs->cap.max_send_sge;
2098
2099         /* QP1 may exceed 127 */
2100         max_wqe_allocated = min_t(u32, attrs->cap.max_send_wr + 1,
2101                                 dev->attr.max_wqe);
2102
2103         status = ocrdma_build_q_conf(&max_wqe_allocated,
2104                 dev->attr.wqe_size, &hw_pages, &hw_page_size);
2105         if (status) {
2106                 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
2107                        max_wqe_allocated);
2108                 return -EINVAL;
2109         }
2110         qp->sq.max_cnt = max_wqe_allocated;
2111         len = (hw_pages * hw_page_size);
2112
2113         qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2114         if (!qp->sq.va)
2115                 return -EINVAL;
2116         memset(qp->sq.va, 0, len);
2117         qp->sq.len = len;
2118         qp->sq.pa = pa;
2119         qp->sq.entry_size = dev->attr.wqe_size;
2120         ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
2121
2122         cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2123                                 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
2124         cmd->num_wq_rq_pages |= (hw_pages <<
2125                                  OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
2126             OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
2127         cmd->max_sge_send_write |= (max_sges <<
2128                                     OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
2129             OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
2130         cmd->max_sge_send_write |= (max_sges <<
2131                                     OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
2132                                         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
2133         cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
2134                              OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
2135                                 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
2136         cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
2137                               OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
2138                                 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
2139         return 0;
2140 }
2141
2142 static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
2143                                         struct ib_qp_init_attr *attrs,
2144                                         struct ocrdma_qp *qp)
2145 {
2146         int status;
2147         u32 len, hw_pages, hw_page_size;
2148         dma_addr_t pa = 0;
2149         struct ocrdma_dev *dev = qp->dev;
2150         struct pci_dev *pdev = dev->nic_info.pdev;
2151         u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
2152
2153         status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
2154                                      &hw_pages, &hw_page_size);
2155         if (status) {
2156                 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
2157                        attrs->cap.max_recv_wr + 1);
2158                 return status;
2159         }
2160         qp->rq.max_cnt = max_rqe_allocated;
2161         len = (hw_pages * hw_page_size);
2162
2163         qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2164         if (!qp->rq.va)
2165                 return -ENOMEM;
2166         memset(qp->rq.va, 0, len);
2167         qp->rq.pa = pa;
2168         qp->rq.len = len;
2169         qp->rq.entry_size = dev->attr.rqe_size;
2170
2171         ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2172         cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
2173                 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
2174         cmd->num_wq_rq_pages |=
2175             (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
2176             OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
2177         cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
2178                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
2179                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
2180         cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
2181                                 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
2182                                 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
2183         cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
2184                         OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
2185                         OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
2186         return 0;
2187 }
2188
2189 static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
2190                                          struct ocrdma_pd *pd,
2191                                          struct ocrdma_qp *qp,
2192                                          u8 enable_dpp_cq, u16 dpp_cq_id)
2193 {
2194         pd->num_dpp_qp--;
2195         qp->dpp_enabled = true;
2196         cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2197         if (!enable_dpp_cq)
2198                 return;
2199         cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2200         cmd->dpp_credits_cqid = dpp_cq_id;
2201         cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
2202                                         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
2203 }
2204
2205 static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
2206                                         struct ocrdma_qp *qp)
2207 {
2208         struct ocrdma_dev *dev = qp->dev;
2209         struct pci_dev *pdev = dev->nic_info.pdev;
2210         dma_addr_t pa = 0;
2211         int ird_page_size = dev->attr.ird_page_size;
2212         int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
2213         struct ocrdma_hdr_wqe *rqe;
2214         int i  = 0;
2215
2216         if (dev->attr.ird == 0)
2217                 return 0;
2218
2219         qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
2220                                         &pa, GFP_KERNEL);
2221         if (!qp->ird_q_va)
2222                 return -ENOMEM;
2223         memset(qp->ird_q_va, 0, ird_q_len);
2224         ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
2225                              pa, ird_page_size);
2226         for (; i < ird_q_len / dev->attr.rqe_size; i++) {
2227                 rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va +
2228                         (i * dev->attr.rqe_size));
2229                 rqe->cw = 0;
2230                 rqe->cw |= 2;
2231                 rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
2232                 rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT);
2233                 rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT);
2234         }
2235         return 0;
2236 }
2237
2238 static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
2239                                      struct ocrdma_qp *qp,
2240                                      struct ib_qp_init_attr *attrs,
2241                                      u16 *dpp_offset, u16 *dpp_credit_lmt)
2242 {
2243         u32 max_wqe_allocated, max_rqe_allocated;
2244         qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
2245         qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
2246         qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
2247         qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
2248         qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
2249         qp->dpp_enabled = false;
2250         if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
2251                 qp->dpp_enabled = true;
2252                 *dpp_credit_lmt = (rsp->dpp_response &
2253                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
2254                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
2255                 *dpp_offset = (rsp->dpp_response &
2256                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
2257                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
2258         }
2259         max_wqe_allocated =
2260                 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
2261         max_wqe_allocated = 1 << max_wqe_allocated;
2262         max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
2263
2264         qp->sq.max_cnt = max_wqe_allocated;
2265         qp->sq.max_wqe_idx = max_wqe_allocated - 1;
2266
2267         if (!attrs->srq) {
2268                 qp->rq.max_cnt = max_rqe_allocated;
2269                 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
2270         }
2271 }
2272
2273 int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
2274                          u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
2275                          u16 *dpp_credit_lmt)
2276 {
2277         int status = -ENOMEM;
2278         u32 flags = 0;
2279         struct ocrdma_dev *dev = qp->dev;
2280         struct ocrdma_pd *pd = qp->pd;
2281         struct pci_dev *pdev = dev->nic_info.pdev;
2282         struct ocrdma_cq *cq;
2283         struct ocrdma_create_qp_req *cmd;
2284         struct ocrdma_create_qp_rsp *rsp;
2285         int qptype;
2286
2287         switch (attrs->qp_type) {
2288         case IB_QPT_GSI:
2289                 qptype = OCRDMA_QPT_GSI;
2290                 break;
2291         case IB_QPT_RC:
2292                 qptype = OCRDMA_QPT_RC;
2293                 break;
2294         case IB_QPT_UD:
2295                 qptype = OCRDMA_QPT_UD;
2296                 break;
2297         default:
2298                 return -EINVAL;
2299         }
2300
2301         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
2302         if (!cmd)
2303                 return status;
2304         cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
2305                                                 OCRDMA_CREATE_QP_REQ_QPT_MASK;
2306         status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
2307         if (status)
2308                 goto sq_err;
2309
2310         if (attrs->srq) {
2311                 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
2312                 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
2313                 cmd->rq_addr[0].lo = srq->id;
2314                 qp->srq = srq;
2315         } else {
2316                 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2317                 if (status)
2318                         goto rq_err;
2319         }
2320
2321         status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2322         if (status)
2323                 goto mbx_err;
2324
2325         cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2326                                 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2327
2328         flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2329
2330         cmd->max_sge_recv_flags |= flags;
2331         cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2332                              OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2333                                 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2334         cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2335                              OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2336                                 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2337         cq = get_ocrdma_cq(attrs->send_cq);
2338         cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2339                                 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2340         qp->sq_cq = cq;
2341         cq = get_ocrdma_cq(attrs->recv_cq);
2342         cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2343                                 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2344         qp->rq_cq = cq;
2345
2346         if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
2347             (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) {
2348                 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2349                                              dpp_cq_id);
2350         }
2351
2352         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2353         if (status)
2354                 goto mbx_err;
2355         rsp = (struct ocrdma_create_qp_rsp *)cmd;
2356         ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2357         qp->state = OCRDMA_QPS_RST;
2358         kfree(cmd);
2359         return 0;
2360 mbx_err:
2361         if (qp->rq.va)
2362                 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2363 rq_err:
2364         pr_err("%s(%d) rq_err\n", __func__, dev->id);
2365         dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2366 sq_err:
2367         pr_err("%s(%d) sq_err\n", __func__, dev->id);
2368         kfree(cmd);
2369         return status;
2370 }
2371
2372 int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2373                         struct ocrdma_qp_params *param)
2374 {
2375         int status = -ENOMEM;
2376         struct ocrdma_query_qp *cmd;
2377         struct ocrdma_query_qp_rsp *rsp;
2378
2379         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd));
2380         if (!cmd)
2381                 return status;
2382         cmd->qp_id = qp->id;
2383         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2384         if (status)
2385                 goto mbx_err;
2386         rsp = (struct ocrdma_query_qp_rsp *)cmd;
2387         memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2388 mbx_err:
2389         kfree(cmd);
2390         return status;
2391 }
2392
2393 static int ocrdma_set_av_params(struct ocrdma_qp *qp,
2394                                 struct ocrdma_modify_qp *cmd,
2395                                 struct ib_qp_attr *attrs,
2396                                 int attr_mask)
2397 {
2398         int status;
2399         struct ib_ah_attr *ah_attr = &attrs->ah_attr;
2400         union ib_gid sgid, zgid;
2401         u32 vlan_id;
2402         u8 mac_addr[6];
2403
2404         if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
2405                 return -EINVAL;
2406         if (atomic_cmpxchg(&qp->dev->update_sl, 1, 0))
2407                 ocrdma_init_service_level(qp->dev);
2408         cmd->params.tclass_sq_psn |=
2409             (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2410         cmd->params.rnt_rc_sl_fl |=
2411             (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2412         cmd->params.rnt_rc_sl_fl |= (ah_attr->sl << OCRDMA_QP_PARAMS_SL_SHIFT);
2413         cmd->params.hop_lmt_rq_psn |=
2414             (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2415         cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2416         memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2417                sizeof(cmd->params.dgid));
2418         status = ocrdma_query_gid(&qp->dev->ibdev, 1,
2419                         ah_attr->grh.sgid_index, &sgid);
2420         if (status)
2421                 return status;
2422
2423         memset(&zgid, 0, sizeof(zgid));
2424         if (!memcmp(&sgid, &zgid, sizeof(zgid)))
2425                 return -EINVAL;
2426
2427         qp->sgid_idx = ah_attr->grh.sgid_index;
2428         memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
2429         ocrdma_resolve_dmac(qp->dev, ah_attr, &mac_addr[0]);
2430         cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2431                                 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2432         /* convert them to LE format. */
2433         ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2434         ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2435         cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
2436         if (attr_mask & IB_QP_VID) {
2437                 vlan_id = attrs->vlan_id;
2438                 cmd->params.vlan_dmac_b4_to_b5 |=
2439                     vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2440                 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2441                 cmd->params.rnt_rc_sl_fl |=
2442                         (qp->dev->sl & 0x07) << OCRDMA_QP_PARAMS_SL_SHIFT;
2443         }
2444         return 0;
2445 }
2446
2447 static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2448                                 struct ocrdma_modify_qp *cmd,
2449                                 struct ib_qp_attr *attrs, int attr_mask)
2450 {
2451         int status = 0;
2452
2453         if (attr_mask & IB_QP_PKEY_INDEX) {
2454                 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2455                                             OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2456                 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2457         }
2458         if (attr_mask & IB_QP_QKEY) {
2459                 qp->qkey = attrs->qkey;
2460                 cmd->params.qkey = attrs->qkey;
2461                 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2462         }
2463         if (attr_mask & IB_QP_AV) {
2464                 status = ocrdma_set_av_params(qp, cmd, attrs, attr_mask);
2465                 if (status)
2466                         return status;
2467         } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
2468                 /* set the default mac address for UD, GSI QPs */
2469                 cmd->params.dmac_b0_to_b3 = qp->dev->nic_info.mac_addr[0] |
2470                         (qp->dev->nic_info.mac_addr[1] << 8) |
2471                         (qp->dev->nic_info.mac_addr[2] << 16) |
2472                         (qp->dev->nic_info.mac_addr[3] << 24);
2473                 cmd->params.vlan_dmac_b4_to_b5 = qp->dev->nic_info.mac_addr[4] |
2474                                         (qp->dev->nic_info.mac_addr[5] << 8);
2475         }
2476         if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2477             attrs->en_sqd_async_notify) {
2478                 cmd->params.max_sge_recv_flags |=
2479                         OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2480                 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2481         }
2482         if (attr_mask & IB_QP_DEST_QPN) {
2483                 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2484                                 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2485                 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2486         }
2487         if (attr_mask & IB_QP_PATH_MTU) {
2488                 if (attrs->path_mtu < IB_MTU_256 ||
2489                     attrs->path_mtu > IB_MTU_4096) {
2490                         status = -EINVAL;
2491                         goto pmtu_err;
2492                 }
2493                 cmd->params.path_mtu_pkey_indx |=
2494                     (ib_mtu_enum_to_int(attrs->path_mtu) <<
2495                      OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2496                     OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2497                 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2498         }
2499         if (attr_mask & IB_QP_TIMEOUT) {
2500                 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2501                     OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2502                 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2503         }
2504         if (attr_mask & IB_QP_RETRY_CNT) {
2505                 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2506                                       OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2507                     OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2508                 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2509         }
2510         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2511                 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2512                                       OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2513                     OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2514                 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2515         }
2516         if (attr_mask & IB_QP_RNR_RETRY) {
2517                 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2518                         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2519                         & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2520                 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2521         }
2522         if (attr_mask & IB_QP_SQ_PSN) {
2523                 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2524                 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2525         }
2526         if (attr_mask & IB_QP_RQ_PSN) {
2527                 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2528                 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2529         }
2530         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2531                 if (attrs->max_rd_atomic > qp->dev->attr.max_ord_per_qp) {
2532                         status = -EINVAL;
2533                         goto pmtu_err;
2534                 }
2535                 qp->max_ord = attrs->max_rd_atomic;
2536                 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2537         }
2538         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2539                 if (attrs->max_dest_rd_atomic > qp->dev->attr.max_ird_per_qp) {
2540                         status = -EINVAL;
2541                         goto pmtu_err;
2542                 }
2543                 qp->max_ird = attrs->max_dest_rd_atomic;
2544                 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2545         }
2546         cmd->params.max_ord_ird = (qp->max_ord <<
2547                                 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2548                                 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2549 pmtu_err:
2550         return status;
2551 }
2552
2553 int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2554                          struct ib_qp_attr *attrs, int attr_mask)
2555 {
2556         int status = -ENOMEM;
2557         struct ocrdma_modify_qp *cmd;
2558
2559         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2560         if (!cmd)
2561                 return status;
2562
2563         cmd->params.id = qp->id;
2564         cmd->flags = 0;
2565         if (attr_mask & IB_QP_STATE) {
2566                 cmd->params.max_sge_recv_flags |=
2567                     (get_ocrdma_qp_state(attrs->qp_state) <<
2568                      OCRDMA_QP_PARAMS_STATE_SHIFT) &
2569                     OCRDMA_QP_PARAMS_STATE_MASK;
2570                 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
2571         } else {
2572                 cmd->params.max_sge_recv_flags |=
2573                     (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2574                     OCRDMA_QP_PARAMS_STATE_MASK;
2575         }
2576
2577         status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask);
2578         if (status)
2579                 goto mbx_err;
2580         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2581         if (status)
2582                 goto mbx_err;
2583
2584 mbx_err:
2585         kfree(cmd);
2586         return status;
2587 }
2588
2589 int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2590 {
2591         int status = -ENOMEM;
2592         struct ocrdma_destroy_qp *cmd;
2593         struct pci_dev *pdev = dev->nic_info.pdev;
2594
2595         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2596         if (!cmd)
2597                 return status;
2598         cmd->qp_id = qp->id;
2599         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2600         if (status)
2601                 goto mbx_err;
2602
2603 mbx_err:
2604         kfree(cmd);
2605         if (qp->sq.va)
2606                 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2607         if (!qp->srq && qp->rq.va)
2608                 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2609         if (qp->dpp_enabled)
2610                 qp->pd->num_dpp_qp++;
2611         return status;
2612 }
2613
2614 int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
2615                           struct ib_srq_init_attr *srq_attr,
2616                           struct ocrdma_pd *pd)
2617 {
2618         int status = -ENOMEM;
2619         int hw_pages, hw_page_size;
2620         int len;
2621         struct ocrdma_create_srq_rsp *rsp;
2622         struct ocrdma_create_srq *cmd;
2623         dma_addr_t pa;
2624         struct pci_dev *pdev = dev->nic_info.pdev;
2625         u32 max_rqe_allocated;
2626
2627         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2628         if (!cmd)
2629                 return status;
2630
2631         cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2632         max_rqe_allocated = srq_attr->attr.max_wr + 1;
2633         status = ocrdma_build_q_conf(&max_rqe_allocated,
2634                                 dev->attr.rqe_size,
2635                                 &hw_pages, &hw_page_size);
2636         if (status) {
2637                 pr_err("%s() req. max_wr=0x%x\n", __func__,
2638                        srq_attr->attr.max_wr);
2639                 status = -EINVAL;
2640                 goto ret;
2641         }
2642         len = hw_pages * hw_page_size;
2643         srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2644         if (!srq->rq.va) {
2645                 status = -ENOMEM;
2646                 goto ret;
2647         }
2648         ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2649
2650         srq->rq.entry_size = dev->attr.rqe_size;
2651         srq->rq.pa = pa;
2652         srq->rq.len = len;
2653         srq->rq.max_cnt = max_rqe_allocated;
2654
2655         cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2656         cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2657                                 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2658
2659         cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2660                 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2661         cmd->pages_rqe_sz |= (dev->attr.rqe_size
2662                 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2663                 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2664         cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2665
2666         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2667         if (status)
2668                 goto mbx_err;
2669         rsp = (struct ocrdma_create_srq_rsp *)cmd;
2670         srq->id = rsp->id;
2671         srq->rq.dbid = rsp->id;
2672         max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2673                 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2674                 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2675         max_rqe_allocated = (1 << max_rqe_allocated);
2676         srq->rq.max_cnt = max_rqe_allocated;
2677         srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2678         srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2679                 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2680                 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2681         goto ret;
2682 mbx_err:
2683         dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2684 ret:
2685         kfree(cmd);
2686         return status;
2687 }
2688
2689 int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2690 {
2691         int status = -ENOMEM;
2692         struct ocrdma_modify_srq *cmd;
2693         struct ocrdma_pd *pd = srq->pd;
2694         struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2695
2696         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_SRQ, sizeof(*cmd));
2697         if (!cmd)
2698                 return status;
2699         cmd->id = srq->id;
2700         cmd->limit_max_rqe |= srq_attr->srq_limit <<
2701             OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
2702         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2703         kfree(cmd);
2704         return status;
2705 }
2706
2707 int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2708 {
2709         int status = -ENOMEM;
2710         struct ocrdma_query_srq *cmd;
2711         struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2712
2713         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_SRQ, sizeof(*cmd));
2714         if (!cmd)
2715                 return status;
2716         cmd->id = srq->rq.dbid;
2717         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2718         if (status == 0) {
2719                 struct ocrdma_query_srq_rsp *rsp =
2720                     (struct ocrdma_query_srq_rsp *)cmd;
2721                 srq_attr->max_sge =
2722                     rsp->srq_lmt_max_sge &
2723                     OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2724                 srq_attr->max_wr =
2725                     rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2726                 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2727                     OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2728         }
2729         kfree(cmd);
2730         return status;
2731 }
2732
2733 int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2734 {
2735         int status = -ENOMEM;
2736         struct ocrdma_destroy_srq *cmd;
2737         struct pci_dev *pdev = dev->nic_info.pdev;
2738         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2739         if (!cmd)
2740                 return status;
2741         cmd->id = srq->id;
2742         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2743         if (srq->rq.va)
2744                 dma_free_coherent(&pdev->dev, srq->rq.len,
2745                                   srq->rq.va, srq->rq.pa);
2746         kfree(cmd);
2747         return status;
2748 }
2749
2750 static int ocrdma_mbx_get_dcbx_config(struct ocrdma_dev *dev, u32 ptype,
2751                                       struct ocrdma_dcbx_cfg *dcbxcfg)
2752 {
2753         int status = 0;
2754         dma_addr_t pa;
2755         struct ocrdma_mqe cmd;
2756
2757         struct ocrdma_get_dcbx_cfg_req *req = NULL;
2758         struct ocrdma_get_dcbx_cfg_rsp *rsp = NULL;
2759         struct pci_dev *pdev = dev->nic_info.pdev;
2760         struct ocrdma_mqe_sge *mqe_sge = cmd.u.nonemb_req.sge;
2761
2762         memset(&cmd, 0, sizeof(struct ocrdma_mqe));
2763         cmd.hdr.pyld_len = max_t (u32, sizeof(struct ocrdma_get_dcbx_cfg_rsp),
2764                                         sizeof(struct ocrdma_get_dcbx_cfg_req));
2765         req = dma_alloc_coherent(&pdev->dev, cmd.hdr.pyld_len, &pa, GFP_KERNEL);
2766         if (!req) {
2767                 status = -ENOMEM;
2768                 goto mem_err;
2769         }
2770
2771         cmd.hdr.spcl_sge_cnt_emb |= (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
2772                                         OCRDMA_MQE_HDR_SGE_CNT_MASK;
2773         mqe_sge->pa_lo = (u32) (pa & 0xFFFFFFFFUL);
2774         mqe_sge->pa_hi = (u32) upper_32_bits(pa);
2775         mqe_sge->len = cmd.hdr.pyld_len;
2776
2777         memset(req, 0, sizeof(struct ocrdma_get_dcbx_cfg_req));
2778         ocrdma_init_mch(&req->hdr, OCRDMA_CMD_GET_DCBX_CONFIG,
2779                         OCRDMA_SUBSYS_DCBX, cmd.hdr.pyld_len);
2780         req->param_type = ptype;
2781
2782         status = ocrdma_mbx_cmd(dev, &cmd);
2783         if (status)
2784                 goto mbx_err;
2785
2786         rsp = (struct ocrdma_get_dcbx_cfg_rsp *)req;
2787         ocrdma_le32_to_cpu(rsp, sizeof(struct ocrdma_get_dcbx_cfg_rsp));
2788         memcpy(dcbxcfg, &rsp->cfg, sizeof(struct ocrdma_dcbx_cfg));
2789
2790 mbx_err:
2791         dma_free_coherent(&pdev->dev, cmd.hdr.pyld_len, req, pa);
2792 mem_err:
2793         return status;
2794 }
2795
2796 #define OCRDMA_MAX_SERVICE_LEVEL_INDEX  0x08
2797 #define OCRDMA_DEFAULT_SERVICE_LEVEL    0x05
2798
2799 static int ocrdma_parse_dcbxcfg_rsp(struct ocrdma_dev *dev, int ptype,
2800                                     struct ocrdma_dcbx_cfg *dcbxcfg,
2801                                     u8 *srvc_lvl)
2802 {
2803         int status = -EINVAL, indx, slindx;
2804         int ventry_cnt;
2805         struct ocrdma_app_parameter *app_param;
2806         u8 valid, proto_sel;
2807         u8 app_prio, pfc_prio;
2808         u16 proto;
2809
2810         if (!(dcbxcfg->tcv_aev_opv_st & OCRDMA_DCBX_STATE_MASK)) {
2811                 pr_info("%s ocrdma%d DCBX is disabled\n",
2812                         dev_name(&dev->nic_info.pdev->dev), dev->id);
2813                 goto out;
2814         }
2815
2816         if (!ocrdma_is_enabled_and_synced(dcbxcfg->pfc_state)) {
2817                 pr_info("%s ocrdma%d priority flow control(%s) is %s%s\n",
2818                         dev_name(&dev->nic_info.pdev->dev), dev->id,
2819                         (ptype > 0 ? "operational" : "admin"),
2820                         (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_ENABLED) ?
2821                         "enabled" : "disabled",
2822                         (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_SYNC) ?
2823                         "" : ", not sync'ed");
2824                 goto out;
2825         } else {
2826                 pr_info("%s ocrdma%d priority flow control is enabled and sync'ed\n",
2827                         dev_name(&dev->nic_info.pdev->dev), dev->id);
2828         }
2829
2830         ventry_cnt = (dcbxcfg->tcv_aev_opv_st >>
2831                                 OCRDMA_DCBX_APP_ENTRY_SHIFT)
2832                                 & OCRDMA_DCBX_STATE_MASK;
2833
2834         for (indx = 0; indx < ventry_cnt; indx++) {
2835                 app_param = &dcbxcfg->app_param[indx];
2836                 valid = (app_param->valid_proto_app >>
2837                                 OCRDMA_APP_PARAM_VALID_SHIFT)
2838                                 & OCRDMA_APP_PARAM_VALID_MASK;
2839                 proto_sel = (app_param->valid_proto_app
2840                                 >>  OCRDMA_APP_PARAM_PROTO_SEL_SHIFT)
2841                                 & OCRDMA_APP_PARAM_PROTO_SEL_MASK;
2842                 proto = app_param->valid_proto_app &
2843                                 OCRDMA_APP_PARAM_APP_PROTO_MASK;
2844
2845                 if (
2846                         valid && proto == OCRDMA_APP_PROTO_ROCE &&
2847                         proto_sel == OCRDMA_PROTO_SELECT_L2) {
2848                         for (slindx = 0; slindx <
2849                                 OCRDMA_MAX_SERVICE_LEVEL_INDEX; slindx++) {
2850                                 app_prio = ocrdma_get_app_prio(
2851                                                 (u8 *)app_param->app_prio,
2852                                                 slindx);
2853                                 pfc_prio = ocrdma_get_pfc_prio(
2854                                                 (u8 *)dcbxcfg->pfc_prio,
2855                                                 slindx);
2856
2857                                 if (app_prio && pfc_prio) {
2858                                         *srvc_lvl = slindx;
2859                                         status = 0;
2860                                         goto out;
2861                                 }
2862                         }
2863                         if (slindx == OCRDMA_MAX_SERVICE_LEVEL_INDEX) {
2864                                 pr_info("%s ocrdma%d application priority not set for 0x%x protocol\n",
2865                                         dev_name(&dev->nic_info.pdev->dev),
2866                                         dev->id, proto);
2867                         }
2868                 }
2869         }
2870
2871 out:
2872         return status;
2873 }
2874
2875 void ocrdma_init_service_level(struct ocrdma_dev *dev)
2876 {
2877         int status = 0, indx;
2878         struct ocrdma_dcbx_cfg dcbxcfg;
2879         u8 srvc_lvl = OCRDMA_DEFAULT_SERVICE_LEVEL;
2880         int ptype = OCRDMA_PARAMETER_TYPE_OPER;
2881
2882         for (indx = 0; indx < 2; indx++) {
2883                 status = ocrdma_mbx_get_dcbx_config(dev, ptype, &dcbxcfg);
2884                 if (status) {
2885                         pr_err("%s(): status=%d\n", __func__, status);
2886                         ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
2887                         continue;
2888                 }
2889
2890                 status = ocrdma_parse_dcbxcfg_rsp(dev, ptype,
2891                                                   &dcbxcfg, &srvc_lvl);
2892                 if (status) {
2893                         ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
2894                         continue;
2895                 }
2896
2897                 break;
2898         }
2899
2900         if (status)
2901                 pr_info("%s ocrdma%d service level default\n",
2902                         dev_name(&dev->nic_info.pdev->dev), dev->id);
2903         else
2904                 pr_info("%s ocrdma%d service level %d\n",
2905                         dev_name(&dev->nic_info.pdev->dev), dev->id,
2906                         srvc_lvl);
2907
2908         dev->pfc_state = ocrdma_is_enabled_and_synced(dcbxcfg.pfc_state);
2909         dev->sl = srvc_lvl;
2910 }
2911
2912 int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2913 {
2914         int i;
2915         int status = -EINVAL;
2916         struct ocrdma_av *av;
2917         unsigned long flags;
2918
2919         av = dev->av_tbl.va;
2920         spin_lock_irqsave(&dev->av_tbl.lock, flags);
2921         for (i = 0; i < dev->av_tbl.num_ah; i++) {
2922                 if (av->valid == 0) {
2923                         av->valid = OCRDMA_AV_VALID;
2924                         ah->av = av;
2925                         ah->id = i;
2926                         status = 0;
2927                         break;
2928                 }
2929                 av++;
2930         }
2931         if (i == dev->av_tbl.num_ah)
2932                 status = -EAGAIN;
2933         spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2934         return status;
2935 }
2936
2937 int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2938 {
2939         unsigned long flags;
2940         spin_lock_irqsave(&dev->av_tbl.lock, flags);
2941         ah->av->valid = 0;
2942         spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2943         return 0;
2944 }
2945
2946 static int ocrdma_create_eqs(struct ocrdma_dev *dev)
2947 {
2948         int num_eq, i, status = 0;
2949         int irq;
2950         unsigned long flags = 0;
2951
2952         num_eq = dev->nic_info.msix.num_vectors -
2953                         dev->nic_info.msix.start_vector;
2954         if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
2955                 num_eq = 1;
2956                 flags = IRQF_SHARED;
2957         } else {
2958                 num_eq = min_t(u32, num_eq, num_online_cpus());
2959         }
2960
2961         if (!num_eq)
2962                 return -EINVAL;
2963
2964         dev->eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
2965         if (!dev->eq_tbl)
2966                 return -ENOMEM;
2967
2968         for (i = 0; i < num_eq; i++) {
2969                 status = ocrdma_create_eq(dev, &dev->eq_tbl[i],
2970                                         OCRDMA_EQ_LEN);
2971                 if (status) {
2972                         status = -EINVAL;
2973                         break;
2974                 }
2975                 sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d",
2976                         dev->id, i);
2977                 irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]);
2978                 status = request_irq(irq, ocrdma_irq_handler, flags,
2979                                      dev->eq_tbl[i].irq_name,
2980                                      &dev->eq_tbl[i]);
2981                 if (status)
2982                         goto done;
2983                 dev->eq_cnt += 1;
2984         }
2985         /* one eq is sufficient for data path to work */
2986         return 0;
2987 done:
2988         ocrdma_destroy_eqs(dev);
2989         return status;
2990 }
2991
2992 int ocrdma_init_hw(struct ocrdma_dev *dev)
2993 {
2994         int status;
2995
2996         /* create the eqs  */
2997         status = ocrdma_create_eqs(dev);
2998         if (status)
2999                 goto qpeq_err;
3000         status = ocrdma_create_mq(dev);
3001         if (status)
3002                 goto mq_err;
3003         status = ocrdma_mbx_query_fw_config(dev);
3004         if (status)
3005                 goto conf_err;
3006         status = ocrdma_mbx_query_dev(dev);
3007         if (status)
3008                 goto conf_err;
3009         status = ocrdma_mbx_query_fw_ver(dev);
3010         if (status)
3011                 goto conf_err;
3012         status = ocrdma_mbx_create_ah_tbl(dev);
3013         if (status)
3014                 goto conf_err;
3015         status = ocrdma_mbx_get_phy_info(dev);
3016         if (status)
3017                 goto info_attrb_err;
3018         status = ocrdma_mbx_get_ctrl_attribs(dev);
3019         if (status)
3020                 goto info_attrb_err;
3021
3022         return 0;
3023
3024 info_attrb_err:
3025         ocrdma_mbx_delete_ah_tbl(dev);
3026 conf_err:
3027         ocrdma_destroy_mq(dev);
3028 mq_err:
3029         ocrdma_destroy_eqs(dev);
3030 qpeq_err:
3031         pr_err("%s() status=%d\n", __func__, status);
3032         return status;
3033 }
3034
3035 void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
3036 {
3037         ocrdma_free_pd_pool(dev);
3038         ocrdma_mbx_delete_ah_tbl(dev);
3039
3040         /* cleanup the eqs */
3041         ocrdma_destroy_eqs(dev);
3042
3043         /* cleanup the control path */
3044         ocrdma_destroy_mq(dev);
3045 }