drivers/infiniband/hw/ocrdma/ocrdma_hw.c

   1 /*******************************************************************
   2  * This file is part of the Emulex RoCE Device Driver for          *
   3  * RoCE (RDMA over Converged Ethernet) CNA Adapters.              *
   4  * Copyright (C) 2008-2012 Emulex. All rights reserved.            *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *
  20  * Contact Information:
  21  * linux-drivers@emulex.com
  22  *
  23  * Emulex
  24  * 3333 Susan Street
  25  * Costa Mesa, CA 92626
  26  *******************************************************************/
  27
  28 #include <linux/sched.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/log2.h>
  31 #include <linux/dma-mapping.h>
  32
  33 #include <rdma/ib_verbs.h>
  34 #include <rdma/ib_user_verbs.h>
  35
  36 #include "ocrdma.h"
  37 #include "ocrdma_hw.h"
  38 #include "ocrdma_verbs.h"
  39 #include "ocrdma_ah.h"
  40
  41 enum mbx_status {
  42         OCRDMA_MBX_STATUS_FAILED                = 1,
  43         OCRDMA_MBX_STATUS_ILLEGAL_FIELD         = 3,
  44         OCRDMA_MBX_STATUS_OOR                   = 100,
  45         OCRDMA_MBX_STATUS_INVALID_PD            = 101,
  46         OCRDMA_MBX_STATUS_PD_INUSE              = 102,
  47         OCRDMA_MBX_STATUS_INVALID_CQ            = 103,
  48         OCRDMA_MBX_STATUS_INVALID_QP            = 104,
  49         OCRDMA_MBX_STATUS_INVALID_LKEY          = 105,
  50         OCRDMA_MBX_STATUS_ORD_EXCEEDS           = 106,
  51         OCRDMA_MBX_STATUS_IRD_EXCEEDS           = 107,
  52         OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS     = 108,
  53         OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS     = 109,
  54         OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS      = 110,
  55         OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS     = 111,
  56         OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS      = 112,
  57         OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE  = 113,
  58         OCRDMA_MBX_STATUS_MW_BOUND              = 114,
  59         OCRDMA_MBX_STATUS_INVALID_VA            = 115,
  60         OCRDMA_MBX_STATUS_INVALID_LENGTH        = 116,
  61         OCRDMA_MBX_STATUS_INVALID_FBO           = 117,
  62         OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS    = 118,
  63         OCRDMA_MBX_STATUS_INVALID_PBE_SIZE      = 119,
  64         OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY     = 120,
  65         OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT     = 121,
  66         OCRDMA_MBX_STATUS_INVALID_SRQ_ID        = 129,
  67         OCRDMA_MBX_STATUS_SRQ_ERROR             = 133,
  68         OCRDMA_MBX_STATUS_RQE_EXCEEDS           = 134,
  69         OCRDMA_MBX_STATUS_MTU_EXCEEDS           = 135,
  70         OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS        = 136,
  71         OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS     = 137,
  72         OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS     = 138,
  73         OCRDMA_MBX_STATUS_QP_BOUND              = 130,
  74         OCRDMA_MBX_STATUS_INVALID_CHANGE        = 139,
  75         OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP      = 140,
  76         OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
  77         OCRDMA_MBX_STATUS_MW_STILL_BOUND        = 142,
  78         OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID    = 143,
  79         OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS    = 144
  80 };
  81
  82 enum additional_status {
  83         OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
  84 };
  85
  86 enum cqe_status {
  87         OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES  = 1,
  88         OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER         = 2,
  89         OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES    = 3,
  90         OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING            = 4,
  91         OCRDMA_MBX_CQE_STATUS_DMA_FAILED                = 5
  92 };
  93
  94 static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
  95 {
  96         return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
  97 }
  98
  99 static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
 100 {
 101         eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
 102 }
 103
 104 static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
 105 {
 106         struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
 107             (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
 108
 109         if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
 110                 return NULL;
 111         return cqe;
 112 }
 113
 114 static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
 115 {
 116         dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
 117 }
 118
 119 static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
 120 {
 121         return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
 122 }
 123
 124 static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
 125 {
 126         dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
 127 }
 128
 129 static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
 130 {
 131         return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
 132 }
 133
 134 enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
 135 {
 136         switch (qps) {
 137         case OCRDMA_QPS_RST:
 138                 return IB_QPS_RESET;
 139         case OCRDMA_QPS_INIT:
 140                 return IB_QPS_INIT;
 141         case OCRDMA_QPS_RTR:
 142                 return IB_QPS_RTR;
 143         case OCRDMA_QPS_RTS:
 144                 return IB_QPS_RTS;
 145         case OCRDMA_QPS_SQD:
 146         case OCRDMA_QPS_SQ_DRAINING:
 147                 return IB_QPS_SQD;
 148         case OCRDMA_QPS_SQE:
 149                 return IB_QPS_SQE;
 150         case OCRDMA_QPS_ERR:
 151                 return IB_QPS_ERR;
 152         }
 153         return IB_QPS_ERR;
 154 }
 155
 156 static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
 157 {
 158         switch (qps) {
 159         case IB_QPS_RESET:
 160                 return OCRDMA_QPS_RST;
 161         case IB_QPS_INIT:
 162                 return OCRDMA_QPS_INIT;
 163         case IB_QPS_RTR:
 164                 return OCRDMA_QPS_RTR;
 165         case IB_QPS_RTS:
 166                 return OCRDMA_QPS_RTS;
 167         case IB_QPS_SQD:
 168                 return OCRDMA_QPS_SQD;
 169         case IB_QPS_SQE:
 170                 return OCRDMA_QPS_SQE;
 171         case IB_QPS_ERR:
 172                 return OCRDMA_QPS_ERR;
 173         }
 174         return OCRDMA_QPS_ERR;
 175 }
 176
 177 static int ocrdma_get_mbx_errno(u32 status)
 178 {
 179         int err_num;
 180         u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
 181                                         OCRDMA_MBX_RSP_STATUS_SHIFT;
 182         u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
 183                                         OCRDMA_MBX_RSP_ASTATUS_SHIFT;
 184
 185         switch (mbox_status) {
 186         case OCRDMA_MBX_STATUS_OOR:
 187         case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
 188                 err_num = -EAGAIN;
 189                 break;
 190
 191         case OCRDMA_MBX_STATUS_INVALID_PD:
 192         case OCRDMA_MBX_STATUS_INVALID_CQ:
 193         case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
 194         case OCRDMA_MBX_STATUS_INVALID_QP:
 195         case OCRDMA_MBX_STATUS_INVALID_CHANGE:
 196         case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
 197         case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
 198         case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
 199         case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
 200         case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
 201         case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
 202         case OCRDMA_MBX_STATUS_INVALID_LKEY:
 203         case OCRDMA_MBX_STATUS_INVALID_VA:
 204         case OCRDMA_MBX_STATUS_INVALID_LENGTH:
 205         case OCRDMA_MBX_STATUS_INVALID_FBO:
 206         case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
 207         case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
 208         case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
 209         case OCRDMA_MBX_STATUS_SRQ_ERROR:
 210         case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
 211                 err_num = -EINVAL;
 212                 break;
 213
 214         case OCRDMA_MBX_STATUS_PD_INUSE:
 215         case OCRDMA_MBX_STATUS_QP_BOUND:
 216         case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
 217         case OCRDMA_MBX_STATUS_MW_BOUND:
 218                 err_num = -EBUSY;
 219                 break;
 220
 221         case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
 222         case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
 223         case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
 224         case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
 225         case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
 226         case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
 227         case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
 228         case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
 229         case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
 230                 err_num = -ENOBUFS;
 231                 break;
 232
 233         case OCRDMA_MBX_STATUS_FAILED:
 234                 switch (add_status) {
 235                 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
 236                         err_num = -EAGAIN;
 237                         break;
 238                 }
 239         default:
 240                 err_num = -EFAULT;
 241         }
 242         return err_num;
 243 }
 244
 245 char *port_speed_string(struct ocrdma_dev *dev)
 246 {
 247         char *str = "";
 248         u16 speeds_supported;
 249
 250         speeds_supported = dev->phy.fixed_speeds_supported |
 251                                 dev->phy.auto_speeds_supported;
 252         if (speeds_supported & OCRDMA_PHY_SPEED_40GBPS)
 253                 str = "40Gbps ";
 254         else if (speeds_supported & OCRDMA_PHY_SPEED_10GBPS)
 255                 str = "10Gbps ";
 256         else if (speeds_supported & OCRDMA_PHY_SPEED_1GBPS)
 257                 str = "1Gbps ";
 258
 259         return str;
 260 }
 261
 262 static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
 263 {
 264         int err_num = -EINVAL;
 265
 266         switch (cqe_status) {
 267         case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
 268                 err_num = -EPERM;
 269                 break;
 270         case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
 271                 err_num = -EINVAL;
 272                 break;
 273         case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
 274         case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
 275                 err_num = -EINVAL;
 276                 break;
 277         case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
 278         default:
 279                 err_num = -EINVAL;
 280                 break;
 281         }
 282         return err_num;
 283 }
 284
 285 void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
 286                        bool solicited, u16 cqe_popped)
 287 {
 288         u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
 289
 290         val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
 291              OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
 292
 293         if (armed)
 294                 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
 295         if (solicited)
 296                 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
 297         val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
 298         iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
 299 }
 300
 301 static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
 302 {
 303         u32 val = 0;
 304
 305         val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
 306         val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
 307         iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
 308 }
 309
 310 static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
 311                               bool arm, bool clear_int, u16 num_eqe)
 312 {
 313         u32 val = 0;
 314
 315         val |= eq_id & OCRDMA_EQ_ID_MASK;
 316         val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
 317         if (arm)
 318                 val |= (1 << OCRDMA_REARM_SHIFT);
 319         if (clear_int)
 320                 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
 321         val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
 322         val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
 323         iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
 324 }
 325
 326 static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
 327                             u8 opcode, u8 subsys, u32 cmd_len)
 328 {
 329         cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
 330         cmd_hdr->timeout = 20; /* seconds */
 331         cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
 332 }
 333
 334 static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
 335 {
 336         struct ocrdma_mqe *mqe;
 337
 338         mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
 339         if (!mqe)
 340                 return NULL;
 341         mqe->hdr.spcl_sge_cnt_emb |=
 342                 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
 343                                         OCRDMA_MQE_HDR_EMB_MASK;
 344         mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
 345
 346         ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
 347                         mqe->hdr.pyld_len);
 348         return mqe;
 349 }
 350
 351 static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
 352 {
 353         dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
 354 }
 355
 356 static int ocrdma_alloc_q(struct ocrdma_dev *dev,
 357                           struct ocrdma_queue_info *q, u16 len, u16 entry_size)
 358 {
 359         memset(q, 0, sizeof(*q));
 360         q->len = len;
 361         q->entry_size = entry_size;
 362         q->size = len * entry_size;
 363         q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
 364                                    &q->dma, GFP_KERNEL);
 365         if (!q->va)
 366                 return -ENOMEM;
 367         memset(q->va, 0, q->size);
 368         return 0;
 369 }
 370
 371 static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
 372                                         dma_addr_t host_pa, int hw_page_size)
 373 {
 374         int i;
 375
 376         for (i = 0; i < cnt; i++) {
 377                 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
 378                 q_pa[i].hi = (u32) upper_32_bits(host_pa);
 379                 host_pa += hw_page_size;
 380         }
 381 }
 382
 383 static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev,
 384                                struct ocrdma_queue_info *q, int queue_type)
 385 {
 386         u8 opcode = 0;
 387         int status;
 388         struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
 389
 390         switch (queue_type) {
 391         case QTYPE_MCCQ:
 392                 opcode = OCRDMA_CMD_DELETE_MQ;
 393                 break;
 394         case QTYPE_CQ:
 395                 opcode = OCRDMA_CMD_DELETE_CQ;
 396                 break;
 397         case QTYPE_EQ:
 398                 opcode = OCRDMA_CMD_DELETE_EQ;
 399                 break;
 400         default:
 401                 BUG();
 402         }
 403         memset(cmd, 0, sizeof(*cmd));
 404         ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 405         cmd->id = q->id;
 406
 407         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 408                                  cmd, sizeof(*cmd), NULL, NULL);
 409         if (!status)
 410                 q->created = false;
 411         return status;
 412 }
 413
 414 static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 415 {
 416         int status;
 417         struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
 418         struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
 419
 420         memset(cmd, 0, sizeof(*cmd));
 421         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
 422                         sizeof(*cmd));
 423
 424         cmd->req.rsvd_version = 2;
 425         cmd->num_pages = 4;
 426         cmd->valid = OCRDMA_CREATE_EQ_VALID;
 427         cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
 428
 429         ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
 430                              PAGE_SIZE_4K);
 431         status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
 432                                  NULL);
 433         if (!status) {
 434                 eq->q.id = rsp->vector_eqid & 0xffff;
 435                 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
 436                 eq->q.created = true;
 437         }
 438         return status;
 439 }
 440
 441 static int ocrdma_create_eq(struct ocrdma_dev *dev,
 442                             struct ocrdma_eq *eq, u16 q_len)
 443 {
 444         int status;
 445
 446         status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
 447                                 sizeof(struct ocrdma_eqe));
 448         if (status)
 449                 return status;
 450
 451         status = ocrdma_mbx_create_eq(dev, eq);
 452         if (status)
 453                 goto mbx_err;
 454         eq->dev = dev;
 455         ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
 456
 457         return 0;
 458 mbx_err:
 459         ocrdma_free_q(dev, &eq->q);
 460         return status;
 461 }
 462
 463 int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 464 {
 465         int irq;
 466
 467         if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
 468                 irq = dev->nic_info.pdev->irq;
 469         else
 470                 irq = dev->nic_info.msix.vector_list[eq->vector];
 471         return irq;
 472 }
 473
 474 static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 475 {
 476         if (eq->q.created) {
 477                 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
 478                 ocrdma_free_q(dev, &eq->q);
 479         }
 480 }
 481
 482 static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 483 {
 484         int irq;
 485
 486         /* disarm EQ so that interrupts are not generated
 487          * during freeing and EQ delete is in progress.
 488          */
 489         ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
 490
 491         irq = ocrdma_get_irq(dev, eq);
 492         free_irq(irq, eq);
 493         _ocrdma_destroy_eq(dev, eq);
 494 }
 495
 496 static void ocrdma_destroy_eqs(struct ocrdma_dev *dev)
 497 {
 498         int i;
 499
 500         for (i = 0; i < dev->eq_cnt; i++)
 501                 ocrdma_destroy_eq(dev, &dev->eq_tbl[i]);
 502 }
 503
 504 static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
 505                                    struct ocrdma_queue_info *cq,
 506                                    struct ocrdma_queue_info *eq)
 507 {
 508         struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
 509         struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
 510         int status;
 511
 512         memset(cmd, 0, sizeof(*cmd));
 513         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
 514                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 515
 516         cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
 517         cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
 518                 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
 519         cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
 520
 521         cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
 522         cmd->eqn = eq->id;
 523         cmd->pdid_cqecnt = cq->size / sizeof(struct ocrdma_mcqe);
 524
 525         ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
 526                              cq->dma, PAGE_SIZE_4K);
 527         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 528                                  cmd, sizeof(*cmd), NULL, NULL);
 529         if (!status) {
 530                 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
 531                 cq->created = true;
 532         }
 533         return status;
 534 }
 535
 536 static u32 ocrdma_encoded_q_len(int q_len)
 537 {
 538         u32 len_encoded = fls(q_len);   /* log2(len) + 1 */
 539
 540         if (len_encoded == 16)
 541                 len_encoded = 0;
 542         return len_encoded;
 543 }
 544
 545 static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
 546                                 struct ocrdma_queue_info *mq,
 547                                 struct ocrdma_queue_info *cq)
 548 {
 549         int num_pages, status;
 550         struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
 551         struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
 552         struct ocrdma_pa *pa;
 553
 554         memset(cmd, 0, sizeof(*cmd));
 555         num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
 556
 557         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
 558                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 559         cmd->req.rsvd_version = 1;
 560         cmd->cqid_pages = num_pages;
 561         cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
 562         cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
 563
 564         cmd->async_event_bitmap = BIT(OCRDMA_ASYNC_GRP5_EVE_CODE);
 565         cmd->async_event_bitmap |= BIT(OCRDMA_ASYNC_RDMA_EVE_CODE);
 566
 567         cmd->async_cqid_ringsize = cq->id;
 568         cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
 569                                 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
 570         cmd->valid = OCRDMA_CREATE_MQ_VALID;
 571         pa = &cmd->pa[0];
 572
 573         ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
 574         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 575                                  cmd, sizeof(*cmd), NULL, NULL);
 576         if (!status) {
 577                 mq->id = rsp->id;
 578                 mq->created = true;
 579         }
 580         return status;
 581 }
 582
 583 static int ocrdma_create_mq(struct ocrdma_dev *dev)
 584 {
 585         int status;
 586
 587         /* Alloc completion queue for Mailbox queue */
 588         status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
 589                                 sizeof(struct ocrdma_mcqe));
 590         if (status)
 591                 goto alloc_err;
 592
 593         dev->eq_tbl[0].cq_cnt++;
 594         status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q);
 595         if (status)
 596                 goto mbx_cq_free;
 597
 598         memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
 599         init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
 600         mutex_init(&dev->mqe_ctx.lock);
 601
 602         /* Alloc Mailbox queue */
 603         status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
 604                                 sizeof(struct ocrdma_mqe));
 605         if (status)
 606                 goto mbx_cq_destroy;
 607         status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
 608         if (status)
 609                 goto mbx_q_free;
 610         ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
 611         return 0;
 612
 613 mbx_q_free:
 614         ocrdma_free_q(dev, &dev->mq.sq);
 615 mbx_cq_destroy:
 616         ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
 617 mbx_cq_free:
 618         ocrdma_free_q(dev, &dev->mq.cq);
 619 alloc_err:
 620         return status;
 621 }
 622
 623 static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
 624 {
 625         struct ocrdma_queue_info *mbxq, *cq;
 626
 627         /* mqe_ctx lock synchronizes with any other pending cmds. */
 628         mutex_lock(&dev->mqe_ctx.lock);
 629         mbxq = &dev->mq.sq;
 630         if (mbxq->created) {
 631                 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
 632                 ocrdma_free_q(dev, mbxq);
 633         }
 634         mutex_unlock(&dev->mqe_ctx.lock);
 635
 636         cq = &dev->mq.cq;
 637         if (cq->created) {
 638                 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
 639                 ocrdma_free_q(dev, cq);
 640         }
 641 }
 642
 643 static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
 644                                        struct ocrdma_qp *qp)
 645 {
 646         enum ib_qp_state new_ib_qps = IB_QPS_ERR;
 647         enum ib_qp_state old_ib_qps;
 648
 649         if (qp == NULL)
 650                 BUG();
 651         ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
 652 }
 653
 654 static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
 655                                     struct ocrdma_ae_mcqe *cqe)
 656 {
 657         struct ocrdma_qp *qp = NULL;
 658         struct ocrdma_cq *cq = NULL;
 659         struct ib_event ib_evt;
 660         int cq_event = 0;
 661         int qp_event = 1;
 662         int srq_event = 0;
 663         int dev_event = 0;
 664         int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
 665             OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
 666
 667         if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID)
 668                 qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK];
 669         if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID)
 670                 cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK];
 671
 672         memset(&ib_evt, 0, sizeof(ib_evt));
 673
 674         ib_evt.device = &dev->ibdev;
 675
 676         switch (type) {
 677         case OCRDMA_CQ_ERROR:
 678                 ib_evt.element.cq = &cq->ibcq;
 679                 ib_evt.event = IB_EVENT_CQ_ERR;
 680                 cq_event = 1;
 681                 qp_event = 0;
 682                 break;
 683         case OCRDMA_CQ_OVERRUN_ERROR:
 684                 ib_evt.element.cq = &cq->ibcq;
 685                 ib_evt.event = IB_EVENT_CQ_ERR;
 686                 cq_event = 1;
 687                 qp_event = 0;
 688                 break;
 689         case OCRDMA_CQ_QPCAT_ERROR:
 690                 ib_evt.element.qp = &qp->ibqp;
 691                 ib_evt.event = IB_EVENT_QP_FATAL;
 692                 ocrdma_process_qpcat_error(dev, qp);
 693                 break;
 694         case OCRDMA_QP_ACCESS_ERROR:
 695                 ib_evt.element.qp = &qp->ibqp;
 696                 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
 697                 break;
 698         case OCRDMA_QP_COMM_EST_EVENT:
 699                 ib_evt.element.qp = &qp->ibqp;
 700                 ib_evt.event = IB_EVENT_COMM_EST;
 701                 break;
 702         case OCRDMA_SQ_DRAINED_EVENT:
 703                 ib_evt.element.qp = &qp->ibqp;
 704                 ib_evt.event = IB_EVENT_SQ_DRAINED;
 705                 break;
 706         case OCRDMA_DEVICE_FATAL_EVENT:
 707                 ib_evt.element.port_num = 1;
 708                 ib_evt.event = IB_EVENT_DEVICE_FATAL;
 709                 qp_event = 0;
 710                 dev_event = 1;
 711                 break;
 712         case OCRDMA_SRQCAT_ERROR:
 713                 ib_evt.element.srq = &qp->srq->ibsrq;
 714                 ib_evt.event = IB_EVENT_SRQ_ERR;
 715                 srq_event = 1;
 716                 qp_event = 0;
 717                 break;
 718         case OCRDMA_SRQ_LIMIT_EVENT:
 719                 ib_evt.element.srq = &qp->srq->ibsrq;
 720                 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
 721                 srq_event = 1;
 722                 qp_event = 0;
 723                 break;
 724         case OCRDMA_QP_LAST_WQE_EVENT:
 725                 ib_evt.element.qp = &qp->ibqp;
 726                 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
 727                 break;
 728         default:
 729                 cq_event = 0;
 730                 qp_event = 0;
 731                 srq_event = 0;
 732                 dev_event = 0;
 733                 pr_err("%s() unknown type=0x%x\n", __func__, type);
 734                 break;
 735         }
 736
 737         if (type < OCRDMA_MAX_ASYNC_ERRORS)
 738                 atomic_inc(&dev->async_err_stats[type]);
 739
 740         if (qp_event) {
 741                 if (qp->ibqp.event_handler)
 742                         qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
 743         } else if (cq_event) {
 744                 if (cq->ibcq.event_handler)
 745                         cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
 746         } else if (srq_event) {
 747                 if (qp->srq->ibsrq.event_handler)
 748                         qp->srq->ibsrq.event_handler(&ib_evt,
 749                                                      qp->srq->ibsrq.
 750                                                      srq_context);
 751         } else if (dev_event) {
 752                 pr_err("%s: Fatal event received\n", dev->ibdev.name);
 753                 ib_dispatch_event(&ib_evt);
 754         }
 755
 756 }
 757
 758 static void ocrdma_process_grp5_aync(struct ocrdma_dev *dev,
 759                                         struct ocrdma_ae_mcqe *cqe)
 760 {
 761         struct ocrdma_ae_pvid_mcqe *evt;
 762         int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
 763                         OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
 764
 765         switch (type) {
 766         case OCRDMA_ASYNC_EVENT_PVID_STATE:
 767                 evt = (struct ocrdma_ae_pvid_mcqe *)cqe;
 768                 if ((evt->tag_enabled & OCRDMA_AE_PVID_MCQE_ENABLED_MASK) >>
 769                         OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT)
 770                         dev->pvid = ((evt->tag_enabled &
 771                                         OCRDMA_AE_PVID_MCQE_TAG_MASK) >>
 772                                         OCRDMA_AE_PVID_MCQE_TAG_SHIFT);
 773                 break;
 774
 775         case OCRDMA_ASYNC_EVENT_COS_VALUE:
 776                 atomic_set(&dev->update_sl, 1);
 777                 break;
 778         default:
 779                 /* Not interested evts. */
 780                 break;
 781         }
 782 }
 783
 784 static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
 785 {
 786         /* async CQE processing */
 787         struct ocrdma_ae_mcqe *cqe = ae_cqe;
 788         u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
 789                         OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
 790
 791         if (evt_code == OCRDMA_ASYNC_RDMA_EVE_CODE)
 792                 ocrdma_dispatch_ibevent(dev, cqe);
 793         else if (evt_code == OCRDMA_ASYNC_GRP5_EVE_CODE)
 794                 ocrdma_process_grp5_aync(dev, cqe);
 795         else
 796                 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
 797                        dev->id, evt_code);
 798 }
 799
 800 static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
 801 {
 802         if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
 803                 dev->mqe_ctx.cqe_status = (cqe->status &
 804                      OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
 805                 dev->mqe_ctx.ext_status =
 806                     (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
 807                     >> OCRDMA_MCQE_ESTATUS_SHIFT;
 808                 dev->mqe_ctx.cmd_done = true;
 809                 wake_up(&dev->mqe_ctx.cmd_wait);
 810         } else
 811                 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
 812                        __func__, cqe->tag_lo, dev->mqe_ctx.tag);
 813 }
 814
 815 static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
 816 {
 817         u16 cqe_popped = 0;
 818         struct ocrdma_mcqe *cqe;
 819
 820         while (1) {
 821                 cqe = ocrdma_get_mcqe(dev);
 822                 if (cqe == NULL)
 823                         break;
 824                 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
 825                 cqe_popped += 1;
 826                 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
 827                         ocrdma_process_acqe(dev, cqe);
 828                 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
 829                         ocrdma_process_mcqe(dev, cqe);
 830                 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
 831                 ocrdma_mcq_inc_tail(dev);
 832         }
 833         ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
 834         return 0;
 835 }
 836
 837 static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
 838                                        struct ocrdma_cq *cq)
 839 {
 840         unsigned long flags;
 841         struct ocrdma_qp *qp;
 842         bool buddy_cq_found = false;
 843         /* Go through list of QPs in error state which are using this CQ
 844          * and invoke its callback handler to trigger CQE processing for
 845          * error/flushed CQE. It is rare to find more than few entries in
 846          * this list as most consumers stops after getting error CQE.
 847          * List is traversed only once when a matching buddy cq found for a QP.
 848          */
 849         spin_lock_irqsave(&dev->flush_q_lock, flags);
 850         list_for_each_entry(qp, &cq->sq_head, sq_entry) {
 851                 if (qp->srq)
 852                         continue;
 853                 /* if wq and rq share the same cq, than comp_handler
 854                  * is already invoked.
 855                  */
 856                 if (qp->sq_cq == qp->rq_cq)
 857                         continue;
 858                 /* if completion came on sq, rq's cq is buddy cq.
 859                  * if completion came on rq, sq's cq is buddy cq.
 860                  */
 861                 if (qp->sq_cq == cq)
 862                         cq = qp->rq_cq;
 863                 else
 864                         cq = qp->sq_cq;
 865                 buddy_cq_found = true;
 866                 break;
 867         }
 868         spin_unlock_irqrestore(&dev->flush_q_lock, flags);
 869         if (buddy_cq_found == false)
 870                 return;
 871         if (cq->ibcq.comp_handler) {
 872                 spin_lock_irqsave(&cq->comp_handler_lock, flags);
 873                 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
 874                 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
 875         }
 876 }
 877
 878 static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
 879 {
 880         unsigned long flags;
 881         struct ocrdma_cq *cq;
 882
 883         if (cq_idx >= OCRDMA_MAX_CQ)
 884                 BUG();
 885
 886         cq = dev->cq_tbl[cq_idx];
 887         if (cq == NULL)
 888                 return;
 889
 890         if (cq->ibcq.comp_handler) {
 891                 spin_lock_irqsave(&cq->comp_handler_lock, flags);
 892                 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
 893                 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
 894         }
 895         ocrdma_qp_buddy_cq_handler(dev, cq);
 896 }
 897
 898 static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
 899 {
 900         /* process the MQ-CQE. */
 901         if (cq_id == dev->mq.cq.id)
 902                 ocrdma_mq_cq_handler(dev, cq_id);
 903         else
 904                 ocrdma_qp_cq_handler(dev, cq_id);
 905 }
 906
 907 static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
 908 {
 909         struct ocrdma_eq *eq = handle;
 910         struct ocrdma_dev *dev = eq->dev;
 911         struct ocrdma_eqe eqe;
 912         struct ocrdma_eqe *ptr;
 913         u16 cq_id;
 914         int budget = eq->cq_cnt;
 915
 916         do {
 917                 ptr = ocrdma_get_eqe(eq);
 918                 eqe = *ptr;
 919                 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
 920                 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
 921                         break;
 922
 923                 ptr->id_valid = 0;
 924                 /* ring eq doorbell as soon as its consumed. */
 925                 ocrdma_ring_eq_db(dev, eq->q.id, false, true, 1);
 926                 /* check whether its CQE or not. */
 927                 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
 928                         cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
 929                         ocrdma_cq_handler(dev, cq_id);
 930                 }
 931                 ocrdma_eq_inc_tail(eq);
 932
 933                 /* There can be a stale EQE after the last bound CQ is
 934                  * destroyed. EQE valid and budget == 0 implies this.
 935                  */
 936                 if (budget)
 937                         budget--;
 938
 939         } while (budget);
 940
 941         ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
 942         return IRQ_HANDLED;
 943 }
 944
 945 static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
 946 {
 947         struct ocrdma_mqe *mqe;
 948
 949         dev->mqe_ctx.tag = dev->mq.sq.head;
 950         dev->mqe_ctx.cmd_done = false;
 951         mqe = ocrdma_get_mqe(dev);
 952         cmd->hdr.tag_lo = dev->mq.sq.head;
 953         ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
 954         /* make sure descriptor is written before ringing doorbell */
 955         wmb();
 956         ocrdma_mq_inc_head(dev);
 957         ocrdma_ring_mq_db(dev);
 958 }
 959
 960 static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
 961 {
 962         long status;
 963         /* 30 sec timeout */
 964         status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
 965                                     (dev->mqe_ctx.cmd_done != false),
 966                                     msecs_to_jiffies(30000));
 967         if (status)
 968                 return 0;
 969         else {
 970                 dev->mqe_ctx.fw_error_state = true;
 971                 pr_err("%s(%d) mailbox timeout: fw not responding\n",
 972                        __func__, dev->id);
 973                 return -1;
 974         }
 975 }
 976
 977 /* issue a mailbox command on the MQ */
 978 static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
 979 {
 980         int status = 0;
 981         u16 cqe_status, ext_status;
 982         struct ocrdma_mqe *rsp_mqe;
 983         struct ocrdma_mbx_rsp *rsp = NULL;
 984
 985         mutex_lock(&dev->mqe_ctx.lock);
 986         if (dev->mqe_ctx.fw_error_state)
 987                 goto mbx_err;
 988         ocrdma_post_mqe(dev, mqe);
 989         status = ocrdma_wait_mqe_cmpl(dev);
 990         if (status)
 991                 goto mbx_err;
 992         cqe_status = dev->mqe_ctx.cqe_status;
 993         ext_status = dev->mqe_ctx.ext_status;
 994         rsp_mqe = ocrdma_get_mqe_rsp(dev);
 995         ocrdma_copy_le32_to_cpu(mqe, rsp_mqe, (sizeof(*mqe)));
 996         if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
 997                                 OCRDMA_MQE_HDR_EMB_SHIFT)
 998                 rsp = &mqe->u.rsp;
 999
1000         if (cqe_status || ext_status) {
1001                 pr_err("%s() cqe_status=0x%x, ext_status=0x%x,",
1002                        __func__, cqe_status, ext_status);
1003                 if (rsp) {
1004                         /* This is for embedded cmds. */
1005                         pr_err("opcode=0x%x, subsystem=0x%x\n",
1006                                (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1007                                 OCRDMA_MBX_RSP_OPCODE_SHIFT,
1008                                 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1009                                 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1010                 }
1011                 status = ocrdma_get_mbx_cqe_errno(cqe_status);
1012                 goto mbx_err;
1013         }
1014         /* For non embedded, rsp errors are handled in ocrdma_nonemb_mbx_cmd */
1015         if (rsp && (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK))
1016                 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
1017 mbx_err:
1018         mutex_unlock(&dev->mqe_ctx.lock);
1019         return status;
1020 }
1021
1022 static int ocrdma_nonemb_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe,
1023                                  void *payload_va)
1024 {
1025         int status = 0;
1026         struct ocrdma_mbx_rsp *rsp = payload_va;
1027
1028         if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1029                                 OCRDMA_MQE_HDR_EMB_SHIFT)
1030                 BUG();
1031
1032         status = ocrdma_mbx_cmd(dev, mqe);
1033         if (!status)
1034                 /* For non embedded, only CQE failures are handled in
1035                  * ocrdma_mbx_cmd. We need to check for RSP errors.
1036                  */
1037                 if (rsp->status & OCRDMA_MBX_RSP_STATUS_MASK)
1038                         status = ocrdma_get_mbx_errno(rsp->status);
1039
1040         if (status)
1041                 pr_err("opcode=0x%x, subsystem=0x%x\n",
1042                        (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1043                         OCRDMA_MBX_RSP_OPCODE_SHIFT,
1044                         (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1045                         OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1046         return status;
1047 }
1048
1049 static void ocrdma_get_attr(struct ocrdma_dev *dev,
1050                               struct ocrdma_dev_attr *attr,
1051                               struct ocrdma_mbx_query_config *rsp)
1052 {
1053         attr->max_pd =
1054             (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
1055             OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
1056         attr->max_dpp_pds =
1057            (rsp->max_dpp_pds_credits & OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK) >>
1058             OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET;
1059         attr->max_qp =
1060             (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
1061             OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
1062         attr->max_srq =
1063                 (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >>
1064                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET;
1065         attr->max_send_sge = ((rsp->max_write_send_sge &
1066                                OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1067                               OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
1068         attr->max_recv_sge = (rsp->max_write_send_sge &
1069                               OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1070             OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
1071         attr->max_srq_sge = (rsp->max_srq_rqe_sge &
1072                               OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
1073             OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
1074         attr->max_rdma_sge = (rsp->max_write_send_sge &
1075                               OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK) >>
1076             OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT;
1077         attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1078                                 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1079             OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
1080         attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1081                                 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1082             OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1083         attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1084                                     OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1085             OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1086         attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1087                                OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1088             OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1089         attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1090                                     OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1091             OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
1092         attr->max_mw = rsp->max_mw;
1093         attr->max_mr = rsp->max_mr;
1094         attr->max_mr_size = ((u64)rsp->max_mr_size_hi << 32) |
1095                               rsp->max_mr_size_lo;
1096         attr->max_fmr = 0;
1097         attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1098         attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1099         attr->max_cqe = rsp->max_cq_cqes_per_cq &
1100                         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
1101         attr->max_cq = (rsp->max_cq_cqes_per_cq &
1102                         OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK) >>
1103                         OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET;
1104         attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1105                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1106                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1107                 OCRDMA_WQE_STRIDE;
1108         attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1109                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1110                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1111                 OCRDMA_WQE_STRIDE;
1112         attr->max_inline_data =
1113             attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1114                               sizeof(struct ocrdma_sge));
1115         if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1116                 attr->ird = 1;
1117                 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1118                 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
1119         }
1120         dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1121                  OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1122         dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1123                 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
1124 }
1125
1126 static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1127                                    struct ocrdma_fw_conf_rsp *conf)
1128 {
1129         u32 fn_mode;
1130
1131         fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1132         if (fn_mode != OCRDMA_FN_MODE_RDMA)
1133                 return -EINVAL;
1134         dev->base_eqid = conf->base_eqid;
1135         dev->max_eq = conf->max_eq;
1136         return 0;
1137 }
1138
1139 /* can be issued only during init time. */
1140 static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1141 {
1142         int status = -ENOMEM;
1143         struct ocrdma_mqe *cmd;
1144         struct ocrdma_fw_ver_rsp *rsp;
1145
1146         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1147         if (!cmd)
1148                 return -ENOMEM;
1149         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1150                         OCRDMA_CMD_GET_FW_VER,
1151                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1152
1153         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1154         if (status)
1155                 goto mbx_err;
1156         rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1157         memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1158         memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1159                sizeof(rsp->running_ver));
1160         ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1161 mbx_err:
1162         kfree(cmd);
1163         return status;
1164 }
1165
1166 /* can be issued only during init time. */
1167 static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1168 {
1169         int status = -ENOMEM;
1170         struct ocrdma_mqe *cmd;
1171         struct ocrdma_fw_conf_rsp *rsp;
1172
1173         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1174         if (!cmd)
1175                 return -ENOMEM;
1176         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1177                         OCRDMA_CMD_GET_FW_CONFIG,
1178                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1179         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1180         if (status)
1181                 goto mbx_err;
1182         rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1183         status = ocrdma_check_fw_config(dev, rsp);
1184 mbx_err:
1185         kfree(cmd);
1186         return status;
1187 }
1188
1189 int ocrdma_mbx_rdma_stats(struct ocrdma_dev *dev, bool reset)
1190 {
1191         struct ocrdma_rdma_stats_req *req = dev->stats_mem.va;
1192         struct ocrdma_mqe *mqe = &dev->stats_mem.mqe;
1193         struct ocrdma_rdma_stats_resp *old_stats;
1194         int status;
1195
1196         old_stats = kmalloc(sizeof(*old_stats), GFP_KERNEL);
1197         if (old_stats == NULL)
1198                 return -ENOMEM;
1199
1200         memset(mqe, 0, sizeof(*mqe));
1201         mqe->hdr.pyld_len = dev->stats_mem.size;
1202         mqe->hdr.spcl_sge_cnt_emb |=
1203                         (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1204                                 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1205         mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dev->stats_mem.pa & 0xffffffff);
1206         mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dev->stats_mem.pa);
1207         mqe->u.nonemb_req.sge[0].len = dev->stats_mem.size;
1208
1209         /* Cache the old stats */
1210         memcpy(old_stats, req, sizeof(struct ocrdma_rdma_stats_resp));
1211         memset(req, 0, dev->stats_mem.size);
1212
1213         ocrdma_init_mch((struct ocrdma_mbx_hdr *)req,
1214                         OCRDMA_CMD_GET_RDMA_STATS,
1215                         OCRDMA_SUBSYS_ROCE,
1216                         dev->stats_mem.size);
1217         if (reset)
1218                 req->reset_stats = reset;
1219
1220         status = ocrdma_nonemb_mbx_cmd(dev, mqe, dev->stats_mem.va);
1221         if (status)
1222                 /* Copy from cache, if mbox fails */
1223                 memcpy(req, old_stats, sizeof(struct ocrdma_rdma_stats_resp));
1224         else
1225                 ocrdma_le32_to_cpu(req, dev->stats_mem.size);
1226
1227         kfree(old_stats);
1228         return status;
1229 }
1230
1231 static int ocrdma_mbx_get_ctrl_attribs(struct ocrdma_dev *dev)
1232 {
1233         int status = -ENOMEM;
1234         struct ocrdma_dma_mem dma;
1235         struct ocrdma_mqe *mqe;
1236         struct ocrdma_get_ctrl_attribs_rsp *ctrl_attr_rsp;
1237         struct mgmt_hba_attribs *hba_attribs;
1238
1239         mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
1240         if (!mqe)
1241                 return status;
1242
1243         dma.size = sizeof(struct ocrdma_get_ctrl_attribs_rsp);
1244         dma.va   = dma_alloc_coherent(&dev->nic_info.pdev->dev,
1245                                         dma.size, &dma.pa, GFP_KERNEL);
1246         if (!dma.va)
1247                 goto free_mqe;
1248
1249         mqe->hdr.pyld_len = dma.size;
1250         mqe->hdr.spcl_sge_cnt_emb |=
1251                         (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1252                         OCRDMA_MQE_HDR_SGE_CNT_MASK;
1253         mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dma.pa & 0xffffffff);
1254         mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dma.pa);
1255         mqe->u.nonemb_req.sge[0].len = dma.size;
1256
1257         memset(dma.va, 0, dma.size);
1258         ocrdma_init_mch((struct ocrdma_mbx_hdr *)dma.va,
1259                         OCRDMA_CMD_GET_CTRL_ATTRIBUTES,
1260                         OCRDMA_SUBSYS_COMMON,
1261                         dma.size);
1262
1263         status = ocrdma_nonemb_mbx_cmd(dev, mqe, dma.va);
1264         if (!status) {
1265                 ctrl_attr_rsp = (struct ocrdma_get_ctrl_attribs_rsp *)dma.va;
1266                 hba_attribs = &ctrl_attr_rsp->ctrl_attribs.hba_attribs;
1267
1268                 dev->hba_port_num = (hba_attribs->ptpnum_maxdoms_hbast_cv &
1269                                         OCRDMA_HBA_ATTRB_PTNUM_MASK)
1270                                         >> OCRDMA_HBA_ATTRB_PTNUM_SHIFT;
1271                 strncpy(dev->model_number,
1272                         hba_attribs->controller_model_number, 31);
1273         }
1274         dma_free_coherent(&dev->nic_info.pdev->dev, dma.size, dma.va, dma.pa);
1275 free_mqe:
1276         kfree(mqe);
1277         return status;
1278 }
1279
1280 static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1281 {
1282         int status = -ENOMEM;
1283         struct ocrdma_mbx_query_config *rsp;
1284         struct ocrdma_mqe *cmd;
1285
1286         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1287         if (!cmd)
1288                 return status;
1289         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1290         if (status)
1291                 goto mbx_err;
1292         rsp = (struct ocrdma_mbx_query_config *)cmd;
1293         ocrdma_get_attr(dev, &dev->attr, rsp);
1294 mbx_err:
1295         kfree(cmd);
1296         return status;
1297 }
1298
1299 int ocrdma_mbx_get_link_speed(struct ocrdma_dev *dev, u8 *lnk_speed)
1300 {
1301         int status = -ENOMEM;
1302         struct ocrdma_get_link_speed_rsp *rsp;
1303         struct ocrdma_mqe *cmd;
1304
1305         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1306                                   sizeof(*cmd));
1307         if (!cmd)
1308                 return status;
1309         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1310                         OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1311                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1312
1313         ((struct ocrdma_mbx_hdr *)cmd->u.cmd)->rsvd_version = 0x1;
1314
1315         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1316         if (status)
1317                 goto mbx_err;
1318
1319         rsp = (struct ocrdma_get_link_speed_rsp *)cmd;
1320         *lnk_speed = (rsp->pflt_pps_ld_pnum & OCRDMA_PHY_PS_MASK)
1321                         >> OCRDMA_PHY_PS_SHIFT;
1322
1323 mbx_err:
1324         kfree(cmd);
1325         return status;
1326 }
1327
1328 static int ocrdma_mbx_get_phy_info(struct ocrdma_dev *dev)
1329 {
1330         int status = -ENOMEM;
1331         struct ocrdma_mqe *cmd;
1332         struct ocrdma_get_phy_info_rsp *rsp;
1333
1334         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_PHY_DETAILS, sizeof(*cmd));
1335         if (!cmd)
1336                 return status;
1337
1338         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1339                         OCRDMA_CMD_PHY_DETAILS, OCRDMA_SUBSYS_COMMON,
1340                         sizeof(*cmd));
1341
1342         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1343         if (status)
1344                 goto mbx_err;
1345
1346         rsp = (struct ocrdma_get_phy_info_rsp *)cmd;
1347         dev->phy.phy_type =
1348                         (rsp->ityp_ptyp & OCRDMA_PHY_TYPE_MASK);
1349         dev->phy.interface_type =
1350                         (rsp->ityp_ptyp & OCRDMA_IF_TYPE_MASK)
1351                                 >> OCRDMA_IF_TYPE_SHIFT;
1352         dev->phy.auto_speeds_supported  =
1353                         (rsp->fspeed_aspeed & OCRDMA_ASPEED_SUPP_MASK);
1354         dev->phy.fixed_speeds_supported =
1355                         (rsp->fspeed_aspeed & OCRDMA_FSPEED_SUPP_MASK)
1356                                 >> OCRDMA_FSPEED_SUPP_SHIFT;
1357 mbx_err:
1358         kfree(cmd);
1359         return status;
1360 }
1361
1362 int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1363 {
1364         int status = -ENOMEM;
1365         struct ocrdma_alloc_pd *cmd;
1366         struct ocrdma_alloc_pd_rsp *rsp;
1367
1368         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1369         if (!cmd)
1370                 return status;
1371         if (pd->dpp_enabled)
1372                 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1373         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1374         if (status)
1375                 goto mbx_err;
1376         rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1377         pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1378         if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1379                 pd->dpp_enabled = true;
1380                 pd->dpp_page = rsp->dpp_page_pdid >>
1381                                 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1382         } else {
1383                 pd->dpp_enabled = false;
1384                 pd->num_dpp_qp = 0;
1385         }
1386 mbx_err:
1387         kfree(cmd);
1388         return status;
1389 }
1390
1391 int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1392 {
1393         int status = -ENOMEM;
1394         struct ocrdma_dealloc_pd *cmd;
1395
1396         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1397         if (!cmd)
1398                 return status;
1399         cmd->id = pd->id;
1400         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1401         kfree(cmd);
1402         return status;
1403 }
1404
1405
1406 static int ocrdma_mbx_alloc_pd_range(struct ocrdma_dev *dev)
1407 {
1408         int status = -ENOMEM;
1409         size_t pd_bitmap_size;
1410         struct ocrdma_alloc_pd_range *cmd;
1411         struct ocrdma_alloc_pd_range_rsp *rsp;
1412
1413         /* Pre allocate the DPP PDs */
1414         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE, sizeof(*cmd));
1415         if (!cmd)
1416                 return -ENOMEM;
1417         cmd->pd_count = dev->attr.max_dpp_pds;
1418         cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1419         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1420         if (status)
1421                 goto mbx_err;
1422         rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd;
1423
1424         if ((rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) && rsp->pd_count) {
1425                 dev->pd_mgr->dpp_page_index = rsp->dpp_page_pdid >>
1426                                 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1427                 dev->pd_mgr->pd_dpp_start = rsp->dpp_page_pdid &
1428                                 OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK;
1429                 dev->pd_mgr->max_dpp_pd = rsp->pd_count;
1430                 pd_bitmap_size = BITS_TO_LONGS(rsp->pd_count) * sizeof(long);
1431                 dev->pd_mgr->pd_dpp_bitmap = kzalloc(pd_bitmap_size,
1432                                                      GFP_KERNEL);
1433         }
1434         kfree(cmd);
1435
1436         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE, sizeof(*cmd));
1437         if (!cmd)
1438                 return -ENOMEM;
1439
1440         cmd->pd_count = dev->attr.max_pd - dev->attr.max_dpp_pds;
1441         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1442         if (status)
1443                 goto mbx_err;
1444         rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd;
1445         if (rsp->pd_count) {
1446                 dev->pd_mgr->pd_norm_start = rsp->dpp_page_pdid &
1447                                         OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK;
1448                 dev->pd_mgr->max_normal_pd = rsp->pd_count;
1449                 pd_bitmap_size = BITS_TO_LONGS(rsp->pd_count) * sizeof(long);
1450                 dev->pd_mgr->pd_norm_bitmap = kzalloc(pd_bitmap_size,
1451                                                       GFP_KERNEL);
1452         }
1453
1454         if (dev->pd_mgr->pd_norm_bitmap || dev->pd_mgr->pd_dpp_bitmap) {
1455                 /* Enable PD resource manager */
1456                 dev->pd_mgr->pd_prealloc_valid = true;
1457         } else {
1458                 return -ENOMEM;
1459         }
1460 mbx_err:
1461         kfree(cmd);
1462         return status;
1463 }
1464
1465 static void ocrdma_mbx_dealloc_pd_range(struct ocrdma_dev *dev)
1466 {
1467         struct ocrdma_dealloc_pd_range *cmd;
1468
1469         /* return normal PDs to firmware */
1470         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE, sizeof(*cmd));
1471         if (!cmd)
1472                 goto mbx_err;
1473
1474         if (dev->pd_mgr->max_normal_pd) {
1475                 cmd->start_pd_id = dev->pd_mgr->pd_norm_start;
1476                 cmd->pd_count = dev->pd_mgr->max_normal_pd;
1477                 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1478         }
1479
1480         if (dev->pd_mgr->max_dpp_pd) {
1481                 kfree(cmd);
1482                 /* return DPP PDs to firmware */
1483                 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE,
1484                                           sizeof(*cmd));
1485                 if (!cmd)
1486                         goto mbx_err;
1487
1488                 cmd->start_pd_id = dev->pd_mgr->pd_dpp_start;
1489                 cmd->pd_count = dev->pd_mgr->max_dpp_pd;
1490                 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1491         }
1492 mbx_err:
1493         kfree(cmd);
1494 }
1495
1496 void ocrdma_alloc_pd_pool(struct ocrdma_dev *dev)
1497 {
1498         int status;
1499
1500         dev->pd_mgr = kzalloc(sizeof(struct ocrdma_pd_resource_mgr),
1501                               GFP_KERNEL);
1502         if (!dev->pd_mgr) {
1503                 pr_err("%s(%d)Memory allocation failure.\n", __func__, dev->id);
1504                 return;
1505         }
1506         status = ocrdma_mbx_alloc_pd_range(dev);
1507         if (status) {
1508                 pr_err("%s(%d) Unable to initialize PD pool, using default.\n",
1509                          __func__, dev->id);
1510         }
1511 }
1512
1513 static void ocrdma_free_pd_pool(struct ocrdma_dev *dev)
1514 {
1515         ocrdma_mbx_dealloc_pd_range(dev);
1516         kfree(dev->pd_mgr->pd_norm_bitmap);
1517         kfree(dev->pd_mgr->pd_dpp_bitmap);
1518         kfree(dev->pd_mgr);
1519 }
1520
1521 static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1522                                int *num_pages, int *page_size)
1523 {
1524         int i;
1525         int mem_size;
1526
1527         *num_entries = roundup_pow_of_two(*num_entries);
1528         mem_size = *num_entries * entry_size;
1529         /* find the possible lowest possible multiplier */
1530         for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1531                 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1532                         break;
1533         }
1534         if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1535                 return -EINVAL;
1536         mem_size = roundup(mem_size,
1537                        ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1538         *num_pages =
1539             mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1540         *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1541         *num_entries = mem_size / entry_size;
1542         return 0;
1543 }
1544
1545 static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1546 {
1547         int i;
1548         int status = 0;
1549         int max_ah;
1550         struct ocrdma_create_ah_tbl *cmd;
1551         struct ocrdma_create_ah_tbl_rsp *rsp;
1552         struct pci_dev *pdev = dev->nic_info.pdev;
1553         dma_addr_t pa;
1554         struct ocrdma_pbe *pbes;
1555
1556         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1557         if (!cmd)
1558                 return status;
1559
1560         max_ah = OCRDMA_MAX_AH;
1561         dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1562
1563         /* number of PBEs in PBL */
1564         cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1565                                 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1566                                 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1567
1568         /* page size */
1569         for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1570                 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1571                         break;
1572         }
1573         cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1574                                 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1575
1576         /* ah_entry size */
1577         cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1578                                 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1579                                 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1580
1581         dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1582                                                 &dev->av_tbl.pbl.pa,
1583                                                 GFP_KERNEL);
1584         if (dev->av_tbl.pbl.va == NULL)
1585                 goto mem_err;
1586
1587         dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1588                                             &pa, GFP_KERNEL);
1589         if (dev->av_tbl.va == NULL)
1590                 goto mem_err_ah;
1591         dev->av_tbl.pa = pa;
1592         dev->av_tbl.num_ah = max_ah;
1593         memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1594
1595         pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1596         for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1597                 pbes[i].pa_lo = (u32)cpu_to_le32(pa & 0xffffffff);
1598                 pbes[i].pa_hi = (u32)cpu_to_le32(upper_32_bits(pa));
1599                 pa += PAGE_SIZE;
1600         }
1601         cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1602         cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1603         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1604         if (status)
1605                 goto mbx_err;
1606         rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1607         dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1608         kfree(cmd);
1609         return 0;
1610
1611 mbx_err:
1612         dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1613                           dev->av_tbl.pa);
1614         dev->av_tbl.va = NULL;
1615 mem_err_ah:
1616         dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1617                           dev->av_tbl.pbl.pa);
1618         dev->av_tbl.pbl.va = NULL;
1619         dev->av_tbl.size = 0;
1620 mem_err:
1621         kfree(cmd);
1622         return status;
1623 }
1624
1625 static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1626 {
1627         struct ocrdma_delete_ah_tbl *cmd;
1628         struct pci_dev *pdev = dev->nic_info.pdev;
1629
1630         if (dev->av_tbl.va == NULL)
1631                 return;
1632
1633         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1634         if (!cmd)
1635                 return;
1636         cmd->ahid = dev->av_tbl.ahid;
1637
1638         ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1639         dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1640                           dev->av_tbl.pa);
1641         dev->av_tbl.va = NULL;
1642         dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1643                           dev->av_tbl.pbl.pa);
1644         kfree(cmd);
1645 }
1646
1647 /* Multiple CQs uses the EQ. This routine returns least used
1648  * EQ to associate with CQ. This will distributes the interrupt
1649  * processing and CPU load to associated EQ, vector and so to that CPU.
1650  */
1651 static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1652 {
1653         int i, selected_eq = 0, cq_cnt = 0;
1654         u16 eq_id;
1655
1656         mutex_lock(&dev->dev_lock);
1657         cq_cnt = dev->eq_tbl[0].cq_cnt;
1658         eq_id = dev->eq_tbl[0].q.id;
1659         /* find the EQ which is has the least number of
1660          * CQs associated with it.
1661          */
1662         for (i = 0; i < dev->eq_cnt; i++) {
1663                 if (dev->eq_tbl[i].cq_cnt < cq_cnt) {
1664                         cq_cnt = dev->eq_tbl[i].cq_cnt;
1665                         eq_id = dev->eq_tbl[i].q.id;
1666                         selected_eq = i;
1667                 }
1668         }
1669         dev->eq_tbl[selected_eq].cq_cnt += 1;
1670         mutex_unlock(&dev->dev_lock);
1671         return eq_id;
1672 }
1673
1674 static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1675 {
1676         int i;
1677
1678         mutex_lock(&dev->dev_lock);
1679         i = ocrdma_get_eq_table_index(dev, eq_id);
1680         if (i == -EINVAL)
1681                 BUG();
1682         dev->eq_tbl[i].cq_cnt -= 1;
1683         mutex_unlock(&dev->dev_lock);
1684 }
1685
1686 int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
1687                          int entries, int dpp_cq, u16 pd_id)
1688 {
1689         int status = -ENOMEM; int max_hw_cqe;
1690         struct pci_dev *pdev = dev->nic_info.pdev;
1691         struct ocrdma_create_cq *cmd;
1692         struct ocrdma_create_cq_rsp *rsp;
1693         u32 hw_pages, cqe_size, page_size, cqe_count;
1694
1695         if (entries > dev->attr.max_cqe) {
1696                 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1697                        __func__, dev->id, dev->attr.max_cqe, entries);
1698                 return -EINVAL;
1699         }
1700         if (dpp_cq && (ocrdma_get_asic_type(dev) != OCRDMA_ASIC_GEN_SKH_R))
1701                 return -EINVAL;
1702
1703         if (dpp_cq) {
1704                 cq->max_hw_cqe = 1;
1705                 max_hw_cqe = 1;
1706                 cqe_size = OCRDMA_DPP_CQE_SIZE;
1707                 hw_pages = 1;
1708         } else {
1709                 cq->max_hw_cqe = dev->attr.max_cqe;
1710                 max_hw_cqe = dev->attr.max_cqe;
1711                 cqe_size = sizeof(struct ocrdma_cqe);
1712                 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1713         }
1714
1715         cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1716
1717         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1718         if (!cmd)
1719                 return -ENOMEM;
1720         ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1721                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1722         cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1723         if (!cq->va) {
1724                 status = -ENOMEM;
1725                 goto mem_err;
1726         }
1727         memset(cq->va, 0, cq->len);
1728         page_size = cq->len / hw_pages;
1729         cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1730                                         OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1731         cmd->cmd.pgsz_pgcnt |= hw_pages;
1732         cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1733
1734         cq->eqn = ocrdma_bind_eq(dev);
1735         cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER3;
1736         cqe_count = cq->len / cqe_size;
1737         cq->cqe_cnt = cqe_count;
1738         if (cqe_count > 1024) {
1739                 /* Set cnt to 3 to indicate more than 1024 cq entries */
1740                 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
1741         } else {
1742                 u8 count = 0;
1743                 switch (cqe_count) {
1744                 case 256:
1745                         count = 0;
1746                         break;
1747                 case 512:
1748                         count = 1;
1749                         break;
1750                 case 1024:
1751                         count = 2;
1752                         break;
1753                 default:
1754                         goto mbx_err;
1755                 }
1756                 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1757         }
1758         /* shared eq between all the consumer cqs. */
1759         cmd->cmd.eqn = cq->eqn;
1760         if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1761                 if (dpp_cq)
1762                         cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1763                                 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1764                 cq->phase_change = false;
1765                 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size);
1766         } else {
1767                 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size) - 1;
1768                 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1769                 cq->phase_change = true;
1770         }
1771
1772         /* pd_id valid only for v3 */
1773         cmd->cmd.pdid_cqecnt |= (pd_id <<
1774                 OCRDMA_CREATE_CQ_CMD_PDID_SHIFT);
1775         ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1776         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1777         if (status)
1778                 goto mbx_err;
1779
1780         rsp = (struct ocrdma_create_cq_rsp *)cmd;
1781         cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1782         kfree(cmd);
1783         return 0;
1784 mbx_err:
1785         ocrdma_unbind_eq(dev, cq->eqn);
1786         dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1787 mem_err:
1788         kfree(cmd);
1789         return status;
1790 }
1791
1792 int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1793 {
1794         int status = -ENOMEM;
1795         struct ocrdma_destroy_cq *cmd;
1796
1797         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1798         if (!cmd)
1799                 return status;
1800         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1801                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1802
1803         cmd->bypass_flush_qid |=
1804             (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1805             OCRDMA_DESTROY_CQ_QID_MASK;
1806
1807         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1808         ocrdma_unbind_eq(dev, cq->eqn);
1809         dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
1810         kfree(cmd);
1811         return status;
1812 }
1813
1814 int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1815                           u32 pdid, int addr_check)
1816 {
1817         int status = -ENOMEM;
1818         struct ocrdma_alloc_lkey *cmd;
1819         struct ocrdma_alloc_lkey_rsp *rsp;
1820
1821         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1822         if (!cmd)
1823                 return status;
1824         cmd->pdid = pdid;
1825         cmd->pbl_sz_flags |= addr_check;
1826         cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1827         cmd->pbl_sz_flags |=
1828             (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1829         cmd->pbl_sz_flags |=
1830             (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1831         cmd->pbl_sz_flags |=
1832             (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1833         cmd->pbl_sz_flags |=
1834             (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1835         cmd->pbl_sz_flags |=
1836             (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1837
1838         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1839         if (status)
1840                 goto mbx_err;
1841         rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1842         hwmr->lkey = rsp->lrkey;
1843 mbx_err:
1844         kfree(cmd);
1845         return status;
1846 }
1847
1848 int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1849 {
1850         int status = -ENOMEM;
1851         struct ocrdma_dealloc_lkey *cmd;
1852
1853         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1854         if (!cmd)
1855                 return -ENOMEM;
1856         cmd->lkey = lkey;
1857         cmd->rsvd_frmr = fr_mr ? 1 : 0;
1858         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1859         if (status)
1860                 goto mbx_err;
1861 mbx_err:
1862         kfree(cmd);
1863         return status;
1864 }
1865
1866 static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1867                              u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1868 {
1869         int status = -ENOMEM;
1870         int i;
1871         struct ocrdma_reg_nsmr *cmd;
1872         struct ocrdma_reg_nsmr_rsp *rsp;
1873
1874         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1875         if (!cmd)
1876                 return -ENOMEM;
1877         cmd->num_pbl_pdid =
1878             pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
1879         cmd->fr_mr = hwmr->fr_mr;
1880
1881         cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1882                                     OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1883         cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1884                                     OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1885         cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1886                                     OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1887         cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1888                                     OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1889         cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1890                                     OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1891         cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1892
1893         cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1894         cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1895                                         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1896         cmd->totlen_low = hwmr->len;
1897         cmd->totlen_high = upper_32_bits(hwmr->len);
1898         cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1899         cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1900         cmd->va_loaddr = (u32) hwmr->va;
1901         cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1902
1903         for (i = 0; i < pbl_cnt; i++) {
1904                 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1905                 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
1906         }
1907         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1908         if (status)
1909                 goto mbx_err;
1910         rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
1911         hwmr->lkey = rsp->lrkey;
1912 mbx_err:
1913         kfree(cmd);
1914         return status;
1915 }
1916
1917 static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
1918                                   struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
1919                                   u32 pbl_offset, u32 last)
1920 {
1921         int status = -ENOMEM;
1922         int i;
1923         struct ocrdma_reg_nsmr_cont *cmd;
1924
1925         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
1926         if (!cmd)
1927                 return -ENOMEM;
1928         cmd->lrkey = hwmr->lkey;
1929         cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
1930             (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
1931         cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
1932
1933         for (i = 0; i < pbl_cnt; i++) {
1934                 cmd->pbl[i].lo =
1935                     (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
1936                 cmd->pbl[i].hi =
1937                     upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
1938         }
1939         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1940         if (status)
1941                 goto mbx_err;
1942 mbx_err:
1943         kfree(cmd);
1944         return status;
1945 }
1946
1947 int ocrdma_reg_mr(struct ocrdma_dev *dev,
1948                   struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
1949 {
1950         int status;
1951         u32 last = 0;
1952         u32 cur_pbl_cnt, pbl_offset;
1953         u32 pending_pbl_cnt = hwmr->num_pbls;
1954
1955         pbl_offset = 0;
1956         cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1957         if (cur_pbl_cnt == pending_pbl_cnt)
1958                 last = 1;
1959
1960         status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
1961                                    cur_pbl_cnt, hwmr->pbe_size, last);
1962         if (status) {
1963                 pr_err("%s() status=%d\n", __func__, status);
1964                 return status;
1965         }
1966         /* if there is no more pbls to register then exit. */
1967         if (last)
1968                 return 0;
1969
1970         while (!last) {
1971                 pbl_offset += cur_pbl_cnt;
1972                 pending_pbl_cnt -= cur_pbl_cnt;
1973                 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1974                 /* if we reach the end of the pbls, then need to set the last
1975                  * bit, indicating no more pbls to register for this memory key.
1976                  */
1977                 if (cur_pbl_cnt == pending_pbl_cnt)
1978                         last = 1;
1979
1980                 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
1981                                                 pbl_offset, last);
1982                 if (status)
1983                         break;
1984         }
1985         if (status)
1986                 pr_err("%s() err. status=%d\n", __func__, status);
1987
1988         return status;
1989 }
1990
1991 bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1992 {
1993         struct ocrdma_qp *tmp;
1994         bool found = false;
1995         list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
1996                 if (qp == tmp) {
1997                         found = true;
1998                         break;
1999                 }
2000         }
2001         return found;
2002 }
2003
2004 bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
2005 {
2006         struct ocrdma_qp *tmp;
2007         bool found = false;
2008         list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
2009                 if (qp == tmp) {
2010                         found = true;
2011                         break;
2012                 }
2013         }
2014         return found;
2015 }
2016
2017 void ocrdma_flush_qp(struct ocrdma_qp *qp)
2018 {
2019         bool found;
2020         unsigned long flags;
2021
2022         spin_lock_irqsave(&qp->dev->flush_q_lock, flags);
2023         found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
2024         if (!found)
2025                 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
2026         if (!qp->srq) {
2027                 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
2028                 if (!found)
2029                         list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
2030         }
2031         spin_unlock_irqrestore(&qp->dev->flush_q_lock, flags);
2032 }
2033
2034 static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp)
2035 {
2036         qp->sq.head = 0;
2037         qp->sq.tail = 0;
2038         qp->rq.head = 0;
2039         qp->rq.tail = 0;
2040 }
2041
2042 int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
2043                            enum ib_qp_state *old_ib_state)
2044 {
2045         unsigned long flags;
2046         int status = 0;
2047         enum ocrdma_qp_state new_state;
2048         new_state = get_ocrdma_qp_state(new_ib_state);
2049
2050         /* sync with wqe and rqe posting */
2051         spin_lock_irqsave(&qp->q_lock, flags);
2052
2053         if (old_ib_state)
2054                 *old_ib_state = get_ibqp_state(qp->state);
2055         if (new_state == qp->state) {
2056                 spin_unlock_irqrestore(&qp->q_lock, flags);
2057                 return 1;
2058         }
2059
2060
2061         if (new_state == OCRDMA_QPS_INIT) {
2062                 ocrdma_init_hwq_ptr(qp);
2063                 ocrdma_del_flush_qp(qp);
2064         } else if (new_state == OCRDMA_QPS_ERR) {
2065                 ocrdma_flush_qp(qp);
2066         }
2067
2068         qp->state = new_state;
2069
2070         spin_unlock_irqrestore(&qp->q_lock, flags);
2071         return status;
2072 }
2073
2074 static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
2075 {
2076         u32 flags = 0;
2077         if (qp->cap_flags & OCRDMA_QP_INB_RD)
2078                 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
2079         if (qp->cap_flags & OCRDMA_QP_INB_WR)
2080                 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
2081         if (qp->cap_flags & OCRDMA_QP_MW_BIND)
2082                 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
2083         if (qp->cap_flags & OCRDMA_QP_LKEY0)
2084                 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
2085         if (qp->cap_flags & OCRDMA_QP_FAST_REG)
2086                 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
2087         return flags;
2088 }
2089
2090 static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
2091                                         struct ib_qp_init_attr *attrs,
2092                                         struct ocrdma_qp *qp)
2093 {
2094         int status;
2095         u32 len, hw_pages, hw_page_size;
2096         dma_addr_t pa;
2097         struct ocrdma_dev *dev = qp->dev;
2098         struct pci_dev *pdev = dev->nic_info.pdev;
2099         u32 max_wqe_allocated;
2100         u32 max_sges = attrs->cap.max_send_sge;
2101
2102         /* QP1 may exceed 127 */
2103         max_wqe_allocated = min_t(u32, attrs->cap.max_send_wr + 1,
2104                                 dev->attr.max_wqe);
2105
2106         status = ocrdma_build_q_conf(&max_wqe_allocated,
2107                 dev->attr.wqe_size, &hw_pages, &hw_page_size);
2108         if (status) {
2109                 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
2110                        max_wqe_allocated);
2111                 return -EINVAL;
2112         }
2113         qp->sq.max_cnt = max_wqe_allocated;
2114         len = (hw_pages * hw_page_size);
2115
2116         qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2117         if (!qp->sq.va)
2118                 return -EINVAL;
2119         memset(qp->sq.va, 0, len);
2120         qp->sq.len = len;
2121         qp->sq.pa = pa;
2122         qp->sq.entry_size = dev->attr.wqe_size;
2123         ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
2124
2125         cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2126                                 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
2127         cmd->num_wq_rq_pages |= (hw_pages <<
2128                                  OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
2129             OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
2130         cmd->max_sge_send_write |= (max_sges <<
2131                                     OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
2132             OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
2133         cmd->max_sge_send_write |= (max_sges <<
2134                                     OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
2135                                         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
2136         cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
2137                              OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
2138                                 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
2139         cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
2140                               OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
2141                                 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
2142         return 0;
2143 }
2144
2145 static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
2146                                         struct ib_qp_init_attr *attrs,
2147                                         struct ocrdma_qp *qp)
2148 {
2149         int status;
2150         u32 len, hw_pages, hw_page_size;
2151         dma_addr_t pa = 0;
2152         struct ocrdma_dev *dev = qp->dev;
2153         struct pci_dev *pdev = dev->nic_info.pdev;
2154         u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
2155
2156         status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
2157                                      &hw_pages, &hw_page_size);
2158         if (status) {
2159                 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
2160                        attrs->cap.max_recv_wr + 1);
2161                 return status;
2162         }
2163         qp->rq.max_cnt = max_rqe_allocated;
2164         len = (hw_pages * hw_page_size);
2165
2166         qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2167         if (!qp->rq.va)
2168                 return -ENOMEM;
2169         memset(qp->rq.va, 0, len);
2170         qp->rq.pa = pa;
2171         qp->rq.len = len;
2172         qp->rq.entry_size = dev->attr.rqe_size;
2173
2174         ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2175         cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
2176                 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
2177         cmd->num_wq_rq_pages |=
2178             (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
2179             OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
2180         cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
2181                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
2182                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
2183         cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
2184                                 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
2185                                 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
2186         cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
2187                         OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
2188                         OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
2189         return 0;
2190 }
2191
2192 static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
2193                                          struct ocrdma_pd *pd,
2194                                          struct ocrdma_qp *qp,
2195                                          u8 enable_dpp_cq, u16 dpp_cq_id)
2196 {
2197         pd->num_dpp_qp--;
2198         qp->dpp_enabled = true;
2199         cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2200         if (!enable_dpp_cq)
2201                 return;
2202         cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2203         cmd->dpp_credits_cqid = dpp_cq_id;
2204         cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
2205                                         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
2206 }
2207
2208 static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
2209                                         struct ocrdma_qp *qp)
2210 {
2211         struct ocrdma_dev *dev = qp->dev;
2212         struct pci_dev *pdev = dev->nic_info.pdev;
2213         dma_addr_t pa = 0;
2214         int ird_page_size = dev->attr.ird_page_size;
2215         int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
2216         struct ocrdma_hdr_wqe *rqe;
2217         int i  = 0;
2218
2219         if (dev->attr.ird == 0)
2220                 return 0;
2221
2222         qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
2223                                         &pa, GFP_KERNEL);
2224         if (!qp->ird_q_va)
2225                 return -ENOMEM;
2226         memset(qp->ird_q_va, 0, ird_q_len);
2227         ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
2228                              pa, ird_page_size);
2229         for (; i < ird_q_len / dev->attr.rqe_size; i++) {
2230                 rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va +
2231                         (i * dev->attr.rqe_size));
2232                 rqe->cw = 0;
2233                 rqe->cw |= 2;
2234                 rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
2235                 rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT);
2236                 rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT);
2237         }
2238         return 0;
2239 }
2240
2241 static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
2242                                      struct ocrdma_qp *qp,
2243                                      struct ib_qp_init_attr *attrs,
2244                                      u16 *dpp_offset, u16 *dpp_credit_lmt)
2245 {
2246         u32 max_wqe_allocated, max_rqe_allocated;
2247         qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
2248         qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
2249         qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
2250         qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
2251         qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
2252         qp->dpp_enabled = false;
2253         if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
2254                 qp->dpp_enabled = true;
2255                 *dpp_credit_lmt = (rsp->dpp_response &
2256                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
2257                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
2258                 *dpp_offset = (rsp->dpp_response &
2259                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
2260                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
2261         }
2262         max_wqe_allocated =
2263                 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
2264         max_wqe_allocated = 1 << max_wqe_allocated;
2265         max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
2266
2267         qp->sq.max_cnt = max_wqe_allocated;
2268         qp->sq.max_wqe_idx = max_wqe_allocated - 1;
2269
2270         if (!attrs->srq) {
2271                 qp->rq.max_cnt = max_rqe_allocated;
2272                 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
2273         }
2274 }
2275
2276 int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
2277                          u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
2278                          u16 *dpp_credit_lmt)
2279 {
2280         int status = -ENOMEM;
2281         u32 flags = 0;
2282         struct ocrdma_dev *dev = qp->dev;
2283         struct ocrdma_pd *pd = qp->pd;
2284         struct pci_dev *pdev = dev->nic_info.pdev;
2285         struct ocrdma_cq *cq;
2286         struct ocrdma_create_qp_req *cmd;
2287         struct ocrdma_create_qp_rsp *rsp;
2288         int qptype;
2289
2290         switch (attrs->qp_type) {
2291         case IB_QPT_GSI:
2292                 qptype = OCRDMA_QPT_GSI;
2293                 break;
2294         case IB_QPT_RC:
2295                 qptype = OCRDMA_QPT_RC;
2296                 break;
2297         case IB_QPT_UD:
2298                 qptype = OCRDMA_QPT_UD;
2299                 break;
2300         default:
2301                 return -EINVAL;
2302         }
2303
2304         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
2305         if (!cmd)
2306                 return status;
2307         cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
2308                                                 OCRDMA_CREATE_QP_REQ_QPT_MASK;
2309         status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
2310         if (status)
2311                 goto sq_err;
2312
2313         if (attrs->srq) {
2314                 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
2315                 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
2316                 cmd->rq_addr[0].lo = srq->id;
2317                 qp->srq = srq;
2318         } else {
2319                 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2320                 if (status)
2321                         goto rq_err;
2322         }
2323
2324         status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2325         if (status)
2326                 goto mbx_err;
2327
2328         cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2329                                 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2330
2331         flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2332
2333         cmd->max_sge_recv_flags |= flags;
2334         cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2335                              OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2336                                 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2337         cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2338                              OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2339                                 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2340         cq = get_ocrdma_cq(attrs->send_cq);
2341         cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2342                                 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2343         qp->sq_cq = cq;
2344         cq = get_ocrdma_cq(attrs->recv_cq);
2345         cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2346                                 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2347         qp->rq_cq = cq;
2348
2349         if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
2350             (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) {
2351                 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2352                                              dpp_cq_id);
2353         }
2354
2355         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2356         if (status)
2357                 goto mbx_err;
2358         rsp = (struct ocrdma_create_qp_rsp *)cmd;
2359         ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2360         qp->state = OCRDMA_QPS_RST;
2361         kfree(cmd);
2362         return 0;
2363 mbx_err:
2364         if (qp->rq.va)
2365                 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2366 rq_err:
2367         pr_err("%s(%d) rq_err\n", __func__, dev->id);
2368         dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2369 sq_err:
2370         pr_err("%s(%d) sq_err\n", __func__, dev->id);
2371         kfree(cmd);
2372         return status;
2373 }
2374
2375 int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2376                         struct ocrdma_qp_params *param)
2377 {
2378         int status = -ENOMEM;
2379         struct ocrdma_query_qp *cmd;
2380         struct ocrdma_query_qp_rsp *rsp;
2381
2382         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd));
2383         if (!cmd)
2384                 return status;
2385         cmd->qp_id = qp->id;
2386         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2387         if (status)
2388                 goto mbx_err;
2389         rsp = (struct ocrdma_query_qp_rsp *)cmd;
2390         memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2391 mbx_err:
2392         kfree(cmd);
2393         return status;
2394 }
2395
2396 static int ocrdma_set_av_params(struct ocrdma_qp *qp,
2397                                 struct ocrdma_modify_qp *cmd,
2398                                 struct ib_qp_attr *attrs,
2399                                 int attr_mask)
2400 {
2401         int status;
2402         struct ib_ah_attr *ah_attr = &attrs->ah_attr;
2403         union ib_gid sgid, zgid;
2404         u32 vlan_id;
2405         u8 mac_addr[6];
2406
2407         if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
2408                 return -EINVAL;
2409         if (atomic_cmpxchg(&qp->dev->update_sl, 1, 0))
2410                 ocrdma_init_service_level(qp->dev);
2411         cmd->params.tclass_sq_psn |=
2412             (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2413         cmd->params.rnt_rc_sl_fl |=
2414             (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2415         cmd->params.rnt_rc_sl_fl |= (ah_attr->sl << OCRDMA_QP_PARAMS_SL_SHIFT);
2416         cmd->params.hop_lmt_rq_psn |=
2417             (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2418         cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2419         memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2420                sizeof(cmd->params.dgid));
2421         status = ocrdma_query_gid(&qp->dev->ibdev, 1,
2422                         ah_attr->grh.sgid_index, &sgid);
2423         if (status)
2424                 return status;
2425
2426         memset(&zgid, 0, sizeof(zgid));
2427         if (!memcmp(&sgid, &zgid, sizeof(zgid)))
2428                 return -EINVAL;
2429
2430         qp->sgid_idx = ah_attr->grh.sgid_index;
2431         memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
2432         ocrdma_resolve_dmac(qp->dev, ah_attr, &mac_addr[0]);
2433         cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2434                                 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2435         /* convert them to LE format. */
2436         ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2437         ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2438         cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
2439         if (attr_mask & IB_QP_VID) {
2440                 vlan_id = attrs->vlan_id;
2441                 cmd->params.vlan_dmac_b4_to_b5 |=
2442                     vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2443                 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2444                 cmd->params.rnt_rc_sl_fl |=
2445                         (qp->dev->sl & 0x07) << OCRDMA_QP_PARAMS_SL_SHIFT;
2446         }
2447         return 0;
2448 }
2449
2450 static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2451                                 struct ocrdma_modify_qp *cmd,
2452                                 struct ib_qp_attr *attrs, int attr_mask)
2453 {
2454         int status = 0;
2455
2456         if (attr_mask & IB_QP_PKEY_INDEX) {
2457                 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2458                                             OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2459                 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2460         }
2461         if (attr_mask & IB_QP_QKEY) {
2462                 qp->qkey = attrs->qkey;
2463                 cmd->params.qkey = attrs->qkey;
2464                 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2465         }
2466         if (attr_mask & IB_QP_AV) {
2467                 status = ocrdma_set_av_params(qp, cmd, attrs, attr_mask);
2468                 if (status)
2469                         return status;
2470         } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
2471                 /* set the default mac address for UD, GSI QPs */
2472                 cmd->params.dmac_b0_to_b3 = qp->dev->nic_info.mac_addr[0] |
2473                         (qp->dev->nic_info.mac_addr[1] << 8) |
2474                         (qp->dev->nic_info.mac_addr[2] << 16) |
2475                         (qp->dev->nic_info.mac_addr[3] << 24);
2476                 cmd->params.vlan_dmac_b4_to_b5 = qp->dev->nic_info.mac_addr[4] |
2477                                         (qp->dev->nic_info.mac_addr[5] << 8);
2478         }
2479         if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2480             attrs->en_sqd_async_notify) {
2481                 cmd->params.max_sge_recv_flags |=
2482                         OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2483                 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2484         }
2485         if (attr_mask & IB_QP_DEST_QPN) {
2486                 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2487                                 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2488                 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2489         }
2490         if (attr_mask & IB_QP_PATH_MTU) {
2491                 if (attrs->path_mtu < IB_MTU_256 ||
2492                     attrs->path_mtu > IB_MTU_4096) {
2493                         status = -EINVAL;
2494                         goto pmtu_err;
2495                 }
2496                 cmd->params.path_mtu_pkey_indx |=
2497                     (ib_mtu_enum_to_int(attrs->path_mtu) <<
2498                      OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2499                     OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2500                 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2501         }
2502         if (attr_mask & IB_QP_TIMEOUT) {
2503                 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2504                     OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2505                 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2506         }
2507         if (attr_mask & IB_QP_RETRY_CNT) {
2508                 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2509                                       OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2510                     OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2511                 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2512         }
2513         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2514                 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2515                                       OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2516                     OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2517                 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2518         }
2519         if (attr_mask & IB_QP_RNR_RETRY) {
2520                 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2521                         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2522                         & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2523                 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2524         }
2525         if (attr_mask & IB_QP_SQ_PSN) {
2526                 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2527                 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2528         }
2529         if (attr_mask & IB_QP_RQ_PSN) {
2530                 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2531                 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2532         }
2533         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2534                 if (attrs->max_rd_atomic > qp->dev->attr.max_ord_per_qp) {
2535                         status = -EINVAL;
2536                         goto pmtu_err;
2537                 }
2538                 qp->max_ord = attrs->max_rd_atomic;
2539                 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2540         }
2541         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2542                 if (attrs->max_dest_rd_atomic > qp->dev->attr.max_ird_per_qp) {
2543                         status = -EINVAL;
2544                         goto pmtu_err;
2545                 }
2546                 qp->max_ird = attrs->max_dest_rd_atomic;
2547                 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2548         }
2549         cmd->params.max_ord_ird = (qp->max_ord <<
2550                                 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2551                                 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2552 pmtu_err:
2553         return status;
2554 }
2555
2556 int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2557                          struct ib_qp_attr *attrs, int attr_mask)
2558 {
2559         int status = -ENOMEM;
2560         struct ocrdma_modify_qp *cmd;
2561
2562         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2563         if (!cmd)
2564                 return status;
2565
2566         cmd->params.id = qp->id;
2567         cmd->flags = 0;
2568         if (attr_mask & IB_QP_STATE) {
2569                 cmd->params.max_sge_recv_flags |=
2570                     (get_ocrdma_qp_state(attrs->qp_state) <<
2571                      OCRDMA_QP_PARAMS_STATE_SHIFT) &
2572                     OCRDMA_QP_PARAMS_STATE_MASK;
2573                 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
2574         } else {
2575                 cmd->params.max_sge_recv_flags |=
2576                     (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2577                     OCRDMA_QP_PARAMS_STATE_MASK;
2578         }
2579
2580         status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask);
2581         if (status)
2582                 goto mbx_err;
2583         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2584         if (status)
2585                 goto mbx_err;
2586
2587 mbx_err:
2588         kfree(cmd);
2589         return status;
2590 }
2591
2592 int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2593 {
2594         int status = -ENOMEM;
2595         struct ocrdma_destroy_qp *cmd;
2596         struct pci_dev *pdev = dev->nic_info.pdev;
2597
2598         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2599         if (!cmd)
2600                 return status;
2601         cmd->qp_id = qp->id;
2602         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2603         if (status)
2604                 goto mbx_err;
2605
2606 mbx_err:
2607         kfree(cmd);
2608         if (qp->sq.va)
2609                 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2610         if (!qp->srq && qp->rq.va)
2611                 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2612         if (qp->dpp_enabled)
2613                 qp->pd->num_dpp_qp++;
2614         return status;
2615 }
2616
2617 int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
2618                           struct ib_srq_init_attr *srq_attr,
2619                           struct ocrdma_pd *pd)
2620 {
2621         int status = -ENOMEM;
2622         int hw_pages, hw_page_size;
2623         int len;
2624         struct ocrdma_create_srq_rsp *rsp;
2625         struct ocrdma_create_srq *cmd;
2626         dma_addr_t pa;
2627         struct pci_dev *pdev = dev->nic_info.pdev;
2628         u32 max_rqe_allocated;
2629
2630         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2631         if (!cmd)
2632                 return status;
2633
2634         cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2635         max_rqe_allocated = srq_attr->attr.max_wr + 1;
2636         status = ocrdma_build_q_conf(&max_rqe_allocated,
2637                                 dev->attr.rqe_size,
2638                                 &hw_pages, &hw_page_size);
2639         if (status) {
2640                 pr_err("%s() req. max_wr=0x%x\n", __func__,
2641                        srq_attr->attr.max_wr);
2642                 status = -EINVAL;
2643                 goto ret;
2644         }
2645         len = hw_pages * hw_page_size;
2646         srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2647         if (!srq->rq.va) {
2648                 status = -ENOMEM;
2649                 goto ret;
2650         }
2651         ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2652
2653         srq->rq.entry_size = dev->attr.rqe_size;
2654         srq->rq.pa = pa;
2655         srq->rq.len = len;
2656         srq->rq.max_cnt = max_rqe_allocated;
2657
2658         cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2659         cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2660                                 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2661
2662         cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2663                 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2664         cmd->pages_rqe_sz |= (dev->attr.rqe_size
2665                 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2666                 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2667         cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2668
2669         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2670         if (status)
2671                 goto mbx_err;
2672         rsp = (struct ocrdma_create_srq_rsp *)cmd;
2673         srq->id = rsp->id;
2674         srq->rq.dbid = rsp->id;
2675         max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2676                 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2677                 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2678         max_rqe_allocated = (1 << max_rqe_allocated);
2679         srq->rq.max_cnt = max_rqe_allocated;
2680         srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2681         srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2682                 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2683                 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2684         goto ret;
2685 mbx_err:
2686         dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2687 ret:
2688         kfree(cmd);
2689         return status;
2690 }
2691
2692 int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2693 {
2694         int status = -ENOMEM;
2695         struct ocrdma_modify_srq *cmd;
2696         struct ocrdma_pd *pd = srq->pd;
2697         struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2698
2699         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_SRQ, sizeof(*cmd));
2700         if (!cmd)
2701                 return status;
2702         cmd->id = srq->id;
2703         cmd->limit_max_rqe |= srq_attr->srq_limit <<
2704             OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
2705         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2706         kfree(cmd);
2707         return status;
2708 }
2709
2710 int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2711 {
2712         int status = -ENOMEM;
2713         struct ocrdma_query_srq *cmd;
2714         struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2715
2716         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_SRQ, sizeof(*cmd));
2717         if (!cmd)
2718                 return status;
2719         cmd->id = srq->rq.dbid;
2720         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2721         if (status == 0) {
2722                 struct ocrdma_query_srq_rsp *rsp =
2723                     (struct ocrdma_query_srq_rsp *)cmd;
2724                 srq_attr->max_sge =
2725                     rsp->srq_lmt_max_sge &
2726                     OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2727                 srq_attr->max_wr =
2728                     rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2729                 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2730                     OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2731         }
2732         kfree(cmd);
2733         return status;
2734 }
2735
2736 int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2737 {
2738         int status = -ENOMEM;
2739         struct ocrdma_destroy_srq *cmd;
2740         struct pci_dev *pdev = dev->nic_info.pdev;
2741         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2742         if (!cmd)
2743                 return status;
2744         cmd->id = srq->id;
2745         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2746         if (srq->rq.va)
2747                 dma_free_coherent(&pdev->dev, srq->rq.len,
2748                                   srq->rq.va, srq->rq.pa);
2749         kfree(cmd);
2750         return status;
2751 }
2752
2753 static int ocrdma_mbx_get_dcbx_config(struct ocrdma_dev *dev, u32 ptype,
2754                                       struct ocrdma_dcbx_cfg *dcbxcfg)
2755 {
2756         int status = 0;
2757         dma_addr_t pa;
2758         struct ocrdma_mqe cmd;
2759
2760         struct ocrdma_get_dcbx_cfg_req *req = NULL;
2761         struct ocrdma_get_dcbx_cfg_rsp *rsp = NULL;
2762         struct pci_dev *pdev = dev->nic_info.pdev;
2763         struct ocrdma_mqe_sge *mqe_sge = cmd.u.nonemb_req.sge;
2764
2765         memset(&cmd, 0, sizeof(struct ocrdma_mqe));
2766         cmd.hdr.pyld_len = max_t (u32, sizeof(struct ocrdma_get_dcbx_cfg_rsp),
2767                                         sizeof(struct ocrdma_get_dcbx_cfg_req));
2768         req = dma_alloc_coherent(&pdev->dev, cmd.hdr.pyld_len, &pa, GFP_KERNEL);
2769         if (!req) {
2770                 status = -ENOMEM;
2771                 goto mem_err;
2772         }
2773
2774         cmd.hdr.spcl_sge_cnt_emb |= (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
2775                                         OCRDMA_MQE_HDR_SGE_CNT_MASK;
2776         mqe_sge->pa_lo = (u32) (pa & 0xFFFFFFFFUL);
2777         mqe_sge->pa_hi = (u32) upper_32_bits(pa);
2778         mqe_sge->len = cmd.hdr.pyld_len;
2779
2780         memset(req, 0, sizeof(struct ocrdma_get_dcbx_cfg_req));
2781         ocrdma_init_mch(&req->hdr, OCRDMA_CMD_GET_DCBX_CONFIG,
2782                         OCRDMA_SUBSYS_DCBX, cmd.hdr.pyld_len);
2783         req->param_type = ptype;
2784
2785         status = ocrdma_mbx_cmd(dev, &cmd);
2786         if (status)
2787                 goto mbx_err;
2788
2789         rsp = (struct ocrdma_get_dcbx_cfg_rsp *)req;
2790         ocrdma_le32_to_cpu(rsp, sizeof(struct ocrdma_get_dcbx_cfg_rsp));
2791         memcpy(dcbxcfg, &rsp->cfg, sizeof(struct ocrdma_dcbx_cfg));
2792
2793 mbx_err:
2794         dma_free_coherent(&pdev->dev, cmd.hdr.pyld_len, req, pa);
2795 mem_err:
2796         return status;
2797 }
2798
2799 #define OCRDMA_MAX_SERVICE_LEVEL_INDEX  0x08
2800 #define OCRDMA_DEFAULT_SERVICE_LEVEL    0x05
2801
2802 static int ocrdma_parse_dcbxcfg_rsp(struct ocrdma_dev *dev, int ptype,
2803                                     struct ocrdma_dcbx_cfg *dcbxcfg,
2804                                     u8 *srvc_lvl)
2805 {
2806         int status = -EINVAL, indx, slindx;
2807         int ventry_cnt;
2808         struct ocrdma_app_parameter *app_param;
2809         u8 valid, proto_sel;
2810         u8 app_prio, pfc_prio;
2811         u16 proto;
2812
2813         if (!(dcbxcfg->tcv_aev_opv_st & OCRDMA_DCBX_STATE_MASK)) {
2814                 pr_info("%s ocrdma%d DCBX is disabled\n",
2815                         dev_name(&dev->nic_info.pdev->dev), dev->id);
2816                 goto out;
2817         }
2818
2819         if (!ocrdma_is_enabled_and_synced(dcbxcfg->pfc_state)) {
2820                 pr_info("%s ocrdma%d priority flow control(%s) is %s%s\n",
2821                         dev_name(&dev->nic_info.pdev->dev), dev->id,
2822                         (ptype > 0 ? "operational" : "admin"),
2823                         (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_ENABLED) ?
2824                         "enabled" : "disabled",
2825                         (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_SYNC) ?
2826                         "" : ", not sync'ed");
2827                 goto out;
2828         } else {
2829                 pr_info("%s ocrdma%d priority flow control is enabled and sync'ed\n",
2830                         dev_name(&dev->nic_info.pdev->dev), dev->id);
2831         }
2832
2833         ventry_cnt = (dcbxcfg->tcv_aev_opv_st >>
2834                                 OCRDMA_DCBX_APP_ENTRY_SHIFT)
2835                                 & OCRDMA_DCBX_STATE_MASK;
2836
2837         for (indx = 0; indx < ventry_cnt; indx++) {
2838                 app_param = &dcbxcfg->app_param[indx];
2839                 valid = (app_param->valid_proto_app >>
2840                                 OCRDMA_APP_PARAM_VALID_SHIFT)
2841                                 & OCRDMA_APP_PARAM_VALID_MASK;
2842                 proto_sel = (app_param->valid_proto_app
2843                                 >>  OCRDMA_APP_PARAM_PROTO_SEL_SHIFT)
2844                                 & OCRDMA_APP_PARAM_PROTO_SEL_MASK;
2845                 proto = app_param->valid_proto_app &
2846                                 OCRDMA_APP_PARAM_APP_PROTO_MASK;
2847
2848                 if (
2849                         valid && proto == OCRDMA_APP_PROTO_ROCE &&
2850                         proto_sel == OCRDMA_PROTO_SELECT_L2) {
2851                         for (slindx = 0; slindx <
2852                                 OCRDMA_MAX_SERVICE_LEVEL_INDEX; slindx++) {
2853                                 app_prio = ocrdma_get_app_prio(
2854                                                 (u8 *)app_param->app_prio,
2855                                                 slindx);
2856                                 pfc_prio = ocrdma_get_pfc_prio(
2857                                                 (u8 *)dcbxcfg->pfc_prio,
2858                                                 slindx);
2859
2860                                 if (app_prio && pfc_prio) {
2861                                         *srvc_lvl = slindx;
2862                                         status = 0;
2863                                         goto out;
2864                                 }
2865                         }
2866                         if (slindx == OCRDMA_MAX_SERVICE_LEVEL_INDEX) {
2867                                 pr_info("%s ocrdma%d application priority not set for 0x%x protocol\n",
2868                                         dev_name(&dev->nic_info.pdev->dev),
2869                                         dev->id, proto);
2870                         }
2871                 }
2872         }
2873
2874 out:
2875         return status;
2876 }
2877
2878 void ocrdma_init_service_level(struct ocrdma_dev *dev)
2879 {
2880         int status = 0, indx;
2881         struct ocrdma_dcbx_cfg dcbxcfg;
2882         u8 srvc_lvl = OCRDMA_DEFAULT_SERVICE_LEVEL;
2883         int ptype = OCRDMA_PARAMETER_TYPE_OPER;
2884
2885         for (indx = 0; indx < 2; indx++) {
2886                 status = ocrdma_mbx_get_dcbx_config(dev, ptype, &dcbxcfg);
2887                 if (status) {
2888                         pr_err("%s(): status=%d\n", __func__, status);
2889                         ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
2890                         continue;
2891                 }
2892
2893                 status = ocrdma_parse_dcbxcfg_rsp(dev, ptype,
2894                                                   &dcbxcfg, &srvc_lvl);
2895                 if (status) {
2896                         ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
2897                         continue;
2898                 }
2899
2900                 break;
2901         }
2902
2903         if (status)
2904                 pr_info("%s ocrdma%d service level default\n",
2905                         dev_name(&dev->nic_info.pdev->dev), dev->id);
2906         else
2907                 pr_info("%s ocrdma%d service level %d\n",
2908                         dev_name(&dev->nic_info.pdev->dev), dev->id,
2909                         srvc_lvl);
2910
2911         dev->pfc_state = ocrdma_is_enabled_and_synced(dcbxcfg.pfc_state);
2912         dev->sl = srvc_lvl;
2913 }
2914
2915 int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2916 {
2917         int i;
2918         int status = -EINVAL;
2919         struct ocrdma_av *av;
2920         unsigned long flags;
2921
2922         av = dev->av_tbl.va;
2923         spin_lock_irqsave(&dev->av_tbl.lock, flags);
2924         for (i = 0; i < dev->av_tbl.num_ah; i++) {
2925                 if (av->valid == 0) {
2926                         av->valid = OCRDMA_AV_VALID;
2927                         ah->av = av;
2928                         ah->id = i;
2929                         status = 0;
2930                         break;
2931                 }
2932                 av++;
2933         }
2934         if (i == dev->av_tbl.num_ah)
2935                 status = -EAGAIN;
2936         spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2937         return status;
2938 }
2939
2940 int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2941 {
2942         unsigned long flags;
2943         spin_lock_irqsave(&dev->av_tbl.lock, flags);
2944         ah->av->valid = 0;
2945         spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2946         return 0;
2947 }
2948
2949 static int ocrdma_create_eqs(struct ocrdma_dev *dev)
2950 {
2951         int num_eq, i, status = 0;
2952         int irq;
2953         unsigned long flags = 0;
2954
2955         num_eq = dev->nic_info.msix.num_vectors -
2956                         dev->nic_info.msix.start_vector;
2957         if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
2958                 num_eq = 1;
2959                 flags = IRQF_SHARED;
2960         } else {
2961                 num_eq = min_t(u32, num_eq, num_online_cpus());
2962         }
2963
2964         if (!num_eq)
2965                 return -EINVAL;
2966
2967         dev->eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
2968         if (!dev->eq_tbl)
2969                 return -ENOMEM;
2970
2971         for (i = 0; i < num_eq; i++) {
2972                 status = ocrdma_create_eq(dev, &dev->eq_tbl[i],
2973                                         OCRDMA_EQ_LEN);
2974                 if (status) {
2975                         status = -EINVAL;
2976                         break;
2977                 }
2978                 sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d",
2979                         dev->id, i);
2980                 irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]);
2981                 status = request_irq(irq, ocrdma_irq_handler, flags,
2982                                      dev->eq_tbl[i].irq_name,
2983                                      &dev->eq_tbl[i]);
2984                 if (status)
2985                         goto done;
2986                 dev->eq_cnt += 1;
2987         }
2988         /* one eq is sufficient for data path to work */
2989         return 0;
2990 done:
2991         ocrdma_destroy_eqs(dev);
2992         return status;
2993 }
2994
2995 int ocrdma_init_hw(struct ocrdma_dev *dev)
2996 {
2997         int status;
2998
2999         /* create the eqs  */
3000         status = ocrdma_create_eqs(dev);
3001         if (status)
3002                 goto qpeq_err;
3003         status = ocrdma_create_mq(dev);
3004         if (status)
3005                 goto mq_err;
3006         status = ocrdma_mbx_query_fw_config(dev);
3007         if (status)
3008                 goto conf_err;
3009         status = ocrdma_mbx_query_dev(dev);
3010         if (status)
3011                 goto conf_err;
3012         status = ocrdma_mbx_query_fw_ver(dev);
3013         if (status)
3014                 goto conf_err;
3015         status = ocrdma_mbx_create_ah_tbl(dev);
3016         if (status)
3017                 goto conf_err;
3018         status = ocrdma_mbx_get_phy_info(dev);
3019         if (status)
3020                 goto info_attrb_err;
3021         status = ocrdma_mbx_get_ctrl_attribs(dev);
3022         if (status)
3023                 goto info_attrb_err;
3024
3025         return 0;
3026
3027 info_attrb_err:
3028         ocrdma_mbx_delete_ah_tbl(dev);
3029 conf_err:
3030         ocrdma_destroy_mq(dev);
3031 mq_err:
3032         ocrdma_destroy_eqs(dev);
3033 qpeq_err:
3034         pr_err("%s() status=%d\n", __func__, status);
3035         return status;
3036 }
3037
3038 void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
3039 {
3040         ocrdma_free_pd_pool(dev);
3041         ocrdma_mbx_delete_ah_tbl(dev);
3042
3043         /* cleanup the eqs */
3044         ocrdma_destroy_eqs(dev);
3045
3046         /* cleanup the control path */
3047         ocrdma_destroy_mq(dev);
3048 }