drivers/infiniband/hw/ocrdma/ocrdma_hw.c

   1 /*******************************************************************
   2  * This file is part of the Emulex RoCE Device Driver for          *
   3  * RoCE (RDMA over Converged Ethernet) CNA Adapters.              *
   4  * Copyright (C) 2008-2012 Emulex. All rights reserved.            *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *
  20  * Contact Information:
  21  * linux-drivers@emulex.com
  22  *
  23  * Emulex
  24  * 3333 Susan Street
  25  * Costa Mesa, CA 92626
  26  *******************************************************************/
  27
  28 #include <linux/sched.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/log2.h>
  31 #include <linux/dma-mapping.h>
  32
  33 #include <rdma/ib_verbs.h>
  34 #include <rdma/ib_user_verbs.h>
  35
  36 #include "ocrdma.h"
  37 #include "ocrdma_hw.h"
  38 #include "ocrdma_verbs.h"
  39 #include "ocrdma_ah.h"
  40
  41 enum mbx_status {
  42         OCRDMA_MBX_STATUS_FAILED                = 1,
  43         OCRDMA_MBX_STATUS_ILLEGAL_FIELD         = 3,
  44         OCRDMA_MBX_STATUS_OOR                   = 100,
  45         OCRDMA_MBX_STATUS_INVALID_PD            = 101,
  46         OCRDMA_MBX_STATUS_PD_INUSE              = 102,
  47         OCRDMA_MBX_STATUS_INVALID_CQ            = 103,
  48         OCRDMA_MBX_STATUS_INVALID_QP            = 104,
  49         OCRDMA_MBX_STATUS_INVALID_LKEY          = 105,
  50         OCRDMA_MBX_STATUS_ORD_EXCEEDS           = 106,
  51         OCRDMA_MBX_STATUS_IRD_EXCEEDS           = 107,
  52         OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS     = 108,
  53         OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS     = 109,
  54         OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS      = 110,
  55         OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS     = 111,
  56         OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS      = 112,
  57         OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE  = 113,
  58         OCRDMA_MBX_STATUS_MW_BOUND              = 114,
  59         OCRDMA_MBX_STATUS_INVALID_VA            = 115,
  60         OCRDMA_MBX_STATUS_INVALID_LENGTH        = 116,
  61         OCRDMA_MBX_STATUS_INVALID_FBO           = 117,
  62         OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS    = 118,
  63         OCRDMA_MBX_STATUS_INVALID_PBE_SIZE      = 119,
  64         OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY     = 120,
  65         OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT     = 121,
  66         OCRDMA_MBX_STATUS_INVALID_SRQ_ID        = 129,
  67         OCRDMA_MBX_STATUS_SRQ_ERROR             = 133,
  68         OCRDMA_MBX_STATUS_RQE_EXCEEDS           = 134,
  69         OCRDMA_MBX_STATUS_MTU_EXCEEDS           = 135,
  70         OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS        = 136,
  71         OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS     = 137,
  72         OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS     = 138,
  73         OCRDMA_MBX_STATUS_QP_BOUND              = 130,
  74         OCRDMA_MBX_STATUS_INVALID_CHANGE        = 139,
  75         OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP      = 140,
  76         OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
  77         OCRDMA_MBX_STATUS_MW_STILL_BOUND        = 142,
  78         OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID    = 143,
  79         OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS    = 144
  80 };
  81
  82 enum additional_status {
  83         OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
  84 };
  85
  86 enum cqe_status {
  87         OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES  = 1,
  88         OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER         = 2,
  89         OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES    = 3,
  90         OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING            = 4,
  91         OCRDMA_MBX_CQE_STATUS_DMA_FAILED                = 5
  92 };
  93
  94 static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
  95 {
  96         return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
  97 }
  98
  99 static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
 100 {
 101         eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
 102 }
 103
 104 static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
 105 {
 106         struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
 107             (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
 108
 109         if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
 110                 return NULL;
 111         return cqe;
 112 }
 113
 114 static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
 115 {
 116         dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
 117 }
 118
 119 static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
 120 {
 121         return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
 122 }
 123
 124 static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
 125 {
 126         dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
 127 }
 128
 129 static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
 130 {
 131         return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
 132 }
 133
 134 enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
 135 {
 136         switch (qps) {
 137         case OCRDMA_QPS_RST:
 138                 return IB_QPS_RESET;
 139         case OCRDMA_QPS_INIT:
 140                 return IB_QPS_INIT;
 141         case OCRDMA_QPS_RTR:
 142                 return IB_QPS_RTR;
 143         case OCRDMA_QPS_RTS:
 144                 return IB_QPS_RTS;
 145         case OCRDMA_QPS_SQD:
 146         case OCRDMA_QPS_SQ_DRAINING:
 147                 return IB_QPS_SQD;
 148         case OCRDMA_QPS_SQE:
 149                 return IB_QPS_SQE;
 150         case OCRDMA_QPS_ERR:
 151                 return IB_QPS_ERR;
 152         }
 153         return IB_QPS_ERR;
 154 }
 155
 156 static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
 157 {
 158         switch (qps) {
 159         case IB_QPS_RESET:
 160                 return OCRDMA_QPS_RST;
 161         case IB_QPS_INIT:
 162                 return OCRDMA_QPS_INIT;
 163         case IB_QPS_RTR:
 164                 return OCRDMA_QPS_RTR;
 165         case IB_QPS_RTS:
 166                 return OCRDMA_QPS_RTS;
 167         case IB_QPS_SQD:
 168                 return OCRDMA_QPS_SQD;
 169         case IB_QPS_SQE:
 170                 return OCRDMA_QPS_SQE;
 171         case IB_QPS_ERR:
 172                 return OCRDMA_QPS_ERR;
 173         }
 174         return OCRDMA_QPS_ERR;
 175 }
 176
 177 static int ocrdma_get_mbx_errno(u32 status)
 178 {
 179         int err_num;
 180         u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
 181                                         OCRDMA_MBX_RSP_STATUS_SHIFT;
 182         u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
 183                                         OCRDMA_MBX_RSP_ASTATUS_SHIFT;
 184
 185         switch (mbox_status) {
 186         case OCRDMA_MBX_STATUS_OOR:
 187         case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
 188                 err_num = -EAGAIN;
 189                 break;
 190
 191         case OCRDMA_MBX_STATUS_INVALID_PD:
 192         case OCRDMA_MBX_STATUS_INVALID_CQ:
 193         case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
 194         case OCRDMA_MBX_STATUS_INVALID_QP:
 195         case OCRDMA_MBX_STATUS_INVALID_CHANGE:
 196         case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
 197         case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
 198         case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
 199         case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
 200         case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
 201         case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
 202         case OCRDMA_MBX_STATUS_INVALID_LKEY:
 203         case OCRDMA_MBX_STATUS_INVALID_VA:
 204         case OCRDMA_MBX_STATUS_INVALID_LENGTH:
 205         case OCRDMA_MBX_STATUS_INVALID_FBO:
 206         case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
 207         case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
 208         case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
 209         case OCRDMA_MBX_STATUS_SRQ_ERROR:
 210         case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
 211                 err_num = -EINVAL;
 212                 break;
 213
 214         case OCRDMA_MBX_STATUS_PD_INUSE:
 215         case OCRDMA_MBX_STATUS_QP_BOUND:
 216         case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
 217         case OCRDMA_MBX_STATUS_MW_BOUND:
 218                 err_num = -EBUSY;
 219                 break;
 220
 221         case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
 222         case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
 223         case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
 224         case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
 225         case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
 226         case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
 227         case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
 228         case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
 229         case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
 230                 err_num = -ENOBUFS;
 231                 break;
 232
 233         case OCRDMA_MBX_STATUS_FAILED:
 234                 switch (add_status) {
 235                 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
 236                         err_num = -EAGAIN;
 237                         break;
 238                 }
 239         default:
 240                 err_num = -EFAULT;
 241         }
 242         return err_num;
 243 }
 244
 245 char *port_speed_string(struct ocrdma_dev *dev)
 246 {
 247         char *str = "";
 248         u16 speeds_supported;
 249
 250         speeds_supported = dev->phy.fixed_speeds_supported |
 251                                 dev->phy.auto_speeds_supported;
 252         if (speeds_supported & OCRDMA_PHY_SPEED_40GBPS)
 253                 str = "40Gbps ";
 254         else if (speeds_supported & OCRDMA_PHY_SPEED_10GBPS)
 255                 str = "10Gbps ";
 256         else if (speeds_supported & OCRDMA_PHY_SPEED_1GBPS)
 257                 str = "1Gbps ";
 258
 259         return str;
 260 }
 261
 262 static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
 263 {
 264         int err_num = -EINVAL;
 265
 266         switch (cqe_status) {
 267         case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
 268                 err_num = -EPERM;
 269                 break;
 270         case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
 271                 err_num = -EINVAL;
 272                 break;
 273         case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
 274         case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
 275                 err_num = -EINVAL;
 276                 break;
 277         case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
 278         default:
 279                 err_num = -EINVAL;
 280                 break;
 281         }
 282         return err_num;
 283 }
 284
 285 void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
 286                        bool solicited, u16 cqe_popped)
 287 {
 288         u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
 289
 290         val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
 291              OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
 292
 293         if (armed)
 294                 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
 295         if (solicited)
 296                 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
 297         val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
 298         iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
 299 }
 300
 301 static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
 302 {
 303         u32 val = 0;
 304
 305         val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
 306         val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
 307         iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
 308 }
 309
 310 static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
 311                               bool arm, bool clear_int, u16 num_eqe)
 312 {
 313         u32 val = 0;
 314
 315         val |= eq_id & OCRDMA_EQ_ID_MASK;
 316         val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
 317         if (arm)
 318                 val |= (1 << OCRDMA_REARM_SHIFT);
 319         if (clear_int)
 320                 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
 321         val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
 322         val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
 323         iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
 324 }
 325
 326 static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
 327                             u8 opcode, u8 subsys, u32 cmd_len)
 328 {
 329         cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
 330         cmd_hdr->timeout = 20; /* seconds */
 331         cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
 332 }
 333
 334 static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
 335 {
 336         struct ocrdma_mqe *mqe;
 337
 338         mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
 339         if (!mqe)
 340                 return NULL;
 341         mqe->hdr.spcl_sge_cnt_emb |=
 342                 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
 343                                         OCRDMA_MQE_HDR_EMB_MASK;
 344         mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
 345
 346         ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
 347                         mqe->hdr.pyld_len);
 348         return mqe;
 349 }
 350
 351 static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
 352 {
 353         dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
 354 }
 355
 356 static int ocrdma_alloc_q(struct ocrdma_dev *dev,
 357                           struct ocrdma_queue_info *q, u16 len, u16 entry_size)
 358 {
 359         memset(q, 0, sizeof(*q));
 360         q->len = len;
 361         q->entry_size = entry_size;
 362         q->size = len * entry_size;
 363         q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
 364                                    &q->dma, GFP_KERNEL);
 365         if (!q->va)
 366                 return -ENOMEM;
 367         memset(q->va, 0, q->size);
 368         return 0;
 369 }
 370
 371 static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
 372                                         dma_addr_t host_pa, int hw_page_size)
 373 {
 374         int i;
 375
 376         for (i = 0; i < cnt; i++) {
 377                 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
 378                 q_pa[i].hi = (u32) upper_32_bits(host_pa);
 379                 host_pa += hw_page_size;
 380         }
 381 }
 382
 383 static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev,
 384                                struct ocrdma_queue_info *q, int queue_type)
 385 {
 386         u8 opcode = 0;
 387         int status;
 388         struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
 389
 390         switch (queue_type) {
 391         case QTYPE_MCCQ:
 392                 opcode = OCRDMA_CMD_DELETE_MQ;
 393                 break;
 394         case QTYPE_CQ:
 395                 opcode = OCRDMA_CMD_DELETE_CQ;
 396                 break;
 397         case QTYPE_EQ:
 398                 opcode = OCRDMA_CMD_DELETE_EQ;
 399                 break;
 400         default:
 401                 BUG();
 402         }
 403         memset(cmd, 0, sizeof(*cmd));
 404         ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 405         cmd->id = q->id;
 406
 407         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 408                                  cmd, sizeof(*cmd), NULL, NULL);
 409         if (!status)
 410                 q->created = false;
 411         return status;
 412 }
 413
 414 static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 415 {
 416         int status;
 417         struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
 418         struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
 419
 420         memset(cmd, 0, sizeof(*cmd));
 421         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
 422                         sizeof(*cmd));
 423
 424         cmd->req.rsvd_version = 2;
 425         cmd->num_pages = 4;
 426         cmd->valid = OCRDMA_CREATE_EQ_VALID;
 427         cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
 428
 429         ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
 430                              PAGE_SIZE_4K);
 431         status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
 432                                  NULL);
 433         if (!status) {
 434                 eq->q.id = rsp->vector_eqid & 0xffff;
 435                 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
 436                 eq->q.created = true;
 437         }
 438         return status;
 439 }
 440
 441 static int ocrdma_create_eq(struct ocrdma_dev *dev,
 442                             struct ocrdma_eq *eq, u16 q_len)
 443 {
 444         int status;
 445
 446         status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
 447                                 sizeof(struct ocrdma_eqe));
 448         if (status)
 449                 return status;
 450
 451         status = ocrdma_mbx_create_eq(dev, eq);
 452         if (status)
 453                 goto mbx_err;
 454         eq->dev = dev;
 455         ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
 456
 457         return 0;
 458 mbx_err:
 459         ocrdma_free_q(dev, &eq->q);
 460         return status;
 461 }
 462
 463 int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 464 {
 465         int irq;
 466
 467         if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
 468                 irq = dev->nic_info.pdev->irq;
 469         else
 470                 irq = dev->nic_info.msix.vector_list[eq->vector];
 471         return irq;
 472 }
 473
 474 static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 475 {
 476         if (eq->q.created) {
 477                 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
 478                 ocrdma_free_q(dev, &eq->q);
 479         }
 480 }
 481
 482 static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 483 {
 484         int irq;
 485
 486         /* disarm EQ so that interrupts are not generated
 487          * during freeing and EQ delete is in progress.
 488          */
 489         ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
 490
 491         irq = ocrdma_get_irq(dev, eq);
 492         free_irq(irq, eq);
 493         _ocrdma_destroy_eq(dev, eq);
 494 }
 495
 496 static void ocrdma_destroy_eqs(struct ocrdma_dev *dev)
 497 {
 498         int i;
 499
 500         for (i = 0; i < dev->eq_cnt; i++)
 501                 ocrdma_destroy_eq(dev, &dev->eq_tbl[i]);
 502 }
 503
 504 static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
 505                                    struct ocrdma_queue_info *cq,
 506                                    struct ocrdma_queue_info *eq)
 507 {
 508         struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
 509         struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
 510         int status;
 511
 512         memset(cmd, 0, sizeof(*cmd));
 513         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
 514                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 515
 516         cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
 517         cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
 518                 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
 519         cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
 520
 521         cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
 522         cmd->eqn = eq->id;
 523         cmd->pdid_cqecnt = cq->size / sizeof(struct ocrdma_mcqe);
 524
 525         ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
 526                              cq->dma, PAGE_SIZE_4K);
 527         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 528                                  cmd, sizeof(*cmd), NULL, NULL);
 529         if (!status) {
 530                 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
 531                 cq->created = true;
 532         }
 533         return status;
 534 }
 535
 536 static u32 ocrdma_encoded_q_len(int q_len)
 537 {
 538         u32 len_encoded = fls(q_len);   /* log2(len) + 1 */
 539
 540         if (len_encoded == 16)
 541                 len_encoded = 0;
 542         return len_encoded;
 543 }
 544
 545 static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
 546                                 struct ocrdma_queue_info *mq,
 547                                 struct ocrdma_queue_info *cq)
 548 {
 549         int num_pages, status;
 550         struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
 551         struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
 552         struct ocrdma_pa *pa;
 553
 554         memset(cmd, 0, sizeof(*cmd));
 555         num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
 556
 557         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
 558                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 559         cmd->req.rsvd_version = 1;
 560         cmd->cqid_pages = num_pages;
 561         cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
 562         cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
 563
 564         cmd->async_event_bitmap = BIT(OCRDMA_ASYNC_GRP5_EVE_CODE);
 565         cmd->async_event_bitmap |= BIT(OCRDMA_ASYNC_RDMA_EVE_CODE);
 566
 567         cmd->async_cqid_ringsize = cq->id;
 568         cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
 569                                 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
 570         cmd->valid = OCRDMA_CREATE_MQ_VALID;
 571         pa = &cmd->pa[0];
 572
 573         ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
 574         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 575                                  cmd, sizeof(*cmd), NULL, NULL);
 576         if (!status) {
 577                 mq->id = rsp->id;
 578                 mq->created = true;
 579         }
 580         return status;
 581 }
 582
 583 static int ocrdma_create_mq(struct ocrdma_dev *dev)
 584 {
 585         int status;
 586
 587         /* Alloc completion queue for Mailbox queue */
 588         status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
 589                                 sizeof(struct ocrdma_mcqe));
 590         if (status)
 591                 goto alloc_err;
 592
 593         dev->eq_tbl[0].cq_cnt++;
 594         status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q);
 595         if (status)
 596                 goto mbx_cq_free;
 597
 598         memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
 599         init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
 600         mutex_init(&dev->mqe_ctx.lock);
 601
 602         /* Alloc Mailbox queue */
 603         status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
 604                                 sizeof(struct ocrdma_mqe));
 605         if (status)
 606                 goto mbx_cq_destroy;
 607         status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
 608         if (status)
 609                 goto mbx_q_free;
 610         ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
 611         return 0;
 612
 613 mbx_q_free:
 614         ocrdma_free_q(dev, &dev->mq.sq);
 615 mbx_cq_destroy:
 616         ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
 617 mbx_cq_free:
 618         ocrdma_free_q(dev, &dev->mq.cq);
 619 alloc_err:
 620         return status;
 621 }
 622
 623 static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
 624 {
 625         struct ocrdma_queue_info *mbxq, *cq;
 626
 627         /* mqe_ctx lock synchronizes with any other pending cmds. */
 628         mutex_lock(&dev->mqe_ctx.lock);
 629         mbxq = &dev->mq.sq;
 630         if (mbxq->created) {
 631                 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
 632                 ocrdma_free_q(dev, mbxq);
 633         }
 634         mutex_unlock(&dev->mqe_ctx.lock);
 635
 636         cq = &dev->mq.cq;
 637         if (cq->created) {
 638                 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
 639                 ocrdma_free_q(dev, cq);
 640         }
 641 }
 642
 643 static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
 644                                        struct ocrdma_qp *qp)
 645 {
 646         enum ib_qp_state new_ib_qps = IB_QPS_ERR;
 647         enum ib_qp_state old_ib_qps;
 648
 649         if (qp == NULL)
 650                 BUG();
 651         ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
 652 }
 653
 654 static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
 655                                     struct ocrdma_ae_mcqe *cqe)
 656 {
 657         struct ocrdma_qp *qp = NULL;
 658         struct ocrdma_cq *cq = NULL;
 659         struct ib_event ib_evt;
 660         int cq_event = 0;
 661         int qp_event = 1;
 662         int srq_event = 0;
 663         int dev_event = 0;
 664         int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
 665             OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
 666
 667         if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID)
 668                 qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK];
 669         if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID)
 670                 cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK];
 671
 672         memset(&ib_evt, 0, sizeof(ib_evt));
 673
 674         ib_evt.device = &dev->ibdev;
 675
 676         switch (type) {
 677         case OCRDMA_CQ_ERROR:
 678                 ib_evt.element.cq = &cq->ibcq;
 679                 ib_evt.event = IB_EVENT_CQ_ERR;
 680                 cq_event = 1;
 681                 qp_event = 0;
 682                 break;
 683         case OCRDMA_CQ_OVERRUN_ERROR:
 684                 ib_evt.element.cq = &cq->ibcq;
 685                 ib_evt.event = IB_EVENT_CQ_ERR;
 686                 cq_event = 1;
 687                 qp_event = 0;
 688                 break;
 689         case OCRDMA_CQ_QPCAT_ERROR:
 690                 ib_evt.element.qp = &qp->ibqp;
 691                 ib_evt.event = IB_EVENT_QP_FATAL;
 692                 ocrdma_process_qpcat_error(dev, qp);
 693                 break;
 694         case OCRDMA_QP_ACCESS_ERROR:
 695                 ib_evt.element.qp = &qp->ibqp;
 696                 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
 697                 break;
 698         case OCRDMA_QP_COMM_EST_EVENT:
 699                 ib_evt.element.qp = &qp->ibqp;
 700                 ib_evt.event = IB_EVENT_COMM_EST;
 701                 break;
 702         case OCRDMA_SQ_DRAINED_EVENT:
 703                 ib_evt.element.qp = &qp->ibqp;
 704                 ib_evt.event = IB_EVENT_SQ_DRAINED;
 705                 break;
 706         case OCRDMA_DEVICE_FATAL_EVENT:
 707                 ib_evt.element.port_num = 1;
 708                 ib_evt.event = IB_EVENT_DEVICE_FATAL;
 709                 qp_event = 0;
 710                 dev_event = 1;
 711                 break;
 712         case OCRDMA_SRQCAT_ERROR:
 713                 ib_evt.element.srq = &qp->srq->ibsrq;
 714                 ib_evt.event = IB_EVENT_SRQ_ERR;
 715                 srq_event = 1;
 716                 qp_event = 0;
 717                 break;
 718         case OCRDMA_SRQ_LIMIT_EVENT:
 719                 ib_evt.element.srq = &qp->srq->ibsrq;
 720                 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
 721                 srq_event = 1;
 722                 qp_event = 0;
 723                 break;
 724         case OCRDMA_QP_LAST_WQE_EVENT:
 725                 ib_evt.element.qp = &qp->ibqp;
 726                 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
 727                 break;
 728         default:
 729                 cq_event = 0;
 730                 qp_event = 0;
 731                 srq_event = 0;
 732                 dev_event = 0;
 733                 pr_err("%s() unknown type=0x%x\n", __func__, type);
 734                 break;
 735         }
 736
 737         if (type < OCRDMA_MAX_ASYNC_ERRORS)
 738                 atomic_inc(&dev->async_err_stats[type]);
 739
 740         if (qp_event) {
 741                 if (qp->ibqp.event_handler)
 742                         qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
 743         } else if (cq_event) {
 744                 if (cq->ibcq.event_handler)
 745                         cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
 746         } else if (srq_event) {
 747                 if (qp->srq->ibsrq.event_handler)
 748                         qp->srq->ibsrq.event_handler(&ib_evt,
 749                                                      qp->srq->ibsrq.
 750                                                      srq_context);
 751         } else if (dev_event) {
 752                 pr_err("%s: Fatal event received\n", dev->ibdev.name);
 753                 ib_dispatch_event(&ib_evt);
 754         }
 755
 756 }
 757
 758 static void ocrdma_process_grp5_aync(struct ocrdma_dev *dev,
 759                                         struct ocrdma_ae_mcqe *cqe)
 760 {
 761         struct ocrdma_ae_pvid_mcqe *evt;
 762         int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
 763                         OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
 764
 765         switch (type) {
 766         case OCRDMA_ASYNC_EVENT_PVID_STATE:
 767                 evt = (struct ocrdma_ae_pvid_mcqe *)cqe;
 768                 if ((evt->tag_enabled & OCRDMA_AE_PVID_MCQE_ENABLED_MASK) >>
 769                         OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT)
 770                         dev->pvid = ((evt->tag_enabled &
 771                                         OCRDMA_AE_PVID_MCQE_TAG_MASK) >>
 772                                         OCRDMA_AE_PVID_MCQE_TAG_SHIFT);
 773                 break;
 774
 775         case OCRDMA_ASYNC_EVENT_COS_VALUE:
 776                 atomic_set(&dev->update_sl, 1);
 777                 break;
 778         default:
 779                 /* Not interested evts. */
 780                 break;
 781         }
 782 }
 783
 784 static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
 785 {
 786         /* async CQE processing */
 787         struct ocrdma_ae_mcqe *cqe = ae_cqe;
 788         u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
 789                         OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
 790
 791         if (evt_code == OCRDMA_ASYNC_RDMA_EVE_CODE)
 792                 ocrdma_dispatch_ibevent(dev, cqe);
 793         else if (evt_code == OCRDMA_ASYNC_GRP5_EVE_CODE)
 794                 ocrdma_process_grp5_aync(dev, cqe);
 795         else
 796                 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
 797                        dev->id, evt_code);
 798 }
 799
 800 static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
 801 {
 802         if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
 803                 dev->mqe_ctx.cqe_status = (cqe->status &
 804                      OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
 805                 dev->mqe_ctx.ext_status =
 806                     (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
 807                     >> OCRDMA_MCQE_ESTATUS_SHIFT;
 808                 dev->mqe_ctx.cmd_done = true;
 809                 wake_up(&dev->mqe_ctx.cmd_wait);
 810         } else
 811                 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
 812                        __func__, cqe->tag_lo, dev->mqe_ctx.tag);
 813 }
 814
 815 static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
 816 {
 817         u16 cqe_popped = 0;
 818         struct ocrdma_mcqe *cqe;
 819
 820         while (1) {
 821                 cqe = ocrdma_get_mcqe(dev);
 822                 if (cqe == NULL)
 823                         break;
 824                 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
 825                 cqe_popped += 1;
 826                 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
 827                         ocrdma_process_acqe(dev, cqe);
 828                 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
 829                         ocrdma_process_mcqe(dev, cqe);
 830                 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
 831                 ocrdma_mcq_inc_tail(dev);
 832         }
 833         ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
 834         return 0;
 835 }
 836
 837 static struct ocrdma_cq *_ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
 838                                 struct ocrdma_cq *cq, bool sq)
 839 {
 840         struct ocrdma_qp *qp;
 841         struct list_head *cur;
 842         struct ocrdma_cq *bcq = NULL;
 843         struct list_head *head = sq?(&cq->sq_head):(&cq->rq_head);
 844
 845         list_for_each(cur, head) {
 846                 if (sq)
 847                         qp = list_entry(cur, struct ocrdma_qp, sq_entry);
 848                 else
 849                         qp = list_entry(cur, struct ocrdma_qp, rq_entry);
 850
 851                 if (qp->srq)
 852                         continue;
 853                 /* if wq and rq share the same cq, than comp_handler
 854                  * is already invoked.
 855                  */
 856                 if (qp->sq_cq == qp->rq_cq)
 857                         continue;
 858                 /* if completion came on sq, rq's cq is buddy cq.
 859                  * if completion came on rq, sq's cq is buddy cq.
 860                  */
 861                 if (qp->sq_cq == cq)
 862                         bcq = qp->rq_cq;
 863                 else
 864                         bcq = qp->sq_cq;
 865                 return bcq;
 866         }
 867         return NULL;
 868 }
 869
 870 static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
 871                                        struct ocrdma_cq *cq)
 872 {
 873         unsigned long flags;
 874         struct ocrdma_cq *bcq = NULL;
 875
 876         /* Go through list of QPs in error state which are using this CQ
 877          * and invoke its callback handler to trigger CQE processing for
 878          * error/flushed CQE. It is rare to find more than few entries in
 879          * this list as most consumers stops after getting error CQE.
 880          * List is traversed only once when a matching buddy cq found for a QP.
 881          */
 882         spin_lock_irqsave(&dev->flush_q_lock, flags);
 883         /* Check if buddy CQ is present.
 884          * true - Check for  SQ CQ
 885          * false - Check for RQ CQ
 886          */
 887         bcq = _ocrdma_qp_buddy_cq_handler(dev, cq, true);
 888         if (bcq == NULL)
 889                 bcq = _ocrdma_qp_buddy_cq_handler(dev, cq, false);
 890         spin_unlock_irqrestore(&dev->flush_q_lock, flags);
 891
 892         /* if there is valid buddy cq, look for its completion handler */
 893         if (bcq && bcq->ibcq.comp_handler) {
 894                 spin_lock_irqsave(&bcq->comp_handler_lock, flags);
 895                 (*bcq->ibcq.comp_handler) (&bcq->ibcq, bcq->ibcq.cq_context);
 896                 spin_unlock_irqrestore(&bcq->comp_handler_lock, flags);
 897         }
 898 }
 899
 900 static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
 901 {
 902         unsigned long flags;
 903         struct ocrdma_cq *cq;
 904
 905         if (cq_idx >= OCRDMA_MAX_CQ)
 906                 BUG();
 907
 908         cq = dev->cq_tbl[cq_idx];
 909         if (cq == NULL)
 910                 return;
 911
 912         if (cq->ibcq.comp_handler) {
 913                 spin_lock_irqsave(&cq->comp_handler_lock, flags);
 914                 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
 915                 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
 916         }
 917         ocrdma_qp_buddy_cq_handler(dev, cq);
 918 }
 919
 920 static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
 921 {
 922         /* process the MQ-CQE. */
 923         if (cq_id == dev->mq.cq.id)
 924                 ocrdma_mq_cq_handler(dev, cq_id);
 925         else
 926                 ocrdma_qp_cq_handler(dev, cq_id);
 927 }
 928
 929 static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
 930 {
 931         struct ocrdma_eq *eq = handle;
 932         struct ocrdma_dev *dev = eq->dev;
 933         struct ocrdma_eqe eqe;
 934         struct ocrdma_eqe *ptr;
 935         u16 cq_id;
 936         int budget = eq->cq_cnt;
 937
 938         do {
 939                 ptr = ocrdma_get_eqe(eq);
 940                 eqe = *ptr;
 941                 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
 942                 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
 943                         break;
 944
 945                 ptr->id_valid = 0;
 946                 /* ring eq doorbell as soon as its consumed. */
 947                 ocrdma_ring_eq_db(dev, eq->q.id, false, true, 1);
 948                 /* check whether its CQE or not. */
 949                 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
 950                         cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
 951                         ocrdma_cq_handler(dev, cq_id);
 952                 }
 953                 ocrdma_eq_inc_tail(eq);
 954
 955                 /* There can be a stale EQE after the last bound CQ is
 956                  * destroyed. EQE valid and budget == 0 implies this.
 957                  */
 958                 if (budget)
 959                         budget--;
 960
 961         } while (budget);
 962
 963         ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
 964         return IRQ_HANDLED;
 965 }
 966
 967 static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
 968 {
 969         struct ocrdma_mqe *mqe;
 970
 971         dev->mqe_ctx.tag = dev->mq.sq.head;
 972         dev->mqe_ctx.cmd_done = false;
 973         mqe = ocrdma_get_mqe(dev);
 974         cmd->hdr.tag_lo = dev->mq.sq.head;
 975         ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
 976         /* make sure descriptor is written before ringing doorbell */
 977         wmb();
 978         ocrdma_mq_inc_head(dev);
 979         ocrdma_ring_mq_db(dev);
 980 }
 981
 982 static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
 983 {
 984         long status;
 985         /* 30 sec timeout */
 986         status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
 987                                     (dev->mqe_ctx.cmd_done != false),
 988                                     msecs_to_jiffies(30000));
 989         if (status)
 990                 return 0;
 991         else {
 992                 dev->mqe_ctx.fw_error_state = true;
 993                 pr_err("%s(%d) mailbox timeout: fw not responding\n",
 994                        __func__, dev->id);
 995                 return -1;
 996         }
 997 }
 998
 999 /* issue a mailbox command on the MQ */
1000 static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
1001 {
1002         int status = 0;
1003         u16 cqe_status, ext_status;
1004         struct ocrdma_mqe *rsp_mqe;
1005         struct ocrdma_mbx_rsp *rsp = NULL;
1006
1007         mutex_lock(&dev->mqe_ctx.lock);
1008         if (dev->mqe_ctx.fw_error_state)
1009                 goto mbx_err;
1010         ocrdma_post_mqe(dev, mqe);
1011         status = ocrdma_wait_mqe_cmpl(dev);
1012         if (status)
1013                 goto mbx_err;
1014         cqe_status = dev->mqe_ctx.cqe_status;
1015         ext_status = dev->mqe_ctx.ext_status;
1016         rsp_mqe = ocrdma_get_mqe_rsp(dev);
1017         ocrdma_copy_le32_to_cpu(mqe, rsp_mqe, (sizeof(*mqe)));
1018         if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1019                                 OCRDMA_MQE_HDR_EMB_SHIFT)
1020                 rsp = &mqe->u.rsp;
1021
1022         if (cqe_status || ext_status) {
1023                 pr_err("%s() cqe_status=0x%x, ext_status=0x%x,",
1024                        __func__, cqe_status, ext_status);
1025                 if (rsp) {
1026                         /* This is for embedded cmds. */
1027                         pr_err("opcode=0x%x, subsystem=0x%x\n",
1028                                (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1029                                 OCRDMA_MBX_RSP_OPCODE_SHIFT,
1030                                 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1031                                 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1032                 }
1033                 status = ocrdma_get_mbx_cqe_errno(cqe_status);
1034                 goto mbx_err;
1035         }
1036         /* For non embedded, rsp errors are handled in ocrdma_nonemb_mbx_cmd */
1037         if (rsp && (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK))
1038                 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
1039 mbx_err:
1040         mutex_unlock(&dev->mqe_ctx.lock);
1041         return status;
1042 }
1043
1044 static int ocrdma_nonemb_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe,
1045                                  void *payload_va)
1046 {
1047         int status = 0;
1048         struct ocrdma_mbx_rsp *rsp = payload_va;
1049
1050         if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1051                                 OCRDMA_MQE_HDR_EMB_SHIFT)
1052                 BUG();
1053
1054         status = ocrdma_mbx_cmd(dev, mqe);
1055         if (!status)
1056                 /* For non embedded, only CQE failures are handled in
1057                  * ocrdma_mbx_cmd. We need to check for RSP errors.
1058                  */
1059                 if (rsp->status & OCRDMA_MBX_RSP_STATUS_MASK)
1060                         status = ocrdma_get_mbx_errno(rsp->status);
1061
1062         if (status)
1063                 pr_err("opcode=0x%x, subsystem=0x%x\n",
1064                        (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1065                         OCRDMA_MBX_RSP_OPCODE_SHIFT,
1066                         (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1067                         OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1068         return status;
1069 }
1070
1071 static void ocrdma_get_attr(struct ocrdma_dev *dev,
1072                               struct ocrdma_dev_attr *attr,
1073                               struct ocrdma_mbx_query_config *rsp)
1074 {
1075         attr->max_pd =
1076             (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
1077             OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
1078         attr->max_dpp_pds =
1079            (rsp->max_dpp_pds_credits & OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK) >>
1080             OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET;
1081         attr->max_qp =
1082             (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
1083             OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
1084         attr->max_srq =
1085                 (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >>
1086                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET;
1087         attr->max_send_sge = ((rsp->max_write_send_sge &
1088                                OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1089                               OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
1090         attr->max_recv_sge = (rsp->max_write_send_sge &
1091                               OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1092             OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
1093         attr->max_srq_sge = (rsp->max_srq_rqe_sge &
1094                               OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
1095             OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
1096         attr->max_rdma_sge = (rsp->max_write_send_sge &
1097                               OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK) >>
1098             OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT;
1099         attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1100                                 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1101             OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
1102         attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1103                                 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1104             OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1105         attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1106                                     OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1107             OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1108         attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1109                                OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1110             OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1111         attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1112                                     OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1113             OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
1114         attr->max_mw = rsp->max_mw;
1115         attr->max_mr = rsp->max_mr;
1116         attr->max_mr_size = ((u64)rsp->max_mr_size_hi << 32) |
1117                               rsp->max_mr_size_lo;
1118         attr->max_fmr = 0;
1119         attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1120         attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1121         attr->max_cqe = rsp->max_cq_cqes_per_cq &
1122                         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
1123         attr->max_cq = (rsp->max_cq_cqes_per_cq &
1124                         OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK) >>
1125                         OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET;
1126         attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1127                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1128                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1129                 OCRDMA_WQE_STRIDE;
1130         attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1131                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1132                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1133                 OCRDMA_WQE_STRIDE;
1134         attr->max_inline_data =
1135             attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1136                               sizeof(struct ocrdma_sge));
1137         if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1138                 attr->ird = 1;
1139                 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1140                 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
1141         }
1142         dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1143                  OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1144         dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1145                 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
1146 }
1147
1148 static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1149                                    struct ocrdma_fw_conf_rsp *conf)
1150 {
1151         u32 fn_mode;
1152
1153         fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1154         if (fn_mode != OCRDMA_FN_MODE_RDMA)
1155                 return -EINVAL;
1156         dev->base_eqid = conf->base_eqid;
1157         dev->max_eq = conf->max_eq;
1158         return 0;
1159 }
1160
1161 /* can be issued only during init time. */
1162 static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1163 {
1164         int status = -ENOMEM;
1165         struct ocrdma_mqe *cmd;
1166         struct ocrdma_fw_ver_rsp *rsp;
1167
1168         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1169         if (!cmd)
1170                 return -ENOMEM;
1171         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1172                         OCRDMA_CMD_GET_FW_VER,
1173                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1174
1175         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1176         if (status)
1177                 goto mbx_err;
1178         rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1179         memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1180         memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1181                sizeof(rsp->running_ver));
1182         ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1183 mbx_err:
1184         kfree(cmd);
1185         return status;
1186 }
1187
1188 /* can be issued only during init time. */
1189 static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1190 {
1191         int status = -ENOMEM;
1192         struct ocrdma_mqe *cmd;
1193         struct ocrdma_fw_conf_rsp *rsp;
1194
1195         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1196         if (!cmd)
1197                 return -ENOMEM;
1198         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1199                         OCRDMA_CMD_GET_FW_CONFIG,
1200                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1201         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1202         if (status)
1203                 goto mbx_err;
1204         rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1205         status = ocrdma_check_fw_config(dev, rsp);
1206 mbx_err:
1207         kfree(cmd);
1208         return status;
1209 }
1210
1211 int ocrdma_mbx_rdma_stats(struct ocrdma_dev *dev, bool reset)
1212 {
1213         struct ocrdma_rdma_stats_req *req = dev->stats_mem.va;
1214         struct ocrdma_mqe *mqe = &dev->stats_mem.mqe;
1215         struct ocrdma_rdma_stats_resp *old_stats;
1216         int status;
1217
1218         old_stats = kmalloc(sizeof(*old_stats), GFP_KERNEL);
1219         if (old_stats == NULL)
1220                 return -ENOMEM;
1221
1222         memset(mqe, 0, sizeof(*mqe));
1223         mqe->hdr.pyld_len = dev->stats_mem.size;
1224         mqe->hdr.spcl_sge_cnt_emb |=
1225                         (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1226                                 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1227         mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dev->stats_mem.pa & 0xffffffff);
1228         mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dev->stats_mem.pa);
1229         mqe->u.nonemb_req.sge[0].len = dev->stats_mem.size;
1230
1231         /* Cache the old stats */
1232         memcpy(old_stats, req, sizeof(struct ocrdma_rdma_stats_resp));
1233         memset(req, 0, dev->stats_mem.size);
1234
1235         ocrdma_init_mch((struct ocrdma_mbx_hdr *)req,
1236                         OCRDMA_CMD_GET_RDMA_STATS,
1237                         OCRDMA_SUBSYS_ROCE,
1238                         dev->stats_mem.size);
1239         if (reset)
1240                 req->reset_stats = reset;
1241
1242         status = ocrdma_nonemb_mbx_cmd(dev, mqe, dev->stats_mem.va);
1243         if (status)
1244                 /* Copy from cache, if mbox fails */
1245                 memcpy(req, old_stats, sizeof(struct ocrdma_rdma_stats_resp));
1246         else
1247                 ocrdma_le32_to_cpu(req, dev->stats_mem.size);
1248
1249         kfree(old_stats);
1250         return status;
1251 }
1252
1253 static int ocrdma_mbx_get_ctrl_attribs(struct ocrdma_dev *dev)
1254 {
1255         int status = -ENOMEM;
1256         struct ocrdma_dma_mem dma;
1257         struct ocrdma_mqe *mqe;
1258         struct ocrdma_get_ctrl_attribs_rsp *ctrl_attr_rsp;
1259         struct mgmt_hba_attribs *hba_attribs;
1260
1261         mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
1262         if (!mqe)
1263                 return status;
1264
1265         dma.size = sizeof(struct ocrdma_get_ctrl_attribs_rsp);
1266         dma.va   = dma_alloc_coherent(&dev->nic_info.pdev->dev,
1267                                         dma.size, &dma.pa, GFP_KERNEL);
1268         if (!dma.va)
1269                 goto free_mqe;
1270
1271         mqe->hdr.pyld_len = dma.size;
1272         mqe->hdr.spcl_sge_cnt_emb |=
1273                         (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1274                         OCRDMA_MQE_HDR_SGE_CNT_MASK;
1275         mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dma.pa & 0xffffffff);
1276         mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dma.pa);
1277         mqe->u.nonemb_req.sge[0].len = dma.size;
1278
1279         memset(dma.va, 0, dma.size);
1280         ocrdma_init_mch((struct ocrdma_mbx_hdr *)dma.va,
1281                         OCRDMA_CMD_GET_CTRL_ATTRIBUTES,
1282                         OCRDMA_SUBSYS_COMMON,
1283                         dma.size);
1284
1285         status = ocrdma_nonemb_mbx_cmd(dev, mqe, dma.va);
1286         if (!status) {
1287                 ctrl_attr_rsp = (struct ocrdma_get_ctrl_attribs_rsp *)dma.va;
1288                 hba_attribs = &ctrl_attr_rsp->ctrl_attribs.hba_attribs;
1289
1290                 dev->hba_port_num = (hba_attribs->ptpnum_maxdoms_hbast_cv &
1291                                         OCRDMA_HBA_ATTRB_PTNUM_MASK)
1292                                         >> OCRDMA_HBA_ATTRB_PTNUM_SHIFT;
1293                 strncpy(dev->model_number,
1294                         hba_attribs->controller_model_number, 31);
1295         }
1296         dma_free_coherent(&dev->nic_info.pdev->dev, dma.size, dma.va, dma.pa);
1297 free_mqe:
1298         kfree(mqe);
1299         return status;
1300 }
1301
1302 static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1303 {
1304         int status = -ENOMEM;
1305         struct ocrdma_mbx_query_config *rsp;
1306         struct ocrdma_mqe *cmd;
1307
1308         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1309         if (!cmd)
1310                 return status;
1311         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1312         if (status)
1313                 goto mbx_err;
1314         rsp = (struct ocrdma_mbx_query_config *)cmd;
1315         ocrdma_get_attr(dev, &dev->attr, rsp);
1316 mbx_err:
1317         kfree(cmd);
1318         return status;
1319 }
1320
1321 int ocrdma_mbx_get_link_speed(struct ocrdma_dev *dev, u8 *lnk_speed)
1322 {
1323         int status = -ENOMEM;
1324         struct ocrdma_get_link_speed_rsp *rsp;
1325         struct ocrdma_mqe *cmd;
1326
1327         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1328                                   sizeof(*cmd));
1329         if (!cmd)
1330                 return status;
1331         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1332                         OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1333                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1334
1335         ((struct ocrdma_mbx_hdr *)cmd->u.cmd)->rsvd_version = 0x1;
1336
1337         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1338         if (status)
1339                 goto mbx_err;
1340
1341         rsp = (struct ocrdma_get_link_speed_rsp *)cmd;
1342         *lnk_speed = (rsp->pflt_pps_ld_pnum & OCRDMA_PHY_PS_MASK)
1343                         >> OCRDMA_PHY_PS_SHIFT;
1344
1345 mbx_err:
1346         kfree(cmd);
1347         return status;
1348 }
1349
1350 static int ocrdma_mbx_get_phy_info(struct ocrdma_dev *dev)
1351 {
1352         int status = -ENOMEM;
1353         struct ocrdma_mqe *cmd;
1354         struct ocrdma_get_phy_info_rsp *rsp;
1355
1356         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_PHY_DETAILS, sizeof(*cmd));
1357         if (!cmd)
1358                 return status;
1359
1360         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1361                         OCRDMA_CMD_PHY_DETAILS, OCRDMA_SUBSYS_COMMON,
1362                         sizeof(*cmd));
1363
1364         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1365         if (status)
1366                 goto mbx_err;
1367
1368         rsp = (struct ocrdma_get_phy_info_rsp *)cmd;
1369         dev->phy.phy_type =
1370                         (rsp->ityp_ptyp & OCRDMA_PHY_TYPE_MASK);
1371         dev->phy.interface_type =
1372                         (rsp->ityp_ptyp & OCRDMA_IF_TYPE_MASK)
1373                                 >> OCRDMA_IF_TYPE_SHIFT;
1374         dev->phy.auto_speeds_supported  =
1375                         (rsp->fspeed_aspeed & OCRDMA_ASPEED_SUPP_MASK);
1376         dev->phy.fixed_speeds_supported =
1377                         (rsp->fspeed_aspeed & OCRDMA_FSPEED_SUPP_MASK)
1378                                 >> OCRDMA_FSPEED_SUPP_SHIFT;
1379 mbx_err:
1380         kfree(cmd);
1381         return status;
1382 }
1383
1384 int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1385 {
1386         int status = -ENOMEM;
1387         struct ocrdma_alloc_pd *cmd;
1388         struct ocrdma_alloc_pd_rsp *rsp;
1389
1390         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1391         if (!cmd)
1392                 return status;
1393         if (pd->dpp_enabled)
1394                 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1395         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1396         if (status)
1397                 goto mbx_err;
1398         rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1399         pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1400         if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1401                 pd->dpp_enabled = true;
1402                 pd->dpp_page = rsp->dpp_page_pdid >>
1403                                 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1404         } else {
1405                 pd->dpp_enabled = false;
1406                 pd->num_dpp_qp = 0;
1407         }
1408 mbx_err:
1409         kfree(cmd);
1410         return status;
1411 }
1412
1413 int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1414 {
1415         int status = -ENOMEM;
1416         struct ocrdma_dealloc_pd *cmd;
1417
1418         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1419         if (!cmd)
1420                 return status;
1421         cmd->id = pd->id;
1422         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1423         kfree(cmd);
1424         return status;
1425 }
1426
1427
1428 static int ocrdma_mbx_alloc_pd_range(struct ocrdma_dev *dev)
1429 {
1430         int status = -ENOMEM;
1431         size_t pd_bitmap_size;
1432         struct ocrdma_alloc_pd_range *cmd;
1433         struct ocrdma_alloc_pd_range_rsp *rsp;
1434
1435         /* Pre allocate the DPP PDs */
1436         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE, sizeof(*cmd));
1437         if (!cmd)
1438                 return -ENOMEM;
1439         cmd->pd_count = dev->attr.max_dpp_pds;
1440         cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1441         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1442         if (status)
1443                 goto mbx_err;
1444         rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd;
1445
1446         if ((rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) && rsp->pd_count) {
1447                 dev->pd_mgr->dpp_page_index = rsp->dpp_page_pdid >>
1448                                 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1449                 dev->pd_mgr->pd_dpp_start = rsp->dpp_page_pdid &
1450                                 OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK;
1451                 dev->pd_mgr->max_dpp_pd = rsp->pd_count;
1452                 pd_bitmap_size = BITS_TO_LONGS(rsp->pd_count) * sizeof(long);
1453                 dev->pd_mgr->pd_dpp_bitmap = kzalloc(pd_bitmap_size,
1454                                                      GFP_KERNEL);
1455         }
1456         kfree(cmd);
1457
1458         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE, sizeof(*cmd));
1459         if (!cmd)
1460                 return -ENOMEM;
1461
1462         cmd->pd_count = dev->attr.max_pd - dev->attr.max_dpp_pds;
1463         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1464         if (status)
1465                 goto mbx_err;
1466         rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd;
1467         if (rsp->pd_count) {
1468                 dev->pd_mgr->pd_norm_start = rsp->dpp_page_pdid &
1469                                         OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK;
1470                 dev->pd_mgr->max_normal_pd = rsp->pd_count;
1471                 pd_bitmap_size = BITS_TO_LONGS(rsp->pd_count) * sizeof(long);
1472                 dev->pd_mgr->pd_norm_bitmap = kzalloc(pd_bitmap_size,
1473                                                       GFP_KERNEL);
1474         }
1475
1476         if (dev->pd_mgr->pd_norm_bitmap || dev->pd_mgr->pd_dpp_bitmap) {
1477                 /* Enable PD resource manager */
1478                 dev->pd_mgr->pd_prealloc_valid = true;
1479         } else {
1480                 return -ENOMEM;
1481         }
1482 mbx_err:
1483         kfree(cmd);
1484         return status;
1485 }
1486
1487 static void ocrdma_mbx_dealloc_pd_range(struct ocrdma_dev *dev)
1488 {
1489         struct ocrdma_dealloc_pd_range *cmd;
1490
1491         /* return normal PDs to firmware */
1492         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE, sizeof(*cmd));
1493         if (!cmd)
1494                 goto mbx_err;
1495
1496         if (dev->pd_mgr->max_normal_pd) {
1497                 cmd->start_pd_id = dev->pd_mgr->pd_norm_start;
1498                 cmd->pd_count = dev->pd_mgr->max_normal_pd;
1499                 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1500         }
1501
1502         if (dev->pd_mgr->max_dpp_pd) {
1503                 kfree(cmd);
1504                 /* return DPP PDs to firmware */
1505                 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE,
1506                                           sizeof(*cmd));
1507                 if (!cmd)
1508                         goto mbx_err;
1509
1510                 cmd->start_pd_id = dev->pd_mgr->pd_dpp_start;
1511                 cmd->pd_count = dev->pd_mgr->max_dpp_pd;
1512                 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1513         }
1514 mbx_err:
1515         kfree(cmd);
1516 }
1517
1518 void ocrdma_alloc_pd_pool(struct ocrdma_dev *dev)
1519 {
1520         int status;
1521
1522         dev->pd_mgr = kzalloc(sizeof(struct ocrdma_pd_resource_mgr),
1523                               GFP_KERNEL);
1524         if (!dev->pd_mgr) {
1525                 pr_err("%s(%d)Memory allocation failure.\n", __func__, dev->id);
1526                 return;
1527         }
1528         status = ocrdma_mbx_alloc_pd_range(dev);
1529         if (status) {
1530                 pr_err("%s(%d) Unable to initialize PD pool, using default.\n",
1531                          __func__, dev->id);
1532         }
1533 }
1534
1535 static void ocrdma_free_pd_pool(struct ocrdma_dev *dev)
1536 {
1537         ocrdma_mbx_dealloc_pd_range(dev);
1538         kfree(dev->pd_mgr->pd_norm_bitmap);
1539         kfree(dev->pd_mgr->pd_dpp_bitmap);
1540         kfree(dev->pd_mgr);
1541 }
1542
1543 static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1544                                int *num_pages, int *page_size)
1545 {
1546         int i;
1547         int mem_size;
1548
1549         *num_entries = roundup_pow_of_two(*num_entries);
1550         mem_size = *num_entries * entry_size;
1551         /* find the possible lowest possible multiplier */
1552         for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1553                 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1554                         break;
1555         }
1556         if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1557                 return -EINVAL;
1558         mem_size = roundup(mem_size,
1559                        ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1560         *num_pages =
1561             mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1562         *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1563         *num_entries = mem_size / entry_size;
1564         return 0;
1565 }
1566
1567 static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1568 {
1569         int i;
1570         int status = 0;
1571         int max_ah;
1572         struct ocrdma_create_ah_tbl *cmd;
1573         struct ocrdma_create_ah_tbl_rsp *rsp;
1574         struct pci_dev *pdev = dev->nic_info.pdev;
1575         dma_addr_t pa;
1576         struct ocrdma_pbe *pbes;
1577
1578         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1579         if (!cmd)
1580                 return status;
1581
1582         max_ah = OCRDMA_MAX_AH;
1583         dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1584
1585         /* number of PBEs in PBL */
1586         cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1587                                 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1588                                 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1589
1590         /* page size */
1591         for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1592                 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1593                         break;
1594         }
1595         cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1596                                 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1597
1598         /* ah_entry size */
1599         cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1600                                 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1601                                 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1602
1603         dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1604                                                 &dev->av_tbl.pbl.pa,
1605                                                 GFP_KERNEL);
1606         if (dev->av_tbl.pbl.va == NULL)
1607                 goto mem_err;
1608
1609         dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1610                                             &pa, GFP_KERNEL);
1611         if (dev->av_tbl.va == NULL)
1612                 goto mem_err_ah;
1613         dev->av_tbl.pa = pa;
1614         dev->av_tbl.num_ah = max_ah;
1615         memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1616
1617         pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1618         for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1619                 pbes[i].pa_lo = (u32)cpu_to_le32(pa & 0xffffffff);
1620                 pbes[i].pa_hi = (u32)cpu_to_le32(upper_32_bits(pa));
1621                 pa += PAGE_SIZE;
1622         }
1623         cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1624         cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1625         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1626         if (status)
1627                 goto mbx_err;
1628         rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1629         dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1630         kfree(cmd);
1631         return 0;
1632
1633 mbx_err:
1634         dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1635                           dev->av_tbl.pa);
1636         dev->av_tbl.va = NULL;
1637 mem_err_ah:
1638         dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1639                           dev->av_tbl.pbl.pa);
1640         dev->av_tbl.pbl.va = NULL;
1641         dev->av_tbl.size = 0;
1642 mem_err:
1643         kfree(cmd);
1644         return status;
1645 }
1646
1647 static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1648 {
1649         struct ocrdma_delete_ah_tbl *cmd;
1650         struct pci_dev *pdev = dev->nic_info.pdev;
1651
1652         if (dev->av_tbl.va == NULL)
1653                 return;
1654
1655         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1656         if (!cmd)
1657                 return;
1658         cmd->ahid = dev->av_tbl.ahid;
1659
1660         ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1661         dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1662                           dev->av_tbl.pa);
1663         dev->av_tbl.va = NULL;
1664         dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1665                           dev->av_tbl.pbl.pa);
1666         kfree(cmd);
1667 }
1668
1669 /* Multiple CQs uses the EQ. This routine returns least used
1670  * EQ to associate with CQ. This will distributes the interrupt
1671  * processing and CPU load to associated EQ, vector and so to that CPU.
1672  */
1673 static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1674 {
1675         int i, selected_eq = 0, cq_cnt = 0;
1676         u16 eq_id;
1677
1678         mutex_lock(&dev->dev_lock);
1679         cq_cnt = dev->eq_tbl[0].cq_cnt;
1680         eq_id = dev->eq_tbl[0].q.id;
1681         /* find the EQ which is has the least number of
1682          * CQs associated with it.
1683          */
1684         for (i = 0; i < dev->eq_cnt; i++) {
1685                 if (dev->eq_tbl[i].cq_cnt < cq_cnt) {
1686                         cq_cnt = dev->eq_tbl[i].cq_cnt;
1687                         eq_id = dev->eq_tbl[i].q.id;
1688                         selected_eq = i;
1689                 }
1690         }
1691         dev->eq_tbl[selected_eq].cq_cnt += 1;
1692         mutex_unlock(&dev->dev_lock);
1693         return eq_id;
1694 }
1695
1696 static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1697 {
1698         int i;
1699
1700         mutex_lock(&dev->dev_lock);
1701         i = ocrdma_get_eq_table_index(dev, eq_id);
1702         if (i == -EINVAL)
1703                 BUG();
1704         dev->eq_tbl[i].cq_cnt -= 1;
1705         mutex_unlock(&dev->dev_lock);
1706 }
1707
1708 int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
1709                          int entries, int dpp_cq, u16 pd_id)
1710 {
1711         int status = -ENOMEM; int max_hw_cqe;
1712         struct pci_dev *pdev = dev->nic_info.pdev;
1713         struct ocrdma_create_cq *cmd;
1714         struct ocrdma_create_cq_rsp *rsp;
1715         u32 hw_pages, cqe_size, page_size, cqe_count;
1716
1717         if (entries > dev->attr.max_cqe) {
1718                 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1719                        __func__, dev->id, dev->attr.max_cqe, entries);
1720                 return -EINVAL;
1721         }
1722         if (dpp_cq && (ocrdma_get_asic_type(dev) != OCRDMA_ASIC_GEN_SKH_R))
1723                 return -EINVAL;
1724
1725         if (dpp_cq) {
1726                 cq->max_hw_cqe = 1;
1727                 max_hw_cqe = 1;
1728                 cqe_size = OCRDMA_DPP_CQE_SIZE;
1729                 hw_pages = 1;
1730         } else {
1731                 cq->max_hw_cqe = dev->attr.max_cqe;
1732                 max_hw_cqe = dev->attr.max_cqe;
1733                 cqe_size = sizeof(struct ocrdma_cqe);
1734                 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1735         }
1736
1737         cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1738
1739         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1740         if (!cmd)
1741                 return -ENOMEM;
1742         ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1743                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1744         cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1745         if (!cq->va) {
1746                 status = -ENOMEM;
1747                 goto mem_err;
1748         }
1749         memset(cq->va, 0, cq->len);
1750         page_size = cq->len / hw_pages;
1751         cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1752                                         OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1753         cmd->cmd.pgsz_pgcnt |= hw_pages;
1754         cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1755
1756         cq->eqn = ocrdma_bind_eq(dev);
1757         cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER3;
1758         cqe_count = cq->len / cqe_size;
1759         cq->cqe_cnt = cqe_count;
1760         if (cqe_count > 1024) {
1761                 /* Set cnt to 3 to indicate more than 1024 cq entries */
1762                 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
1763         } else {
1764                 u8 count = 0;
1765                 switch (cqe_count) {
1766                 case 256:
1767                         count = 0;
1768                         break;
1769                 case 512:
1770                         count = 1;
1771                         break;
1772                 case 1024:
1773                         count = 2;
1774                         break;
1775                 default:
1776                         goto mbx_err;
1777                 }
1778                 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1779         }
1780         /* shared eq between all the consumer cqs. */
1781         cmd->cmd.eqn = cq->eqn;
1782         if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1783                 if (dpp_cq)
1784                         cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1785                                 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1786                 cq->phase_change = false;
1787                 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size);
1788         } else {
1789                 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size) - 1;
1790                 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1791                 cq->phase_change = true;
1792         }
1793
1794         /* pd_id valid only for v3 */
1795         cmd->cmd.pdid_cqecnt |= (pd_id <<
1796                 OCRDMA_CREATE_CQ_CMD_PDID_SHIFT);
1797         ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1798         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1799         if (status)
1800                 goto mbx_err;
1801
1802         rsp = (struct ocrdma_create_cq_rsp *)cmd;
1803         cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1804         kfree(cmd);
1805         return 0;
1806 mbx_err:
1807         ocrdma_unbind_eq(dev, cq->eqn);
1808         dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1809 mem_err:
1810         kfree(cmd);
1811         return status;
1812 }
1813
1814 int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1815 {
1816         int status = -ENOMEM;
1817         struct ocrdma_destroy_cq *cmd;
1818
1819         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1820         if (!cmd)
1821                 return status;
1822         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1823                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1824
1825         cmd->bypass_flush_qid |=
1826             (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1827             OCRDMA_DESTROY_CQ_QID_MASK;
1828
1829         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1830         ocrdma_unbind_eq(dev, cq->eqn);
1831         dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
1832         kfree(cmd);
1833         return status;
1834 }
1835
1836 int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1837                           u32 pdid, int addr_check)
1838 {
1839         int status = -ENOMEM;
1840         struct ocrdma_alloc_lkey *cmd;
1841         struct ocrdma_alloc_lkey_rsp *rsp;
1842
1843         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1844         if (!cmd)
1845                 return status;
1846         cmd->pdid = pdid;
1847         cmd->pbl_sz_flags |= addr_check;
1848         cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1849         cmd->pbl_sz_flags |=
1850             (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1851         cmd->pbl_sz_flags |=
1852             (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1853         cmd->pbl_sz_flags |=
1854             (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1855         cmd->pbl_sz_flags |=
1856             (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1857         cmd->pbl_sz_flags |=
1858             (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1859
1860         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1861         if (status)
1862                 goto mbx_err;
1863         rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1864         hwmr->lkey = rsp->lrkey;
1865 mbx_err:
1866         kfree(cmd);
1867         return status;
1868 }
1869
1870 int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1871 {
1872         int status = -ENOMEM;
1873         struct ocrdma_dealloc_lkey *cmd;
1874
1875         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1876         if (!cmd)
1877                 return -ENOMEM;
1878         cmd->lkey = lkey;
1879         cmd->rsvd_frmr = fr_mr ? 1 : 0;
1880         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1881         if (status)
1882                 goto mbx_err;
1883 mbx_err:
1884         kfree(cmd);
1885         return status;
1886 }
1887
1888 static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1889                              u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1890 {
1891         int status = -ENOMEM;
1892         int i;
1893         struct ocrdma_reg_nsmr *cmd;
1894         struct ocrdma_reg_nsmr_rsp *rsp;
1895
1896         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1897         if (!cmd)
1898                 return -ENOMEM;
1899         cmd->num_pbl_pdid =
1900             pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
1901         cmd->fr_mr = hwmr->fr_mr;
1902
1903         cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1904                                     OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1905         cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1906                                     OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1907         cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1908                                     OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1909         cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1910                                     OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1911         cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1912                                     OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1913         cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1914
1915         cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1916         cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1917                                         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1918         cmd->totlen_low = hwmr->len;
1919         cmd->totlen_high = upper_32_bits(hwmr->len);
1920         cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1921         cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1922         cmd->va_loaddr = (u32) hwmr->va;
1923         cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1924
1925         for (i = 0; i < pbl_cnt; i++) {
1926                 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1927                 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
1928         }
1929         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1930         if (status)
1931                 goto mbx_err;
1932         rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
1933         hwmr->lkey = rsp->lrkey;
1934 mbx_err:
1935         kfree(cmd);
1936         return status;
1937 }
1938
1939 static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
1940                                   struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
1941                                   u32 pbl_offset, u32 last)
1942 {
1943         int status = -ENOMEM;
1944         int i;
1945         struct ocrdma_reg_nsmr_cont *cmd;
1946
1947         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
1948         if (!cmd)
1949                 return -ENOMEM;
1950         cmd->lrkey = hwmr->lkey;
1951         cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
1952             (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
1953         cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
1954
1955         for (i = 0; i < pbl_cnt; i++) {
1956                 cmd->pbl[i].lo =
1957                     (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
1958                 cmd->pbl[i].hi =
1959                     upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
1960         }
1961         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1962         if (status)
1963                 goto mbx_err;
1964 mbx_err:
1965         kfree(cmd);
1966         return status;
1967 }
1968
1969 int ocrdma_reg_mr(struct ocrdma_dev *dev,
1970                   struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
1971 {
1972         int status;
1973         u32 last = 0;
1974         u32 cur_pbl_cnt, pbl_offset;
1975         u32 pending_pbl_cnt = hwmr->num_pbls;
1976
1977         pbl_offset = 0;
1978         cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1979         if (cur_pbl_cnt == pending_pbl_cnt)
1980                 last = 1;
1981
1982         status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
1983                                    cur_pbl_cnt, hwmr->pbe_size, last);
1984         if (status) {
1985                 pr_err("%s() status=%d\n", __func__, status);
1986                 return status;
1987         }
1988         /* if there is no more pbls to register then exit. */
1989         if (last)
1990                 return 0;
1991
1992         while (!last) {
1993                 pbl_offset += cur_pbl_cnt;
1994                 pending_pbl_cnt -= cur_pbl_cnt;
1995                 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1996                 /* if we reach the end of the pbls, then need to set the last
1997                  * bit, indicating no more pbls to register for this memory key.
1998                  */
1999                 if (cur_pbl_cnt == pending_pbl_cnt)
2000                         last = 1;
2001
2002                 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
2003                                                 pbl_offset, last);
2004                 if (status)
2005                         break;
2006         }
2007         if (status)
2008                 pr_err("%s() err. status=%d\n", __func__, status);
2009
2010         return status;
2011 }
2012
2013 bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
2014 {
2015         struct ocrdma_qp *tmp;
2016         bool found = false;
2017         list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
2018                 if (qp == tmp) {
2019                         found = true;
2020                         break;
2021                 }
2022         }
2023         return found;
2024 }
2025
2026 bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
2027 {
2028         struct ocrdma_qp *tmp;
2029         bool found = false;
2030         list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
2031                 if (qp == tmp) {
2032                         found = true;
2033                         break;
2034                 }
2035         }
2036         return found;
2037 }
2038
2039 void ocrdma_flush_qp(struct ocrdma_qp *qp)
2040 {
2041         bool found;
2042         unsigned long flags;
2043
2044         spin_lock_irqsave(&qp->dev->flush_q_lock, flags);
2045         found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
2046         if (!found)
2047                 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
2048         if (!qp->srq) {
2049                 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
2050                 if (!found)
2051                         list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
2052         }
2053         spin_unlock_irqrestore(&qp->dev->flush_q_lock, flags);
2054 }
2055
2056 static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp)
2057 {
2058         qp->sq.head = 0;
2059         qp->sq.tail = 0;
2060         qp->rq.head = 0;
2061         qp->rq.tail = 0;
2062 }
2063
2064 int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
2065                            enum ib_qp_state *old_ib_state)
2066 {
2067         unsigned long flags;
2068         int status = 0;
2069         enum ocrdma_qp_state new_state;
2070         new_state = get_ocrdma_qp_state(new_ib_state);
2071
2072         /* sync with wqe and rqe posting */
2073         spin_lock_irqsave(&qp->q_lock, flags);
2074
2075         if (old_ib_state)
2076                 *old_ib_state = get_ibqp_state(qp->state);
2077         if (new_state == qp->state) {
2078                 spin_unlock_irqrestore(&qp->q_lock, flags);
2079                 return 1;
2080         }
2081
2082
2083         if (new_state == OCRDMA_QPS_INIT) {
2084                 ocrdma_init_hwq_ptr(qp);
2085                 ocrdma_del_flush_qp(qp);
2086         } else if (new_state == OCRDMA_QPS_ERR) {
2087                 ocrdma_flush_qp(qp);
2088         }
2089
2090         qp->state = new_state;
2091
2092         spin_unlock_irqrestore(&qp->q_lock, flags);
2093         return status;
2094 }
2095
2096 static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
2097 {
2098         u32 flags = 0;
2099         if (qp->cap_flags & OCRDMA_QP_INB_RD)
2100                 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
2101         if (qp->cap_flags & OCRDMA_QP_INB_WR)
2102                 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
2103         if (qp->cap_flags & OCRDMA_QP_MW_BIND)
2104                 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
2105         if (qp->cap_flags & OCRDMA_QP_LKEY0)
2106                 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
2107         if (qp->cap_flags & OCRDMA_QP_FAST_REG)
2108                 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
2109         return flags;
2110 }
2111
2112 static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
2113                                         struct ib_qp_init_attr *attrs,
2114                                         struct ocrdma_qp *qp)
2115 {
2116         int status;
2117         u32 len, hw_pages, hw_page_size;
2118         dma_addr_t pa;
2119         struct ocrdma_dev *dev = qp->dev;
2120         struct pci_dev *pdev = dev->nic_info.pdev;
2121         u32 max_wqe_allocated;
2122         u32 max_sges = attrs->cap.max_send_sge;
2123
2124         /* QP1 may exceed 127 */
2125         max_wqe_allocated = min_t(u32, attrs->cap.max_send_wr + 1,
2126                                 dev->attr.max_wqe);
2127
2128         status = ocrdma_build_q_conf(&max_wqe_allocated,
2129                 dev->attr.wqe_size, &hw_pages, &hw_page_size);
2130         if (status) {
2131                 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
2132                        max_wqe_allocated);
2133                 return -EINVAL;
2134         }
2135         qp->sq.max_cnt = max_wqe_allocated;
2136         len = (hw_pages * hw_page_size);
2137
2138         qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2139         if (!qp->sq.va)
2140                 return -EINVAL;
2141         memset(qp->sq.va, 0, len);
2142         qp->sq.len = len;
2143         qp->sq.pa = pa;
2144         qp->sq.entry_size = dev->attr.wqe_size;
2145         ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
2146
2147         cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2148                                 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
2149         cmd->num_wq_rq_pages |= (hw_pages <<
2150                                  OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
2151             OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
2152         cmd->max_sge_send_write |= (max_sges <<
2153                                     OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
2154             OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
2155         cmd->max_sge_send_write |= (max_sges <<
2156                                     OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
2157                                         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
2158         cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
2159                              OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
2160                                 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
2161         cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
2162                               OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
2163                                 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
2164         return 0;
2165 }
2166
2167 static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
2168                                         struct ib_qp_init_attr *attrs,
2169                                         struct ocrdma_qp *qp)
2170 {
2171         int status;
2172         u32 len, hw_pages, hw_page_size;
2173         dma_addr_t pa = 0;
2174         struct ocrdma_dev *dev = qp->dev;
2175         struct pci_dev *pdev = dev->nic_info.pdev;
2176         u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
2177
2178         status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
2179                                      &hw_pages, &hw_page_size);
2180         if (status) {
2181                 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
2182                        attrs->cap.max_recv_wr + 1);
2183                 return status;
2184         }
2185         qp->rq.max_cnt = max_rqe_allocated;
2186         len = (hw_pages * hw_page_size);
2187
2188         qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2189         if (!qp->rq.va)
2190                 return -ENOMEM;
2191         memset(qp->rq.va, 0, len);
2192         qp->rq.pa = pa;
2193         qp->rq.len = len;
2194         qp->rq.entry_size = dev->attr.rqe_size;
2195
2196         ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2197         cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
2198                 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
2199         cmd->num_wq_rq_pages |=
2200             (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
2201             OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
2202         cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
2203                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
2204                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
2205         cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
2206                                 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
2207                                 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
2208         cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
2209                         OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
2210                         OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
2211         return 0;
2212 }
2213
2214 static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
2215                                          struct ocrdma_pd *pd,
2216                                          struct ocrdma_qp *qp,
2217                                          u8 enable_dpp_cq, u16 dpp_cq_id)
2218 {
2219         pd->num_dpp_qp--;
2220         qp->dpp_enabled = true;
2221         cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2222         if (!enable_dpp_cq)
2223                 return;
2224         cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2225         cmd->dpp_credits_cqid = dpp_cq_id;
2226         cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
2227                                         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
2228 }
2229
2230 static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
2231                                         struct ocrdma_qp *qp)
2232 {
2233         struct ocrdma_dev *dev = qp->dev;
2234         struct pci_dev *pdev = dev->nic_info.pdev;
2235         dma_addr_t pa = 0;
2236         int ird_page_size = dev->attr.ird_page_size;
2237         int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
2238         struct ocrdma_hdr_wqe *rqe;
2239         int i  = 0;
2240
2241         if (dev->attr.ird == 0)
2242                 return 0;
2243
2244         qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
2245                                         &pa, GFP_KERNEL);
2246         if (!qp->ird_q_va)
2247                 return -ENOMEM;
2248         memset(qp->ird_q_va, 0, ird_q_len);
2249         ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
2250                              pa, ird_page_size);
2251         for (; i < ird_q_len / dev->attr.rqe_size; i++) {
2252                 rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va +
2253                         (i * dev->attr.rqe_size));
2254                 rqe->cw = 0;
2255                 rqe->cw |= 2;
2256                 rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
2257                 rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT);
2258                 rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT);
2259         }
2260         return 0;
2261 }
2262
2263 static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
2264                                      struct ocrdma_qp *qp,
2265                                      struct ib_qp_init_attr *attrs,
2266                                      u16 *dpp_offset, u16 *dpp_credit_lmt)
2267 {
2268         u32 max_wqe_allocated, max_rqe_allocated;
2269         qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
2270         qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
2271         qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
2272         qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
2273         qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
2274         qp->dpp_enabled = false;
2275         if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
2276                 qp->dpp_enabled = true;
2277                 *dpp_credit_lmt = (rsp->dpp_response &
2278                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
2279                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
2280                 *dpp_offset = (rsp->dpp_response &
2281                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
2282                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
2283         }
2284         max_wqe_allocated =
2285                 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
2286         max_wqe_allocated = 1 << max_wqe_allocated;
2287         max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
2288
2289         qp->sq.max_cnt = max_wqe_allocated;
2290         qp->sq.max_wqe_idx = max_wqe_allocated - 1;
2291
2292         if (!attrs->srq) {
2293                 qp->rq.max_cnt = max_rqe_allocated;
2294                 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
2295         }
2296 }
2297
2298 int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
2299                          u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
2300                          u16 *dpp_credit_lmt)
2301 {
2302         int status = -ENOMEM;
2303         u32 flags = 0;
2304         struct ocrdma_dev *dev = qp->dev;
2305         struct ocrdma_pd *pd = qp->pd;
2306         struct pci_dev *pdev = dev->nic_info.pdev;
2307         struct ocrdma_cq *cq;
2308         struct ocrdma_create_qp_req *cmd;
2309         struct ocrdma_create_qp_rsp *rsp;
2310         int qptype;
2311
2312         switch (attrs->qp_type) {
2313         case IB_QPT_GSI:
2314                 qptype = OCRDMA_QPT_GSI;
2315                 break;
2316         case IB_QPT_RC:
2317                 qptype = OCRDMA_QPT_RC;
2318                 break;
2319         case IB_QPT_UD:
2320                 qptype = OCRDMA_QPT_UD;
2321                 break;
2322         default:
2323                 return -EINVAL;
2324         }
2325
2326         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
2327         if (!cmd)
2328                 return status;
2329         cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
2330                                                 OCRDMA_CREATE_QP_REQ_QPT_MASK;
2331         status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
2332         if (status)
2333                 goto sq_err;
2334
2335         if (attrs->srq) {
2336                 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
2337                 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
2338                 cmd->rq_addr[0].lo = srq->id;
2339                 qp->srq = srq;
2340         } else {
2341                 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2342                 if (status)
2343                         goto rq_err;
2344         }
2345
2346         status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2347         if (status)
2348                 goto mbx_err;
2349
2350         cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2351                                 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2352
2353         flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2354
2355         cmd->max_sge_recv_flags |= flags;
2356         cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2357                              OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2358                                 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2359         cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2360                              OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2361                                 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2362         cq = get_ocrdma_cq(attrs->send_cq);
2363         cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2364                                 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2365         qp->sq_cq = cq;
2366         cq = get_ocrdma_cq(attrs->recv_cq);
2367         cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2368                                 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2369         qp->rq_cq = cq;
2370
2371         if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
2372             (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) {
2373                 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2374                                              dpp_cq_id);
2375         }
2376
2377         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2378         if (status)
2379                 goto mbx_err;
2380         rsp = (struct ocrdma_create_qp_rsp *)cmd;
2381         ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2382         qp->state = OCRDMA_QPS_RST;
2383         kfree(cmd);
2384         return 0;
2385 mbx_err:
2386         if (qp->rq.va)
2387                 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2388 rq_err:
2389         pr_err("%s(%d) rq_err\n", __func__, dev->id);
2390         dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2391 sq_err:
2392         pr_err("%s(%d) sq_err\n", __func__, dev->id);
2393         kfree(cmd);
2394         return status;
2395 }
2396
2397 int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2398                         struct ocrdma_qp_params *param)
2399 {
2400         int status = -ENOMEM;
2401         struct ocrdma_query_qp *cmd;
2402         struct ocrdma_query_qp_rsp *rsp;
2403
2404         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd));
2405         if (!cmd)
2406                 return status;
2407         cmd->qp_id = qp->id;
2408         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2409         if (status)
2410                 goto mbx_err;
2411         rsp = (struct ocrdma_query_qp_rsp *)cmd;
2412         memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2413 mbx_err:
2414         kfree(cmd);
2415         return status;
2416 }
2417
2418 static int ocrdma_set_av_params(struct ocrdma_qp *qp,
2419                                 struct ocrdma_modify_qp *cmd,
2420                                 struct ib_qp_attr *attrs,
2421                                 int attr_mask)
2422 {
2423         int status;
2424         struct ib_ah_attr *ah_attr = &attrs->ah_attr;
2425         union ib_gid sgid, zgid;
2426         u32 vlan_id;
2427         u8 mac_addr[6];
2428
2429         if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
2430                 return -EINVAL;
2431         if (atomic_cmpxchg(&qp->dev->update_sl, 1, 0))
2432                 ocrdma_init_service_level(qp->dev);
2433         cmd->params.tclass_sq_psn |=
2434             (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2435         cmd->params.rnt_rc_sl_fl |=
2436             (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2437         cmd->params.rnt_rc_sl_fl |= (ah_attr->sl << OCRDMA_QP_PARAMS_SL_SHIFT);
2438         cmd->params.hop_lmt_rq_psn |=
2439             (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2440         cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2441         memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2442                sizeof(cmd->params.dgid));
2443         status = ocrdma_query_gid(&qp->dev->ibdev, 1,
2444                         ah_attr->grh.sgid_index, &sgid);
2445         if (status)
2446                 return status;
2447
2448         memset(&zgid, 0, sizeof(zgid));
2449         if (!memcmp(&sgid, &zgid, sizeof(zgid)))
2450                 return -EINVAL;
2451
2452         qp->sgid_idx = ah_attr->grh.sgid_index;
2453         memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
2454         ocrdma_resolve_dmac(qp->dev, ah_attr, &mac_addr[0]);
2455         cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2456                                 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2457         /* convert them to LE format. */
2458         ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2459         ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2460         cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
2461         if (attr_mask & IB_QP_VID) {
2462                 vlan_id = attrs->vlan_id;
2463                 cmd->params.vlan_dmac_b4_to_b5 |=
2464                     vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2465                 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2466                 cmd->params.rnt_rc_sl_fl |=
2467                         (qp->dev->sl & 0x07) << OCRDMA_QP_PARAMS_SL_SHIFT;
2468         }
2469         return 0;
2470 }
2471
2472 static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2473                                 struct ocrdma_modify_qp *cmd,
2474                                 struct ib_qp_attr *attrs, int attr_mask)
2475 {
2476         int status = 0;
2477
2478         if (attr_mask & IB_QP_PKEY_INDEX) {
2479                 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2480                                             OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2481                 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2482         }
2483         if (attr_mask & IB_QP_QKEY) {
2484                 qp->qkey = attrs->qkey;
2485                 cmd->params.qkey = attrs->qkey;
2486                 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2487         }
2488         if (attr_mask & IB_QP_AV) {
2489                 status = ocrdma_set_av_params(qp, cmd, attrs, attr_mask);
2490                 if (status)
2491                         return status;
2492         } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
2493                 /* set the default mac address for UD, GSI QPs */
2494                 cmd->params.dmac_b0_to_b3 = qp->dev->nic_info.mac_addr[0] |
2495                         (qp->dev->nic_info.mac_addr[1] << 8) |
2496                         (qp->dev->nic_info.mac_addr[2] << 16) |
2497                         (qp->dev->nic_info.mac_addr[3] << 24);
2498                 cmd->params.vlan_dmac_b4_to_b5 = qp->dev->nic_info.mac_addr[4] |
2499                                         (qp->dev->nic_info.mac_addr[5] << 8);
2500         }
2501         if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2502             attrs->en_sqd_async_notify) {
2503                 cmd->params.max_sge_recv_flags |=
2504                         OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2505                 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2506         }
2507         if (attr_mask & IB_QP_DEST_QPN) {
2508                 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2509                                 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2510                 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2511         }
2512         if (attr_mask & IB_QP_PATH_MTU) {
2513                 if (attrs->path_mtu < IB_MTU_256 ||
2514                     attrs->path_mtu > IB_MTU_4096) {
2515                         status = -EINVAL;
2516                         goto pmtu_err;
2517                 }
2518                 cmd->params.path_mtu_pkey_indx |=
2519                     (ib_mtu_enum_to_int(attrs->path_mtu) <<
2520                      OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2521                     OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2522                 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2523         }
2524         if (attr_mask & IB_QP_TIMEOUT) {
2525                 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2526                     OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2527                 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2528         }
2529         if (attr_mask & IB_QP_RETRY_CNT) {
2530                 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2531                                       OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2532                     OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2533                 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2534         }
2535         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2536                 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2537                                       OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2538                     OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2539                 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2540         }
2541         if (attr_mask & IB_QP_RNR_RETRY) {
2542                 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2543                         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2544                         & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2545                 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2546         }
2547         if (attr_mask & IB_QP_SQ_PSN) {
2548                 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2549                 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2550         }
2551         if (attr_mask & IB_QP_RQ_PSN) {
2552                 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2553                 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2554         }
2555         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2556                 if (attrs->max_rd_atomic > qp->dev->attr.max_ord_per_qp) {
2557                         status = -EINVAL;
2558                         goto pmtu_err;
2559                 }
2560                 qp->max_ord = attrs->max_rd_atomic;
2561                 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2562         }
2563         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2564                 if (attrs->max_dest_rd_atomic > qp->dev->attr.max_ird_per_qp) {
2565                         status = -EINVAL;
2566                         goto pmtu_err;
2567                 }
2568                 qp->max_ird = attrs->max_dest_rd_atomic;
2569                 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2570         }
2571         cmd->params.max_ord_ird = (qp->max_ord <<
2572                                 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2573                                 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2574 pmtu_err:
2575         return status;
2576 }
2577
2578 int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2579                          struct ib_qp_attr *attrs, int attr_mask)
2580 {
2581         int status = -ENOMEM;
2582         struct ocrdma_modify_qp *cmd;
2583
2584         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2585         if (!cmd)
2586                 return status;
2587
2588         cmd->params.id = qp->id;
2589         cmd->flags = 0;
2590         if (attr_mask & IB_QP_STATE) {
2591                 cmd->params.max_sge_recv_flags |=
2592                     (get_ocrdma_qp_state(attrs->qp_state) <<
2593                      OCRDMA_QP_PARAMS_STATE_SHIFT) &
2594                     OCRDMA_QP_PARAMS_STATE_MASK;
2595                 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
2596         } else {
2597                 cmd->params.max_sge_recv_flags |=
2598                     (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2599                     OCRDMA_QP_PARAMS_STATE_MASK;
2600         }
2601
2602         status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask);
2603         if (status)
2604                 goto mbx_err;
2605         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2606         if (status)
2607                 goto mbx_err;
2608
2609 mbx_err:
2610         kfree(cmd);
2611         return status;
2612 }
2613
2614 int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2615 {
2616         int status = -ENOMEM;
2617         struct ocrdma_destroy_qp *cmd;
2618         struct pci_dev *pdev = dev->nic_info.pdev;
2619
2620         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2621         if (!cmd)
2622                 return status;
2623         cmd->qp_id = qp->id;
2624         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2625         if (status)
2626                 goto mbx_err;
2627
2628 mbx_err:
2629         kfree(cmd);
2630         if (qp->sq.va)
2631                 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2632         if (!qp->srq && qp->rq.va)
2633                 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2634         if (qp->dpp_enabled)
2635                 qp->pd->num_dpp_qp++;
2636         return status;
2637 }
2638
2639 int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
2640                           struct ib_srq_init_attr *srq_attr,
2641                           struct ocrdma_pd *pd)
2642 {
2643         int status = -ENOMEM;
2644         int hw_pages, hw_page_size;
2645         int len;
2646         struct ocrdma_create_srq_rsp *rsp;
2647         struct ocrdma_create_srq *cmd;
2648         dma_addr_t pa;
2649         struct pci_dev *pdev = dev->nic_info.pdev;
2650         u32 max_rqe_allocated;
2651
2652         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2653         if (!cmd)
2654                 return status;
2655
2656         cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2657         max_rqe_allocated = srq_attr->attr.max_wr + 1;
2658         status = ocrdma_build_q_conf(&max_rqe_allocated,
2659                                 dev->attr.rqe_size,
2660                                 &hw_pages, &hw_page_size);
2661         if (status) {
2662                 pr_err("%s() req. max_wr=0x%x\n", __func__,
2663                        srq_attr->attr.max_wr);
2664                 status = -EINVAL;
2665                 goto ret;
2666         }
2667         len = hw_pages * hw_page_size;
2668         srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2669         if (!srq->rq.va) {
2670                 status = -ENOMEM;
2671                 goto ret;
2672         }
2673         ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2674
2675         srq->rq.entry_size = dev->attr.rqe_size;
2676         srq->rq.pa = pa;
2677         srq->rq.len = len;
2678         srq->rq.max_cnt = max_rqe_allocated;
2679
2680         cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2681         cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2682                                 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2683
2684         cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2685                 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2686         cmd->pages_rqe_sz |= (dev->attr.rqe_size
2687                 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2688                 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2689         cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2690
2691         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2692         if (status)
2693                 goto mbx_err;
2694         rsp = (struct ocrdma_create_srq_rsp *)cmd;
2695         srq->id = rsp->id;
2696         srq->rq.dbid = rsp->id;
2697         max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2698                 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2699                 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2700         max_rqe_allocated = (1 << max_rqe_allocated);
2701         srq->rq.max_cnt = max_rqe_allocated;
2702         srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2703         srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2704                 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2705                 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2706         goto ret;
2707 mbx_err:
2708         dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2709 ret:
2710         kfree(cmd);
2711         return status;
2712 }
2713
2714 int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2715 {
2716         int status = -ENOMEM;
2717         struct ocrdma_modify_srq *cmd;
2718         struct ocrdma_pd *pd = srq->pd;
2719         struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2720
2721         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_SRQ, sizeof(*cmd));
2722         if (!cmd)
2723                 return status;
2724         cmd->id = srq->id;
2725         cmd->limit_max_rqe |= srq_attr->srq_limit <<
2726             OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
2727         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2728         kfree(cmd);
2729         return status;
2730 }
2731
2732 int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2733 {
2734         int status = -ENOMEM;
2735         struct ocrdma_query_srq *cmd;
2736         struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2737
2738         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_SRQ, sizeof(*cmd));
2739         if (!cmd)
2740                 return status;
2741         cmd->id = srq->rq.dbid;
2742         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2743         if (status == 0) {
2744                 struct ocrdma_query_srq_rsp *rsp =
2745                     (struct ocrdma_query_srq_rsp *)cmd;
2746                 srq_attr->max_sge =
2747                     rsp->srq_lmt_max_sge &
2748                     OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2749                 srq_attr->max_wr =
2750                     rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2751                 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2752                     OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2753         }
2754         kfree(cmd);
2755         return status;
2756 }
2757
2758 int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2759 {
2760         int status = -ENOMEM;
2761         struct ocrdma_destroy_srq *cmd;
2762         struct pci_dev *pdev = dev->nic_info.pdev;
2763         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2764         if (!cmd)
2765                 return status;
2766         cmd->id = srq->id;
2767         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2768         if (srq->rq.va)
2769                 dma_free_coherent(&pdev->dev, srq->rq.len,
2770                                   srq->rq.va, srq->rq.pa);
2771         kfree(cmd);
2772         return status;
2773 }
2774
2775 static int ocrdma_mbx_get_dcbx_config(struct ocrdma_dev *dev, u32 ptype,
2776                                       struct ocrdma_dcbx_cfg *dcbxcfg)
2777 {
2778         int status = 0;
2779         dma_addr_t pa;
2780         struct ocrdma_mqe cmd;
2781
2782         struct ocrdma_get_dcbx_cfg_req *req = NULL;
2783         struct ocrdma_get_dcbx_cfg_rsp *rsp = NULL;
2784         struct pci_dev *pdev = dev->nic_info.pdev;
2785         struct ocrdma_mqe_sge *mqe_sge = cmd.u.nonemb_req.sge;
2786
2787         memset(&cmd, 0, sizeof(struct ocrdma_mqe));
2788         cmd.hdr.pyld_len = max_t (u32, sizeof(struct ocrdma_get_dcbx_cfg_rsp),
2789                                         sizeof(struct ocrdma_get_dcbx_cfg_req));
2790         req = dma_alloc_coherent(&pdev->dev, cmd.hdr.pyld_len, &pa, GFP_KERNEL);
2791         if (!req) {
2792                 status = -ENOMEM;
2793                 goto mem_err;
2794         }
2795
2796         cmd.hdr.spcl_sge_cnt_emb |= (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
2797                                         OCRDMA_MQE_HDR_SGE_CNT_MASK;
2798         mqe_sge->pa_lo = (u32) (pa & 0xFFFFFFFFUL);
2799         mqe_sge->pa_hi = (u32) upper_32_bits(pa);
2800         mqe_sge->len = cmd.hdr.pyld_len;
2801
2802         memset(req, 0, sizeof(struct ocrdma_get_dcbx_cfg_req));
2803         ocrdma_init_mch(&req->hdr, OCRDMA_CMD_GET_DCBX_CONFIG,
2804                         OCRDMA_SUBSYS_DCBX, cmd.hdr.pyld_len);
2805         req->param_type = ptype;
2806
2807         status = ocrdma_mbx_cmd(dev, &cmd);
2808         if (status)
2809                 goto mbx_err;
2810
2811         rsp = (struct ocrdma_get_dcbx_cfg_rsp *)req;
2812         ocrdma_le32_to_cpu(rsp, sizeof(struct ocrdma_get_dcbx_cfg_rsp));
2813         memcpy(dcbxcfg, &rsp->cfg, sizeof(struct ocrdma_dcbx_cfg));
2814
2815 mbx_err:
2816         dma_free_coherent(&pdev->dev, cmd.hdr.pyld_len, req, pa);
2817 mem_err:
2818         return status;
2819 }
2820
2821 #define OCRDMA_MAX_SERVICE_LEVEL_INDEX  0x08
2822 #define OCRDMA_DEFAULT_SERVICE_LEVEL    0x05
2823
2824 static int ocrdma_parse_dcbxcfg_rsp(struct ocrdma_dev *dev, int ptype,
2825                                     struct ocrdma_dcbx_cfg *dcbxcfg,
2826                                     u8 *srvc_lvl)
2827 {
2828         int status = -EINVAL, indx, slindx;
2829         int ventry_cnt;
2830         struct ocrdma_app_parameter *app_param;
2831         u8 valid, proto_sel;
2832         u8 app_prio, pfc_prio;
2833         u16 proto;
2834
2835         if (!(dcbxcfg->tcv_aev_opv_st & OCRDMA_DCBX_STATE_MASK)) {
2836                 pr_info("%s ocrdma%d DCBX is disabled\n",
2837                         dev_name(&dev->nic_info.pdev->dev), dev->id);
2838                 goto out;
2839         }
2840
2841         if (!ocrdma_is_enabled_and_synced(dcbxcfg->pfc_state)) {
2842                 pr_info("%s ocrdma%d priority flow control(%s) is %s%s\n",
2843                         dev_name(&dev->nic_info.pdev->dev), dev->id,
2844                         (ptype > 0 ? "operational" : "admin"),
2845                         (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_ENABLED) ?
2846                         "enabled" : "disabled",
2847                         (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_SYNC) ?
2848                         "" : ", not sync'ed");
2849                 goto out;
2850         } else {
2851                 pr_info("%s ocrdma%d priority flow control is enabled and sync'ed\n",
2852                         dev_name(&dev->nic_info.pdev->dev), dev->id);
2853         }
2854
2855         ventry_cnt = (dcbxcfg->tcv_aev_opv_st >>
2856                                 OCRDMA_DCBX_APP_ENTRY_SHIFT)
2857                                 & OCRDMA_DCBX_STATE_MASK;
2858
2859         for (indx = 0; indx < ventry_cnt; indx++) {
2860                 app_param = &dcbxcfg->app_param[indx];
2861                 valid = (app_param->valid_proto_app >>
2862                                 OCRDMA_APP_PARAM_VALID_SHIFT)
2863                                 & OCRDMA_APP_PARAM_VALID_MASK;
2864                 proto_sel = (app_param->valid_proto_app
2865                                 >>  OCRDMA_APP_PARAM_PROTO_SEL_SHIFT)
2866                                 & OCRDMA_APP_PARAM_PROTO_SEL_MASK;
2867                 proto = app_param->valid_proto_app &
2868                                 OCRDMA_APP_PARAM_APP_PROTO_MASK;
2869
2870                 if (
2871                         valid && proto == OCRDMA_APP_PROTO_ROCE &&
2872                         proto_sel == OCRDMA_PROTO_SELECT_L2) {
2873                         for (slindx = 0; slindx <
2874                                 OCRDMA_MAX_SERVICE_LEVEL_INDEX; slindx++) {
2875                                 app_prio = ocrdma_get_app_prio(
2876                                                 (u8 *)app_param->app_prio,
2877                                                 slindx);
2878                                 pfc_prio = ocrdma_get_pfc_prio(
2879                                                 (u8 *)dcbxcfg->pfc_prio,
2880                                                 slindx);
2881
2882                                 if (app_prio && pfc_prio) {
2883                                         *srvc_lvl = slindx;
2884                                         status = 0;
2885                                         goto out;
2886                                 }
2887                         }
2888                         if (slindx == OCRDMA_MAX_SERVICE_LEVEL_INDEX) {
2889                                 pr_info("%s ocrdma%d application priority not set for 0x%x protocol\n",
2890                                         dev_name(&dev->nic_info.pdev->dev),
2891                                         dev->id, proto);
2892                         }
2893                 }
2894         }
2895
2896 out:
2897         return status;
2898 }
2899
2900 void ocrdma_init_service_level(struct ocrdma_dev *dev)
2901 {
2902         int status = 0, indx;
2903         struct ocrdma_dcbx_cfg dcbxcfg;
2904         u8 srvc_lvl = OCRDMA_DEFAULT_SERVICE_LEVEL;
2905         int ptype = OCRDMA_PARAMETER_TYPE_OPER;
2906
2907         for (indx = 0; indx < 2; indx++) {
2908                 status = ocrdma_mbx_get_dcbx_config(dev, ptype, &dcbxcfg);
2909                 if (status) {
2910                         pr_err("%s(): status=%d\n", __func__, status);
2911                         ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
2912                         continue;
2913                 }
2914
2915                 status = ocrdma_parse_dcbxcfg_rsp(dev, ptype,
2916                                                   &dcbxcfg, &srvc_lvl);
2917                 if (status) {
2918                         ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
2919                         continue;
2920                 }
2921
2922                 break;
2923         }
2924
2925         if (status)
2926                 pr_info("%s ocrdma%d service level default\n",
2927                         dev_name(&dev->nic_info.pdev->dev), dev->id);
2928         else
2929                 pr_info("%s ocrdma%d service level %d\n",
2930                         dev_name(&dev->nic_info.pdev->dev), dev->id,
2931                         srvc_lvl);
2932
2933         dev->pfc_state = ocrdma_is_enabled_and_synced(dcbxcfg.pfc_state);
2934         dev->sl = srvc_lvl;
2935 }
2936
2937 int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2938 {
2939         int i;
2940         int status = -EINVAL;
2941         struct ocrdma_av *av;
2942         unsigned long flags;
2943
2944         av = dev->av_tbl.va;
2945         spin_lock_irqsave(&dev->av_tbl.lock, flags);
2946         for (i = 0; i < dev->av_tbl.num_ah; i++) {
2947                 if (av->valid == 0) {
2948                         av->valid = OCRDMA_AV_VALID;
2949                         ah->av = av;
2950                         ah->id = i;
2951                         status = 0;
2952                         break;
2953                 }
2954                 av++;
2955         }
2956         if (i == dev->av_tbl.num_ah)
2957                 status = -EAGAIN;
2958         spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2959         return status;
2960 }
2961
2962 int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2963 {
2964         unsigned long flags;
2965         spin_lock_irqsave(&dev->av_tbl.lock, flags);
2966         ah->av->valid = 0;
2967         spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2968         return 0;
2969 }
2970
2971 static int ocrdma_create_eqs(struct ocrdma_dev *dev)
2972 {
2973         int num_eq, i, status = 0;
2974         int irq;
2975         unsigned long flags = 0;
2976
2977         num_eq = dev->nic_info.msix.num_vectors -
2978                         dev->nic_info.msix.start_vector;
2979         if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
2980                 num_eq = 1;
2981                 flags = IRQF_SHARED;
2982         } else {
2983                 num_eq = min_t(u32, num_eq, num_online_cpus());
2984         }
2985
2986         if (!num_eq)
2987                 return -EINVAL;
2988
2989         dev->eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
2990         if (!dev->eq_tbl)
2991                 return -ENOMEM;
2992
2993         for (i = 0; i < num_eq; i++) {
2994                 status = ocrdma_create_eq(dev, &dev->eq_tbl[i],
2995                                         OCRDMA_EQ_LEN);
2996                 if (status) {
2997                         status = -EINVAL;
2998                         break;
2999                 }
3000                 sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d",
3001                         dev->id, i);
3002                 irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]);
3003                 status = request_irq(irq, ocrdma_irq_handler, flags,
3004                                      dev->eq_tbl[i].irq_name,
3005                                      &dev->eq_tbl[i]);
3006                 if (status)
3007                         goto done;
3008                 dev->eq_cnt += 1;
3009         }
3010         /* one eq is sufficient for data path to work */
3011         return 0;
3012 done:
3013         ocrdma_destroy_eqs(dev);
3014         return status;
3015 }
3016
3017 int ocrdma_init_hw(struct ocrdma_dev *dev)
3018 {
3019         int status;
3020
3021         /* create the eqs  */
3022         status = ocrdma_create_eqs(dev);
3023         if (status)
3024                 goto qpeq_err;
3025         status = ocrdma_create_mq(dev);
3026         if (status)
3027                 goto mq_err;
3028         status = ocrdma_mbx_query_fw_config(dev);
3029         if (status)
3030                 goto conf_err;
3031         status = ocrdma_mbx_query_dev(dev);
3032         if (status)
3033                 goto conf_err;
3034         status = ocrdma_mbx_query_fw_ver(dev);
3035         if (status)
3036                 goto conf_err;
3037         status = ocrdma_mbx_create_ah_tbl(dev);
3038         if (status)
3039                 goto conf_err;
3040         status = ocrdma_mbx_get_phy_info(dev);
3041         if (status)
3042                 goto info_attrb_err;
3043         status = ocrdma_mbx_get_ctrl_attribs(dev);
3044         if (status)
3045                 goto info_attrb_err;
3046
3047         return 0;
3048
3049 info_attrb_err:
3050         ocrdma_mbx_delete_ah_tbl(dev);
3051 conf_err:
3052         ocrdma_destroy_mq(dev);
3053 mq_err:
3054         ocrdma_destroy_eqs(dev);
3055 qpeq_err:
3056         pr_err("%s() status=%d\n", __func__, status);
3057         return status;
3058 }
3059
3060 void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
3061 {
3062         ocrdma_free_pd_pool(dev);
3063         ocrdma_mbx_delete_ah_tbl(dev);
3064
3065         /* cleanup the eqs */
3066         ocrdma_destroy_eqs(dev);
3067
3068         /* cleanup the control path */
3069         ocrdma_destroy_mq(dev);
3070 }