2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <asm/msidef.h>
35 #include <asm/proto.h>
36 #include <asm/iommu.h>
40 #include "amd_iommu_proto.h"
41 #include "amd_iommu_types.h"
43 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
45 #define LOOP_TIMEOUT 100000
47 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
49 /* A list of preallocated protection domains */
50 static LIST_HEAD(iommu_pd_list);
51 static DEFINE_SPINLOCK(iommu_pd_list_lock);
53 /* List of all available dev_data structures */
54 static LIST_HEAD(dev_data_list);
55 static DEFINE_SPINLOCK(dev_data_list_lock);
58 * Domain for untranslated devices - only allocated
59 * if iommu=pt passed on kernel cmd line.
61 static struct protection_domain *pt_domain;
63 static struct iommu_ops amd_iommu_ops;
65 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
66 int amd_iommu_max_glx_val = -1;
69 * general struct to manage commands send to an IOMMU
75 static void update_domain(struct protection_domain *domain);
76 static int __init alloc_passthrough_domain(void);
78 /****************************************************************************
82 ****************************************************************************/
84 static struct iommu_dev_data *alloc_dev_data(u16 devid)
86 struct iommu_dev_data *dev_data;
89 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
93 dev_data->devid = devid;
94 atomic_set(&dev_data->bind, 0);
96 spin_lock_irqsave(&dev_data_list_lock, flags);
97 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
98 spin_unlock_irqrestore(&dev_data_list_lock, flags);
103 static void free_dev_data(struct iommu_dev_data *dev_data)
107 spin_lock_irqsave(&dev_data_list_lock, flags);
108 list_del(&dev_data->dev_data_list);
109 spin_unlock_irqrestore(&dev_data_list_lock, flags);
114 static struct iommu_dev_data *search_dev_data(u16 devid)
116 struct iommu_dev_data *dev_data;
119 spin_lock_irqsave(&dev_data_list_lock, flags);
120 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
121 if (dev_data->devid == devid)
128 spin_unlock_irqrestore(&dev_data_list_lock, flags);
133 static struct iommu_dev_data *find_dev_data(u16 devid)
135 struct iommu_dev_data *dev_data;
137 dev_data = search_dev_data(devid);
139 if (dev_data == NULL)
140 dev_data = alloc_dev_data(devid);
145 static inline u16 get_device_id(struct device *dev)
147 struct pci_dev *pdev = to_pci_dev(dev);
149 return calc_devid(pdev->bus->number, pdev->devfn);
152 static struct iommu_dev_data *get_dev_data(struct device *dev)
154 return dev->archdata.iommu;
157 static bool pci_iommuv2_capable(struct pci_dev *pdev)
159 static const int caps[] = {
166 for (i = 0; i < 3; ++i) {
167 pos = pci_find_ext_capability(pdev, caps[i]);
175 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
177 struct iommu_dev_data *dev_data;
179 dev_data = get_dev_data(&pdev->dev);
181 return dev_data->errata & (1 << erratum) ? true : false;
185 * In this function the list of preallocated protection domains is traversed to
186 * find the domain for a specific device
188 static struct dma_ops_domain *find_protection_domain(u16 devid)
190 struct dma_ops_domain *entry, *ret = NULL;
192 u16 alias = amd_iommu_alias_table[devid];
194 if (list_empty(&iommu_pd_list))
197 spin_lock_irqsave(&iommu_pd_list_lock, flags);
199 list_for_each_entry(entry, &iommu_pd_list, list) {
200 if (entry->target_dev == devid ||
201 entry->target_dev == alias) {
207 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
213 * This function checks if the driver got a valid device from the caller to
214 * avoid dereferencing invalid pointers.
216 static bool check_device(struct device *dev)
220 if (!dev || !dev->dma_mask)
223 /* No device or no PCI device */
224 if (dev->bus != &pci_bus_type)
227 devid = get_device_id(dev);
229 /* Out of our scope? */
230 if (devid > amd_iommu_last_bdf)
233 if (amd_iommu_rlookup_table[devid] == NULL)
239 static int iommu_init_device(struct device *dev)
241 struct pci_dev *pdev = to_pci_dev(dev);
242 struct iommu_dev_data *dev_data;
245 if (dev->archdata.iommu)
248 dev_data = find_dev_data(get_device_id(dev));
252 alias = amd_iommu_alias_table[dev_data->devid];
253 if (alias != dev_data->devid) {
254 struct iommu_dev_data *alias_data;
256 alias_data = find_dev_data(alias);
257 if (alias_data == NULL) {
258 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
260 free_dev_data(dev_data);
263 dev_data->alias_data = alias_data;
266 if (pci_iommuv2_capable(pdev)) {
267 struct amd_iommu *iommu;
269 iommu = amd_iommu_rlookup_table[dev_data->devid];
270 dev_data->iommu_v2 = iommu->is_iommu_v2;
273 dev->archdata.iommu = dev_data;
278 static void iommu_ignore_device(struct device *dev)
282 devid = get_device_id(dev);
283 alias = amd_iommu_alias_table[devid];
285 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
286 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
288 amd_iommu_rlookup_table[devid] = NULL;
289 amd_iommu_rlookup_table[alias] = NULL;
292 static void iommu_uninit_device(struct device *dev)
295 * Nothing to do here - we keep dev_data around for unplugged devices
296 * and reuse it when the device is re-plugged - not doing so would
297 * introduce a ton of races.
301 void __init amd_iommu_uninit_devices(void)
303 struct iommu_dev_data *dev_data, *n;
304 struct pci_dev *pdev = NULL;
306 for_each_pci_dev(pdev) {
308 if (!check_device(&pdev->dev))
311 iommu_uninit_device(&pdev->dev);
314 /* Free all of our dev_data structures */
315 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
316 free_dev_data(dev_data);
319 int __init amd_iommu_init_devices(void)
321 struct pci_dev *pdev = NULL;
324 for_each_pci_dev(pdev) {
326 if (!check_device(&pdev->dev))
329 ret = iommu_init_device(&pdev->dev);
330 if (ret == -ENOTSUPP)
331 iommu_ignore_device(&pdev->dev);
340 amd_iommu_uninit_devices();
344 #ifdef CONFIG_AMD_IOMMU_STATS
347 * Initialization code for statistics collection
350 DECLARE_STATS_COUNTER(compl_wait);
351 DECLARE_STATS_COUNTER(cnt_map_single);
352 DECLARE_STATS_COUNTER(cnt_unmap_single);
353 DECLARE_STATS_COUNTER(cnt_map_sg);
354 DECLARE_STATS_COUNTER(cnt_unmap_sg);
355 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
356 DECLARE_STATS_COUNTER(cnt_free_coherent);
357 DECLARE_STATS_COUNTER(cross_page);
358 DECLARE_STATS_COUNTER(domain_flush_single);
359 DECLARE_STATS_COUNTER(domain_flush_all);
360 DECLARE_STATS_COUNTER(alloced_io_mem);
361 DECLARE_STATS_COUNTER(total_map_requests);
363 static struct dentry *stats_dir;
364 static struct dentry *de_fflush;
366 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
368 if (stats_dir == NULL)
371 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
375 static void amd_iommu_stats_init(void)
377 stats_dir = debugfs_create_dir("amd-iommu", NULL);
378 if (stats_dir == NULL)
381 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
382 (u32 *)&amd_iommu_unmap_flush);
384 amd_iommu_stats_add(&compl_wait);
385 amd_iommu_stats_add(&cnt_map_single);
386 amd_iommu_stats_add(&cnt_unmap_single);
387 amd_iommu_stats_add(&cnt_map_sg);
388 amd_iommu_stats_add(&cnt_unmap_sg);
389 amd_iommu_stats_add(&cnt_alloc_coherent);
390 amd_iommu_stats_add(&cnt_free_coherent);
391 amd_iommu_stats_add(&cross_page);
392 amd_iommu_stats_add(&domain_flush_single);
393 amd_iommu_stats_add(&domain_flush_all);
394 amd_iommu_stats_add(&alloced_io_mem);
395 amd_iommu_stats_add(&total_map_requests);
400 /****************************************************************************
402 * Interrupt handling functions
404 ****************************************************************************/
406 static void dump_dte_entry(u16 devid)
410 for (i = 0; i < 4; ++i)
411 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
412 amd_iommu_dev_table[devid].data[i]);
415 static void dump_command(unsigned long phys_addr)
417 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
420 for (i = 0; i < 4; ++i)
421 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
424 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
427 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
428 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
429 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
430 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
431 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
433 printk(KERN_ERR "AMD-Vi: Event logged [");
436 case EVENT_TYPE_ILL_DEV:
437 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
438 "address=0x%016llx flags=0x%04x]\n",
439 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
441 dump_dte_entry(devid);
443 case EVENT_TYPE_IO_FAULT:
444 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
445 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
446 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
447 domid, address, flags);
449 case EVENT_TYPE_DEV_TAB_ERR:
450 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
451 "address=0x%016llx flags=0x%04x]\n",
452 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
455 case EVENT_TYPE_PAGE_TAB_ERR:
456 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
457 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
458 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
459 domid, address, flags);
461 case EVENT_TYPE_ILL_CMD:
462 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
463 dump_command(address);
465 case EVENT_TYPE_CMD_HARD_ERR:
466 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
467 "flags=0x%04x]\n", address, flags);
469 case EVENT_TYPE_IOTLB_INV_TO:
470 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
471 "address=0x%016llx]\n",
472 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
475 case EVENT_TYPE_INV_DEV_REQ:
476 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
477 "address=0x%016llx flags=0x%04x]\n",
478 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
482 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
486 static void iommu_poll_events(struct amd_iommu *iommu)
491 spin_lock_irqsave(&iommu->lock, flags);
493 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
494 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
496 while (head != tail) {
497 iommu_print_event(iommu, iommu->evt_buf + head);
498 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
501 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
503 spin_unlock_irqrestore(&iommu->lock, flags);
506 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u32 head)
508 struct amd_iommu_fault fault;
512 raw = (u64 *)(iommu->ppr_log + head);
515 * Hardware bug: Interrupt may arrive before the entry is written to
516 * memory. If this happens we need to wait for the entry to arrive.
518 for (i = 0; i < LOOP_TIMEOUT; ++i) {
519 if (PPR_REQ_TYPE(raw[0]) != 0)
524 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
525 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
529 fault.address = raw[1];
530 fault.pasid = PPR_PASID(raw[0]);
531 fault.device_id = PPR_DEVID(raw[0]);
532 fault.tag = PPR_TAG(raw[0]);
533 fault.flags = PPR_FLAGS(raw[0]);
536 * To detect the hardware bug we need to clear the entry
541 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
544 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
549 if (iommu->ppr_log == NULL)
552 spin_lock_irqsave(&iommu->lock, flags);
554 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
555 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
557 while (head != tail) {
559 /* Handle PPR entry */
560 iommu_handle_ppr_entry(iommu, head);
562 /* Update and refresh ring-buffer state*/
563 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
564 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
565 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
568 /* enable ppr interrupts again */
569 writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET);
571 spin_unlock_irqrestore(&iommu->lock, flags);
574 irqreturn_t amd_iommu_int_thread(int irq, void *data)
576 struct amd_iommu *iommu;
578 for_each_iommu(iommu) {
579 iommu_poll_events(iommu);
580 iommu_poll_ppr_log(iommu);
586 irqreturn_t amd_iommu_int_handler(int irq, void *data)
588 return IRQ_WAKE_THREAD;
591 /****************************************************************************
593 * IOMMU command queuing functions
595 ****************************************************************************/
597 static int wait_on_sem(volatile u64 *sem)
601 while (*sem == 0 && i < LOOP_TIMEOUT) {
606 if (i == LOOP_TIMEOUT) {
607 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
614 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
615 struct iommu_cmd *cmd,
620 target = iommu->cmd_buf + tail;
621 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
623 /* Copy command to buffer */
624 memcpy(target, cmd, sizeof(*cmd));
626 /* Tell the IOMMU about it */
627 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
630 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
632 WARN_ON(address & 0x7ULL);
634 memset(cmd, 0, sizeof(*cmd));
635 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
636 cmd->data[1] = upper_32_bits(__pa(address));
638 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
641 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
643 memset(cmd, 0, sizeof(*cmd));
644 cmd->data[0] = devid;
645 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
648 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
649 size_t size, u16 domid, int pde)
654 pages = iommu_num_pages(address, size, PAGE_SIZE);
659 * If we have to flush more than one page, flush all
660 * TLB entries for this domain
662 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
666 address &= PAGE_MASK;
668 memset(cmd, 0, sizeof(*cmd));
669 cmd->data[1] |= domid;
670 cmd->data[2] = lower_32_bits(address);
671 cmd->data[3] = upper_32_bits(address);
672 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
673 if (s) /* size bit - we flush more than one 4kb page */
674 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
675 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
676 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
679 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
680 u64 address, size_t size)
685 pages = iommu_num_pages(address, size, PAGE_SIZE);
690 * If we have to flush more than one page, flush all
691 * TLB entries for this domain
693 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
697 address &= PAGE_MASK;
699 memset(cmd, 0, sizeof(*cmd));
700 cmd->data[0] = devid;
701 cmd->data[0] |= (qdep & 0xff) << 24;
702 cmd->data[1] = devid;
703 cmd->data[2] = lower_32_bits(address);
704 cmd->data[3] = upper_32_bits(address);
705 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
707 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
710 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
711 u64 address, bool size)
713 memset(cmd, 0, sizeof(*cmd));
715 address &= ~(0xfffULL);
717 cmd->data[0] = pasid & PASID_MASK;
718 cmd->data[1] = domid;
719 cmd->data[2] = lower_32_bits(address);
720 cmd->data[3] = upper_32_bits(address);
721 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
722 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
724 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
725 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
728 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
729 int qdep, u64 address, bool size)
731 memset(cmd, 0, sizeof(*cmd));
733 address &= ~(0xfffULL);
735 cmd->data[0] = devid;
736 cmd->data[0] |= (pasid & 0xff) << 16;
737 cmd->data[0] |= (qdep & 0xff) << 24;
738 cmd->data[1] = devid;
739 cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16;
740 cmd->data[2] = lower_32_bits(address);
741 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
742 cmd->data[3] = upper_32_bits(address);
744 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
745 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
748 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
749 int status, int tag, bool gn)
751 memset(cmd, 0, sizeof(*cmd));
753 cmd->data[0] = devid;
755 cmd->data[1] = pasid & PASID_MASK;
756 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
758 cmd->data[3] = tag & 0x1ff;
759 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
761 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
764 static void build_inv_all(struct iommu_cmd *cmd)
766 memset(cmd, 0, sizeof(*cmd));
767 CMD_SET_TYPE(cmd, CMD_INV_ALL);
771 * Writes the command to the IOMMUs command buffer and informs the
772 * hardware about the new command.
774 static int iommu_queue_command_sync(struct amd_iommu *iommu,
775 struct iommu_cmd *cmd,
778 u32 left, tail, head, next_tail;
781 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
784 spin_lock_irqsave(&iommu->lock, flags);
786 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
787 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
788 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
789 left = (head - next_tail) % iommu->cmd_buf_size;
792 struct iommu_cmd sync_cmd;
793 volatile u64 sem = 0;
796 build_completion_wait(&sync_cmd, (u64)&sem);
797 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
799 spin_unlock_irqrestore(&iommu->lock, flags);
801 if ((ret = wait_on_sem(&sem)) != 0)
807 copy_cmd_to_buffer(iommu, cmd, tail);
809 /* We need to sync now to make sure all commands are processed */
810 iommu->need_sync = sync;
812 spin_unlock_irqrestore(&iommu->lock, flags);
817 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
819 return iommu_queue_command_sync(iommu, cmd, true);
823 * This function queues a completion wait command into the command
826 static int iommu_completion_wait(struct amd_iommu *iommu)
828 struct iommu_cmd cmd;
829 volatile u64 sem = 0;
832 if (!iommu->need_sync)
835 build_completion_wait(&cmd, (u64)&sem);
837 ret = iommu_queue_command_sync(iommu, &cmd, false);
841 return wait_on_sem(&sem);
844 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
846 struct iommu_cmd cmd;
848 build_inv_dte(&cmd, devid);
850 return iommu_queue_command(iommu, &cmd);
853 static void iommu_flush_dte_all(struct amd_iommu *iommu)
857 for (devid = 0; devid <= 0xffff; ++devid)
858 iommu_flush_dte(iommu, devid);
860 iommu_completion_wait(iommu);
864 * This function uses heavy locking and may disable irqs for some time. But
865 * this is no issue because it is only called during resume.
867 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
871 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
872 struct iommu_cmd cmd;
873 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
875 iommu_queue_command(iommu, &cmd);
878 iommu_completion_wait(iommu);
881 static void iommu_flush_all(struct amd_iommu *iommu)
883 struct iommu_cmd cmd;
887 iommu_queue_command(iommu, &cmd);
888 iommu_completion_wait(iommu);
891 void iommu_flush_all_caches(struct amd_iommu *iommu)
893 if (iommu_feature(iommu, FEATURE_IA)) {
894 iommu_flush_all(iommu);
896 iommu_flush_dte_all(iommu);
897 iommu_flush_tlb_all(iommu);
902 * Command send function for flushing on-device TLB
904 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
905 u64 address, size_t size)
907 struct amd_iommu *iommu;
908 struct iommu_cmd cmd;
911 qdep = dev_data->ats.qdep;
912 iommu = amd_iommu_rlookup_table[dev_data->devid];
914 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
916 return iommu_queue_command(iommu, &cmd);
920 * Command send function for invalidating a device table entry
922 static int device_flush_dte(struct iommu_dev_data *dev_data)
924 struct amd_iommu *iommu;
927 iommu = amd_iommu_rlookup_table[dev_data->devid];
929 ret = iommu_flush_dte(iommu, dev_data->devid);
933 if (dev_data->ats.enabled)
934 ret = device_flush_iotlb(dev_data, 0, ~0UL);
940 * TLB invalidation function which is called from the mapping functions.
941 * It invalidates a single PTE if the range to flush is within a single
942 * page. Otherwise it flushes the whole TLB of the IOMMU.
944 static void __domain_flush_pages(struct protection_domain *domain,
945 u64 address, size_t size, int pde)
947 struct iommu_dev_data *dev_data;
948 struct iommu_cmd cmd;
951 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
953 for (i = 0; i < amd_iommus_present; ++i) {
954 if (!domain->dev_iommu[i])
958 * Devices of this domain are behind this IOMMU
959 * We need a TLB flush
961 ret |= iommu_queue_command(amd_iommus[i], &cmd);
964 list_for_each_entry(dev_data, &domain->dev_list, list) {
966 if (!dev_data->ats.enabled)
969 ret |= device_flush_iotlb(dev_data, address, size);
975 static void domain_flush_pages(struct protection_domain *domain,
976 u64 address, size_t size)
978 __domain_flush_pages(domain, address, size, 0);
981 /* Flush the whole IO/TLB for a given protection domain */
982 static void domain_flush_tlb(struct protection_domain *domain)
984 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
987 /* Flush the whole IO/TLB for a given protection domain - including PDE */
988 static void domain_flush_tlb_pde(struct protection_domain *domain)
990 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
993 static void domain_flush_complete(struct protection_domain *domain)
997 for (i = 0; i < amd_iommus_present; ++i) {
998 if (!domain->dev_iommu[i])
1002 * Devices of this domain are behind this IOMMU
1003 * We need to wait for completion of all commands.
1005 iommu_completion_wait(amd_iommus[i]);
1011 * This function flushes the DTEs for all devices in domain
1013 static void domain_flush_devices(struct protection_domain *domain)
1015 struct iommu_dev_data *dev_data;
1017 list_for_each_entry(dev_data, &domain->dev_list, list)
1018 device_flush_dte(dev_data);
1021 /****************************************************************************
1023 * The functions below are used the create the page table mappings for
1024 * unity mapped regions.
1026 ****************************************************************************/
1029 * This function is used to add another level to an IO page table. Adding
1030 * another level increases the size of the address space by 9 bits to a size up
1033 static bool increase_address_space(struct protection_domain *domain,
1038 if (domain->mode == PAGE_MODE_6_LEVEL)
1039 /* address space already 64 bit large */
1042 pte = (void *)get_zeroed_page(gfp);
1046 *pte = PM_LEVEL_PDE(domain->mode,
1047 virt_to_phys(domain->pt_root));
1048 domain->pt_root = pte;
1050 domain->updated = true;
1055 static u64 *alloc_pte(struct protection_domain *domain,
1056 unsigned long address,
1057 unsigned long page_size,
1064 BUG_ON(!is_power_of_2(page_size));
1066 while (address > PM_LEVEL_SIZE(domain->mode))
1067 increase_address_space(domain, gfp);
1069 level = domain->mode - 1;
1070 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1071 address = PAGE_SIZE_ALIGN(address, page_size);
1072 end_lvl = PAGE_SIZE_LEVEL(page_size);
1074 while (level > end_lvl) {
1075 if (!IOMMU_PTE_PRESENT(*pte)) {
1076 page = (u64 *)get_zeroed_page(gfp);
1079 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1082 /* No level skipping support yet */
1083 if (PM_PTE_LEVEL(*pte) != level)
1088 pte = IOMMU_PTE_PAGE(*pte);
1090 if (pte_page && level == end_lvl)
1093 pte = &pte[PM_LEVEL_INDEX(level, address)];
1100 * This function checks if there is a PTE for a given dma address. If
1101 * there is one, it returns the pointer to it.
1103 static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
1108 if (address > PM_LEVEL_SIZE(domain->mode))
1111 level = domain->mode - 1;
1112 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1117 if (!IOMMU_PTE_PRESENT(*pte))
1121 if (PM_PTE_LEVEL(*pte) == 0x07) {
1122 unsigned long pte_mask, __pte;
1125 * If we have a series of large PTEs, make
1126 * sure to return a pointer to the first one.
1128 pte_mask = PTE_PAGE_SIZE(*pte);
1129 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1130 __pte = ((unsigned long)pte) & pte_mask;
1132 return (u64 *)__pte;
1135 /* No level skipping support yet */
1136 if (PM_PTE_LEVEL(*pte) != level)
1141 /* Walk to the next level */
1142 pte = IOMMU_PTE_PAGE(*pte);
1143 pte = &pte[PM_LEVEL_INDEX(level, address)];
1150 * Generic mapping functions. It maps a physical address into a DMA
1151 * address space. It allocates the page table pages if necessary.
1152 * In the future it can be extended to a generic mapping function
1153 * supporting all features of AMD IOMMU page tables like level skipping
1154 * and full 64 bit address spaces.
1156 static int iommu_map_page(struct protection_domain *dom,
1157 unsigned long bus_addr,
1158 unsigned long phys_addr,
1160 unsigned long page_size)
1165 if (!(prot & IOMMU_PROT_MASK))
1168 bus_addr = PAGE_ALIGN(bus_addr);
1169 phys_addr = PAGE_ALIGN(phys_addr);
1170 count = PAGE_SIZE_PTE_COUNT(page_size);
1171 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1173 for (i = 0; i < count; ++i)
1174 if (IOMMU_PTE_PRESENT(pte[i]))
1177 if (page_size > PAGE_SIZE) {
1178 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1179 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1181 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1183 if (prot & IOMMU_PROT_IR)
1184 __pte |= IOMMU_PTE_IR;
1185 if (prot & IOMMU_PROT_IW)
1186 __pte |= IOMMU_PTE_IW;
1188 for (i = 0; i < count; ++i)
1196 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1197 unsigned long bus_addr,
1198 unsigned long page_size)
1200 unsigned long long unmap_size, unmapped;
1203 BUG_ON(!is_power_of_2(page_size));
1207 while (unmapped < page_size) {
1209 pte = fetch_pte(dom, bus_addr);
1213 * No PTE for this address
1214 * move forward in 4kb steps
1216 unmap_size = PAGE_SIZE;
1217 } else if (PM_PTE_LEVEL(*pte) == 0) {
1218 /* 4kb PTE found for this address */
1219 unmap_size = PAGE_SIZE;
1224 /* Large PTE found which maps this address */
1225 unmap_size = PTE_PAGE_SIZE(*pte);
1226 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1227 for (i = 0; i < count; i++)
1231 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1232 unmapped += unmap_size;
1235 BUG_ON(!is_power_of_2(unmapped));
1241 * This function checks if a specific unity mapping entry is needed for
1242 * this specific IOMMU.
1244 static int iommu_for_unity_map(struct amd_iommu *iommu,
1245 struct unity_map_entry *entry)
1249 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1250 bdf = amd_iommu_alias_table[i];
1251 if (amd_iommu_rlookup_table[bdf] == iommu)
1259 * This function actually applies the mapping to the page table of the
1262 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1263 struct unity_map_entry *e)
1268 for (addr = e->address_start; addr < e->address_end;
1269 addr += PAGE_SIZE) {
1270 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
1275 * if unity mapping is in aperture range mark the page
1276 * as allocated in the aperture
1278 if (addr < dma_dom->aperture_size)
1279 __set_bit(addr >> PAGE_SHIFT,
1280 dma_dom->aperture[0]->bitmap);
1287 * Init the unity mappings for a specific IOMMU in the system
1289 * Basically iterates over all unity mapping entries and applies them to
1290 * the default domain DMA of that IOMMU if necessary.
1292 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1294 struct unity_map_entry *entry;
1297 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1298 if (!iommu_for_unity_map(iommu, entry))
1300 ret = dma_ops_unity_map(iommu->default_dom, entry);
1309 * Inits the unity mappings required for a specific device
1311 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1314 struct unity_map_entry *e;
1317 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1318 if (!(devid >= e->devid_start && devid <= e->devid_end))
1320 ret = dma_ops_unity_map(dma_dom, e);
1328 /****************************************************************************
1330 * The next functions belong to the address allocator for the dma_ops
1331 * interface functions. They work like the allocators in the other IOMMU
1332 * drivers. Its basically a bitmap which marks the allocated pages in
1333 * the aperture. Maybe it could be enhanced in the future to a more
1334 * efficient allocator.
1336 ****************************************************************************/
1339 * The address allocator core functions.
1341 * called with domain->lock held
1345 * Used to reserve address ranges in the aperture (e.g. for exclusion
1348 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1349 unsigned long start_page,
1352 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1354 if (start_page + pages > last_page)
1355 pages = last_page - start_page;
1357 for (i = start_page; i < start_page + pages; ++i) {
1358 int index = i / APERTURE_RANGE_PAGES;
1359 int page = i % APERTURE_RANGE_PAGES;
1360 __set_bit(page, dom->aperture[index]->bitmap);
1365 * This function is used to add a new aperture range to an existing
1366 * aperture in case of dma_ops domain allocation or address allocation
1369 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1370 bool populate, gfp_t gfp)
1372 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1373 struct amd_iommu *iommu;
1374 unsigned long i, old_size;
1376 #ifdef CONFIG_IOMMU_STRESS
1380 if (index >= APERTURE_MAX_RANGES)
1383 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1384 if (!dma_dom->aperture[index])
1387 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1388 if (!dma_dom->aperture[index]->bitmap)
1391 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1394 unsigned long address = dma_dom->aperture_size;
1395 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1396 u64 *pte, *pte_page;
1398 for (i = 0; i < num_ptes; ++i) {
1399 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1404 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1406 address += APERTURE_RANGE_SIZE / 64;
1410 old_size = dma_dom->aperture_size;
1411 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1413 /* Reserve address range used for MSI messages */
1414 if (old_size < MSI_ADDR_BASE_LO &&
1415 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1416 unsigned long spage;
1419 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1420 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1422 dma_ops_reserve_addresses(dma_dom, spage, pages);
1425 /* Initialize the exclusion range if necessary */
1426 for_each_iommu(iommu) {
1427 if (iommu->exclusion_start &&
1428 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1429 && iommu->exclusion_start < dma_dom->aperture_size) {
1430 unsigned long startpage;
1431 int pages = iommu_num_pages(iommu->exclusion_start,
1432 iommu->exclusion_length,
1434 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1435 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1440 * Check for areas already mapped as present in the new aperture
1441 * range and mark those pages as reserved in the allocator. Such
1442 * mappings may already exist as a result of requested unity
1443 * mappings for devices.
1445 for (i = dma_dom->aperture[index]->offset;
1446 i < dma_dom->aperture_size;
1448 u64 *pte = fetch_pte(&dma_dom->domain, i);
1449 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1452 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1);
1455 update_domain(&dma_dom->domain);
1460 update_domain(&dma_dom->domain);
1462 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1464 kfree(dma_dom->aperture[index]);
1465 dma_dom->aperture[index] = NULL;
1470 static unsigned long dma_ops_area_alloc(struct device *dev,
1471 struct dma_ops_domain *dom,
1473 unsigned long align_mask,
1475 unsigned long start)
1477 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1478 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1479 int i = start >> APERTURE_RANGE_SHIFT;
1480 unsigned long boundary_size;
1481 unsigned long address = -1;
1482 unsigned long limit;
1484 next_bit >>= PAGE_SHIFT;
1486 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1487 PAGE_SIZE) >> PAGE_SHIFT;
1489 for (;i < max_index; ++i) {
1490 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1492 if (dom->aperture[i]->offset >= dma_mask)
1495 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1496 dma_mask >> PAGE_SHIFT);
1498 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1499 limit, next_bit, pages, 0,
1500 boundary_size, align_mask);
1501 if (address != -1) {
1502 address = dom->aperture[i]->offset +
1503 (address << PAGE_SHIFT);
1504 dom->next_address = address + (pages << PAGE_SHIFT);
1514 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1515 struct dma_ops_domain *dom,
1517 unsigned long align_mask,
1520 unsigned long address;
1522 #ifdef CONFIG_IOMMU_STRESS
1523 dom->next_address = 0;
1524 dom->need_flush = true;
1527 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1528 dma_mask, dom->next_address);
1530 if (address == -1) {
1531 dom->next_address = 0;
1532 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1534 dom->need_flush = true;
1537 if (unlikely(address == -1))
1538 address = DMA_ERROR_CODE;
1540 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1546 * The address free function.
1548 * called with domain->lock held
1550 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1551 unsigned long address,
1554 unsigned i = address >> APERTURE_RANGE_SHIFT;
1555 struct aperture_range *range = dom->aperture[i];
1557 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1559 #ifdef CONFIG_IOMMU_STRESS
1564 if (address >= dom->next_address)
1565 dom->need_flush = true;
1567 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1569 bitmap_clear(range->bitmap, address, pages);
1573 /****************************************************************************
1575 * The next functions belong to the domain allocation. A domain is
1576 * allocated for every IOMMU as the default domain. If device isolation
1577 * is enabled, every device get its own domain. The most important thing
1578 * about domains is the page table mapping the DMA address space they
1581 ****************************************************************************/
1584 * This function adds a protection domain to the global protection domain list
1586 static void add_domain_to_list(struct protection_domain *domain)
1588 unsigned long flags;
1590 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1591 list_add(&domain->list, &amd_iommu_pd_list);
1592 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1596 * This function removes a protection domain to the global
1597 * protection domain list
1599 static void del_domain_from_list(struct protection_domain *domain)
1601 unsigned long flags;
1603 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1604 list_del(&domain->list);
1605 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1608 static u16 domain_id_alloc(void)
1610 unsigned long flags;
1613 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1614 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1616 if (id > 0 && id < MAX_DOMAIN_ID)
1617 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1620 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1625 static void domain_id_free(int id)
1627 unsigned long flags;
1629 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1630 if (id > 0 && id < MAX_DOMAIN_ID)
1631 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1632 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1635 static void free_pagetable(struct protection_domain *domain)
1640 p1 = domain->pt_root;
1645 for (i = 0; i < 512; ++i) {
1646 if (!IOMMU_PTE_PRESENT(p1[i]))
1649 p2 = IOMMU_PTE_PAGE(p1[i]);
1650 for (j = 0; j < 512; ++j) {
1651 if (!IOMMU_PTE_PRESENT(p2[j]))
1653 p3 = IOMMU_PTE_PAGE(p2[j]);
1654 free_page((unsigned long)p3);
1657 free_page((unsigned long)p2);
1660 free_page((unsigned long)p1);
1662 domain->pt_root = NULL;
1665 static void free_gcr3_tbl_level1(u64 *tbl)
1670 for (i = 0; i < 512; ++i) {
1671 if (!(tbl[i] & GCR3_VALID))
1674 ptr = __va(tbl[i] & PAGE_MASK);
1676 free_page((unsigned long)ptr);
1680 static void free_gcr3_tbl_level2(u64 *tbl)
1685 for (i = 0; i < 512; ++i) {
1686 if (!(tbl[i] & GCR3_VALID))
1689 ptr = __va(tbl[i] & PAGE_MASK);
1691 free_gcr3_tbl_level1(ptr);
1695 static void free_gcr3_table(struct protection_domain *domain)
1697 if (domain->glx == 2)
1698 free_gcr3_tbl_level2(domain->gcr3_tbl);
1699 else if (domain->glx == 1)
1700 free_gcr3_tbl_level1(domain->gcr3_tbl);
1701 else if (domain->glx != 0)
1704 free_page((unsigned long)domain->gcr3_tbl);
1708 * Free a domain, only used if something went wrong in the
1709 * allocation path and we need to free an already allocated page table
1711 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1718 del_domain_from_list(&dom->domain);
1720 free_pagetable(&dom->domain);
1722 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1723 if (!dom->aperture[i])
1725 free_page((unsigned long)dom->aperture[i]->bitmap);
1726 kfree(dom->aperture[i]);
1733 * Allocates a new protection domain usable for the dma_ops functions.
1734 * It also initializes the page table and the address allocator data
1735 * structures required for the dma_ops interface
1737 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1739 struct dma_ops_domain *dma_dom;
1741 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1745 spin_lock_init(&dma_dom->domain.lock);
1747 dma_dom->domain.id = domain_id_alloc();
1748 if (dma_dom->domain.id == 0)
1750 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1751 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1752 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1753 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1754 dma_dom->domain.priv = dma_dom;
1755 if (!dma_dom->domain.pt_root)
1758 dma_dom->need_flush = false;
1759 dma_dom->target_dev = 0xffff;
1761 add_domain_to_list(&dma_dom->domain);
1763 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1767 * mark the first page as allocated so we never return 0 as
1768 * a valid dma-address. So we can use 0 as error value
1770 dma_dom->aperture[0]->bitmap[0] = 1;
1771 dma_dom->next_address = 0;
1777 dma_ops_domain_free(dma_dom);
1783 * little helper function to check whether a given protection domain is a
1786 static bool dma_ops_domain(struct protection_domain *domain)
1788 return domain->flags & PD_DMA_OPS_MASK;
1791 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1796 if (domain->mode != PAGE_MODE_NONE)
1797 pte_root = virt_to_phys(domain->pt_root);
1799 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1800 << DEV_ENTRY_MODE_SHIFT;
1801 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1803 flags = amd_iommu_dev_table[devid].data[1];
1806 flags |= DTE_FLAG_IOTLB;
1808 if (domain->flags & PD_IOMMUV2_MASK) {
1809 u64 gcr3 = __pa(domain->gcr3_tbl);
1810 u64 glx = domain->glx;
1813 pte_root |= DTE_FLAG_GV;
1814 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1816 /* First mask out possible old values for GCR3 table */
1817 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1820 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1823 /* Encode GCR3 table into DTE */
1824 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1827 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1830 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1834 flags &= ~(0xffffUL);
1835 flags |= domain->id;
1837 amd_iommu_dev_table[devid].data[1] = flags;
1838 amd_iommu_dev_table[devid].data[0] = pte_root;
1841 static void clear_dte_entry(u16 devid)
1843 /* remove entry from the device table seen by the hardware */
1844 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1845 amd_iommu_dev_table[devid].data[1] = 0;
1847 amd_iommu_apply_erratum_63(devid);
1850 static void do_attach(struct iommu_dev_data *dev_data,
1851 struct protection_domain *domain)
1853 struct amd_iommu *iommu;
1856 iommu = amd_iommu_rlookup_table[dev_data->devid];
1857 ats = dev_data->ats.enabled;
1859 /* Update data structures */
1860 dev_data->domain = domain;
1861 list_add(&dev_data->list, &domain->dev_list);
1862 set_dte_entry(dev_data->devid, domain, ats);
1864 /* Do reference counting */
1865 domain->dev_iommu[iommu->index] += 1;
1866 domain->dev_cnt += 1;
1868 /* Flush the DTE entry */
1869 device_flush_dte(dev_data);
1872 static void do_detach(struct iommu_dev_data *dev_data)
1874 struct amd_iommu *iommu;
1876 iommu = amd_iommu_rlookup_table[dev_data->devid];
1878 /* decrease reference counters */
1879 dev_data->domain->dev_iommu[iommu->index] -= 1;
1880 dev_data->domain->dev_cnt -= 1;
1882 /* Update data structures */
1883 dev_data->domain = NULL;
1884 list_del(&dev_data->list);
1885 clear_dte_entry(dev_data->devid);
1887 /* Flush the DTE entry */
1888 device_flush_dte(dev_data);
1892 * If a device is not yet associated with a domain, this function does
1893 * assigns it visible for the hardware
1895 static int __attach_device(struct iommu_dev_data *dev_data,
1896 struct protection_domain *domain)
1901 spin_lock(&domain->lock);
1903 if (dev_data->alias_data != NULL) {
1904 struct iommu_dev_data *alias_data = dev_data->alias_data;
1906 /* Some sanity checks */
1908 if (alias_data->domain != NULL &&
1909 alias_data->domain != domain)
1912 if (dev_data->domain != NULL &&
1913 dev_data->domain != domain)
1916 /* Do real assignment */
1917 if (alias_data->domain == NULL)
1918 do_attach(alias_data, domain);
1920 atomic_inc(&alias_data->bind);
1923 if (dev_data->domain == NULL)
1924 do_attach(dev_data, domain);
1926 atomic_inc(&dev_data->bind);
1933 spin_unlock(&domain->lock);
1939 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1941 pci_disable_ats(pdev);
1942 pci_disable_pri(pdev);
1943 pci_disable_pasid(pdev);
1946 /* FIXME: Change generic reset-function to do the same */
1947 static int pri_reset_while_enabled(struct pci_dev *pdev)
1952 pos = pci_find_ext_capability(pdev, PCI_PRI_CAP);
1956 pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);
1957 control |= PCI_PRI_RESET;
1958 pci_write_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, control);
1963 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1968 /* FIXME: Hardcode number of outstanding requests for now */
1970 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
1972 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
1974 /* Only allow access to user-accessible pages */
1975 ret = pci_enable_pasid(pdev, 0);
1979 /* First reset the PRI state of the device */
1980 ret = pci_reset_pri(pdev);
1985 ret = pci_enable_pri(pdev, reqs);
1990 ret = pri_reset_while_enabled(pdev);
1995 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2002 pci_disable_pri(pdev);
2003 pci_disable_pasid(pdev);
2008 /* FIXME: Move this to PCI code */
2009 #define PCI_PRI_TLP_OFF (1 << 2)
2011 bool pci_pri_tlp_required(struct pci_dev *pdev)
2016 pos = pci_find_ext_capability(pdev, PCI_PRI_CAP);
2020 pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);
2022 return (control & PCI_PRI_TLP_OFF) ? true : false;
2026 * If a device is not yet associated with a domain, this function does
2027 * assigns it visible for the hardware
2029 static int attach_device(struct device *dev,
2030 struct protection_domain *domain)
2032 struct pci_dev *pdev = to_pci_dev(dev);
2033 struct iommu_dev_data *dev_data;
2034 unsigned long flags;
2037 dev_data = get_dev_data(dev);
2039 if (domain->flags & PD_IOMMUV2_MASK) {
2040 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2043 if (pdev_iommuv2_enable(pdev) != 0)
2046 dev_data->ats.enabled = true;
2047 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2048 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2049 } else if (amd_iommu_iotlb_sup &&
2050 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2051 dev_data->ats.enabled = true;
2052 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2055 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2056 ret = __attach_device(dev_data, domain);
2057 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2060 * We might boot into a crash-kernel here. The crashed kernel
2061 * left the caches in the IOMMU dirty. So we have to flush
2062 * here to evict all dirty stuff.
2064 domain_flush_tlb_pde(domain);
2070 * Removes a device from a protection domain (unlocked)
2072 static void __detach_device(struct iommu_dev_data *dev_data)
2074 struct protection_domain *domain;
2075 unsigned long flags;
2077 BUG_ON(!dev_data->domain);
2079 domain = dev_data->domain;
2081 spin_lock_irqsave(&domain->lock, flags);
2083 if (dev_data->alias_data != NULL) {
2084 struct iommu_dev_data *alias_data = dev_data->alias_data;
2086 if (atomic_dec_and_test(&alias_data->bind))
2087 do_detach(alias_data);
2090 if (atomic_dec_and_test(&dev_data->bind))
2091 do_detach(dev_data);
2093 spin_unlock_irqrestore(&domain->lock, flags);
2096 * If we run in passthrough mode the device must be assigned to the
2097 * passthrough domain if it is detached from any other domain.
2098 * Make sure we can deassign from the pt_domain itself.
2100 if (dev_data->passthrough &&
2101 (dev_data->domain == NULL && domain != pt_domain))
2102 __attach_device(dev_data, pt_domain);
2106 * Removes a device from a protection domain (with devtable_lock held)
2108 static void detach_device(struct device *dev)
2110 struct protection_domain *domain;
2111 struct iommu_dev_data *dev_data;
2112 unsigned long flags;
2114 dev_data = get_dev_data(dev);
2115 domain = dev_data->domain;
2117 /* lock device table */
2118 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2119 __detach_device(dev_data);
2120 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2122 if (domain->flags & PD_IOMMUV2_MASK)
2123 pdev_iommuv2_disable(to_pci_dev(dev));
2124 else if (dev_data->ats.enabled)
2125 pci_disable_ats(to_pci_dev(dev));
2127 dev_data->ats.enabled = false;
2131 * Find out the protection domain structure for a given PCI device. This
2132 * will give us the pointer to the page table root for example.
2134 static struct protection_domain *domain_for_device(struct device *dev)
2136 struct iommu_dev_data *dev_data;
2137 struct protection_domain *dom = NULL;
2138 unsigned long flags;
2140 dev_data = get_dev_data(dev);
2142 if (dev_data->domain)
2143 return dev_data->domain;
2145 if (dev_data->alias_data != NULL) {
2146 struct iommu_dev_data *alias_data = dev_data->alias_data;
2148 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2149 if (alias_data->domain != NULL) {
2150 __attach_device(dev_data, alias_data->domain);
2151 dom = alias_data->domain;
2153 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2159 static int device_change_notifier(struct notifier_block *nb,
2160 unsigned long action, void *data)
2162 struct dma_ops_domain *dma_domain;
2163 struct protection_domain *domain;
2164 struct iommu_dev_data *dev_data;
2165 struct device *dev = data;
2166 struct amd_iommu *iommu;
2167 unsigned long flags;
2170 if (!check_device(dev))
2173 devid = get_device_id(dev);
2174 iommu = amd_iommu_rlookup_table[devid];
2175 dev_data = get_dev_data(dev);
2178 case BUS_NOTIFY_UNBOUND_DRIVER:
2180 domain = domain_for_device(dev);
2184 if (dev_data->passthrough)
2188 case BUS_NOTIFY_ADD_DEVICE:
2190 iommu_init_device(dev);
2192 domain = domain_for_device(dev);
2194 /* allocate a protection domain if a device is added */
2195 dma_domain = find_protection_domain(devid);
2198 dma_domain = dma_ops_domain_alloc();
2201 dma_domain->target_dev = devid;
2203 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2204 list_add_tail(&dma_domain->list, &iommu_pd_list);
2205 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2208 case BUS_NOTIFY_DEL_DEVICE:
2210 iommu_uninit_device(dev);
2216 iommu_completion_wait(iommu);
2222 static struct notifier_block device_nb = {
2223 .notifier_call = device_change_notifier,
2226 void amd_iommu_init_notifier(void)
2228 bus_register_notifier(&pci_bus_type, &device_nb);
2231 /*****************************************************************************
2233 * The next functions belong to the dma_ops mapping/unmapping code.
2235 *****************************************************************************/
2238 * In the dma_ops path we only have the struct device. This function
2239 * finds the corresponding IOMMU, the protection domain and the
2240 * requestor id for a given device.
2241 * If the device is not yet associated with a domain this is also done
2244 static struct protection_domain *get_domain(struct device *dev)
2246 struct protection_domain *domain;
2247 struct dma_ops_domain *dma_dom;
2248 u16 devid = get_device_id(dev);
2250 if (!check_device(dev))
2251 return ERR_PTR(-EINVAL);
2253 domain = domain_for_device(dev);
2254 if (domain != NULL && !dma_ops_domain(domain))
2255 return ERR_PTR(-EBUSY);
2260 /* Device not bount yet - bind it */
2261 dma_dom = find_protection_domain(devid);
2263 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2264 attach_device(dev, &dma_dom->domain);
2265 DUMP_printk("Using protection domain %d for device %s\n",
2266 dma_dom->domain.id, dev_name(dev));
2268 return &dma_dom->domain;
2271 static void update_device_table(struct protection_domain *domain)
2273 struct iommu_dev_data *dev_data;
2275 list_for_each_entry(dev_data, &domain->dev_list, list)
2276 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2279 static void update_domain(struct protection_domain *domain)
2281 if (!domain->updated)
2284 update_device_table(domain);
2286 domain_flush_devices(domain);
2287 domain_flush_tlb_pde(domain);
2289 domain->updated = false;
2293 * This function fetches the PTE for a given address in the aperture
2295 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2296 unsigned long address)
2298 struct aperture_range *aperture;
2299 u64 *pte, *pte_page;
2301 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2305 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2307 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2309 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2311 pte += PM_LEVEL_INDEX(0, address);
2313 update_domain(&dom->domain);
2319 * This is the generic map function. It maps one 4kb page at paddr to
2320 * the given address in the DMA address space for the domain.
2322 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2323 unsigned long address,
2329 WARN_ON(address > dom->aperture_size);
2333 pte = dma_ops_get_pte(dom, address);
2335 return DMA_ERROR_CODE;
2337 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2339 if (direction == DMA_TO_DEVICE)
2340 __pte |= IOMMU_PTE_IR;
2341 else if (direction == DMA_FROM_DEVICE)
2342 __pte |= IOMMU_PTE_IW;
2343 else if (direction == DMA_BIDIRECTIONAL)
2344 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2350 return (dma_addr_t)address;
2354 * The generic unmapping function for on page in the DMA address space.
2356 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2357 unsigned long address)
2359 struct aperture_range *aperture;
2362 if (address >= dom->aperture_size)
2365 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2369 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2373 pte += PM_LEVEL_INDEX(0, address);
2381 * This function contains common code for mapping of a physically
2382 * contiguous memory region into DMA address space. It is used by all
2383 * mapping functions provided with this IOMMU driver.
2384 * Must be called with the domain lock held.
2386 static dma_addr_t __map_single(struct device *dev,
2387 struct dma_ops_domain *dma_dom,
2394 dma_addr_t offset = paddr & ~PAGE_MASK;
2395 dma_addr_t address, start, ret;
2397 unsigned long align_mask = 0;
2400 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2403 INC_STATS_COUNTER(total_map_requests);
2406 INC_STATS_COUNTER(cross_page);
2409 align_mask = (1UL << get_order(size)) - 1;
2412 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2414 if (unlikely(address == DMA_ERROR_CODE)) {
2416 * setting next_address here will let the address
2417 * allocator only scan the new allocated range in the
2418 * first run. This is a small optimization.
2420 dma_dom->next_address = dma_dom->aperture_size;
2422 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2426 * aperture was successfully enlarged by 128 MB, try
2433 for (i = 0; i < pages; ++i) {
2434 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2435 if (ret == DMA_ERROR_CODE)
2443 ADD_STATS_COUNTER(alloced_io_mem, size);
2445 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2446 domain_flush_tlb(&dma_dom->domain);
2447 dma_dom->need_flush = false;
2448 } else if (unlikely(amd_iommu_np_cache))
2449 domain_flush_pages(&dma_dom->domain, address, size);
2456 for (--i; i >= 0; --i) {
2458 dma_ops_domain_unmap(dma_dom, start);
2461 dma_ops_free_addresses(dma_dom, address, pages);
2463 return DMA_ERROR_CODE;
2467 * Does the reverse of the __map_single function. Must be called with
2468 * the domain lock held too
2470 static void __unmap_single(struct dma_ops_domain *dma_dom,
2471 dma_addr_t dma_addr,
2475 dma_addr_t flush_addr;
2476 dma_addr_t i, start;
2479 if ((dma_addr == DMA_ERROR_CODE) ||
2480 (dma_addr + size > dma_dom->aperture_size))
2483 flush_addr = dma_addr;
2484 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2485 dma_addr &= PAGE_MASK;
2488 for (i = 0; i < pages; ++i) {
2489 dma_ops_domain_unmap(dma_dom, start);
2493 SUB_STATS_COUNTER(alloced_io_mem, size);
2495 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2497 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2498 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2499 dma_dom->need_flush = false;
2504 * The exported map_single function for dma_ops.
2506 static dma_addr_t map_page(struct device *dev, struct page *page,
2507 unsigned long offset, size_t size,
2508 enum dma_data_direction dir,
2509 struct dma_attrs *attrs)
2511 unsigned long flags;
2512 struct protection_domain *domain;
2515 phys_addr_t paddr = page_to_phys(page) + offset;
2517 INC_STATS_COUNTER(cnt_map_single);
2519 domain = get_domain(dev);
2520 if (PTR_ERR(domain) == -EINVAL)
2521 return (dma_addr_t)paddr;
2522 else if (IS_ERR(domain))
2523 return DMA_ERROR_CODE;
2525 dma_mask = *dev->dma_mask;
2527 spin_lock_irqsave(&domain->lock, flags);
2529 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2531 if (addr == DMA_ERROR_CODE)
2534 domain_flush_complete(domain);
2537 spin_unlock_irqrestore(&domain->lock, flags);
2543 * The exported unmap_single function for dma_ops.
2545 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2546 enum dma_data_direction dir, struct dma_attrs *attrs)
2548 unsigned long flags;
2549 struct protection_domain *domain;
2551 INC_STATS_COUNTER(cnt_unmap_single);
2553 domain = get_domain(dev);
2557 spin_lock_irqsave(&domain->lock, flags);
2559 __unmap_single(domain->priv, dma_addr, size, dir);
2561 domain_flush_complete(domain);
2563 spin_unlock_irqrestore(&domain->lock, flags);
2567 * This is a special map_sg function which is used if we should map a
2568 * device which is not handled by an AMD IOMMU in the system.
2570 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
2571 int nelems, int dir)
2573 struct scatterlist *s;
2576 for_each_sg(sglist, s, nelems, i) {
2577 s->dma_address = (dma_addr_t)sg_phys(s);
2578 s->dma_length = s->length;
2585 * The exported map_sg function for dma_ops (handles scatter-gather
2588 static int map_sg(struct device *dev, struct scatterlist *sglist,
2589 int nelems, enum dma_data_direction dir,
2590 struct dma_attrs *attrs)
2592 unsigned long flags;
2593 struct protection_domain *domain;
2595 struct scatterlist *s;
2597 int mapped_elems = 0;
2600 INC_STATS_COUNTER(cnt_map_sg);
2602 domain = get_domain(dev);
2603 if (PTR_ERR(domain) == -EINVAL)
2604 return map_sg_no_iommu(dev, sglist, nelems, dir);
2605 else if (IS_ERR(domain))
2608 dma_mask = *dev->dma_mask;
2610 spin_lock_irqsave(&domain->lock, flags);
2612 for_each_sg(sglist, s, nelems, i) {
2615 s->dma_address = __map_single(dev, domain->priv,
2616 paddr, s->length, dir, false,
2619 if (s->dma_address) {
2620 s->dma_length = s->length;
2626 domain_flush_complete(domain);
2629 spin_unlock_irqrestore(&domain->lock, flags);
2631 return mapped_elems;
2633 for_each_sg(sglist, s, mapped_elems, i) {
2635 __unmap_single(domain->priv, s->dma_address,
2636 s->dma_length, dir);
2637 s->dma_address = s->dma_length = 0;
2646 * The exported map_sg function for dma_ops (handles scatter-gather
2649 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2650 int nelems, enum dma_data_direction dir,
2651 struct dma_attrs *attrs)
2653 unsigned long flags;
2654 struct protection_domain *domain;
2655 struct scatterlist *s;
2658 INC_STATS_COUNTER(cnt_unmap_sg);
2660 domain = get_domain(dev);
2664 spin_lock_irqsave(&domain->lock, flags);
2666 for_each_sg(sglist, s, nelems, i) {
2667 __unmap_single(domain->priv, s->dma_address,
2668 s->dma_length, dir);
2669 s->dma_address = s->dma_length = 0;
2672 domain_flush_complete(domain);
2674 spin_unlock_irqrestore(&domain->lock, flags);
2678 * The exported alloc_coherent function for dma_ops.
2680 static void *alloc_coherent(struct device *dev, size_t size,
2681 dma_addr_t *dma_addr, gfp_t flag)
2683 unsigned long flags;
2685 struct protection_domain *domain;
2687 u64 dma_mask = dev->coherent_dma_mask;
2689 INC_STATS_COUNTER(cnt_alloc_coherent);
2691 domain = get_domain(dev);
2692 if (PTR_ERR(domain) == -EINVAL) {
2693 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2694 *dma_addr = __pa(virt_addr);
2696 } else if (IS_ERR(domain))
2699 dma_mask = dev->coherent_dma_mask;
2700 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2703 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2707 paddr = virt_to_phys(virt_addr);
2710 dma_mask = *dev->dma_mask;
2712 spin_lock_irqsave(&domain->lock, flags);
2714 *dma_addr = __map_single(dev, domain->priv, paddr,
2715 size, DMA_BIDIRECTIONAL, true, dma_mask);
2717 if (*dma_addr == DMA_ERROR_CODE) {
2718 spin_unlock_irqrestore(&domain->lock, flags);
2722 domain_flush_complete(domain);
2724 spin_unlock_irqrestore(&domain->lock, flags);
2730 free_pages((unsigned long)virt_addr, get_order(size));
2736 * The exported free_coherent function for dma_ops.
2738 static void free_coherent(struct device *dev, size_t size,
2739 void *virt_addr, dma_addr_t dma_addr)
2741 unsigned long flags;
2742 struct protection_domain *domain;
2744 INC_STATS_COUNTER(cnt_free_coherent);
2746 domain = get_domain(dev);
2750 spin_lock_irqsave(&domain->lock, flags);
2752 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2754 domain_flush_complete(domain);
2756 spin_unlock_irqrestore(&domain->lock, flags);
2759 free_pages((unsigned long)virt_addr, get_order(size));
2763 * This function is called by the DMA layer to find out if we can handle a
2764 * particular device. It is part of the dma_ops.
2766 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2768 return check_device(dev);
2772 * The function for pre-allocating protection domains.
2774 * If the driver core informs the DMA layer if a driver grabs a device
2775 * we don't need to preallocate the protection domains anymore.
2776 * For now we have to.
2778 static void prealloc_protection_domains(void)
2780 struct iommu_dev_data *dev_data;
2781 struct dma_ops_domain *dma_dom;
2782 struct pci_dev *dev = NULL;
2785 for_each_pci_dev(dev) {
2787 /* Do we handle this device? */
2788 if (!check_device(&dev->dev))
2791 dev_data = get_dev_data(&dev->dev);
2792 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
2793 /* Make sure passthrough domain is allocated */
2794 alloc_passthrough_domain();
2795 dev_data->passthrough = true;
2796 attach_device(&dev->dev, pt_domain);
2797 pr_info("AMD-Vi: Using passthough domain for device %s\n",
2798 dev_name(&dev->dev));
2801 /* Is there already any domain for it? */
2802 if (domain_for_device(&dev->dev))
2805 devid = get_device_id(&dev->dev);
2807 dma_dom = dma_ops_domain_alloc();
2810 init_unity_mappings_for_device(dma_dom, devid);
2811 dma_dom->target_dev = devid;
2813 attach_device(&dev->dev, &dma_dom->domain);
2815 list_add_tail(&dma_dom->list, &iommu_pd_list);
2819 static struct dma_map_ops amd_iommu_dma_ops = {
2820 .alloc_coherent = alloc_coherent,
2821 .free_coherent = free_coherent,
2822 .map_page = map_page,
2823 .unmap_page = unmap_page,
2825 .unmap_sg = unmap_sg,
2826 .dma_supported = amd_iommu_dma_supported,
2829 static unsigned device_dma_ops_init(void)
2831 struct iommu_dev_data *dev_data;
2832 struct pci_dev *pdev = NULL;
2833 unsigned unhandled = 0;
2835 for_each_pci_dev(pdev) {
2836 if (!check_device(&pdev->dev)) {
2841 dev_data = get_dev_data(&pdev->dev);
2843 if (!dev_data->passthrough)
2844 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
2846 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
2853 * The function which clues the AMD IOMMU driver into dma_ops.
2856 void __init amd_iommu_init_api(void)
2858 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2861 int __init amd_iommu_init_dma_ops(void)
2863 struct amd_iommu *iommu;
2867 * first allocate a default protection domain for every IOMMU we
2868 * found in the system. Devices not assigned to any other
2869 * protection domain will be assigned to the default one.
2871 for_each_iommu(iommu) {
2872 iommu->default_dom = dma_ops_domain_alloc();
2873 if (iommu->default_dom == NULL)
2875 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2876 ret = iommu_init_unity_mappings(iommu);
2882 * Pre-allocate the protection domains for each device.
2884 prealloc_protection_domains();
2889 /* Make the driver finally visible to the drivers */
2890 unhandled = device_dma_ops_init();
2891 if (unhandled && max_pfn > MAX_DMA32_PFN) {
2892 /* There are unhandled devices - initialize swiotlb for them */
2896 amd_iommu_stats_init();
2902 for_each_iommu(iommu) {
2903 if (iommu->default_dom)
2904 dma_ops_domain_free(iommu->default_dom);
2910 /*****************************************************************************
2912 * The following functions belong to the exported interface of AMD IOMMU
2914 * This interface allows access to lower level functions of the IOMMU
2915 * like protection domain handling and assignement of devices to domains
2916 * which is not possible with the dma_ops interface.
2918 *****************************************************************************/
2920 static void cleanup_domain(struct protection_domain *domain)
2922 struct iommu_dev_data *dev_data, *next;
2923 unsigned long flags;
2925 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2927 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
2928 __detach_device(dev_data);
2929 atomic_set(&dev_data->bind, 0);
2932 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2935 static void protection_domain_free(struct protection_domain *domain)
2940 del_domain_from_list(domain);
2943 domain_id_free(domain->id);
2948 static struct protection_domain *protection_domain_alloc(void)
2950 struct protection_domain *domain;
2952 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2956 spin_lock_init(&domain->lock);
2957 mutex_init(&domain->api_lock);
2958 domain->id = domain_id_alloc();
2961 INIT_LIST_HEAD(&domain->dev_list);
2963 add_domain_to_list(domain);
2973 static int __init alloc_passthrough_domain(void)
2975 if (pt_domain != NULL)
2978 /* allocate passthrough domain */
2979 pt_domain = protection_domain_alloc();
2983 pt_domain->mode = PAGE_MODE_NONE;
2987 static int amd_iommu_domain_init(struct iommu_domain *dom)
2989 struct protection_domain *domain;
2991 domain = protection_domain_alloc();
2995 domain->mode = PAGE_MODE_3_LEVEL;
2996 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2997 if (!domain->pt_root)
3000 domain->iommu_domain = dom;
3007 protection_domain_free(domain);
3012 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
3014 struct protection_domain *domain = dom->priv;
3019 if (domain->dev_cnt > 0)
3020 cleanup_domain(domain);
3022 BUG_ON(domain->dev_cnt != 0);
3024 if (domain->mode != PAGE_MODE_NONE)
3025 free_pagetable(domain);
3027 if (domain->flags & PD_IOMMUV2_MASK)
3028 free_gcr3_table(domain);
3030 protection_domain_free(domain);
3035 static void amd_iommu_detach_device(struct iommu_domain *dom,
3038 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3039 struct amd_iommu *iommu;
3042 if (!check_device(dev))
3045 devid = get_device_id(dev);
3047 if (dev_data->domain != NULL)
3050 iommu = amd_iommu_rlookup_table[devid];
3054 iommu_completion_wait(iommu);
3057 static int amd_iommu_attach_device(struct iommu_domain *dom,
3060 struct protection_domain *domain = dom->priv;
3061 struct iommu_dev_data *dev_data;
3062 struct amd_iommu *iommu;
3065 if (!check_device(dev))
3068 dev_data = dev->archdata.iommu;
3070 iommu = amd_iommu_rlookup_table[dev_data->devid];
3074 if (dev_data->domain)
3077 ret = attach_device(dev, domain);
3079 iommu_completion_wait(iommu);
3084 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3085 phys_addr_t paddr, int gfp_order, int iommu_prot)
3087 unsigned long page_size = 0x1000UL << gfp_order;
3088 struct protection_domain *domain = dom->priv;
3092 if (domain->mode == PAGE_MODE_NONE)
3095 if (iommu_prot & IOMMU_READ)
3096 prot |= IOMMU_PROT_IR;
3097 if (iommu_prot & IOMMU_WRITE)
3098 prot |= IOMMU_PROT_IW;
3100 mutex_lock(&domain->api_lock);
3101 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
3102 mutex_unlock(&domain->api_lock);
3107 static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3110 struct protection_domain *domain = dom->priv;
3111 unsigned long page_size, unmap_size;
3113 if (domain->mode == PAGE_MODE_NONE)
3116 page_size = 0x1000UL << gfp_order;
3118 mutex_lock(&domain->api_lock);
3119 unmap_size = iommu_unmap_page(domain, iova, page_size);
3120 mutex_unlock(&domain->api_lock);
3122 domain_flush_tlb_pde(domain);
3124 return get_order(unmap_size);
3127 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3130 struct protection_domain *domain = dom->priv;
3131 unsigned long offset_mask;
3135 if (domain->mode == PAGE_MODE_NONE)
3138 pte = fetch_pte(domain, iova);
3140 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3143 if (PM_PTE_LEVEL(*pte) == 0)
3144 offset_mask = PAGE_SIZE - 1;
3146 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
3148 __pte = *pte & PM_ADDR_MASK;
3149 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
3154 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
3158 case IOMMU_CAP_CACHE_COHERENCY:
3165 static struct iommu_ops amd_iommu_ops = {
3166 .domain_init = amd_iommu_domain_init,
3167 .domain_destroy = amd_iommu_domain_destroy,
3168 .attach_dev = amd_iommu_attach_device,
3169 .detach_dev = amd_iommu_detach_device,
3170 .map = amd_iommu_map,
3171 .unmap = amd_iommu_unmap,
3172 .iova_to_phys = amd_iommu_iova_to_phys,
3173 .domain_has_cap = amd_iommu_domain_has_cap,
3176 /*****************************************************************************
3178 * The next functions do a basic initialization of IOMMU for pass through
3181 * In passthrough mode the IOMMU is initialized and enabled but not used for
3182 * DMA-API translation.
3184 *****************************************************************************/
3186 int __init amd_iommu_init_passthrough(void)
3188 struct iommu_dev_data *dev_data;
3189 struct pci_dev *dev = NULL;
3190 struct amd_iommu *iommu;
3194 ret = alloc_passthrough_domain();
3198 for_each_pci_dev(dev) {
3199 if (!check_device(&dev->dev))
3202 dev_data = get_dev_data(&dev->dev);
3203 dev_data->passthrough = true;
3205 devid = get_device_id(&dev->dev);
3207 iommu = amd_iommu_rlookup_table[devid];
3211 attach_device(&dev->dev, pt_domain);
3214 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3219 /* IOMMUv2 specific functions */
3220 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3222 return atomic_notifier_chain_register(&ppr_notifier, nb);
3224 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3226 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3228 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3230 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3232 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3234 struct protection_domain *domain = dom->priv;
3235 unsigned long flags;
3237 spin_lock_irqsave(&domain->lock, flags);
3239 /* Update data structure */
3240 domain->mode = PAGE_MODE_NONE;
3241 domain->updated = true;
3243 /* Make changes visible to IOMMUs */
3244 update_domain(domain);
3246 /* Page-table is not visible to IOMMU anymore, so free it */
3247 free_pagetable(domain);
3249 spin_unlock_irqrestore(&domain->lock, flags);
3251 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3253 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3255 struct protection_domain *domain = dom->priv;
3256 unsigned long flags;
3259 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3262 /* Number of GCR3 table levels required */
3263 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3266 if (levels > amd_iommu_max_glx_val)
3269 spin_lock_irqsave(&domain->lock, flags);
3272 * Save us all sanity checks whether devices already in the
3273 * domain support IOMMUv2. Just force that the domain has no
3274 * devices attached when it is switched into IOMMUv2 mode.
3277 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3281 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3282 if (domain->gcr3_tbl == NULL)
3285 domain->glx = levels;
3286 domain->flags |= PD_IOMMUV2_MASK;
3287 domain->updated = true;
3289 update_domain(domain);
3294 spin_unlock_irqrestore(&domain->lock, flags);
3298 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3300 static int __flush_pasid(struct protection_domain *domain, int pasid,
3301 u64 address, bool size)
3303 struct iommu_dev_data *dev_data;
3304 struct iommu_cmd cmd;
3307 if (!(domain->flags & PD_IOMMUV2_MASK))
3310 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3313 * IOMMU TLB needs to be flushed before Device TLB to
3314 * prevent device TLB refill from IOMMU TLB
3316 for (i = 0; i < amd_iommus_present; ++i) {
3317 if (domain->dev_iommu[i] == 0)
3320 ret = iommu_queue_command(amd_iommus[i], &cmd);
3325 /* Wait until IOMMU TLB flushes are complete */
3326 domain_flush_complete(domain);
3328 /* Now flush device TLBs */
3329 list_for_each_entry(dev_data, &domain->dev_list, list) {
3330 struct amd_iommu *iommu;
3333 BUG_ON(!dev_data->ats.enabled);
3335 qdep = dev_data->ats.qdep;
3336 iommu = amd_iommu_rlookup_table[dev_data->devid];
3338 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3339 qdep, address, size);
3341 ret = iommu_queue_command(iommu, &cmd);
3346 /* Wait until all device TLBs are flushed */
3347 domain_flush_complete(domain);
3356 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3359 return __flush_pasid(domain, pasid, address, false);
3362 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3365 struct protection_domain *domain = dom->priv;
3366 unsigned long flags;
3369 spin_lock_irqsave(&domain->lock, flags);
3370 ret = __amd_iommu_flush_page(domain, pasid, address);
3371 spin_unlock_irqrestore(&domain->lock, flags);
3375 EXPORT_SYMBOL(amd_iommu_flush_page);
3377 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3379 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3383 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3385 struct protection_domain *domain = dom->priv;
3386 unsigned long flags;
3389 spin_lock_irqsave(&domain->lock, flags);
3390 ret = __amd_iommu_flush_tlb(domain, pasid);
3391 spin_unlock_irqrestore(&domain->lock, flags);
3395 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3397 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3404 index = (pasid >> (9 * level)) & 0x1ff;
3410 if (!(*pte & GCR3_VALID)) {
3414 root = (void *)get_zeroed_page(GFP_ATOMIC);
3418 *pte = __pa(root) | GCR3_VALID;
3421 root = __va(*pte & PAGE_MASK);
3429 static int __set_gcr3(struct protection_domain *domain, int pasid,
3434 if (domain->mode != PAGE_MODE_NONE)
3437 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3441 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3443 return __amd_iommu_flush_tlb(domain, pasid);
3446 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3450 if (domain->mode != PAGE_MODE_NONE)
3453 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3459 return __amd_iommu_flush_tlb(domain, pasid);
3462 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3465 struct protection_domain *domain = dom->priv;
3466 unsigned long flags;
3469 spin_lock_irqsave(&domain->lock, flags);
3470 ret = __set_gcr3(domain, pasid, cr3);
3471 spin_unlock_irqrestore(&domain->lock, flags);
3475 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3477 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3479 struct protection_domain *domain = dom->priv;
3480 unsigned long flags;
3483 spin_lock_irqsave(&domain->lock, flags);
3484 ret = __clear_gcr3(domain, pasid);
3485 spin_unlock_irqrestore(&domain->lock, flags);
3489 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3491 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3492 int status, int tag)
3494 struct iommu_dev_data *dev_data;
3495 struct amd_iommu *iommu;
3496 struct iommu_cmd cmd;
3498 dev_data = get_dev_data(&pdev->dev);
3499 iommu = amd_iommu_rlookup_table[dev_data->devid];
3501 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3502 tag, dev_data->pri_tlp);
3504 return iommu_queue_command(iommu, &cmd);
3506 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3508 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3510 struct protection_domain *domain;
3512 domain = get_domain(&pdev->dev);
3516 /* Only return IOMMUv2 domains */
3517 if (!(domain->flags & PD_IOMMUV2_MASK))
3520 return domain->iommu_domain;
3522 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3524 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3526 struct iommu_dev_data *dev_data;
3528 if (!amd_iommu_v2_supported())
3531 dev_data = get_dev_data(&pdev->dev);
3532 dev_data->errata |= (1 << erratum);
3534 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);