2 * IOMMU API for ARM architected SMMUv3 implementations.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 * Copyright (C) 2015 ARM Limited
18 * Author: Will Deacon <will.deacon@arm.com>
20 * This driver is powered by bad coffee and bombay mix.
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/interrupt.h>
26 #include <linux/iommu.h>
27 #include <linux/iopoll.h>
28 #include <linux/module.h>
29 #include <linux/msi.h>
31 #include <linux/of_address.h>
32 #include <linux/of_platform.h>
33 #include <linux/pci.h>
34 #include <linux/platform_device.h>
36 #include "io-pgtable.h"
39 #define ARM_SMMU_IDR0 0x0
40 #define IDR0_ST_LVL_SHIFT 27
41 #define IDR0_ST_LVL_MASK 0x3
42 #define IDR0_ST_LVL_2LVL (1 << IDR0_ST_LVL_SHIFT)
43 #define IDR0_STALL_MODEL (3 << 24)
44 #define IDR0_TTENDIAN_SHIFT 21
45 #define IDR0_TTENDIAN_MASK 0x3
46 #define IDR0_TTENDIAN_LE (2 << IDR0_TTENDIAN_SHIFT)
47 #define IDR0_TTENDIAN_BE (3 << IDR0_TTENDIAN_SHIFT)
48 #define IDR0_TTENDIAN_MIXED (0 << IDR0_TTENDIAN_SHIFT)
49 #define IDR0_CD2L (1 << 19)
50 #define IDR0_VMID16 (1 << 18)
51 #define IDR0_PRI (1 << 16)
52 #define IDR0_SEV (1 << 14)
53 #define IDR0_MSI (1 << 13)
54 #define IDR0_ASID16 (1 << 12)
55 #define IDR0_ATS (1 << 10)
56 #define IDR0_HYP (1 << 9)
57 #define IDR0_COHACC (1 << 4)
58 #define IDR0_TTF_SHIFT 2
59 #define IDR0_TTF_MASK 0x3
60 #define IDR0_TTF_AARCH64 (2 << IDR0_TTF_SHIFT)
61 #define IDR0_TTF_AARCH32_64 (3 << IDR0_TTF_SHIFT)
62 #define IDR0_S1P (1 << 1)
63 #define IDR0_S2P (1 << 0)
65 #define ARM_SMMU_IDR1 0x4
66 #define IDR1_TABLES_PRESET (1 << 30)
67 #define IDR1_QUEUES_PRESET (1 << 29)
68 #define IDR1_REL (1 << 28)
69 #define IDR1_CMDQ_SHIFT 21
70 #define IDR1_CMDQ_MASK 0x1f
71 #define IDR1_EVTQ_SHIFT 16
72 #define IDR1_EVTQ_MASK 0x1f
73 #define IDR1_PRIQ_SHIFT 11
74 #define IDR1_PRIQ_MASK 0x1f
75 #define IDR1_SSID_SHIFT 6
76 #define IDR1_SSID_MASK 0x1f
77 #define IDR1_SID_SHIFT 0
78 #define IDR1_SID_MASK 0x3f
80 #define ARM_SMMU_IDR5 0x14
81 #define IDR5_STALL_MAX_SHIFT 16
82 #define IDR5_STALL_MAX_MASK 0xffff
83 #define IDR5_GRAN64K (1 << 6)
84 #define IDR5_GRAN16K (1 << 5)
85 #define IDR5_GRAN4K (1 << 4)
86 #define IDR5_OAS_SHIFT 0
87 #define IDR5_OAS_MASK 0x7
88 #define IDR5_OAS_32_BIT (0 << IDR5_OAS_SHIFT)
89 #define IDR5_OAS_36_BIT (1 << IDR5_OAS_SHIFT)
90 #define IDR5_OAS_40_BIT (2 << IDR5_OAS_SHIFT)
91 #define IDR5_OAS_42_BIT (3 << IDR5_OAS_SHIFT)
92 #define IDR5_OAS_44_BIT (4 << IDR5_OAS_SHIFT)
93 #define IDR5_OAS_48_BIT (5 << IDR5_OAS_SHIFT)
95 #define ARM_SMMU_CR0 0x20
96 #define CR0_CMDQEN (1 << 3)
97 #define CR0_EVTQEN (1 << 2)
98 #define CR0_PRIQEN (1 << 1)
99 #define CR0_SMMUEN (1 << 0)
101 #define ARM_SMMU_CR0ACK 0x24
103 #define ARM_SMMU_CR1 0x28
107 #define CR1_CACHE_NC 0
108 #define CR1_CACHE_WB 1
109 #define CR1_CACHE_WT 2
110 #define CR1_TABLE_SH_SHIFT 10
111 #define CR1_TABLE_OC_SHIFT 8
112 #define CR1_TABLE_IC_SHIFT 6
113 #define CR1_QUEUE_SH_SHIFT 4
114 #define CR1_QUEUE_OC_SHIFT 2
115 #define CR1_QUEUE_IC_SHIFT 0
117 #define ARM_SMMU_CR2 0x2c
118 #define CR2_PTM (1 << 2)
119 #define CR2_RECINVSID (1 << 1)
120 #define CR2_E2H (1 << 0)
122 #define ARM_SMMU_IRQ_CTRL 0x50
123 #define IRQ_CTRL_EVTQ_IRQEN (1 << 2)
124 #define IRQ_CTRL_PRIQ_IRQEN (1 << 1)
125 #define IRQ_CTRL_GERROR_IRQEN (1 << 0)
127 #define ARM_SMMU_IRQ_CTRLACK 0x54
129 #define ARM_SMMU_GERROR 0x60
130 #define GERROR_SFM_ERR (1 << 8)
131 #define GERROR_MSI_GERROR_ABT_ERR (1 << 7)
132 #define GERROR_MSI_PRIQ_ABT_ERR (1 << 6)
133 #define GERROR_MSI_EVTQ_ABT_ERR (1 << 5)
134 #define GERROR_MSI_CMDQ_ABT_ERR (1 << 4)
135 #define GERROR_PRIQ_ABT_ERR (1 << 3)
136 #define GERROR_EVTQ_ABT_ERR (1 << 2)
137 #define GERROR_CMDQ_ERR (1 << 0)
138 #define GERROR_ERR_MASK 0xfd
140 #define ARM_SMMU_GERRORN 0x64
142 #define ARM_SMMU_GERROR_IRQ_CFG0 0x68
143 #define ARM_SMMU_GERROR_IRQ_CFG1 0x70
144 #define ARM_SMMU_GERROR_IRQ_CFG2 0x74
146 #define ARM_SMMU_STRTAB_BASE 0x80
147 #define STRTAB_BASE_RA (1UL << 62)
148 #define STRTAB_BASE_ADDR_SHIFT 6
149 #define STRTAB_BASE_ADDR_MASK 0x3ffffffffffUL
151 #define ARM_SMMU_STRTAB_BASE_CFG 0x88
152 #define STRTAB_BASE_CFG_LOG2SIZE_SHIFT 0
153 #define STRTAB_BASE_CFG_LOG2SIZE_MASK 0x3f
154 #define STRTAB_BASE_CFG_SPLIT_SHIFT 6
155 #define STRTAB_BASE_CFG_SPLIT_MASK 0x1f
156 #define STRTAB_BASE_CFG_FMT_SHIFT 16
157 #define STRTAB_BASE_CFG_FMT_MASK 0x3
158 #define STRTAB_BASE_CFG_FMT_LINEAR (0 << STRTAB_BASE_CFG_FMT_SHIFT)
159 #define STRTAB_BASE_CFG_FMT_2LVL (1 << STRTAB_BASE_CFG_FMT_SHIFT)
161 #define ARM_SMMU_CMDQ_BASE 0x90
162 #define ARM_SMMU_CMDQ_PROD 0x98
163 #define ARM_SMMU_CMDQ_CONS 0x9c
165 #define ARM_SMMU_EVTQ_BASE 0xa0
166 #define ARM_SMMU_EVTQ_PROD 0x100a8
167 #define ARM_SMMU_EVTQ_CONS 0x100ac
168 #define ARM_SMMU_EVTQ_IRQ_CFG0 0xb0
169 #define ARM_SMMU_EVTQ_IRQ_CFG1 0xb8
170 #define ARM_SMMU_EVTQ_IRQ_CFG2 0xbc
172 #define ARM_SMMU_PRIQ_BASE 0xc0
173 #define ARM_SMMU_PRIQ_PROD 0x100c8
174 #define ARM_SMMU_PRIQ_CONS 0x100cc
175 #define ARM_SMMU_PRIQ_IRQ_CFG0 0xd0
176 #define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8
177 #define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc
179 /* Common MSI config fields */
180 #define MSI_CFG0_ADDR_SHIFT 2
181 #define MSI_CFG0_ADDR_MASK 0x3fffffffffffUL
182 #define MSI_CFG2_SH_SHIFT 4
183 #define MSI_CFG2_SH_NSH (0UL << MSI_CFG2_SH_SHIFT)
184 #define MSI_CFG2_SH_OSH (2UL << MSI_CFG2_SH_SHIFT)
185 #define MSI_CFG2_SH_ISH (3UL << MSI_CFG2_SH_SHIFT)
186 #define MSI_CFG2_MEMATTR_SHIFT 0
187 #define MSI_CFG2_MEMATTR_DEVICE_nGnRE (0x1 << MSI_CFG2_MEMATTR_SHIFT)
189 #define Q_IDX(q, p) ((p) & ((1 << (q)->max_n_shift) - 1))
190 #define Q_WRP(q, p) ((p) & (1 << (q)->max_n_shift))
191 #define Q_OVERFLOW_FLAG (1 << 31)
192 #define Q_OVF(q, p) ((p) & Q_OVERFLOW_FLAG)
193 #define Q_ENT(q, p) ((q)->base + \
194 Q_IDX(q, p) * (q)->ent_dwords)
196 #define Q_BASE_RWA (1UL << 62)
197 #define Q_BASE_ADDR_SHIFT 5
198 #define Q_BASE_ADDR_MASK 0xfffffffffffUL
199 #define Q_BASE_LOG2SIZE_SHIFT 0
200 #define Q_BASE_LOG2SIZE_MASK 0x1fUL
205 * Linear: Enough to cover 1 << IDR1.SIDSIZE entries
206 * 2lvl: 128k L1 entries,
207 * 256 lazy entries per table (each table covers a PCI bus)
209 #define STRTAB_L1_SZ_SHIFT 20
210 #define STRTAB_SPLIT 8
212 #define STRTAB_L1_DESC_DWORDS 1
213 #define STRTAB_L1_DESC_SPAN_SHIFT 0
214 #define STRTAB_L1_DESC_SPAN_MASK 0x1fUL
215 #define STRTAB_L1_DESC_L2PTR_SHIFT 6
216 #define STRTAB_L1_DESC_L2PTR_MASK 0x3ffffffffffUL
218 #define STRTAB_STE_DWORDS 8
219 #define STRTAB_STE_0_V (1UL << 0)
220 #define STRTAB_STE_0_CFG_SHIFT 1
221 #define STRTAB_STE_0_CFG_MASK 0x7UL
222 #define STRTAB_STE_0_CFG_ABORT (0UL << STRTAB_STE_0_CFG_SHIFT)
223 #define STRTAB_STE_0_CFG_BYPASS (4UL << STRTAB_STE_0_CFG_SHIFT)
224 #define STRTAB_STE_0_CFG_S1_TRANS (5UL << STRTAB_STE_0_CFG_SHIFT)
225 #define STRTAB_STE_0_CFG_S2_TRANS (6UL << STRTAB_STE_0_CFG_SHIFT)
227 #define STRTAB_STE_0_S1FMT_SHIFT 4
228 #define STRTAB_STE_0_S1FMT_LINEAR (0UL << STRTAB_STE_0_S1FMT_SHIFT)
229 #define STRTAB_STE_0_S1CTXPTR_SHIFT 6
230 #define STRTAB_STE_0_S1CTXPTR_MASK 0x3ffffffffffUL
231 #define STRTAB_STE_0_S1CDMAX_SHIFT 59
232 #define STRTAB_STE_0_S1CDMAX_MASK 0x1fUL
234 #define STRTAB_STE_1_S1C_CACHE_NC 0UL
235 #define STRTAB_STE_1_S1C_CACHE_WBRA 1UL
236 #define STRTAB_STE_1_S1C_CACHE_WT 2UL
237 #define STRTAB_STE_1_S1C_CACHE_WB 3UL
238 #define STRTAB_STE_1_S1C_SH_NSH 0UL
239 #define STRTAB_STE_1_S1C_SH_OSH 2UL
240 #define STRTAB_STE_1_S1C_SH_ISH 3UL
241 #define STRTAB_STE_1_S1CIR_SHIFT 2
242 #define STRTAB_STE_1_S1COR_SHIFT 4
243 #define STRTAB_STE_1_S1CSH_SHIFT 6
245 #define STRTAB_STE_1_S1STALLD (1UL << 27)
247 #define STRTAB_STE_1_EATS_ABT 0UL
248 #define STRTAB_STE_1_EATS_TRANS 1UL
249 #define STRTAB_STE_1_EATS_S1CHK 2UL
250 #define STRTAB_STE_1_EATS_SHIFT 28
252 #define STRTAB_STE_1_STRW_NSEL1 0UL
253 #define STRTAB_STE_1_STRW_EL2 2UL
254 #define STRTAB_STE_1_STRW_SHIFT 30
256 #define STRTAB_STE_2_S2VMID_SHIFT 0
257 #define STRTAB_STE_2_S2VMID_MASK 0xffffUL
258 #define STRTAB_STE_2_VTCR_SHIFT 32
259 #define STRTAB_STE_2_VTCR_MASK 0x7ffffUL
260 #define STRTAB_STE_2_S2AA64 (1UL << 51)
261 #define STRTAB_STE_2_S2ENDI (1UL << 52)
262 #define STRTAB_STE_2_S2PTW (1UL << 54)
263 #define STRTAB_STE_2_S2R (1UL << 58)
265 #define STRTAB_STE_3_S2TTB_SHIFT 4
266 #define STRTAB_STE_3_S2TTB_MASK 0xfffffffffffUL
268 /* Context descriptor (stage-1 only) */
269 #define CTXDESC_CD_DWORDS 8
270 #define CTXDESC_CD_0_TCR_T0SZ_SHIFT 0
271 #define ARM64_TCR_T0SZ_SHIFT 0
272 #define ARM64_TCR_T0SZ_MASK 0x1fUL
273 #define CTXDESC_CD_0_TCR_TG0_SHIFT 6
274 #define ARM64_TCR_TG0_SHIFT 14
275 #define ARM64_TCR_TG0_MASK 0x3UL
276 #define CTXDESC_CD_0_TCR_IRGN0_SHIFT 8
277 #define ARM64_TCR_IRGN0_SHIFT 8
278 #define ARM64_TCR_IRGN0_MASK 0x3UL
279 #define CTXDESC_CD_0_TCR_ORGN0_SHIFT 10
280 #define ARM64_TCR_ORGN0_SHIFT 10
281 #define ARM64_TCR_ORGN0_MASK 0x3UL
282 #define CTXDESC_CD_0_TCR_SH0_SHIFT 12
283 #define ARM64_TCR_SH0_SHIFT 12
284 #define ARM64_TCR_SH0_MASK 0x3UL
285 #define CTXDESC_CD_0_TCR_EPD0_SHIFT 14
286 #define ARM64_TCR_EPD0_SHIFT 7
287 #define ARM64_TCR_EPD0_MASK 0x1UL
288 #define CTXDESC_CD_0_TCR_EPD1_SHIFT 30
289 #define ARM64_TCR_EPD1_SHIFT 23
290 #define ARM64_TCR_EPD1_MASK 0x1UL
292 #define CTXDESC_CD_0_ENDI (1UL << 15)
293 #define CTXDESC_CD_0_V (1UL << 31)
295 #define CTXDESC_CD_0_TCR_IPS_SHIFT 32
296 #define ARM64_TCR_IPS_SHIFT 32
297 #define ARM64_TCR_IPS_MASK 0x7UL
298 #define CTXDESC_CD_0_TCR_TBI0_SHIFT 38
299 #define ARM64_TCR_TBI0_SHIFT 37
300 #define ARM64_TCR_TBI0_MASK 0x1UL
302 #define CTXDESC_CD_0_AA64 (1UL << 41)
303 #define CTXDESC_CD_0_R (1UL << 45)
304 #define CTXDESC_CD_0_A (1UL << 46)
305 #define CTXDESC_CD_0_ASET_SHIFT 47
306 #define CTXDESC_CD_0_ASET_SHARED (0UL << CTXDESC_CD_0_ASET_SHIFT)
307 #define CTXDESC_CD_0_ASET_PRIVATE (1UL << CTXDESC_CD_0_ASET_SHIFT)
308 #define CTXDESC_CD_0_ASID_SHIFT 48
309 #define CTXDESC_CD_0_ASID_MASK 0xffffUL
311 #define CTXDESC_CD_1_TTB0_SHIFT 4
312 #define CTXDESC_CD_1_TTB0_MASK 0xfffffffffffUL
314 #define CTXDESC_CD_3_MAIR_SHIFT 0
316 /* Convert between AArch64 (CPU) TCR format and SMMU CD format */
317 #define ARM_SMMU_TCR2CD(tcr, fld) \
318 (((tcr) >> ARM64_TCR_##fld##_SHIFT & ARM64_TCR_##fld##_MASK) \
319 << CTXDESC_CD_0_TCR_##fld##_SHIFT)
322 #define CMDQ_ENT_DWORDS 2
323 #define CMDQ_MAX_SZ_SHIFT 8
325 #define CMDQ_ERR_SHIFT 24
326 #define CMDQ_ERR_MASK 0x7f
327 #define CMDQ_ERR_CERROR_NONE_IDX 0
328 #define CMDQ_ERR_CERROR_ILL_IDX 1
329 #define CMDQ_ERR_CERROR_ABT_IDX 2
331 #define CMDQ_0_OP_SHIFT 0
332 #define CMDQ_0_OP_MASK 0xffUL
333 #define CMDQ_0_SSV (1UL << 11)
335 #define CMDQ_PREFETCH_0_SID_SHIFT 32
336 #define CMDQ_PREFETCH_1_SIZE_SHIFT 0
337 #define CMDQ_PREFETCH_1_ADDR_MASK ~0xfffUL
339 #define CMDQ_CFGI_0_SID_SHIFT 32
340 #define CMDQ_CFGI_0_SID_MASK 0xffffffffUL
341 #define CMDQ_CFGI_1_LEAF (1UL << 0)
342 #define CMDQ_CFGI_1_RANGE_SHIFT 0
343 #define CMDQ_CFGI_1_RANGE_MASK 0x1fUL
345 #define CMDQ_TLBI_0_VMID_SHIFT 32
346 #define CMDQ_TLBI_0_ASID_SHIFT 48
347 #define CMDQ_TLBI_1_LEAF (1UL << 0)
348 #define CMDQ_TLBI_1_VA_MASK ~0xfffUL
349 #define CMDQ_TLBI_1_IPA_MASK 0xfffffffff000UL
351 #define CMDQ_PRI_0_SSID_SHIFT 12
352 #define CMDQ_PRI_0_SSID_MASK 0xfffffUL
353 #define CMDQ_PRI_0_SID_SHIFT 32
354 #define CMDQ_PRI_0_SID_MASK 0xffffffffUL
355 #define CMDQ_PRI_1_GRPID_SHIFT 0
356 #define CMDQ_PRI_1_GRPID_MASK 0x1ffUL
357 #define CMDQ_PRI_1_RESP_SHIFT 12
358 #define CMDQ_PRI_1_RESP_DENY (0UL << CMDQ_PRI_1_RESP_SHIFT)
359 #define CMDQ_PRI_1_RESP_FAIL (1UL << CMDQ_PRI_1_RESP_SHIFT)
360 #define CMDQ_PRI_1_RESP_SUCC (2UL << CMDQ_PRI_1_RESP_SHIFT)
362 #define CMDQ_SYNC_0_CS_SHIFT 12
363 #define CMDQ_SYNC_0_CS_NONE (0UL << CMDQ_SYNC_0_CS_SHIFT)
364 #define CMDQ_SYNC_0_CS_SEV (2UL << CMDQ_SYNC_0_CS_SHIFT)
367 #define EVTQ_ENT_DWORDS 4
368 #define EVTQ_MAX_SZ_SHIFT 7
370 #define EVTQ_0_ID_SHIFT 0
371 #define EVTQ_0_ID_MASK 0xffUL
374 #define PRIQ_ENT_DWORDS 2
375 #define PRIQ_MAX_SZ_SHIFT 8
377 #define PRIQ_0_SID_SHIFT 0
378 #define PRIQ_0_SID_MASK 0xffffffffUL
379 #define PRIQ_0_SSID_SHIFT 32
380 #define PRIQ_0_SSID_MASK 0xfffffUL
381 #define PRIQ_0_PERM_PRIV (1UL << 58)
382 #define PRIQ_0_PERM_EXEC (1UL << 59)
383 #define PRIQ_0_PERM_READ (1UL << 60)
384 #define PRIQ_0_PERM_WRITE (1UL << 61)
385 #define PRIQ_0_PRG_LAST (1UL << 62)
386 #define PRIQ_0_SSID_V (1UL << 63)
388 #define PRIQ_1_PRG_IDX_SHIFT 0
389 #define PRIQ_1_PRG_IDX_MASK 0x1ffUL
390 #define PRIQ_1_ADDR_SHIFT 12
391 #define PRIQ_1_ADDR_MASK 0xfffffffffffffUL
393 /* High-level queue structures */
394 #define ARM_SMMU_POLL_TIMEOUT_US 100
396 static bool disable_bypass;
397 module_param_named(disable_bypass, disable_bypass, bool, S_IRUGO);
398 MODULE_PARM_DESC(disable_bypass,
399 "Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
407 enum arm_smmu_msi_index {
414 static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = {
416 ARM_SMMU_EVTQ_IRQ_CFG0,
417 ARM_SMMU_EVTQ_IRQ_CFG1,
418 ARM_SMMU_EVTQ_IRQ_CFG2,
420 [GERROR_MSI_INDEX] = {
421 ARM_SMMU_GERROR_IRQ_CFG0,
422 ARM_SMMU_GERROR_IRQ_CFG1,
423 ARM_SMMU_GERROR_IRQ_CFG2,
426 ARM_SMMU_PRIQ_IRQ_CFG0,
427 ARM_SMMU_PRIQ_IRQ_CFG1,
428 ARM_SMMU_PRIQ_IRQ_CFG2,
432 struct arm_smmu_cmdq_ent {
435 bool substream_valid;
437 /* Command-specific fields */
439 #define CMDQ_OP_PREFETCH_CFG 0x1
446 #define CMDQ_OP_CFGI_STE 0x3
447 #define CMDQ_OP_CFGI_ALL 0x4
456 #define CMDQ_OP_TLBI_NH_ASID 0x11
457 #define CMDQ_OP_TLBI_NH_VA 0x12
458 #define CMDQ_OP_TLBI_EL2_ALL 0x20
459 #define CMDQ_OP_TLBI_S12_VMALL 0x28
460 #define CMDQ_OP_TLBI_S2_IPA 0x2a
461 #define CMDQ_OP_TLBI_NSNH_ALL 0x30
469 #define CMDQ_OP_PRI_RESP 0x41
477 #define CMDQ_OP_CMD_SYNC 0x46
481 struct arm_smmu_queue {
482 int irq; /* Wired interrupt */
493 u32 __iomem *prod_reg;
494 u32 __iomem *cons_reg;
497 struct arm_smmu_cmdq {
498 struct arm_smmu_queue q;
502 struct arm_smmu_evtq {
503 struct arm_smmu_queue q;
507 struct arm_smmu_priq {
508 struct arm_smmu_queue q;
511 /* High-level stream table and context descriptor structures */
512 struct arm_smmu_strtab_l1_desc {
516 dma_addr_t l2ptr_dma;
519 struct arm_smmu_s1_cfg {
521 dma_addr_t cdptr_dma;
523 struct arm_smmu_ctx_desc {
531 struct arm_smmu_s2_cfg {
537 struct arm_smmu_strtab_ent {
540 bool bypass; /* Overrides s1/s2 config */
541 struct arm_smmu_s1_cfg *s1_cfg;
542 struct arm_smmu_s2_cfg *s2_cfg;
545 struct arm_smmu_strtab_cfg {
547 dma_addr_t strtab_dma;
548 struct arm_smmu_strtab_l1_desc *l1_desc;
549 unsigned int num_l1_ents;
555 /* An SMMUv3 instance */
556 struct arm_smmu_device {
560 #define ARM_SMMU_FEAT_2_LVL_STRTAB (1 << 0)
561 #define ARM_SMMU_FEAT_2_LVL_CDTAB (1 << 1)
562 #define ARM_SMMU_FEAT_TT_LE (1 << 2)
563 #define ARM_SMMU_FEAT_TT_BE (1 << 3)
564 #define ARM_SMMU_FEAT_PRI (1 << 4)
565 #define ARM_SMMU_FEAT_ATS (1 << 5)
566 #define ARM_SMMU_FEAT_SEV (1 << 6)
567 #define ARM_SMMU_FEAT_MSI (1 << 7)
568 #define ARM_SMMU_FEAT_COHERENCY (1 << 8)
569 #define ARM_SMMU_FEAT_TRANS_S1 (1 << 9)
570 #define ARM_SMMU_FEAT_TRANS_S2 (1 << 10)
571 #define ARM_SMMU_FEAT_STALLS (1 << 11)
572 #define ARM_SMMU_FEAT_HYP (1 << 12)
575 #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0)
578 struct arm_smmu_cmdq cmdq;
579 struct arm_smmu_evtq evtq;
580 struct arm_smmu_priq priq;
584 unsigned long ias; /* IPA */
585 unsigned long oas; /* PA */
587 #define ARM_SMMU_MAX_ASIDS (1 << 16)
588 unsigned int asid_bits;
589 DECLARE_BITMAP(asid_map, ARM_SMMU_MAX_ASIDS);
591 #define ARM_SMMU_MAX_VMIDS (1 << 16)
592 unsigned int vmid_bits;
593 DECLARE_BITMAP(vmid_map, ARM_SMMU_MAX_VMIDS);
595 unsigned int ssid_bits;
596 unsigned int sid_bits;
598 struct arm_smmu_strtab_cfg strtab_cfg;
601 /* SMMU private data for an IOMMU group */
602 struct arm_smmu_group {
603 struct arm_smmu_device *smmu;
604 struct arm_smmu_domain *domain;
607 struct arm_smmu_strtab_ent ste;
610 /* SMMU private data for an IOMMU domain */
611 enum arm_smmu_domain_stage {
612 ARM_SMMU_DOMAIN_S1 = 0,
614 ARM_SMMU_DOMAIN_NESTED,
617 struct arm_smmu_domain {
618 struct arm_smmu_device *smmu;
619 struct mutex init_mutex; /* Protects smmu pointer */
621 struct io_pgtable_ops *pgtbl_ops;
622 spinlock_t pgtbl_lock;
624 enum arm_smmu_domain_stage stage;
626 struct arm_smmu_s1_cfg s1_cfg;
627 struct arm_smmu_s2_cfg s2_cfg;
630 struct iommu_domain domain;
633 struct arm_smmu_option_prop {
638 static struct arm_smmu_option_prop arm_smmu_options[] = {
639 { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
643 static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
645 return container_of(dom, struct arm_smmu_domain, domain);
648 static void parse_driver_options(struct arm_smmu_device *smmu)
653 if (of_property_read_bool(smmu->dev->of_node,
654 arm_smmu_options[i].prop)) {
655 smmu->options |= arm_smmu_options[i].opt;
656 dev_notice(smmu->dev, "option %s\n",
657 arm_smmu_options[i].prop);
659 } while (arm_smmu_options[++i].opt);
662 /* Low-level queue manipulation functions */
663 static bool queue_full(struct arm_smmu_queue *q)
665 return Q_IDX(q, q->prod) == Q_IDX(q, q->cons) &&
666 Q_WRP(q, q->prod) != Q_WRP(q, q->cons);
669 static bool queue_empty(struct arm_smmu_queue *q)
671 return Q_IDX(q, q->prod) == Q_IDX(q, q->cons) &&
672 Q_WRP(q, q->prod) == Q_WRP(q, q->cons);
675 static void queue_sync_cons(struct arm_smmu_queue *q)
677 q->cons = readl_relaxed(q->cons_reg);
680 static void queue_inc_cons(struct arm_smmu_queue *q)
682 u32 cons = (Q_WRP(q, q->cons) | Q_IDX(q, q->cons)) + 1;
684 q->cons = Q_OVF(q, q->cons) | Q_WRP(q, cons) | Q_IDX(q, cons);
685 writel(q->cons, q->cons_reg);
688 static int queue_sync_prod(struct arm_smmu_queue *q)
691 u32 prod = readl_relaxed(q->prod_reg);
693 if (Q_OVF(q, prod) != Q_OVF(q, q->prod))
700 static void queue_inc_prod(struct arm_smmu_queue *q)
702 u32 prod = (Q_WRP(q, q->prod) | Q_IDX(q, q->prod)) + 1;
704 q->prod = Q_OVF(q, q->prod) | Q_WRP(q, prod) | Q_IDX(q, prod);
705 writel(q->prod, q->prod_reg);
708 static bool __queue_cons_before(struct arm_smmu_queue *q, u32 until)
710 if (Q_WRP(q, q->cons) == Q_WRP(q, until))
711 return Q_IDX(q, q->cons) < Q_IDX(q, until);
713 return Q_IDX(q, q->cons) >= Q_IDX(q, until);
716 static int queue_poll_cons(struct arm_smmu_queue *q, u32 until, bool wfe)
718 ktime_t timeout = ktime_add_us(ktime_get(), ARM_SMMU_POLL_TIMEOUT_US);
720 while (queue_sync_cons(q), __queue_cons_before(q, until)) {
721 if (ktime_compare(ktime_get(), timeout) > 0)
735 static void queue_write(__le64 *dst, u64 *src, size_t n_dwords)
739 for (i = 0; i < n_dwords; ++i)
740 *dst++ = cpu_to_le64(*src++);
743 static int queue_insert_raw(struct arm_smmu_queue *q, u64 *ent)
748 queue_write(Q_ENT(q, q->prod), ent, q->ent_dwords);
753 static void queue_read(__le64 *dst, u64 *src, size_t n_dwords)
757 for (i = 0; i < n_dwords; ++i)
758 *dst++ = le64_to_cpu(*src++);
761 static int queue_remove_raw(struct arm_smmu_queue *q, u64 *ent)
766 queue_read(ent, Q_ENT(q, q->cons), q->ent_dwords);
771 /* High-level queue accessors */
772 static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent)
774 memset(cmd, 0, CMDQ_ENT_DWORDS << 3);
775 cmd[0] |= (ent->opcode & CMDQ_0_OP_MASK) << CMDQ_0_OP_SHIFT;
777 switch (ent->opcode) {
778 case CMDQ_OP_TLBI_EL2_ALL:
779 case CMDQ_OP_TLBI_NSNH_ALL:
781 case CMDQ_OP_PREFETCH_CFG:
782 cmd[0] |= (u64)ent->prefetch.sid << CMDQ_PREFETCH_0_SID_SHIFT;
783 cmd[1] |= ent->prefetch.size << CMDQ_PREFETCH_1_SIZE_SHIFT;
784 cmd[1] |= ent->prefetch.addr & CMDQ_PREFETCH_1_ADDR_MASK;
786 case CMDQ_OP_CFGI_STE:
787 cmd[0] |= (u64)ent->cfgi.sid << CMDQ_CFGI_0_SID_SHIFT;
788 cmd[1] |= ent->cfgi.leaf ? CMDQ_CFGI_1_LEAF : 0;
790 case CMDQ_OP_CFGI_ALL:
791 /* Cover the entire SID range */
792 cmd[1] |= CMDQ_CFGI_1_RANGE_MASK << CMDQ_CFGI_1_RANGE_SHIFT;
794 case CMDQ_OP_TLBI_NH_VA:
795 cmd[0] |= (u64)ent->tlbi.asid << CMDQ_TLBI_0_ASID_SHIFT;
796 cmd[1] |= ent->tlbi.leaf ? CMDQ_TLBI_1_LEAF : 0;
797 cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_VA_MASK;
799 case CMDQ_OP_TLBI_S2_IPA:
800 cmd[0] |= (u64)ent->tlbi.vmid << CMDQ_TLBI_0_VMID_SHIFT;
801 cmd[1] |= ent->tlbi.leaf ? CMDQ_TLBI_1_LEAF : 0;
802 cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_IPA_MASK;
804 case CMDQ_OP_TLBI_NH_ASID:
805 cmd[0] |= (u64)ent->tlbi.asid << CMDQ_TLBI_0_ASID_SHIFT;
807 case CMDQ_OP_TLBI_S12_VMALL:
808 cmd[0] |= (u64)ent->tlbi.vmid << CMDQ_TLBI_0_VMID_SHIFT;
810 case CMDQ_OP_PRI_RESP:
811 cmd[0] |= ent->substream_valid ? CMDQ_0_SSV : 0;
812 cmd[0] |= ent->pri.ssid << CMDQ_PRI_0_SSID_SHIFT;
813 cmd[0] |= (u64)ent->pri.sid << CMDQ_PRI_0_SID_SHIFT;
814 cmd[1] |= ent->pri.grpid << CMDQ_PRI_1_GRPID_SHIFT;
815 switch (ent->pri.resp) {
817 cmd[1] |= CMDQ_PRI_1_RESP_DENY;
820 cmd[1] |= CMDQ_PRI_1_RESP_FAIL;
823 cmd[1] |= CMDQ_PRI_1_RESP_SUCC;
829 case CMDQ_OP_CMD_SYNC:
830 cmd[0] |= CMDQ_SYNC_0_CS_SEV;
839 static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu)
841 static const char *cerror_str[] = {
842 [CMDQ_ERR_CERROR_NONE_IDX] = "No error",
843 [CMDQ_ERR_CERROR_ILL_IDX] = "Illegal command",
844 [CMDQ_ERR_CERROR_ABT_IDX] = "Abort on command fetch",
848 u64 cmd[CMDQ_ENT_DWORDS];
849 struct arm_smmu_queue *q = &smmu->cmdq.q;
850 u32 cons = readl_relaxed(q->cons_reg);
851 u32 idx = cons >> CMDQ_ERR_SHIFT & CMDQ_ERR_MASK;
852 struct arm_smmu_cmdq_ent cmd_sync = {
853 .opcode = CMDQ_OP_CMD_SYNC,
856 dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons,
860 case CMDQ_ERR_CERROR_ILL_IDX:
862 case CMDQ_ERR_CERROR_ABT_IDX:
863 dev_err(smmu->dev, "retrying command fetch\n");
864 case CMDQ_ERR_CERROR_NONE_IDX:
869 * We may have concurrent producers, so we need to be careful
870 * not to touch any of the shadow cmdq state.
872 queue_read(cmd, Q_ENT(q, idx), q->ent_dwords);
873 dev_err(smmu->dev, "skipping command in error state:\n");
874 for (i = 0; i < ARRAY_SIZE(cmd); ++i)
875 dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]);
877 /* Convert the erroneous command into a CMD_SYNC */
878 if (arm_smmu_cmdq_build_cmd(cmd, &cmd_sync)) {
879 dev_err(smmu->dev, "failed to convert to CMD_SYNC\n");
883 queue_write(cmd, Q_ENT(q, idx), q->ent_dwords);
886 static void arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,
887 struct arm_smmu_cmdq_ent *ent)
890 u64 cmd[CMDQ_ENT_DWORDS];
891 bool wfe = !!(smmu->features & ARM_SMMU_FEAT_SEV);
892 struct arm_smmu_queue *q = &smmu->cmdq.q;
894 if (arm_smmu_cmdq_build_cmd(cmd, ent)) {
895 dev_warn(smmu->dev, "ignoring unknown CMDQ opcode 0x%x\n",
900 spin_lock(&smmu->cmdq.lock);
901 while (until = q->prod + 1, queue_insert_raw(q, cmd) == -ENOSPC) {
903 * Keep the queue locked, otherwise the producer could wrap
904 * twice and we could see a future consumer pointer that looks
905 * like it's behind us.
907 if (queue_poll_cons(q, until, wfe))
908 dev_err_ratelimited(smmu->dev, "CMDQ timeout\n");
911 if (ent->opcode == CMDQ_OP_CMD_SYNC && queue_poll_cons(q, until, wfe))
912 dev_err_ratelimited(smmu->dev, "CMD_SYNC timeout\n");
913 spin_unlock(&smmu->cmdq.lock);
916 /* Context descriptor manipulation functions */
917 static u64 arm_smmu_cpu_tcr_to_cd(u64 tcr)
921 /* Repack the TCR. Just care about TTBR0 for now */
922 val |= ARM_SMMU_TCR2CD(tcr, T0SZ);
923 val |= ARM_SMMU_TCR2CD(tcr, TG0);
924 val |= ARM_SMMU_TCR2CD(tcr, IRGN0);
925 val |= ARM_SMMU_TCR2CD(tcr, ORGN0);
926 val |= ARM_SMMU_TCR2CD(tcr, SH0);
927 val |= ARM_SMMU_TCR2CD(tcr, EPD0);
928 val |= ARM_SMMU_TCR2CD(tcr, EPD1);
929 val |= ARM_SMMU_TCR2CD(tcr, IPS);
930 val |= ARM_SMMU_TCR2CD(tcr, TBI0);
935 static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu,
936 struct arm_smmu_s1_cfg *cfg)
941 * We don't need to issue any invalidation here, as we'll invalidate
942 * the STE when installing the new entry anyway.
944 val = arm_smmu_cpu_tcr_to_cd(cfg->cd.tcr) |
948 CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET_PRIVATE |
949 CTXDESC_CD_0_AA64 | (u64)cfg->cd.asid << CTXDESC_CD_0_ASID_SHIFT |
951 cfg->cdptr[0] = cpu_to_le64(val);
953 val = cfg->cd.ttbr & CTXDESC_CD_1_TTB0_MASK << CTXDESC_CD_1_TTB0_SHIFT;
954 cfg->cdptr[1] = cpu_to_le64(val);
956 cfg->cdptr[3] = cpu_to_le64(cfg->cd.mair << CTXDESC_CD_3_MAIR_SHIFT);
959 /* Stream table manipulation functions */
961 arm_smmu_write_strtab_l1_desc(__le64 *dst, struct arm_smmu_strtab_l1_desc *desc)
965 val |= (desc->span & STRTAB_L1_DESC_SPAN_MASK)
966 << STRTAB_L1_DESC_SPAN_SHIFT;
967 val |= desc->l2ptr_dma &
968 STRTAB_L1_DESC_L2PTR_MASK << STRTAB_L1_DESC_L2PTR_SHIFT;
970 *dst = cpu_to_le64(val);
973 static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid)
975 struct arm_smmu_cmdq_ent cmd = {
976 .opcode = CMDQ_OP_CFGI_STE,
983 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
984 cmd.opcode = CMDQ_OP_CMD_SYNC;
985 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
988 static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
989 __le64 *dst, struct arm_smmu_strtab_ent *ste)
992 * This is hideously complicated, but we only really care about
993 * three cases at the moment:
995 * 1. Invalid (all zero) -> bypass (init)
996 * 2. Bypass -> translation (attach)
997 * 3. Translation -> bypass (detach)
999 * Given that we can't update the STE atomically and the SMMU
1000 * doesn't read the thing in a defined order, that leaves us
1001 * with the following maintenance requirements:
1003 * 1. Update Config, return (init time STEs aren't live)
1004 * 2. Write everything apart from dword 0, sync, write dword 0, sync
1005 * 3. Update Config, sync
1007 u64 val = le64_to_cpu(dst[0]);
1008 bool ste_live = false;
1009 struct arm_smmu_cmdq_ent prefetch_cmd = {
1010 .opcode = CMDQ_OP_PREFETCH_CFG,
1016 if (val & STRTAB_STE_0_V) {
1019 cfg = val & STRTAB_STE_0_CFG_MASK << STRTAB_STE_0_CFG_SHIFT;
1021 case STRTAB_STE_0_CFG_BYPASS:
1023 case STRTAB_STE_0_CFG_S1_TRANS:
1024 case STRTAB_STE_0_CFG_S2_TRANS:
1028 BUG(); /* STE corruption */
1032 /* Nuke the existing Config, as we're going to rewrite it */
1033 val &= ~(STRTAB_STE_0_CFG_MASK << STRTAB_STE_0_CFG_SHIFT);
1036 val |= STRTAB_STE_0_V;
1038 val &= ~STRTAB_STE_0_V;
1041 val |= disable_bypass ? STRTAB_STE_0_CFG_ABORT
1042 : STRTAB_STE_0_CFG_BYPASS;
1043 dst[0] = cpu_to_le64(val);
1044 dst[2] = 0; /* Nuke the VMID */
1046 arm_smmu_sync_ste_for_sid(smmu, sid);
1052 dst[1] = cpu_to_le64(
1053 STRTAB_STE_1_S1C_CACHE_WBRA
1054 << STRTAB_STE_1_S1CIR_SHIFT |
1055 STRTAB_STE_1_S1C_CACHE_WBRA
1056 << STRTAB_STE_1_S1COR_SHIFT |
1057 STRTAB_STE_1_S1C_SH_ISH << STRTAB_STE_1_S1CSH_SHIFT |
1058 STRTAB_STE_1_S1STALLD |
1059 #ifdef CONFIG_PCI_ATS
1060 STRTAB_STE_1_EATS_TRANS << STRTAB_STE_1_EATS_SHIFT |
1062 STRTAB_STE_1_STRW_NSEL1 << STRTAB_STE_1_STRW_SHIFT);
1064 val |= (ste->s1_cfg->cdptr_dma & STRTAB_STE_0_S1CTXPTR_MASK
1065 << STRTAB_STE_0_S1CTXPTR_SHIFT) |
1066 STRTAB_STE_0_CFG_S1_TRANS;
1072 dst[2] = cpu_to_le64(
1073 ste->s2_cfg->vmid << STRTAB_STE_2_S2VMID_SHIFT |
1074 (ste->s2_cfg->vtcr & STRTAB_STE_2_VTCR_MASK)
1075 << STRTAB_STE_2_VTCR_SHIFT |
1077 STRTAB_STE_2_S2ENDI |
1079 STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 |
1082 dst[3] = cpu_to_le64(ste->s2_cfg->vttbr &
1083 STRTAB_STE_3_S2TTB_MASK << STRTAB_STE_3_S2TTB_SHIFT);
1085 val |= STRTAB_STE_0_CFG_S2_TRANS;
1088 arm_smmu_sync_ste_for_sid(smmu, sid);
1089 dst[0] = cpu_to_le64(val);
1090 arm_smmu_sync_ste_for_sid(smmu, sid);
1092 /* It's likely that we'll want to use the new STE soon */
1093 if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH))
1094 arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd);
1097 static void arm_smmu_init_bypass_stes(u64 *strtab, unsigned int nent)
1100 struct arm_smmu_strtab_ent ste = {
1105 for (i = 0; i < nent; ++i) {
1106 arm_smmu_write_strtab_ent(NULL, -1, strtab, &ste);
1107 strtab += STRTAB_STE_DWORDS;
1111 static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid)
1115 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
1116 struct arm_smmu_strtab_l1_desc *desc = &cfg->l1_desc[sid >> STRTAB_SPLIT];
1121 size = 1 << (STRTAB_SPLIT + ilog2(STRTAB_STE_DWORDS) + 3);
1122 strtab = &cfg->strtab[(sid >> STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS];
1124 desc->span = STRTAB_SPLIT + 1;
1125 desc->l2ptr = dmam_alloc_coherent(smmu->dev, size, &desc->l2ptr_dma,
1126 GFP_KERNEL | __GFP_ZERO);
1129 "failed to allocate l2 stream table for SID %u\n",
1134 arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT);
1135 arm_smmu_write_strtab_l1_desc(strtab, desc);
1139 /* IRQ and event handlers */
1140 static irqreturn_t arm_smmu_evtq_thread(int irq, void *dev)
1143 struct arm_smmu_device *smmu = dev;
1144 struct arm_smmu_queue *q = &smmu->evtq.q;
1145 u64 evt[EVTQ_ENT_DWORDS];
1147 while (!queue_remove_raw(q, evt)) {
1148 u8 id = evt[0] >> EVTQ_0_ID_SHIFT & EVTQ_0_ID_MASK;
1150 dev_info(smmu->dev, "event 0x%02x received:\n", id);
1151 for (i = 0; i < ARRAY_SIZE(evt); ++i)
1152 dev_info(smmu->dev, "\t0x%016llx\n",
1153 (unsigned long long)evt[i]);
1156 /* Sync our overflow flag, as we believe we're up to speed */
1157 q->cons = Q_OVF(q, q->prod) | Q_WRP(q, q->cons) | Q_IDX(q, q->cons);
1161 static irqreturn_t arm_smmu_evtq_handler(int irq, void *dev)
1163 irqreturn_t ret = IRQ_WAKE_THREAD;
1164 struct arm_smmu_device *smmu = dev;
1165 struct arm_smmu_queue *q = &smmu->evtq.q;
1168 * Not much we can do on overflow, so scream and pretend we're
1171 if (queue_sync_prod(q) == -EOVERFLOW)
1172 dev_err(smmu->dev, "EVTQ overflow detected -- events lost\n");
1173 else if (queue_empty(q))
1179 static irqreturn_t arm_smmu_priq_thread(int irq, void *dev)
1181 struct arm_smmu_device *smmu = dev;
1182 struct arm_smmu_queue *q = &smmu->priq.q;
1183 u64 evt[PRIQ_ENT_DWORDS];
1185 while (!queue_remove_raw(q, evt)) {
1190 sid = evt[0] >> PRIQ_0_SID_SHIFT & PRIQ_0_SID_MASK;
1191 ssv = evt[0] & PRIQ_0_SSID_V;
1192 ssid = ssv ? evt[0] >> PRIQ_0_SSID_SHIFT & PRIQ_0_SSID_MASK : 0;
1193 last = evt[0] & PRIQ_0_PRG_LAST;
1194 grpid = evt[1] >> PRIQ_1_PRG_IDX_SHIFT & PRIQ_1_PRG_IDX_MASK;
1196 dev_info(smmu->dev, "unexpected PRI request received:\n");
1198 "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at iova 0x%016llx\n",
1199 sid, ssid, grpid, last ? "L" : "",
1200 evt[0] & PRIQ_0_PERM_PRIV ? "" : "un",
1201 evt[0] & PRIQ_0_PERM_READ ? "R" : "",
1202 evt[0] & PRIQ_0_PERM_WRITE ? "W" : "",
1203 evt[0] & PRIQ_0_PERM_EXEC ? "X" : "",
1204 evt[1] & PRIQ_1_ADDR_MASK << PRIQ_1_ADDR_SHIFT);
1207 struct arm_smmu_cmdq_ent cmd = {
1208 .opcode = CMDQ_OP_PRI_RESP,
1209 .substream_valid = ssv,
1214 .resp = PRI_RESP_DENY,
1218 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
1222 /* Sync our overflow flag, as we believe we're up to speed */
1223 q->cons = Q_OVF(q, q->prod) | Q_WRP(q, q->cons) | Q_IDX(q, q->cons);
1227 static irqreturn_t arm_smmu_priq_handler(int irq, void *dev)
1229 irqreturn_t ret = IRQ_WAKE_THREAD;
1230 struct arm_smmu_device *smmu = dev;
1231 struct arm_smmu_queue *q = &smmu->priq.q;
1233 /* PRIQ overflow indicates a programming error */
1234 if (queue_sync_prod(q) == -EOVERFLOW)
1235 dev_err(smmu->dev, "PRIQ overflow detected -- requests lost\n");
1236 else if (queue_empty(q))
1242 static irqreturn_t arm_smmu_cmdq_sync_handler(int irq, void *dev)
1244 /* We don't actually use CMD_SYNC interrupts for anything */
1248 static int arm_smmu_device_disable(struct arm_smmu_device *smmu);
1250 static irqreturn_t arm_smmu_gerror_handler(int irq, void *dev)
1252 u32 gerror, gerrorn;
1253 struct arm_smmu_device *smmu = dev;
1255 gerror = readl_relaxed(smmu->base + ARM_SMMU_GERROR);
1256 gerrorn = readl_relaxed(smmu->base + ARM_SMMU_GERRORN);
1259 if (!(gerror & GERROR_ERR_MASK))
1260 return IRQ_NONE; /* No errors pending */
1263 "unexpected global error reported (0x%08x), this could be serious\n",
1266 if (gerror & GERROR_SFM_ERR) {
1267 dev_err(smmu->dev, "device has entered Service Failure Mode!\n");
1268 arm_smmu_device_disable(smmu);
1271 if (gerror & GERROR_MSI_GERROR_ABT_ERR)
1272 dev_warn(smmu->dev, "GERROR MSI write aborted\n");
1274 if (gerror & GERROR_MSI_PRIQ_ABT_ERR) {
1275 dev_warn(smmu->dev, "PRIQ MSI write aborted\n");
1276 arm_smmu_priq_handler(irq, smmu->dev);
1279 if (gerror & GERROR_MSI_EVTQ_ABT_ERR) {
1280 dev_warn(smmu->dev, "EVTQ MSI write aborted\n");
1281 arm_smmu_evtq_handler(irq, smmu->dev);
1284 if (gerror & GERROR_MSI_CMDQ_ABT_ERR) {
1285 dev_warn(smmu->dev, "CMDQ MSI write aborted\n");
1286 arm_smmu_cmdq_sync_handler(irq, smmu->dev);
1289 if (gerror & GERROR_PRIQ_ABT_ERR)
1290 dev_err(smmu->dev, "PRIQ write aborted -- events may have been lost\n");
1292 if (gerror & GERROR_EVTQ_ABT_ERR)
1293 dev_err(smmu->dev, "EVTQ write aborted -- events may have been lost\n");
1295 if (gerror & GERROR_CMDQ_ERR)
1296 arm_smmu_cmdq_skip_err(smmu);
1298 writel(gerror, smmu->base + ARM_SMMU_GERRORN);
1302 /* IO_PGTABLE API */
1303 static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
1305 struct arm_smmu_cmdq_ent cmd;
1307 cmd.opcode = CMDQ_OP_CMD_SYNC;
1308 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
1311 static void arm_smmu_tlb_sync(void *cookie)
1313 struct arm_smmu_domain *smmu_domain = cookie;
1314 __arm_smmu_tlb_sync(smmu_domain->smmu);
1317 static void arm_smmu_tlb_inv_context(void *cookie)
1319 struct arm_smmu_domain *smmu_domain = cookie;
1320 struct arm_smmu_device *smmu = smmu_domain->smmu;
1321 struct arm_smmu_cmdq_ent cmd;
1323 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
1324 cmd.opcode = CMDQ_OP_TLBI_NH_ASID;
1325 cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid;
1328 cmd.opcode = CMDQ_OP_TLBI_S12_VMALL;
1329 cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid;
1332 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
1333 __arm_smmu_tlb_sync(smmu);
1336 static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
1337 bool leaf, void *cookie)
1339 struct arm_smmu_domain *smmu_domain = cookie;
1340 struct arm_smmu_device *smmu = smmu_domain->smmu;
1341 struct arm_smmu_cmdq_ent cmd = {
1348 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
1349 cmd.opcode = CMDQ_OP_TLBI_NH_VA;
1350 cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid;
1352 cmd.opcode = CMDQ_OP_TLBI_S2_IPA;
1353 cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid;
1356 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
1359 static struct iommu_gather_ops arm_smmu_gather_ops = {
1360 .tlb_flush_all = arm_smmu_tlb_inv_context,
1361 .tlb_add_flush = arm_smmu_tlb_inv_range_nosync,
1362 .tlb_sync = arm_smmu_tlb_sync,
1366 static bool arm_smmu_capable(enum iommu_cap cap)
1369 case IOMMU_CAP_CACHE_COHERENCY:
1371 case IOMMU_CAP_INTR_REMAP:
1372 return true; /* MSIs are just memory writes */
1373 case IOMMU_CAP_NOEXEC:
1380 static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
1382 struct arm_smmu_domain *smmu_domain;
1384 if (type != IOMMU_DOMAIN_UNMANAGED)
1388 * Allocate the domain and initialise some of its data structures.
1389 * We can't really do anything meaningful until we've added a
1392 smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
1396 mutex_init(&smmu_domain->init_mutex);
1397 spin_lock_init(&smmu_domain->pgtbl_lock);
1398 return &smmu_domain->domain;
1401 static int arm_smmu_bitmap_alloc(unsigned long *map, int span)
1403 int idx, size = 1 << span;
1406 idx = find_first_zero_bit(map, size);
1409 } while (test_and_set_bit(idx, map));
1414 static void arm_smmu_bitmap_free(unsigned long *map, int idx)
1416 clear_bit(idx, map);
1419 static void arm_smmu_domain_free(struct iommu_domain *domain)
1421 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1422 struct arm_smmu_device *smmu = smmu_domain->smmu;
1424 free_io_pgtable_ops(smmu_domain->pgtbl_ops);
1426 /* Free the CD and ASID, if we allocated them */
1427 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
1428 struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg;
1431 dmam_free_coherent(smmu_domain->smmu->dev,
1432 CTXDESC_CD_DWORDS << 3,
1436 arm_smmu_bitmap_free(smmu->asid_map, cfg->cd.asid);
1439 struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg;
1441 arm_smmu_bitmap_free(smmu->vmid_map, cfg->vmid);
1447 static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain,
1448 struct io_pgtable_cfg *pgtbl_cfg)
1452 struct arm_smmu_device *smmu = smmu_domain->smmu;
1453 struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg;
1455 asid = arm_smmu_bitmap_alloc(smmu->asid_map, smmu->asid_bits);
1456 if (IS_ERR_VALUE(asid))
1459 cfg->cdptr = dmam_alloc_coherent(smmu->dev, CTXDESC_CD_DWORDS << 3,
1461 GFP_KERNEL | __GFP_ZERO);
1463 dev_warn(smmu->dev, "failed to allocate context descriptor\n");
1468 cfg->cd.asid = (u16)asid;
1469 cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
1470 cfg->cd.tcr = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
1471 cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair[0];
1475 arm_smmu_bitmap_free(smmu->asid_map, asid);
1479 static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain,
1480 struct io_pgtable_cfg *pgtbl_cfg)
1483 struct arm_smmu_device *smmu = smmu_domain->smmu;
1484 struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg;
1486 vmid = arm_smmu_bitmap_alloc(smmu->vmid_map, smmu->vmid_bits);
1487 if (IS_ERR_VALUE(vmid))
1490 cfg->vmid = (u16)vmid;
1491 cfg->vttbr = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
1492 cfg->vtcr = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
1496 static struct iommu_ops arm_smmu_ops;
1498 static int arm_smmu_domain_finalise(struct iommu_domain *domain)
1501 unsigned long ias, oas;
1502 enum io_pgtable_fmt fmt;
1503 struct io_pgtable_cfg pgtbl_cfg;
1504 struct io_pgtable_ops *pgtbl_ops;
1505 int (*finalise_stage_fn)(struct arm_smmu_domain *,
1506 struct io_pgtable_cfg *);
1507 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1508 struct arm_smmu_device *smmu = smmu_domain->smmu;
1510 /* Restrict the stage to what we can actually support */
1511 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1))
1512 smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
1513 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2))
1514 smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
1516 switch (smmu_domain->stage) {
1517 case ARM_SMMU_DOMAIN_S1:
1520 fmt = ARM_64_LPAE_S1;
1521 finalise_stage_fn = arm_smmu_domain_finalise_s1;
1523 case ARM_SMMU_DOMAIN_NESTED:
1524 case ARM_SMMU_DOMAIN_S2:
1527 fmt = ARM_64_LPAE_S2;
1528 finalise_stage_fn = arm_smmu_domain_finalise_s2;
1534 pgtbl_cfg = (struct io_pgtable_cfg) {
1535 .pgsize_bitmap = arm_smmu_ops.pgsize_bitmap,
1538 .tlb = &arm_smmu_gather_ops,
1539 .iommu_dev = smmu->dev,
1542 pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);
1546 arm_smmu_ops.pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
1547 smmu_domain->pgtbl_ops = pgtbl_ops;
1549 ret = finalise_stage_fn(smmu_domain, &pgtbl_cfg);
1550 if (IS_ERR_VALUE(ret))
1551 free_io_pgtable_ops(pgtbl_ops);
1556 static struct arm_smmu_group *arm_smmu_group_get(struct device *dev)
1558 struct iommu_group *group;
1559 struct arm_smmu_group *smmu_group;
1561 group = iommu_group_get(dev);
1565 smmu_group = iommu_group_get_iommudata(group);
1566 iommu_group_put(group);
1570 static __le64 *arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid)
1573 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
1575 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) {
1576 struct arm_smmu_strtab_l1_desc *l1_desc;
1579 /* Two-level walk */
1580 idx = (sid >> STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS;
1581 l1_desc = &cfg->l1_desc[idx];
1582 idx = (sid & ((1 << STRTAB_SPLIT) - 1)) * STRTAB_STE_DWORDS;
1583 step = &l1_desc->l2ptr[idx];
1585 /* Simple linear lookup */
1586 step = &cfg->strtab[sid * STRTAB_STE_DWORDS];
1592 static int arm_smmu_install_ste_for_group(struct arm_smmu_group *smmu_group)
1595 struct arm_smmu_domain *smmu_domain = smmu_group->domain;
1596 struct arm_smmu_strtab_ent *ste = &smmu_group->ste;
1597 struct arm_smmu_device *smmu = smmu_group->smmu;
1599 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
1600 ste->s1_cfg = &smmu_domain->s1_cfg;
1602 arm_smmu_write_ctx_desc(smmu, ste->s1_cfg);
1605 ste->s2_cfg = &smmu_domain->s2_cfg;
1608 for (i = 0; i < smmu_group->num_sids; ++i) {
1609 u32 sid = smmu_group->sids[i];
1610 __le64 *step = arm_smmu_get_step_for_sid(smmu, sid);
1612 arm_smmu_write_strtab_ent(smmu, sid, step, ste);
1618 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1621 struct arm_smmu_device *smmu;
1622 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1623 struct arm_smmu_group *smmu_group = arm_smmu_group_get(dev);
1628 /* Already attached to a different domain? */
1629 if (smmu_group->domain && smmu_group->domain != smmu_domain)
1632 smmu = smmu_group->smmu;
1633 mutex_lock(&smmu_domain->init_mutex);
1635 if (!smmu_domain->smmu) {
1636 smmu_domain->smmu = smmu;
1637 ret = arm_smmu_domain_finalise(domain);
1639 smmu_domain->smmu = NULL;
1642 } else if (smmu_domain->smmu != smmu) {
1644 "cannot attach to SMMU %s (upstream of %s)\n",
1645 dev_name(smmu_domain->smmu->dev),
1646 dev_name(smmu->dev));
1651 /* Group already attached to this domain? */
1652 if (smmu_group->domain)
1655 smmu_group->domain = smmu_domain;
1656 smmu_group->ste.bypass = false;
1658 ret = arm_smmu_install_ste_for_group(smmu_group);
1659 if (IS_ERR_VALUE(ret))
1660 smmu_group->domain = NULL;
1663 mutex_unlock(&smmu_domain->init_mutex);
1667 static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1669 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1670 struct arm_smmu_group *smmu_group = arm_smmu_group_get(dev);
1672 BUG_ON(!smmu_domain);
1673 BUG_ON(!smmu_group);
1675 mutex_lock(&smmu_domain->init_mutex);
1676 BUG_ON(smmu_group->domain != smmu_domain);
1678 smmu_group->ste.bypass = true;
1679 if (IS_ERR_VALUE(arm_smmu_install_ste_for_group(smmu_group)))
1680 dev_warn(dev, "failed to install bypass STE\n");
1682 smmu_group->domain = NULL;
1683 mutex_unlock(&smmu_domain->init_mutex);
1686 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1687 phys_addr_t paddr, size_t size, int prot)
1690 unsigned long flags;
1691 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1692 struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops;
1697 spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1698 ret = ops->map(ops, iova, paddr, size, prot);
1699 spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1704 arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, size_t size)
1707 unsigned long flags;
1708 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1709 struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops;
1714 spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1715 ret = ops->unmap(ops, iova, size);
1716 spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1721 arm_smmu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova)
1724 unsigned long flags;
1725 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1726 struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops;
1731 spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1732 ret = ops->iova_to_phys(ops, iova);
1733 spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1738 static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *sidp)
1740 *(u32 *)sidp = alias;
1741 return 0; /* Continue walking */
1744 static void __arm_smmu_release_pci_iommudata(void *data)
1749 static struct arm_smmu_device *arm_smmu_get_for_pci_dev(struct pci_dev *pdev)
1751 struct device_node *of_node;
1752 struct platform_device *smmu_pdev;
1753 struct arm_smmu_device *smmu = NULL;
1754 struct pci_bus *bus = pdev->bus;
1756 /* Walk up to the root bus */
1757 while (!pci_is_root_bus(bus))
1760 /* Follow the "iommus" phandle from the host controller */
1761 of_node = of_parse_phandle(bus->bridge->parent->of_node, "iommus", 0);
1765 /* See if we can find an SMMU corresponding to the phandle */
1766 smmu_pdev = of_find_device_by_node(of_node);
1768 smmu = platform_get_drvdata(smmu_pdev);
1770 of_node_put(of_node);
1774 static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid)
1776 unsigned long limit = smmu->strtab_cfg.num_l1_ents;
1778 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB)
1779 limit *= 1UL << STRTAB_SPLIT;
1784 static int arm_smmu_add_device(struct device *dev)
1788 struct pci_dev *pdev;
1789 struct iommu_group *group;
1790 struct arm_smmu_group *smmu_group;
1791 struct arm_smmu_device *smmu;
1793 /* We only support PCI, for now */
1794 if (!dev_is_pci(dev))
1797 pdev = to_pci_dev(dev);
1798 group = iommu_group_get_for_dev(dev);
1800 return PTR_ERR(group);
1802 smmu_group = iommu_group_get_iommudata(group);
1804 smmu = arm_smmu_get_for_pci_dev(pdev);
1810 smmu_group = kzalloc(sizeof(*smmu_group), GFP_KERNEL);
1816 smmu_group->ste.valid = true;
1817 smmu_group->smmu = smmu;
1818 iommu_group_set_iommudata(group, smmu_group,
1819 __arm_smmu_release_pci_iommudata);
1821 smmu = smmu_group->smmu;
1824 /* Assume SID == RID until firmware tells us otherwise */
1825 pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, &sid);
1826 for (i = 0; i < smmu_group->num_sids; ++i) {
1827 /* If we already know about this SID, then we're done */
1828 if (smmu_group->sids[i] == sid)
1832 /* Check the SID is in range of the SMMU and our stream table */
1833 if (!arm_smmu_sid_in_range(smmu, sid)) {
1838 /* Ensure l2 strtab is initialised */
1839 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) {
1840 ret = arm_smmu_init_l2_strtab(smmu, sid);
1845 /* Resize the SID array for the group */
1846 smmu_group->num_sids++;
1847 sids = krealloc(smmu_group->sids, smmu_group->num_sids * sizeof(*sids),
1850 smmu_group->num_sids--;
1855 /* Add the new SID */
1856 sids[smmu_group->num_sids - 1] = sid;
1857 smmu_group->sids = sids;
1861 iommu_group_put(group);
1865 static void arm_smmu_remove_device(struct device *dev)
1867 iommu_group_remove_device(dev);
1870 static int arm_smmu_domain_get_attr(struct iommu_domain *domain,
1871 enum iommu_attr attr, void *data)
1873 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1876 case DOMAIN_ATTR_NESTING:
1877 *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED);
1884 static int arm_smmu_domain_set_attr(struct iommu_domain *domain,
1885 enum iommu_attr attr, void *data)
1888 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1890 mutex_lock(&smmu_domain->init_mutex);
1893 case DOMAIN_ATTR_NESTING:
1894 if (smmu_domain->smmu) {
1900 smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED;
1902 smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
1910 mutex_unlock(&smmu_domain->init_mutex);
1914 static struct iommu_ops arm_smmu_ops = {
1915 .capable = arm_smmu_capable,
1916 .domain_alloc = arm_smmu_domain_alloc,
1917 .domain_free = arm_smmu_domain_free,
1918 .attach_dev = arm_smmu_attach_dev,
1919 .detach_dev = arm_smmu_detach_dev,
1920 .map = arm_smmu_map,
1921 .unmap = arm_smmu_unmap,
1922 .iova_to_phys = arm_smmu_iova_to_phys,
1923 .add_device = arm_smmu_add_device,
1924 .remove_device = arm_smmu_remove_device,
1925 .device_group = pci_device_group,
1926 .domain_get_attr = arm_smmu_domain_get_attr,
1927 .domain_set_attr = arm_smmu_domain_set_attr,
1928 .pgsize_bitmap = -1UL, /* Restricted during device attach */
1931 /* Probing and initialisation functions */
1932 static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,
1933 struct arm_smmu_queue *q,
1934 unsigned long prod_off,
1935 unsigned long cons_off,
1938 size_t qsz = ((1 << q->max_n_shift) * dwords) << 3;
1940 q->base = dmam_alloc_coherent(smmu->dev, qsz, &q->base_dma, GFP_KERNEL);
1942 dev_err(smmu->dev, "failed to allocate queue (0x%zx bytes)\n",
1947 q->prod_reg = smmu->base + prod_off;
1948 q->cons_reg = smmu->base + cons_off;
1949 q->ent_dwords = dwords;
1951 q->q_base = Q_BASE_RWA;
1952 q->q_base |= q->base_dma & Q_BASE_ADDR_MASK << Q_BASE_ADDR_SHIFT;
1953 q->q_base |= (q->max_n_shift & Q_BASE_LOG2SIZE_MASK)
1954 << Q_BASE_LOG2SIZE_SHIFT;
1956 q->prod = q->cons = 0;
1960 static int arm_smmu_init_queues(struct arm_smmu_device *smmu)
1965 spin_lock_init(&smmu->cmdq.lock);
1966 ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, ARM_SMMU_CMDQ_PROD,
1967 ARM_SMMU_CMDQ_CONS, CMDQ_ENT_DWORDS);
1972 ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, ARM_SMMU_EVTQ_PROD,
1973 ARM_SMMU_EVTQ_CONS, EVTQ_ENT_DWORDS);
1978 if (!(smmu->features & ARM_SMMU_FEAT_PRI))
1981 return arm_smmu_init_one_queue(smmu, &smmu->priq.q, ARM_SMMU_PRIQ_PROD,
1982 ARM_SMMU_PRIQ_CONS, PRIQ_ENT_DWORDS);
1985 static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu)
1988 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
1989 size_t size = sizeof(*cfg->l1_desc) * cfg->num_l1_ents;
1990 void *strtab = smmu->strtab_cfg.strtab;
1992 cfg->l1_desc = devm_kzalloc(smmu->dev, size, GFP_KERNEL);
1993 if (!cfg->l1_desc) {
1994 dev_err(smmu->dev, "failed to allocate l1 stream table desc\n");
1998 for (i = 0; i < cfg->num_l1_ents; ++i) {
1999 arm_smmu_write_strtab_l1_desc(strtab, &cfg->l1_desc[i]);
2000 strtab += STRTAB_L1_DESC_DWORDS << 3;
2006 static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu)
2011 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
2014 * If we can resolve everything with a single L2 table, then we
2015 * just need a single L1 descriptor. Otherwise, calculate the L1
2016 * size, capped to the SIDSIZE.
2018 if (smmu->sid_bits < STRTAB_SPLIT) {
2021 size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_L1_DESC_DWORDS) + 3);
2022 size = min(size, smmu->sid_bits - STRTAB_SPLIT);
2024 cfg->num_l1_ents = 1 << size;
2026 size += STRTAB_SPLIT;
2027 if (size < smmu->sid_bits)
2029 "2-level strtab only covers %u/%u bits of SID\n",
2030 size, smmu->sid_bits);
2032 l1size = cfg->num_l1_ents * (STRTAB_L1_DESC_DWORDS << 3);
2033 strtab = dmam_alloc_coherent(smmu->dev, l1size, &cfg->strtab_dma,
2034 GFP_KERNEL | __GFP_ZERO);
2037 "failed to allocate l1 stream table (%u bytes)\n",
2041 cfg->strtab = strtab;
2043 /* Configure strtab_base_cfg for 2 levels */
2044 reg = STRTAB_BASE_CFG_FMT_2LVL;
2045 reg |= (size & STRTAB_BASE_CFG_LOG2SIZE_MASK)
2046 << STRTAB_BASE_CFG_LOG2SIZE_SHIFT;
2047 reg |= (STRTAB_SPLIT & STRTAB_BASE_CFG_SPLIT_MASK)
2048 << STRTAB_BASE_CFG_SPLIT_SHIFT;
2049 cfg->strtab_base_cfg = reg;
2051 return arm_smmu_init_l1_strtab(smmu);
2054 static int arm_smmu_init_strtab_linear(struct arm_smmu_device *smmu)
2059 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
2061 size = (1 << smmu->sid_bits) * (STRTAB_STE_DWORDS << 3);
2062 strtab = dmam_alloc_coherent(smmu->dev, size, &cfg->strtab_dma,
2063 GFP_KERNEL | __GFP_ZERO);
2066 "failed to allocate linear stream table (%u bytes)\n",
2070 cfg->strtab = strtab;
2071 cfg->num_l1_ents = 1 << smmu->sid_bits;
2073 /* Configure strtab_base_cfg for a linear table covering all SIDs */
2074 reg = STRTAB_BASE_CFG_FMT_LINEAR;
2075 reg |= (smmu->sid_bits & STRTAB_BASE_CFG_LOG2SIZE_MASK)
2076 << STRTAB_BASE_CFG_LOG2SIZE_SHIFT;
2077 cfg->strtab_base_cfg = reg;
2079 arm_smmu_init_bypass_stes(strtab, cfg->num_l1_ents);
2083 static int arm_smmu_init_strtab(struct arm_smmu_device *smmu)
2088 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB)
2089 ret = arm_smmu_init_strtab_2lvl(smmu);
2091 ret = arm_smmu_init_strtab_linear(smmu);
2096 /* Set the strtab base address */
2097 reg = smmu->strtab_cfg.strtab_dma &
2098 STRTAB_BASE_ADDR_MASK << STRTAB_BASE_ADDR_SHIFT;
2099 reg |= STRTAB_BASE_RA;
2100 smmu->strtab_cfg.strtab_base = reg;
2102 /* Allocate the first VMID for stage-2 bypass STEs */
2103 set_bit(0, smmu->vmid_map);
2107 static int arm_smmu_init_structures(struct arm_smmu_device *smmu)
2111 ret = arm_smmu_init_queues(smmu);
2115 return arm_smmu_init_strtab(smmu);
2118 static int arm_smmu_write_reg_sync(struct arm_smmu_device *smmu, u32 val,
2119 unsigned int reg_off, unsigned int ack_off)
2123 writel_relaxed(val, smmu->base + reg_off);
2124 return readl_relaxed_poll_timeout(smmu->base + ack_off, reg, reg == val,
2125 1, ARM_SMMU_POLL_TIMEOUT_US);
2128 static void arm_smmu_free_msis(void *data)
2130 struct device *dev = data;
2131 platform_msi_domain_free_irqs(dev);
2134 static void arm_smmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
2136 phys_addr_t doorbell;
2137 struct device *dev = msi_desc_to_dev(desc);
2138 struct arm_smmu_device *smmu = dev_get_drvdata(dev);
2139 phys_addr_t *cfg = arm_smmu_msi_cfg[desc->platform.msi_index];
2141 doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo;
2142 doorbell &= MSI_CFG0_ADDR_MASK << MSI_CFG0_ADDR_SHIFT;
2144 writeq_relaxed(doorbell, smmu->base + cfg[0]);
2145 writel_relaxed(msg->data, smmu->base + cfg[1]);
2146 writel_relaxed(MSI_CFG2_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]);
2149 static void arm_smmu_setup_msis(struct arm_smmu_device *smmu)
2151 struct msi_desc *desc;
2152 int ret, nvec = ARM_SMMU_MAX_MSIS;
2153 struct device *dev = smmu->dev;
2155 /* Clear the MSI address regs */
2156 writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0);
2157 writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0);
2159 if (smmu->features & ARM_SMMU_FEAT_PRI)
2160 writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0);
2164 if (!(smmu->features & ARM_SMMU_FEAT_MSI))
2167 /* Allocate MSIs for evtq, gerror and priq. Ignore cmdq */
2168 ret = platform_msi_domain_alloc_irqs(dev, nvec, arm_smmu_write_msi_msg);
2170 dev_warn(dev, "failed to allocate MSIs\n");
2174 for_each_msi_entry(desc, dev) {
2175 switch (desc->platform.msi_index) {
2176 case EVTQ_MSI_INDEX:
2177 smmu->evtq.q.irq = desc->irq;
2179 case GERROR_MSI_INDEX:
2180 smmu->gerr_irq = desc->irq;
2182 case PRIQ_MSI_INDEX:
2183 smmu->priq.q.irq = desc->irq;
2185 default: /* Unknown */
2190 /* Add callback to free MSIs on teardown */
2191 devm_add_action(dev, arm_smmu_free_msis, dev);
2194 static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
2197 u32 irqen_flags = IRQ_CTRL_EVTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN;
2199 /* Disable IRQs first */
2200 ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL,
2201 ARM_SMMU_IRQ_CTRLACK);
2203 dev_err(smmu->dev, "failed to disable irqs\n");
2207 arm_smmu_setup_msis(smmu);
2209 /* Request interrupt lines */
2210 irq = smmu->evtq.q.irq;
2212 ret = devm_request_threaded_irq(smmu->dev, irq,
2213 arm_smmu_evtq_handler,
2214 arm_smmu_evtq_thread,
2215 0, "arm-smmu-v3-evtq", smmu);
2216 if (IS_ERR_VALUE(ret))
2217 dev_warn(smmu->dev, "failed to enable evtq irq\n");
2220 irq = smmu->cmdq.q.irq;
2222 ret = devm_request_irq(smmu->dev, irq,
2223 arm_smmu_cmdq_sync_handler, 0,
2224 "arm-smmu-v3-cmdq-sync", smmu);
2225 if (IS_ERR_VALUE(ret))
2226 dev_warn(smmu->dev, "failed to enable cmdq-sync irq\n");
2229 irq = smmu->gerr_irq;
2231 ret = devm_request_irq(smmu->dev, irq, arm_smmu_gerror_handler,
2232 0, "arm-smmu-v3-gerror", smmu);
2233 if (IS_ERR_VALUE(ret))
2234 dev_warn(smmu->dev, "failed to enable gerror irq\n");
2237 if (smmu->features & ARM_SMMU_FEAT_PRI) {
2238 irq = smmu->priq.q.irq;
2240 ret = devm_request_threaded_irq(smmu->dev, irq,
2241 arm_smmu_priq_handler,
2242 arm_smmu_priq_thread,
2243 0, "arm-smmu-v3-priq",
2245 if (IS_ERR_VALUE(ret))
2247 "failed to enable priq irq\n");
2249 irqen_flags |= IRQ_CTRL_PRIQ_IRQEN;
2253 /* Enable interrupt generation on the SMMU */
2254 ret = arm_smmu_write_reg_sync(smmu, irqen_flags,
2255 ARM_SMMU_IRQ_CTRL, ARM_SMMU_IRQ_CTRLACK);
2257 dev_warn(smmu->dev, "failed to enable irqs\n");
2262 static int arm_smmu_device_disable(struct arm_smmu_device *smmu)
2266 ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_CR0, ARM_SMMU_CR0ACK);
2268 dev_err(smmu->dev, "failed to clear cr0\n");
2273 static int arm_smmu_device_reset(struct arm_smmu_device *smmu)
2277 struct arm_smmu_cmdq_ent cmd;
2279 /* Clear CR0 and sync (disables SMMU and queue processing) */
2280 reg = readl_relaxed(smmu->base + ARM_SMMU_CR0);
2281 if (reg & CR0_SMMUEN)
2282 dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n");
2284 ret = arm_smmu_device_disable(smmu);
2288 /* CR1 (table and queue memory attributes) */
2289 reg = (CR1_SH_ISH << CR1_TABLE_SH_SHIFT) |
2290 (CR1_CACHE_WB << CR1_TABLE_OC_SHIFT) |
2291 (CR1_CACHE_WB << CR1_TABLE_IC_SHIFT) |
2292 (CR1_SH_ISH << CR1_QUEUE_SH_SHIFT) |
2293 (CR1_CACHE_WB << CR1_QUEUE_OC_SHIFT) |
2294 (CR1_CACHE_WB << CR1_QUEUE_IC_SHIFT);
2295 writel_relaxed(reg, smmu->base + ARM_SMMU_CR1);
2297 /* CR2 (random crap) */
2298 reg = CR2_PTM | CR2_RECINVSID | CR2_E2H;
2299 writel_relaxed(reg, smmu->base + ARM_SMMU_CR2);
2302 writeq_relaxed(smmu->strtab_cfg.strtab_base,
2303 smmu->base + ARM_SMMU_STRTAB_BASE);
2304 writel_relaxed(smmu->strtab_cfg.strtab_base_cfg,
2305 smmu->base + ARM_SMMU_STRTAB_BASE_CFG);
2308 writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE);
2309 writel_relaxed(smmu->cmdq.q.prod, smmu->base + ARM_SMMU_CMDQ_PROD);
2310 writel_relaxed(smmu->cmdq.q.cons, smmu->base + ARM_SMMU_CMDQ_CONS);
2312 enables = CR0_CMDQEN;
2313 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
2316 dev_err(smmu->dev, "failed to enable command queue\n");
2320 /* Invalidate any cached configuration */
2321 cmd.opcode = CMDQ_OP_CFGI_ALL;
2322 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
2323 cmd.opcode = CMDQ_OP_CMD_SYNC;
2324 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
2326 /* Invalidate any stale TLB entries */
2327 if (smmu->features & ARM_SMMU_FEAT_HYP) {
2328 cmd.opcode = CMDQ_OP_TLBI_EL2_ALL;
2329 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
2332 cmd.opcode = CMDQ_OP_TLBI_NSNH_ALL;
2333 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
2334 cmd.opcode = CMDQ_OP_CMD_SYNC;
2335 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
2338 writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE);
2339 writel_relaxed(smmu->evtq.q.prod, smmu->base + ARM_SMMU_EVTQ_PROD);
2340 writel_relaxed(smmu->evtq.q.cons, smmu->base + ARM_SMMU_EVTQ_CONS);
2342 enables |= CR0_EVTQEN;
2343 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
2346 dev_err(smmu->dev, "failed to enable event queue\n");
2351 if (smmu->features & ARM_SMMU_FEAT_PRI) {
2352 writeq_relaxed(smmu->priq.q.q_base,
2353 smmu->base + ARM_SMMU_PRIQ_BASE);
2354 writel_relaxed(smmu->priq.q.prod,
2355 smmu->base + ARM_SMMU_PRIQ_PROD);
2356 writel_relaxed(smmu->priq.q.cons,
2357 smmu->base + ARM_SMMU_PRIQ_CONS);
2359 enables |= CR0_PRIQEN;
2360 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
2363 dev_err(smmu->dev, "failed to enable PRI queue\n");
2368 ret = arm_smmu_setup_irqs(smmu);
2370 dev_err(smmu->dev, "failed to setup irqs\n");
2374 /* Enable the SMMU interface */
2375 enables |= CR0_SMMUEN;
2376 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
2379 dev_err(smmu->dev, "failed to enable SMMU interface\n");
2386 static int arm_smmu_device_probe(struct arm_smmu_device *smmu)
2390 unsigned long pgsize_bitmap = 0;
2393 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0);
2395 /* 2-level structures */
2396 if ((reg & IDR0_ST_LVL_MASK << IDR0_ST_LVL_SHIFT) == IDR0_ST_LVL_2LVL)
2397 smmu->features |= ARM_SMMU_FEAT_2_LVL_STRTAB;
2399 if (reg & IDR0_CD2L)
2400 smmu->features |= ARM_SMMU_FEAT_2_LVL_CDTAB;
2403 * Translation table endianness.
2404 * We currently require the same endianness as the CPU, but this
2405 * could be changed later by adding a new IO_PGTABLE_QUIRK.
2407 switch (reg & IDR0_TTENDIAN_MASK << IDR0_TTENDIAN_SHIFT) {
2408 case IDR0_TTENDIAN_MIXED:
2409 smmu->features |= ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE;
2412 case IDR0_TTENDIAN_BE:
2413 smmu->features |= ARM_SMMU_FEAT_TT_BE;
2416 case IDR0_TTENDIAN_LE:
2417 smmu->features |= ARM_SMMU_FEAT_TT_LE;
2421 dev_err(smmu->dev, "unknown/unsupported TT endianness!\n");
2425 /* Boolean feature flags */
2426 if (IS_ENABLED(CONFIG_PCI_PRI) && reg & IDR0_PRI)
2427 smmu->features |= ARM_SMMU_FEAT_PRI;
2429 if (IS_ENABLED(CONFIG_PCI_ATS) && reg & IDR0_ATS)
2430 smmu->features |= ARM_SMMU_FEAT_ATS;
2433 smmu->features |= ARM_SMMU_FEAT_SEV;
2436 smmu->features |= ARM_SMMU_FEAT_MSI;
2439 smmu->features |= ARM_SMMU_FEAT_HYP;
2442 * The dma-coherent property is used in preference to the ID
2443 * register, but warn on mismatch.
2445 coherent = of_dma_is_coherent(smmu->dev->of_node);
2447 smmu->features |= ARM_SMMU_FEAT_COHERENCY;
2449 if (!!(reg & IDR0_COHACC) != coherent)
2450 dev_warn(smmu->dev, "IDR0.COHACC overridden by dma-coherent property (%s)\n",
2451 coherent ? "true" : "false");
2453 if (reg & IDR0_STALL_MODEL)
2454 smmu->features |= ARM_SMMU_FEAT_STALLS;
2457 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
2460 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
2462 if (!(reg & (IDR0_S1P | IDR0_S2P))) {
2463 dev_err(smmu->dev, "no translation support!\n");
2467 /* We only support the AArch64 table format at present */
2468 switch (reg & IDR0_TTF_MASK << IDR0_TTF_SHIFT) {
2469 case IDR0_TTF_AARCH32_64:
2472 case IDR0_TTF_AARCH64:
2475 dev_err(smmu->dev, "AArch64 table format not supported!\n");
2479 /* ASID/VMID sizes */
2480 smmu->asid_bits = reg & IDR0_ASID16 ? 16 : 8;
2481 smmu->vmid_bits = reg & IDR0_VMID16 ? 16 : 8;
2484 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR1);
2485 if (reg & (IDR1_TABLES_PRESET | IDR1_QUEUES_PRESET | IDR1_REL)) {
2486 dev_err(smmu->dev, "embedded implementation not supported\n");
2490 /* Queue sizes, capped at 4k */
2491 smmu->cmdq.q.max_n_shift = min((u32)CMDQ_MAX_SZ_SHIFT,
2492 reg >> IDR1_CMDQ_SHIFT & IDR1_CMDQ_MASK);
2493 if (!smmu->cmdq.q.max_n_shift) {
2494 /* Odd alignment restrictions on the base, so ignore for now */
2495 dev_err(smmu->dev, "unit-length command queue not supported\n");
2499 smmu->evtq.q.max_n_shift = min((u32)EVTQ_MAX_SZ_SHIFT,
2500 reg >> IDR1_EVTQ_SHIFT & IDR1_EVTQ_MASK);
2501 smmu->priq.q.max_n_shift = min((u32)PRIQ_MAX_SZ_SHIFT,
2502 reg >> IDR1_PRIQ_SHIFT & IDR1_PRIQ_MASK);
2504 /* SID/SSID sizes */
2505 smmu->ssid_bits = reg >> IDR1_SSID_SHIFT & IDR1_SSID_MASK;
2506 smmu->sid_bits = reg >> IDR1_SID_SHIFT & IDR1_SID_MASK;
2509 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5);
2511 /* Maximum number of outstanding stalls */
2512 smmu->evtq.max_stalls = reg >> IDR5_STALL_MAX_SHIFT
2513 & IDR5_STALL_MAX_MASK;
2516 if (reg & IDR5_GRAN64K)
2517 pgsize_bitmap |= SZ_64K | SZ_512M;
2518 if (reg & IDR5_GRAN16K)
2519 pgsize_bitmap |= SZ_16K | SZ_32M;
2520 if (reg & IDR5_GRAN4K)
2521 pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G;
2523 arm_smmu_ops.pgsize_bitmap &= pgsize_bitmap;
2525 /* Output address size */
2526 switch (reg & IDR5_OAS_MASK << IDR5_OAS_SHIFT) {
2527 case IDR5_OAS_32_BIT:
2530 case IDR5_OAS_36_BIT:
2533 case IDR5_OAS_40_BIT:
2536 case IDR5_OAS_42_BIT:
2539 case IDR5_OAS_44_BIT:
2544 "unknown output address size. Truncating to 48-bit\n");
2546 case IDR5_OAS_48_BIT:
2550 /* Set the DMA mask for our table walker */
2551 if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(smmu->oas)))
2553 "failed to set DMA mask for table walker\n");
2555 smmu->ias = max(smmu->ias, smmu->oas);
2557 dev_info(smmu->dev, "ias %lu-bit, oas %lu-bit (features 0x%08x)\n",
2558 smmu->ias, smmu->oas, smmu->features);
2562 static int arm_smmu_device_dt_probe(struct platform_device *pdev)
2565 struct resource *res;
2566 struct arm_smmu_device *smmu;
2567 struct device *dev = &pdev->dev;
2569 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
2571 dev_err(dev, "failed to allocate arm_smmu_device\n");
2577 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2578 if (resource_size(res) + 1 < SZ_128K) {
2579 dev_err(dev, "MMIO region too small (%pr)\n", res);
2583 smmu->base = devm_ioremap_resource(dev, res);
2584 if (IS_ERR(smmu->base))
2585 return PTR_ERR(smmu->base);
2587 /* Interrupt lines */
2588 irq = platform_get_irq_byname(pdev, "eventq");
2590 smmu->evtq.q.irq = irq;
2592 irq = platform_get_irq_byname(pdev, "priq");
2594 smmu->priq.q.irq = irq;
2596 irq = platform_get_irq_byname(pdev, "cmdq-sync");
2598 smmu->cmdq.q.irq = irq;
2600 irq = platform_get_irq_byname(pdev, "gerror");
2602 smmu->gerr_irq = irq;
2604 parse_driver_options(smmu);
2607 ret = arm_smmu_device_probe(smmu);
2611 /* Initialise in-memory data structures */
2612 ret = arm_smmu_init_structures(smmu);
2616 /* Record our private device structure */
2617 platform_set_drvdata(pdev, smmu);
2619 /* Reset the device */
2620 return arm_smmu_device_reset(smmu);
2623 static int arm_smmu_device_remove(struct platform_device *pdev)
2625 struct arm_smmu_device *smmu = platform_get_drvdata(pdev);
2627 arm_smmu_device_disable(smmu);
2631 static struct of_device_id arm_smmu_of_match[] = {
2632 { .compatible = "arm,smmu-v3", },
2635 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
2637 static struct platform_driver arm_smmu_driver = {
2639 .name = "arm-smmu-v3",
2640 .of_match_table = of_match_ptr(arm_smmu_of_match),
2642 .probe = arm_smmu_device_dt_probe,
2643 .remove = arm_smmu_device_remove,
2646 static int __init arm_smmu_init(void)
2648 struct device_node *np;
2651 np = of_find_matching_node(NULL, arm_smmu_of_match);
2657 ret = platform_driver_register(&arm_smmu_driver);
2661 return bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
2664 static void __exit arm_smmu_exit(void)
2666 return platform_driver_unregister(&arm_smmu_driver);
2669 subsys_initcall(arm_smmu_init);
2670 module_exit(arm_smmu_exit);
2672 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 implementations");
2673 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
2674 MODULE_LICENSE("GPL v2");