drivers/iommu/exynos-iommu.c

   1 /* linux/drivers/iommu/exynos_iommu.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #ifdef CONFIG_EXYNOS_IOMMU_DEBUG
  12 #define DEBUG
  13 #endif
  14
  15 #include <linux/clk.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19 #include <linux/iommu.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/list.h>
  22 #include <linux/of.h>
  23 #include <linux/of_iommu.h>
  24 #include <linux/of_platform.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/slab.h>
  28 #include <linux/dma-iommu.h>
  29
  30 typedef u32 sysmmu_iova_t;
  31 typedef u32 sysmmu_pte_t;
  32
  33 /* We do not consider super section mapping (16MB) */
  34 #define SECT_ORDER 20
  35 #define LPAGE_ORDER 16
  36 #define SPAGE_ORDER 12
  37
  38 #define SECT_SIZE (1 << SECT_ORDER)
  39 #define LPAGE_SIZE (1 << LPAGE_ORDER)
  40 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  41
  42 #define SECT_MASK (~(SECT_SIZE - 1))
  43 #define LPAGE_MASK (~(LPAGE_SIZE - 1))
  44 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  45
  46 #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \
  47                            ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
  48 #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK)
  49 #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1)
  50 #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \
  51                           ((*(sent) & 3) == 1))
  52 #define lv1ent_section(sent) ((*(sent) & 3) == 2)
  53
  54 #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
  55 #define lv2ent_small(pent) ((*(pent) & 2) == 2)
  56 #define lv2ent_large(pent) ((*(pent) & 3) == 1)
  57
  58 static u32 sysmmu_page_offset(sysmmu_iova_t iova, u32 size)
  59 {
  60         return iova & (size - 1);
  61 }
  62
  63 #define section_phys(sent) (*(sent) & SECT_MASK)
  64 #define section_offs(iova) sysmmu_page_offset((iova), SECT_SIZE)
  65 #define lpage_phys(pent) (*(pent) & LPAGE_MASK)
  66 #define lpage_offs(iova) sysmmu_page_offset((iova), LPAGE_SIZE)
  67 #define spage_phys(pent) (*(pent) & SPAGE_MASK)
  68 #define spage_offs(iova) sysmmu_page_offset((iova), SPAGE_SIZE)
  69
  70 #define NUM_LV1ENTRIES 4096
  71 #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
  72
  73 static u32 lv1ent_offset(sysmmu_iova_t iova)
  74 {
  75         return iova >> SECT_ORDER;
  76 }
  77
  78 static u32 lv2ent_offset(sysmmu_iova_t iova)
  79 {
  80         return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1);
  81 }
  82
  83 #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t))
  84 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
  85
  86 #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
  87
  88 #define lv2table_base(sent) (*(sent) & 0xFFFFFC00)
  89
  90 #define mk_lv1ent_sect(pa) ((pa) | 2)
  91 #define mk_lv1ent_page(pa) ((pa) | 1)
  92 #define mk_lv2ent_lpage(pa) ((pa) | 1)
  93 #define mk_lv2ent_spage(pa) ((pa) | 2)
  94
  95 #define CTRL_ENABLE     0x5
  96 #define CTRL_BLOCK      0x7
  97 #define CTRL_DISABLE    0x0
  98
  99 #define CFG_LRU         0x1
 100 #define CFG_QOS(n)      ((n & 0xF) << 7)
 101 #define CFG_MASK        0x0150FFFF /* Selecting bit 0-15, 20, 22 and 24 */
 102 #define CFG_ACGEN       (1 << 24) /* System MMU 3.3 only */
 103 #define CFG_SYSSEL      (1 << 22) /* System MMU 3.2 only */
 104 #define CFG_FLPDCACHE   (1 << 20) /* System MMU 3.2+ only */
 105
 106 #define REG_MMU_CTRL            0x000
 107 #define REG_MMU_CFG             0x004
 108 #define REG_MMU_STATUS          0x008
 109 #define REG_MMU_FLUSH           0x00C
 110 #define REG_MMU_FLUSH_ENTRY     0x010
 111 #define REG_PT_BASE_ADDR        0x014
 112 #define REG_INT_STATUS          0x018
 113 #define REG_INT_CLEAR           0x01C
 114
 115 #define REG_PAGE_FAULT_ADDR     0x024
 116 #define REG_AW_FAULT_ADDR       0x028
 117 #define REG_AR_FAULT_ADDR       0x02C
 118 #define REG_DEFAULT_SLAVE_ADDR  0x030
 119
 120 #define REG_MMU_VERSION         0x034
 121
 122 #define MMU_MAJ_VER(val)        ((val) >> 7)
 123 #define MMU_MIN_VER(val)        ((val) & 0x7F)
 124 #define MMU_RAW_VER(reg)        (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */
 125
 126 #define MAKE_MMU_VER(maj, min)  ((((maj) & 0xF) << 7) | ((min) & 0x7F))
 127
 128 #define REG_PB0_SADDR           0x04C
 129 #define REG_PB0_EADDR           0x050
 130 #define REG_PB1_SADDR           0x054
 131 #define REG_PB1_EADDR           0x058
 132
 133 #define has_sysmmu(dev)         (dev->archdata.iommu != NULL)
 134
 135 static struct device *dma_dev;
 136 static struct kmem_cache *lv2table_kmem_cache;
 137 static sysmmu_pte_t *zero_lv2_table;
 138 #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table))
 139
 140 static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova)
 141 {
 142         return pgtable + lv1ent_offset(iova);
 143 }
 144
 145 static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
 146 {
 147         return (sysmmu_pte_t *)phys_to_virt(
 148                                 lv2table_base(sent)) + lv2ent_offset(iova);
 149 }
 150
 151 enum exynos_sysmmu_inttype {
 152         SYSMMU_PAGEFAULT,
 153         SYSMMU_AR_MULTIHIT,
 154         SYSMMU_AW_MULTIHIT,
 155         SYSMMU_BUSERROR,
 156         SYSMMU_AR_SECURITY,
 157         SYSMMU_AR_ACCESS,
 158         SYSMMU_AW_SECURITY,
 159         SYSMMU_AW_PROTECTION, /* 7 */
 160         SYSMMU_FAULT_UNKNOWN,
 161         SYSMMU_FAULTS_NUM
 162 };
 163
 164 static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
 165         REG_PAGE_FAULT_ADDR,
 166         REG_AR_FAULT_ADDR,
 167         REG_AW_FAULT_ADDR,
 168         REG_DEFAULT_SLAVE_ADDR,
 169         REG_AR_FAULT_ADDR,
 170         REG_AR_FAULT_ADDR,
 171         REG_AW_FAULT_ADDR,
 172         REG_AW_FAULT_ADDR
 173 };
 174
 175 static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
 176         "PAGE FAULT",
 177         "AR MULTI-HIT FAULT",
 178         "AW MULTI-HIT FAULT",
 179         "BUS ERROR",
 180         "AR SECURITY PROTECTION FAULT",
 181         "AR ACCESS PROTECTION FAULT",
 182         "AW SECURITY PROTECTION FAULT",
 183         "AW ACCESS PROTECTION FAULT",
 184         "UNKNOWN FAULT"
 185 };
 186
 187 /*
 188  * This structure is attached to dev.archdata.iommu of the master device
 189  * on device add, contains a list of SYSMMU controllers defined by device tree,
 190  * which are bound to given master device. It is usually referenced by 'owner'
 191  * pointer.
 192 */
 193 struct exynos_iommu_owner {
 194         struct list_head controllers;   /* list of sysmmu_drvdata.owner_node */
 195 };
 196
 197 /*
 198  * This structure exynos specific generalization of struct iommu_domain.
 199  * It contains list of SYSMMU controllers from all master devices, which has
 200  * been attached to this domain and page tables of IO address space defined by
 201  * it. It is usually referenced by 'domain' pointer.
 202  */
 203 struct exynos_iommu_domain {
 204         struct list_head clients; /* list of sysmmu_drvdata.domain_node */
 205         sysmmu_pte_t *pgtable;  /* lv1 page table, 16KB */
 206         short *lv2entcnt;       /* free lv2 entry counter for each section */
 207         spinlock_t lock;        /* lock for modyfying list of clients */
 208         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 209         struct iommu_domain domain; /* generic domain data structure */
 210 };
 211
 212 /*
 213  * This structure hold all data of a single SYSMMU controller, this includes
 214  * hw resources like registers and clocks, pointers and list nodes to connect
 215  * it to all other structures, internal state and parameters read from device
 216  * tree. It is usually referenced by 'data' pointer.
 217  */
 218 struct sysmmu_drvdata {
 219         struct device *sysmmu;          /* SYSMMU controller device */
 220         struct device *master;          /* master device (owner) */
 221         void __iomem *sfrbase;          /* our registers */
 222         struct clk *clk;                /* SYSMMU's clock */
 223         struct clk *clk_master;         /* master's device clock */
 224         int activations;                /* number of calls to sysmmu_enable */
 225         spinlock_t lock;                /* lock for modyfying state */
 226         struct exynos_iommu_domain *domain; /* domain we belong to */
 227         struct list_head domain_node;   /* node for domain clients list */
 228         struct list_head owner_node;    /* node for owner controllers list */
 229         phys_addr_t pgtable;            /* assigned page table structure */
 230         unsigned int version;           /* our version */
 231 };
 232
 233 static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom)
 234 {
 235         return container_of(dom, struct exynos_iommu_domain, domain);
 236 }
 237
 238 static bool set_sysmmu_active(struct sysmmu_drvdata *data)
 239 {
 240         /* return true if the System MMU was not active previously
 241            and it needs to be initialized */
 242         return ++data->activations == 1;
 243 }
 244
 245 static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
 246 {
 247         /* return true if the System MMU is needed to be disabled */
 248         BUG_ON(data->activations < 1);
 249         return --data->activations == 0;
 250 }
 251
 252 static bool is_sysmmu_active(struct sysmmu_drvdata *data)
 253 {
 254         return data->activations > 0;
 255 }
 256
 257 static void sysmmu_unblock(struct sysmmu_drvdata *data)
 258 {
 259         __raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 260 }
 261
 262 static bool sysmmu_block(struct sysmmu_drvdata *data)
 263 {
 264         int i = 120;
 265
 266         __raw_writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 267         while ((i > 0) && !(__raw_readl(data->sfrbase + REG_MMU_STATUS) & 1))
 268                 --i;
 269
 270         if (!(__raw_readl(data->sfrbase + REG_MMU_STATUS) & 1)) {
 271                 sysmmu_unblock(data);
 272                 return false;
 273         }
 274
 275         return true;
 276 }
 277
 278 static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data)
 279 {
 280         __raw_writel(0x1, data->sfrbase + REG_MMU_FLUSH);
 281 }
 282
 283 static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 284                                 sysmmu_iova_t iova, unsigned int num_inv)
 285 {
 286         unsigned int i;
 287
 288         for (i = 0; i < num_inv; i++) {
 289                 __raw_writel((iova & SPAGE_MASK) | 1,
 290                                 data->sfrbase + REG_MMU_FLUSH_ENTRY);
 291                 iova += SPAGE_SIZE;
 292         }
 293 }
 294
 295 static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd)
 296 {
 297         __raw_writel(pgd, data->sfrbase + REG_PT_BASE_ADDR);
 298
 299         __sysmmu_tlb_invalidate(data);
 300 }
 301
 302 static void show_fault_information(const char *name,
 303                 enum exynos_sysmmu_inttype itype,
 304                 phys_addr_t pgtable_base, sysmmu_iova_t fault_addr)
 305 {
 306         sysmmu_pte_t *ent;
 307
 308         if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT))
 309                 itype = SYSMMU_FAULT_UNKNOWN;
 310
 311         pr_err("%s occurred at %#x by %s(Page table base: %pa)\n",
 312                 sysmmu_fault_name[itype], fault_addr, name, &pgtable_base);
 313
 314         ent = section_entry(phys_to_virt(pgtable_base), fault_addr);
 315         pr_err("\tLv1 entry: %#x\n", *ent);
 316
 317         if (lv1ent_page(ent)) {
 318                 ent = page_entry(ent, fault_addr);
 319                 pr_err("\t Lv2 entry: %#x\n", *ent);
 320         }
 321 }
 322
 323 static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
 324 {
 325         /* SYSMMU is in blocked state when interrupt occurred. */
 326         struct sysmmu_drvdata *data = dev_id;
 327         enum exynos_sysmmu_inttype itype;
 328         sysmmu_iova_t addr = -1;
 329         int ret = -ENOSYS;
 330
 331         WARN_ON(!is_sysmmu_active(data));
 332
 333         spin_lock(&data->lock);
 334
 335         clk_enable(data->clk_master);
 336
 337         itype = (enum exynos_sysmmu_inttype)
 338                 __ffs(__raw_readl(data->sfrbase + REG_INT_STATUS));
 339         if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN))))
 340                 itype = SYSMMU_FAULT_UNKNOWN;
 341         else
 342                 addr = __raw_readl(data->sfrbase + fault_reg_offset[itype]);
 343
 344         if (itype == SYSMMU_FAULT_UNKNOWN) {
 345                 pr_err("%s: Fault is not occurred by System MMU '%s'!\n",
 346                         __func__, dev_name(data->sysmmu));
 347                 pr_err("%s: Please check if IRQ is correctly configured.\n",
 348                         __func__);
 349                 BUG();
 350         } else {
 351                 unsigned int base =
 352                                 __raw_readl(data->sfrbase + REG_PT_BASE_ADDR);
 353                 show_fault_information(dev_name(data->sysmmu),
 354                                         itype, base, addr);
 355                 if (data->domain)
 356                         ret = report_iommu_fault(&data->domain->domain,
 357                                         data->master, addr, itype);
 358         }
 359
 360         /* fault is not recovered by fault handler */
 361         BUG_ON(ret != 0);
 362
 363         __raw_writel(1 << itype, data->sfrbase + REG_INT_CLEAR);
 364
 365         sysmmu_unblock(data);
 366
 367         clk_disable(data->clk_master);
 368
 369         spin_unlock(&data->lock);
 370
 371         return IRQ_HANDLED;
 372 }
 373
 374 static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data)
 375 {
 376         clk_enable(data->clk_master);
 377
 378         __raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
 379         __raw_writel(0, data->sfrbase + REG_MMU_CFG);
 380
 381         clk_disable(data->clk);
 382         clk_disable(data->clk_master);
 383 }
 384
 385 static bool __sysmmu_disable(struct sysmmu_drvdata *data)
 386 {
 387         bool disabled;
 388         unsigned long flags;
 389
 390         spin_lock_irqsave(&data->lock, flags);
 391
 392         disabled = set_sysmmu_inactive(data);
 393
 394         if (disabled) {
 395                 data->pgtable = 0;
 396                 data->domain = NULL;
 397
 398                 __sysmmu_disable_nocount(data);
 399
 400                 dev_dbg(data->sysmmu, "Disabled\n");
 401         } else  {
 402                 dev_dbg(data->sysmmu, "%d times left to disable\n",
 403                                         data->activations);
 404         }
 405
 406         spin_unlock_irqrestore(&data->lock, flags);
 407
 408         return disabled;
 409 }
 410
 411 static void __sysmmu_init_config(struct sysmmu_drvdata *data)
 412 {
 413         unsigned int cfg = CFG_LRU | CFG_QOS(15);
 414         unsigned int ver;
 415
 416         ver = MMU_RAW_VER(__raw_readl(data->sfrbase + REG_MMU_VERSION));
 417         if (MMU_MAJ_VER(ver) == 3) {
 418                 if (MMU_MIN_VER(ver) >= 2) {
 419                         cfg |= CFG_FLPDCACHE;
 420                         if (MMU_MIN_VER(ver) == 3) {
 421                                 cfg |= CFG_ACGEN;
 422                                 cfg &= ~CFG_LRU;
 423                         } else {
 424                                 cfg |= CFG_SYSSEL;
 425                         }
 426                 }
 427         }
 428
 429         __raw_writel(cfg, data->sfrbase + REG_MMU_CFG);
 430         data->version = ver;
 431 }
 432
 433 static void __sysmmu_enable_nocount(struct sysmmu_drvdata *data)
 434 {
 435         clk_enable(data->clk_master);
 436         clk_enable(data->clk);
 437
 438         __raw_writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 439
 440         __sysmmu_init_config(data);
 441
 442         __sysmmu_set_ptbase(data, data->pgtable);
 443
 444         __raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 445
 446         clk_disable(data->clk_master);
 447 }
 448
 449 static int __sysmmu_enable(struct sysmmu_drvdata *data, phys_addr_t pgtable,
 450                            struct exynos_iommu_domain *domain)
 451 {
 452         int ret = 0;
 453         unsigned long flags;
 454
 455         spin_lock_irqsave(&data->lock, flags);
 456         if (set_sysmmu_active(data)) {
 457                 data->pgtable = pgtable;
 458                 data->domain = domain;
 459
 460                 __sysmmu_enable_nocount(data);
 461
 462                 dev_dbg(data->sysmmu, "Enabled\n");
 463         } else {
 464                 ret = (pgtable == data->pgtable) ? 1 : -EBUSY;
 465
 466                 dev_dbg(data->sysmmu, "already enabled\n");
 467         }
 468
 469         if (WARN_ON(ret < 0))
 470                 set_sysmmu_inactive(data); /* decrement count */
 471
 472         spin_unlock_irqrestore(&data->lock, flags);
 473
 474         return ret;
 475 }
 476
 477 static void __sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
 478                                               sysmmu_iova_t iova)
 479 {
 480         if (data->version == MAKE_MMU_VER(3, 3))
 481                 __raw_writel(iova | 0x1, data->sfrbase + REG_MMU_FLUSH_ENTRY);
 482 }
 483
 484 static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
 485                                             sysmmu_iova_t iova)
 486 {
 487         unsigned long flags;
 488
 489         clk_enable(data->clk_master);
 490
 491         spin_lock_irqsave(&data->lock, flags);
 492         if (is_sysmmu_active(data))
 493                 __sysmmu_tlb_invalidate_flpdcache(data, iova);
 494         spin_unlock_irqrestore(&data->lock, flags);
 495
 496         clk_disable(data->clk_master);
 497 }
 498
 499 static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 500                                         sysmmu_iova_t iova, size_t size)
 501 {
 502         unsigned long flags;
 503
 504         spin_lock_irqsave(&data->lock, flags);
 505         if (is_sysmmu_active(data)) {
 506                 unsigned int num_inv = 1;
 507
 508                 clk_enable(data->clk_master);
 509
 510                 /*
 511                  * L2TLB invalidation required
 512                  * 4KB page: 1 invalidation
 513                  * 64KB page: 16 invalidations
 514                  * 1MB page: 64 invalidations
 515                  * because it is set-associative TLB
 516                  * with 8-way and 64 sets.
 517                  * 1MB page can be cached in one of all sets.
 518                  * 64KB page can be one of 16 consecutive sets.
 519                  */
 520                 if (MMU_MAJ_VER(data->version) == 2)
 521                         num_inv = min_t(unsigned int, size / PAGE_SIZE, 64);
 522
 523                 if (sysmmu_block(data)) {
 524                         __sysmmu_tlb_invalidate_entry(data, iova, num_inv);
 525                         sysmmu_unblock(data);
 526                 }
 527                 clk_disable(data->clk_master);
 528         } else {
 529                 dev_dbg(data->master,
 530                         "disabled. Skipping TLB invalidation @ %#x\n", iova);
 531         }
 532         spin_unlock_irqrestore(&data->lock, flags);
 533 }
 534
 535 static int __init exynos_sysmmu_probe(struct platform_device *pdev)
 536 {
 537         int irq, ret;
 538         struct device *dev = &pdev->dev;
 539         struct sysmmu_drvdata *data;
 540         struct resource *res;
 541
 542         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 543         if (!data)
 544                 return -ENOMEM;
 545
 546         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 547         data->sfrbase = devm_ioremap_resource(dev, res);
 548         if (IS_ERR(data->sfrbase))
 549                 return PTR_ERR(data->sfrbase);
 550
 551         irq = platform_get_irq(pdev, 0);
 552         if (irq <= 0) {
 553                 dev_err(dev, "Unable to find IRQ resource\n");
 554                 return irq;
 555         }
 556
 557         ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,
 558                                 dev_name(dev), data);
 559         if (ret) {
 560                 dev_err(dev, "Unabled to register handler of irq %d\n", irq);
 561                 return ret;
 562         }
 563
 564         data->clk = devm_clk_get(dev, "sysmmu");
 565         if (IS_ERR(data->clk)) {
 566                 dev_err(dev, "Failed to get clock!\n");
 567                 return PTR_ERR(data->clk);
 568         } else  {
 569                 ret = clk_prepare(data->clk);
 570                 if (ret) {
 571                         dev_err(dev, "Failed to prepare clk\n");
 572                         return ret;
 573                 }
 574         }
 575
 576         data->clk_master = devm_clk_get(dev, "master");
 577         if (!IS_ERR(data->clk_master)) {
 578                 ret = clk_prepare(data->clk_master);
 579                 if (ret) {
 580                         clk_unprepare(data->clk);
 581                         dev_err(dev, "Failed to prepare master's clk\n");
 582                         return ret;
 583                 }
 584         } else {
 585                 data->clk_master = NULL;
 586         }
 587
 588         data->sysmmu = dev;
 589         spin_lock_init(&data->lock);
 590
 591         platform_set_drvdata(pdev, data);
 592
 593         pm_runtime_enable(dev);
 594
 595         return 0;
 596 }
 597
 598 #ifdef CONFIG_PM_SLEEP
 599 static int exynos_sysmmu_suspend(struct device *dev)
 600 {
 601         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 602
 603         dev_dbg(dev, "suspend\n");
 604         if (is_sysmmu_active(data)) {
 605                 __sysmmu_disable_nocount(data);
 606                 pm_runtime_put(dev);
 607         }
 608         return 0;
 609 }
 610
 611 static int exynos_sysmmu_resume(struct device *dev)
 612 {
 613         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 614
 615         dev_dbg(dev, "resume\n");
 616         if (is_sysmmu_active(data)) {
 617                 pm_runtime_get_sync(dev);
 618                 __sysmmu_enable_nocount(data);
 619         }
 620         return 0;
 621 }
 622 #endif
 623
 624 static const struct dev_pm_ops sysmmu_pm_ops = {
 625         SET_LATE_SYSTEM_SLEEP_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume)
 626 };
 627
 628 static const struct of_device_id sysmmu_of_match[] __initconst = {
 629         { .compatible   = "samsung,exynos-sysmmu", },
 630         { },
 631 };
 632
 633 static struct platform_driver exynos_sysmmu_driver __refdata = {
 634         .probe  = exynos_sysmmu_probe,
 635         .driver = {
 636                 .name           = "exynos-sysmmu",
 637                 .of_match_table = sysmmu_of_match,
 638                 .pm             = &sysmmu_pm_ops,
 639         }
 640 };
 641
 642 static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val)
 643 {
 644         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent),
 645                                 DMA_TO_DEVICE);
 646         *ent = val;
 647         dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent),
 648                                    DMA_TO_DEVICE);
 649 }
 650
 651 static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type)
 652 {
 653         struct exynos_iommu_domain *domain;
 654         dma_addr_t handle;
 655         int i;
 656
 657
 658         domain = kzalloc(sizeof(*domain), GFP_KERNEL);
 659         if (!domain)
 660                 return NULL;
 661
 662         if (type == IOMMU_DOMAIN_DMA) {
 663                 if (iommu_get_dma_cookie(&domain->domain) != 0)
 664                         goto err_pgtable;
 665         } else if (type != IOMMU_DOMAIN_UNMANAGED) {
 666                 goto err_pgtable;
 667         }
 668
 669         domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2);
 670         if (!domain->pgtable)
 671                 goto err_dma_cookie;
 672
 673         domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1);
 674         if (!domain->lv2entcnt)
 675                 goto err_counter;
 676
 677         /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */
 678         for (i = 0; i < NUM_LV1ENTRIES; i += 8) {
 679                 domain->pgtable[i + 0] = ZERO_LV2LINK;
 680                 domain->pgtable[i + 1] = ZERO_LV2LINK;
 681                 domain->pgtable[i + 2] = ZERO_LV2LINK;
 682                 domain->pgtable[i + 3] = ZERO_LV2LINK;
 683                 domain->pgtable[i + 4] = ZERO_LV2LINK;
 684                 domain->pgtable[i + 5] = ZERO_LV2LINK;
 685                 domain->pgtable[i + 6] = ZERO_LV2LINK;
 686                 domain->pgtable[i + 7] = ZERO_LV2LINK;
 687         }
 688
 689         handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE,
 690                                 DMA_TO_DEVICE);
 691         /* For mapping page table entries we rely on dma == phys */
 692         BUG_ON(handle != virt_to_phys(domain->pgtable));
 693
 694         spin_lock_init(&domain->lock);
 695         spin_lock_init(&domain->pgtablelock);
 696         INIT_LIST_HEAD(&domain->clients);
 697
 698         domain->domain.geometry.aperture_start = 0;
 699         domain->domain.geometry.aperture_end   = ~0UL;
 700         domain->domain.geometry.force_aperture = true;
 701
 702         return &domain->domain;
 703
 704 err_counter:
 705         free_pages((unsigned long)domain->pgtable, 2);
 706 err_dma_cookie:
 707         if (type == IOMMU_DOMAIN_DMA)
 708                 iommu_put_dma_cookie(&domain->domain);
 709 err_pgtable:
 710         kfree(domain);
 711         return NULL;
 712 }
 713
 714 static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain)
 715 {
 716         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 717         struct sysmmu_drvdata *data, *next;
 718         unsigned long flags;
 719         int i;
 720
 721         WARN_ON(!list_empty(&domain->clients));
 722
 723         spin_lock_irqsave(&domain->lock, flags);
 724
 725         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 726                 if (__sysmmu_disable(data))
 727                         data->master = NULL;
 728                 list_del_init(&data->domain_node);
 729         }
 730
 731         spin_unlock_irqrestore(&domain->lock, flags);
 732
 733         if (iommu_domain->type == IOMMU_DOMAIN_DMA)
 734                 iommu_put_dma_cookie(iommu_domain);
 735
 736         dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE,
 737                          DMA_TO_DEVICE);
 738
 739         for (i = 0; i < NUM_LV1ENTRIES; i++)
 740                 if (lv1ent_page(domain->pgtable + i)) {
 741                         phys_addr_t base = lv2table_base(domain->pgtable + i);
 742
 743                         dma_unmap_single(dma_dev, base, LV2TABLE_SIZE,
 744                                          DMA_TO_DEVICE);
 745                         kmem_cache_free(lv2table_kmem_cache,
 746                                         phys_to_virt(base));
 747                 }
 748
 749         free_pages((unsigned long)domain->pgtable, 2);
 750         free_pages((unsigned long)domain->lv2entcnt, 1);
 751         kfree(domain);
 752 }
 753
 754 static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain,
 755                                    struct device *dev)
 756 {
 757         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 758         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 759         struct sysmmu_drvdata *data;
 760         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 761         unsigned long flags;
 762         int ret = -ENODEV;
 763
 764         if (!has_sysmmu(dev))
 765                 return -ENODEV;
 766
 767         list_for_each_entry(data, &owner->controllers, owner_node) {
 768                 pm_runtime_get_sync(data->sysmmu);
 769                 ret = __sysmmu_enable(data, pagetable, domain);
 770                 if (ret >= 0) {
 771                         data->master = dev;
 772
 773                         spin_lock_irqsave(&domain->lock, flags);
 774                         list_add_tail(&data->domain_node, &domain->clients);
 775                         spin_unlock_irqrestore(&domain->lock, flags);
 776                 }
 777         }
 778
 779         if (ret < 0) {
 780                 dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n",
 781                                         __func__, &pagetable);
 782                 return ret;
 783         }
 784
 785         dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n",
 786                 __func__, &pagetable, (ret == 0) ? "" : ", again");
 787
 788         return ret;
 789 }
 790
 791 static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain,
 792                                     struct device *dev)
 793 {
 794         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 795         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 796         struct sysmmu_drvdata *data, *next;
 797         unsigned long flags;
 798         bool found = false;
 799
 800         if (!has_sysmmu(dev))
 801                 return;
 802
 803         spin_lock_irqsave(&domain->lock, flags);
 804         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 805                 if (data->master == dev) {
 806                         if (__sysmmu_disable(data)) {
 807                                 data->master = NULL;
 808                                 list_del_init(&data->domain_node);
 809                         }
 810                         pm_runtime_put(data->sysmmu);
 811                         found = true;
 812                 }
 813         }
 814         spin_unlock_irqrestore(&domain->lock, flags);
 815
 816         if (found)
 817                 dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n",
 818                                         __func__, &pagetable);
 819         else
 820                 dev_err(dev, "%s: No IOMMU is attached\n", __func__);
 821 }
 822
 823 static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain,
 824                 sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter)
 825 {
 826         if (lv1ent_section(sent)) {
 827                 WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova);
 828                 return ERR_PTR(-EADDRINUSE);
 829         }
 830
 831         if (lv1ent_fault(sent)) {
 832                 sysmmu_pte_t *pent;
 833                 bool need_flush_flpd_cache = lv1ent_zero(sent);
 834
 835                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 836                 BUG_ON((unsigned int)pent & (LV2TABLE_SIZE - 1));
 837                 if (!pent)
 838                         return ERR_PTR(-ENOMEM);
 839
 840                 update_pte(sent, mk_lv1ent_page(virt_to_phys(pent)));
 841                 kmemleak_ignore(pent);
 842                 *pgcounter = NUM_LV2ENTRIES;
 843                 dma_map_single(dma_dev, pent, LV2TABLE_SIZE, DMA_TO_DEVICE);
 844
 845                 /*
 846                  * If pre-fetched SLPD is a faulty SLPD in zero_l2_table,
 847                  * FLPD cache may cache the address of zero_l2_table. This
 848                  * function replaces the zero_l2_table with new L2 page table
 849                  * to write valid mappings.
 850                  * Accessing the valid area may cause page fault since FLPD
 851                  * cache may still cache zero_l2_table for the valid area
 852                  * instead of new L2 page table that has the mapping
 853                  * information of the valid area.
 854                  * Thus any replacement of zero_l2_table with other valid L2
 855                  * page table must involve FLPD cache invalidation for System
 856                  * MMU v3.3.
 857                  * FLPD cache invalidation is performed with TLB invalidation
 858                  * by VPN without blocking. It is safe to invalidate TLB without
 859                  * blocking because the target address of TLB invalidation is
 860                  * not currently mapped.
 861                  */
 862                 if (need_flush_flpd_cache) {
 863                         struct sysmmu_drvdata *data;
 864
 865                         spin_lock(&domain->lock);
 866                         list_for_each_entry(data, &domain->clients, domain_node)
 867                                 sysmmu_tlb_invalidate_flpdcache(data, iova);
 868                         spin_unlock(&domain->lock);
 869                 }
 870         }
 871
 872         return page_entry(sent, iova);
 873 }
 874
 875 static int lv1set_section(struct exynos_iommu_domain *domain,
 876                           sysmmu_pte_t *sent, sysmmu_iova_t iova,
 877                           phys_addr_t paddr, short *pgcnt)
 878 {
 879         if (lv1ent_section(sent)) {
 880                 WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 881                         iova);
 882                 return -EADDRINUSE;
 883         }
 884
 885         if (lv1ent_page(sent)) {
 886                 if (*pgcnt != NUM_LV2ENTRIES) {
 887                         WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 888                                 iova);
 889                         return -EADDRINUSE;
 890                 }
 891
 892                 kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
 893                 *pgcnt = 0;
 894         }
 895
 896         update_pte(sent, mk_lv1ent_sect(paddr));
 897
 898         spin_lock(&domain->lock);
 899         if (lv1ent_page_zero(sent)) {
 900                 struct sysmmu_drvdata *data;
 901                 /*
 902                  * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD
 903                  * entry by speculative prefetch of SLPD which has no mapping.
 904                  */
 905                 list_for_each_entry(data, &domain->clients, domain_node)
 906                         sysmmu_tlb_invalidate_flpdcache(data, iova);
 907         }
 908         spin_unlock(&domain->lock);
 909
 910         return 0;
 911 }
 912
 913 static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size,
 914                                                                 short *pgcnt)
 915 {
 916         if (size == SPAGE_SIZE) {
 917                 if (WARN_ON(!lv2ent_fault(pent)))
 918                         return -EADDRINUSE;
 919
 920                 update_pte(pent, mk_lv2ent_spage(paddr));
 921                 *pgcnt -= 1;
 922         } else { /* size == LPAGE_SIZE */
 923                 int i;
 924                 dma_addr_t pent_base = virt_to_phys(pent);
 925
 926                 dma_sync_single_for_cpu(dma_dev, pent_base,
 927                                         sizeof(*pent) * SPAGES_PER_LPAGE,
 928                                         DMA_TO_DEVICE);
 929                 for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
 930                         if (WARN_ON(!lv2ent_fault(pent))) {
 931                                 if (i > 0)
 932                                         memset(pent - i, 0, sizeof(*pent) * i);
 933                                 return -EADDRINUSE;
 934                         }
 935
 936                         *pent = mk_lv2ent_lpage(paddr);
 937                 }
 938                 dma_sync_single_for_device(dma_dev, pent_base,
 939                                            sizeof(*pent) * SPAGES_PER_LPAGE,
 940                                            DMA_TO_DEVICE);
 941                 *pgcnt -= SPAGES_PER_LPAGE;
 942         }
 943
 944         return 0;
 945 }
 946
 947 /*
 948  * *CAUTION* to the I/O virtual memory managers that support exynos-iommu:
 949  *
 950  * System MMU v3.x has advanced logic to improve address translation
 951  * performance with caching more page table entries by a page table walk.
 952  * However, the logic has a bug that while caching faulty page table entries,
 953  * System MMU reports page fault if the cached fault entry is hit even though
 954  * the fault entry is updated to a valid entry after the entry is cached.
 955  * To prevent caching faulty page table entries which may be updated to valid
 956  * entries later, the virtual memory manager should care about the workaround
 957  * for the problem. The following describes the workaround.
 958  *
 959  * Any two consecutive I/O virtual address regions must have a hole of 128KiB
 960  * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug).
 961  *
 962  * Precisely, any start address of I/O virtual region must be aligned with
 963  * the following sizes for System MMU v3.1 and v3.2.
 964  * System MMU v3.1: 128KiB
 965  * System MMU v3.2: 256KiB
 966  *
 967  * Because System MMU v3.3 caches page table entries more aggressively, it needs
 968  * more workarounds.
 969  * - Any two consecutive I/O virtual regions must have a hole of size larger
 970  *   than or equal to 128KiB.
 971  * - Start address of an I/O virtual region must be aligned by 128KiB.
 972  */
 973 static int exynos_iommu_map(struct iommu_domain *iommu_domain,
 974                             unsigned long l_iova, phys_addr_t paddr, size_t size,
 975                             int prot)
 976 {
 977         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 978         sysmmu_pte_t *entry;
 979         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
 980         unsigned long flags;
 981         int ret = -ENOMEM;
 982
 983         BUG_ON(domain->pgtable == NULL);
 984
 985         spin_lock_irqsave(&domain->pgtablelock, flags);
 986
 987         entry = section_entry(domain->pgtable, iova);
 988
 989         if (size == SECT_SIZE) {
 990                 ret = lv1set_section(domain, entry, iova, paddr,
 991                                      &domain->lv2entcnt[lv1ent_offset(iova)]);
 992         } else {
 993                 sysmmu_pte_t *pent;
 994
 995                 pent = alloc_lv2entry(domain, entry, iova,
 996                                       &domain->lv2entcnt[lv1ent_offset(iova)]);
 997
 998                 if (IS_ERR(pent))
 999                         ret = PTR_ERR(pent);
1000                 else
1001                         ret = lv2set_page(pent, paddr, size,
1002                                        &domain->lv2entcnt[lv1ent_offset(iova)]);
1003         }
1004
1005         if (ret)
1006                 pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n",
1007                         __func__, ret, size, iova);
1008
1009         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1010
1011         return ret;
1012 }
1013
1014 static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain,
1015                                               sysmmu_iova_t iova, size_t size)
1016 {
1017         struct sysmmu_drvdata *data;
1018         unsigned long flags;
1019
1020         spin_lock_irqsave(&domain->lock, flags);
1021
1022         list_for_each_entry(data, &domain->clients, domain_node)
1023                 sysmmu_tlb_invalidate_entry(data, iova, size);
1024
1025         spin_unlock_irqrestore(&domain->lock, flags);
1026 }
1027
1028 static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain,
1029                                  unsigned long l_iova, size_t size)
1030 {
1031         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1032         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1033         sysmmu_pte_t *ent;
1034         size_t err_pgsize;
1035         unsigned long flags;
1036
1037         BUG_ON(domain->pgtable == NULL);
1038
1039         spin_lock_irqsave(&domain->pgtablelock, flags);
1040
1041         ent = section_entry(domain->pgtable, iova);
1042
1043         if (lv1ent_section(ent)) {
1044                 if (WARN_ON(size < SECT_SIZE)) {
1045                         err_pgsize = SECT_SIZE;
1046                         goto err;
1047                 }
1048
1049                 /* workaround for h/w bug in System MMU v3.3 */
1050                 update_pte(ent, ZERO_LV2LINK);
1051                 size = SECT_SIZE;
1052                 goto done;
1053         }
1054
1055         if (unlikely(lv1ent_fault(ent))) {
1056                 if (size > SECT_SIZE)
1057                         size = SECT_SIZE;
1058                 goto done;
1059         }
1060
1061         /* lv1ent_page(sent) == true here */
1062
1063         ent = page_entry(ent, iova);
1064
1065         if (unlikely(lv2ent_fault(ent))) {
1066                 size = SPAGE_SIZE;
1067                 goto done;
1068         }
1069
1070         if (lv2ent_small(ent)) {
1071                 update_pte(ent, 0);
1072                 size = SPAGE_SIZE;
1073                 domain->lv2entcnt[lv1ent_offset(iova)] += 1;
1074                 goto done;
1075         }
1076
1077         /* lv1ent_large(ent) == true here */
1078         if (WARN_ON(size < LPAGE_SIZE)) {
1079                 err_pgsize = LPAGE_SIZE;
1080                 goto err;
1081         }
1082
1083         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent),
1084                                 sizeof(*ent) * SPAGES_PER_LPAGE,
1085                                 DMA_TO_DEVICE);
1086         memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
1087         dma_sync_single_for_device(dma_dev, virt_to_phys(ent),
1088                                    sizeof(*ent) * SPAGES_PER_LPAGE,
1089                                    DMA_TO_DEVICE);
1090         size = LPAGE_SIZE;
1091         domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
1092 done:
1093         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1094
1095         exynos_iommu_tlb_invalidate_entry(domain, iova, size);
1096
1097         return size;
1098 err:
1099         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1100
1101         pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n",
1102                 __func__, size, iova, err_pgsize);
1103
1104         return 0;
1105 }
1106
1107 static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain,
1108                                           dma_addr_t iova)
1109 {
1110         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1111         sysmmu_pte_t *entry;
1112         unsigned long flags;
1113         phys_addr_t phys = 0;
1114
1115         spin_lock_irqsave(&domain->pgtablelock, flags);
1116
1117         entry = section_entry(domain->pgtable, iova);
1118
1119         if (lv1ent_section(entry)) {
1120                 phys = section_phys(entry) + section_offs(iova);
1121         } else if (lv1ent_page(entry)) {
1122                 entry = page_entry(entry, iova);
1123
1124                 if (lv2ent_large(entry))
1125                         phys = lpage_phys(entry) + lpage_offs(iova);
1126                 else if (lv2ent_small(entry))
1127                         phys = spage_phys(entry) + spage_offs(iova);
1128         }
1129
1130         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1131
1132         return phys;
1133 }
1134
1135 static struct iommu_group *get_device_iommu_group(struct device *dev)
1136 {
1137         struct iommu_group *group;
1138
1139         group = iommu_group_get(dev);
1140         if (!group)
1141                 group = iommu_group_alloc();
1142
1143         return group;
1144 }
1145
1146 static int exynos_iommu_add_device(struct device *dev)
1147 {
1148         struct iommu_group *group;
1149
1150         if (!has_sysmmu(dev))
1151                 return -ENODEV;
1152
1153         group = iommu_group_get_for_dev(dev);
1154
1155         if (IS_ERR(group))
1156                 return PTR_ERR(group);
1157
1158         iommu_group_put(group);
1159
1160         return 0;
1161 }
1162
1163 static void exynos_iommu_remove_device(struct device *dev)
1164 {
1165         if (!has_sysmmu(dev))
1166                 return;
1167
1168         iommu_group_remove_device(dev);
1169 }
1170
1171 static int exynos_iommu_of_xlate(struct device *dev,
1172                                  struct of_phandle_args *spec)
1173 {
1174         struct exynos_iommu_owner *owner = dev->archdata.iommu;
1175         struct platform_device *sysmmu = of_find_device_by_node(spec->np);
1176         struct sysmmu_drvdata *data;
1177
1178         if (!sysmmu)
1179                 return -ENODEV;
1180
1181         data = platform_get_drvdata(sysmmu);
1182         if (!data)
1183                 return -ENODEV;
1184
1185         if (!owner) {
1186                 owner = kzalloc(sizeof(*owner), GFP_KERNEL);
1187                 if (!owner)
1188                         return -ENOMEM;
1189
1190                 INIT_LIST_HEAD(&owner->controllers);
1191                 dev->archdata.iommu = owner;
1192         }
1193
1194         list_add_tail(&data->owner_node, &owner->controllers);
1195         return 0;
1196 }
1197
1198 static struct iommu_ops exynos_iommu_ops = {
1199         .domain_alloc = exynos_iommu_domain_alloc,
1200         .domain_free = exynos_iommu_domain_free,
1201         .attach_dev = exynos_iommu_attach_device,
1202         .detach_dev = exynos_iommu_detach_device,
1203         .map = exynos_iommu_map,
1204         .unmap = exynos_iommu_unmap,
1205         .map_sg = default_iommu_map_sg,
1206         .iova_to_phys = exynos_iommu_iova_to_phys,
1207         .device_group = get_device_iommu_group,
1208         .add_device = exynos_iommu_add_device,
1209         .remove_device = exynos_iommu_remove_device,
1210         .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
1211         .of_xlate = exynos_iommu_of_xlate,
1212 };
1213
1214 static bool init_done;
1215
1216 static int __init exynos_iommu_init(void)
1217 {
1218         int ret;
1219
1220         lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
1221                                 LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
1222         if (!lv2table_kmem_cache) {
1223                 pr_err("%s: Failed to create kmem cache\n", __func__);
1224                 return -ENOMEM;
1225         }
1226
1227         ret = platform_driver_register(&exynos_sysmmu_driver);
1228         if (ret) {
1229                 pr_err("%s: Failed to register driver\n", __func__);
1230                 goto err_reg_driver;
1231         }
1232
1233         zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL);
1234         if (zero_lv2_table == NULL) {
1235                 pr_err("%s: Failed to allocate zero level2 page table\n",
1236                         __func__);
1237                 ret = -ENOMEM;
1238                 goto err_zero_lv2;
1239         }
1240
1241         ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
1242         if (ret) {
1243                 pr_err("%s: Failed to register exynos-iommu driver.\n",
1244                                                                 __func__);
1245                 goto err_set_iommu;
1246         }
1247
1248         init_done = true;
1249
1250         return 0;
1251 err_set_iommu:
1252         kmem_cache_free(lv2table_kmem_cache, zero_lv2_table);
1253 err_zero_lv2:
1254         platform_driver_unregister(&exynos_sysmmu_driver);
1255 err_reg_driver:
1256         kmem_cache_destroy(lv2table_kmem_cache);
1257         return ret;
1258 }
1259
1260 static int __init exynos_iommu_of_setup(struct device_node *np)
1261 {
1262         struct platform_device *pdev;
1263
1264         if (!init_done)
1265                 exynos_iommu_init();
1266
1267         pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root);
1268         if (IS_ERR(pdev))
1269                 return PTR_ERR(pdev);
1270
1271         /*
1272          * use the first registered sysmmu device for performing
1273          * dma mapping operations on iommu page tables (cpu cache flush)
1274          */
1275         if (!dma_dev)
1276                 dma_dev = &pdev->dev;
1277
1278         of_iommu_set_ops(np, &exynos_iommu_ops);
1279         return 0;
1280 }
1281
1282 IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu",
1283                  exynos_iommu_of_setup);