drivers/iommu/exynos-iommu.c

   1 /* linux/drivers/iommu/exynos_iommu.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #ifdef CONFIG_EXYNOS_IOMMU_DEBUG
  12 #define DEBUG
  13 #endif
  14
  15 #include <linux/clk.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19 #include <linux/iommu.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/list.h>
  22 #include <linux/of.h>
  23 #include <linux/of_iommu.h>
  24 #include <linux/of_platform.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/slab.h>
  28 #include <linux/dma-iommu.h>
  29
  30 typedef u32 sysmmu_iova_t;
  31 typedef u32 sysmmu_pte_t;
  32
  33 /* We do not consider super section mapping (16MB) */
  34 #define SECT_ORDER 20
  35 #define LPAGE_ORDER 16
  36 #define SPAGE_ORDER 12
  37
  38 #define SECT_SIZE (1 << SECT_ORDER)
  39 #define LPAGE_SIZE (1 << LPAGE_ORDER)
  40 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  41
  42 #define SECT_MASK (~(SECT_SIZE - 1))
  43 #define LPAGE_MASK (~(LPAGE_SIZE - 1))
  44 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  45
  46 #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \
  47                            ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
  48 #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK)
  49 #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1)
  50 #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \
  51                           ((*(sent) & 3) == 1))
  52 #define lv1ent_section(sent) ((*(sent) & 3) == 2)
  53
  54 #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
  55 #define lv2ent_small(pent) ((*(pent) & 2) == 2)
  56 #define lv2ent_large(pent) ((*(pent) & 3) == 1)
  57
  58 static u32 sysmmu_page_offset(sysmmu_iova_t iova, u32 size)
  59 {
  60         return iova & (size - 1);
  61 }
  62
  63 #define section_phys(sent) (*(sent) & SECT_MASK)
  64 #define section_offs(iova) sysmmu_page_offset((iova), SECT_SIZE)
  65 #define lpage_phys(pent) (*(pent) & LPAGE_MASK)
  66 #define lpage_offs(iova) sysmmu_page_offset((iova), LPAGE_SIZE)
  67 #define spage_phys(pent) (*(pent) & SPAGE_MASK)
  68 #define spage_offs(iova) sysmmu_page_offset((iova), SPAGE_SIZE)
  69
  70 #define NUM_LV1ENTRIES 4096
  71 #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
  72
  73 static u32 lv1ent_offset(sysmmu_iova_t iova)
  74 {
  75         return iova >> SECT_ORDER;
  76 }
  77
  78 static u32 lv2ent_offset(sysmmu_iova_t iova)
  79 {
  80         return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1);
  81 }
  82
  83 #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t))
  84 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
  85
  86 #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
  87
  88 #define lv2table_base(sent) (*(sent) & 0xFFFFFC00)
  89
  90 #define mk_lv1ent_sect(pa) ((pa) | 2)
  91 #define mk_lv1ent_page(pa) ((pa) | 1)
  92 #define mk_lv2ent_lpage(pa) ((pa) | 1)
  93 #define mk_lv2ent_spage(pa) ((pa) | 2)
  94
  95 #define CTRL_ENABLE     0x5
  96 #define CTRL_BLOCK      0x7
  97 #define CTRL_DISABLE    0x0
  98
  99 #define CFG_LRU         0x1
 100 #define CFG_QOS(n)      ((n & 0xF) << 7)
 101 #define CFG_MASK        0x0150FFFF /* Selecting bit 0-15, 20, 22 and 24 */
 102 #define CFG_ACGEN       (1 << 24) /* System MMU 3.3 only */
 103 #define CFG_SYSSEL      (1 << 22) /* System MMU 3.2 only */
 104 #define CFG_FLPDCACHE   (1 << 20) /* System MMU 3.2+ only */
 105
 106 #define REG_MMU_CTRL            0x000
 107 #define REG_MMU_CFG             0x004
 108 #define REG_MMU_STATUS          0x008
 109 #define REG_MMU_FLUSH           0x00C
 110 #define REG_MMU_FLUSH_ENTRY     0x010
 111 #define REG_PT_BASE_ADDR        0x014
 112 #define REG_INT_STATUS          0x018
 113 #define REG_INT_CLEAR           0x01C
 114
 115 #define REG_PAGE_FAULT_ADDR     0x024
 116 #define REG_AW_FAULT_ADDR       0x028
 117 #define REG_AR_FAULT_ADDR       0x02C
 118 #define REG_DEFAULT_SLAVE_ADDR  0x030
 119
 120 #define REG_MMU_VERSION         0x034
 121
 122 #define MMU_MAJ_VER(val)        ((val) >> 7)
 123 #define MMU_MIN_VER(val)        ((val) & 0x7F)
 124 #define MMU_RAW_VER(reg)        (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */
 125
 126 #define MAKE_MMU_VER(maj, min)  ((((maj) & 0xF) << 7) | ((min) & 0x7F))
 127
 128 #define REG_PB0_SADDR           0x04C
 129 #define REG_PB0_EADDR           0x050
 130 #define REG_PB1_SADDR           0x054
 131 #define REG_PB1_EADDR           0x058
 132
 133 #define has_sysmmu(dev)         (dev->archdata.iommu != NULL)
 134
 135 static struct device *dma_dev;
 136 static struct kmem_cache *lv2table_kmem_cache;
 137 static sysmmu_pte_t *zero_lv2_table;
 138 #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table))
 139
 140 static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova)
 141 {
 142         return pgtable + lv1ent_offset(iova);
 143 }
 144
 145 static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
 146 {
 147         return (sysmmu_pte_t *)phys_to_virt(
 148                                 lv2table_base(sent)) + lv2ent_offset(iova);
 149 }
 150
 151 /*
 152  * IOMMU fault information register
 153  */
 154 struct sysmmu_fault_info {
 155         unsigned int bit;       /* bit number in STATUS register */
 156         unsigned short addr_reg; /* register to read VA fault address */
 157         const char *name;       /* human readable fault name */
 158         unsigned int type;      /* fault type for report_iommu_fault */
 159 };
 160
 161 static const struct sysmmu_fault_info sysmmu_faults[] = {
 162         { 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ },
 163         { 1, REG_AR_FAULT_ADDR, "AR MULTI-HIT", IOMMU_FAULT_READ },
 164         { 2, REG_AW_FAULT_ADDR, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
 165         { 3, REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ },
 166         { 4, REG_AR_FAULT_ADDR, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
 167         { 5, REG_AR_FAULT_ADDR, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
 168         { 6, REG_AW_FAULT_ADDR, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
 169         { 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
 170 };
 171
 172 /*
 173  * This structure is attached to dev.archdata.iommu of the master device
 174  * on device add, contains a list of SYSMMU controllers defined by device tree,
 175  * which are bound to given master device. It is usually referenced by 'owner'
 176  * pointer.
 177 */
 178 struct exynos_iommu_owner {
 179         struct list_head controllers;   /* list of sysmmu_drvdata.owner_node */
 180 };
 181
 182 /*
 183  * This structure exynos specific generalization of struct iommu_domain.
 184  * It contains list of SYSMMU controllers from all master devices, which has
 185  * been attached to this domain and page tables of IO address space defined by
 186  * it. It is usually referenced by 'domain' pointer.
 187  */
 188 struct exynos_iommu_domain {
 189         struct list_head clients; /* list of sysmmu_drvdata.domain_node */
 190         sysmmu_pte_t *pgtable;  /* lv1 page table, 16KB */
 191         short *lv2entcnt;       /* free lv2 entry counter for each section */
 192         spinlock_t lock;        /* lock for modyfying list of clients */
 193         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 194         struct iommu_domain domain; /* generic domain data structure */
 195 };
 196
 197 /*
 198  * This structure hold all data of a single SYSMMU controller, this includes
 199  * hw resources like registers and clocks, pointers and list nodes to connect
 200  * it to all other structures, internal state and parameters read from device
 201  * tree. It is usually referenced by 'data' pointer.
 202  */
 203 struct sysmmu_drvdata {
 204         struct device *sysmmu;          /* SYSMMU controller device */
 205         struct device *master;          /* master device (owner) */
 206         void __iomem *sfrbase;          /* our registers */
 207         struct clk *clk;                /* SYSMMU's clock */
 208         struct clk *clk_master;         /* master's device clock */
 209         int activations;                /* number of calls to sysmmu_enable */
 210         spinlock_t lock;                /* lock for modyfying state */
 211         struct exynos_iommu_domain *domain; /* domain we belong to */
 212         struct list_head domain_node;   /* node for domain clients list */
 213         struct list_head owner_node;    /* node for owner controllers list */
 214         phys_addr_t pgtable;            /* assigned page table structure */
 215         unsigned int version;           /* our version */
 216 };
 217
 218 static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom)
 219 {
 220         return container_of(dom, struct exynos_iommu_domain, domain);
 221 }
 222
 223 static bool set_sysmmu_active(struct sysmmu_drvdata *data)
 224 {
 225         /* return true if the System MMU was not active previously
 226            and it needs to be initialized */
 227         return ++data->activations == 1;
 228 }
 229
 230 static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
 231 {
 232         /* return true if the System MMU is needed to be disabled */
 233         BUG_ON(data->activations < 1);
 234         return --data->activations == 0;
 235 }
 236
 237 static bool is_sysmmu_active(struct sysmmu_drvdata *data)
 238 {
 239         return data->activations > 0;
 240 }
 241
 242 static void sysmmu_unblock(struct sysmmu_drvdata *data)
 243 {
 244         __raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 245 }
 246
 247 static bool sysmmu_block(struct sysmmu_drvdata *data)
 248 {
 249         int i = 120;
 250
 251         __raw_writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 252         while ((i > 0) && !(__raw_readl(data->sfrbase + REG_MMU_STATUS) & 1))
 253                 --i;
 254
 255         if (!(__raw_readl(data->sfrbase + REG_MMU_STATUS) & 1)) {
 256                 sysmmu_unblock(data);
 257                 return false;
 258         }
 259
 260         return true;
 261 }
 262
 263 static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data)
 264 {
 265         __raw_writel(0x1, data->sfrbase + REG_MMU_FLUSH);
 266 }
 267
 268 static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 269                                 sysmmu_iova_t iova, unsigned int num_inv)
 270 {
 271         unsigned int i;
 272
 273         for (i = 0; i < num_inv; i++) {
 274                 __raw_writel((iova & SPAGE_MASK) | 1,
 275                                 data->sfrbase + REG_MMU_FLUSH_ENTRY);
 276                 iova += SPAGE_SIZE;
 277         }
 278 }
 279
 280 static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd)
 281 {
 282         __raw_writel(pgd, data->sfrbase + REG_PT_BASE_ADDR);
 283
 284         __sysmmu_tlb_invalidate(data);
 285 }
 286
 287 static void show_fault_information(struct sysmmu_drvdata *data,
 288                                    const struct sysmmu_fault_info *finfo,
 289                                    sysmmu_iova_t fault_addr)
 290 {
 291         sysmmu_pte_t *ent;
 292
 293         dev_err(data->sysmmu, "%s FAULT occurred at %#x (page table base: %pa)\n",
 294                 finfo->name, fault_addr, &data->pgtable);
 295         ent = section_entry(phys_to_virt(data->pgtable), fault_addr);
 296         dev_err(data->sysmmu, "\tLv1 entry: %#x\n", *ent);
 297         if (lv1ent_page(ent)) {
 298                 ent = page_entry(ent, fault_addr);
 299                 dev_err(data->sysmmu, "\t Lv2 entry: %#x\n", *ent);
 300         }
 301 }
 302
 303 static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
 304 {
 305         /* SYSMMU is in blocked state when interrupt occurred. */
 306         struct sysmmu_drvdata *data = dev_id;
 307         const struct sysmmu_fault_info *finfo = sysmmu_faults;
 308         int i, n = ARRAY_SIZE(sysmmu_faults);
 309         unsigned int itype;
 310         sysmmu_iova_t fault_addr = -1;
 311         int ret = -ENOSYS;
 312
 313         WARN_ON(!is_sysmmu_active(data));
 314
 315         spin_lock(&data->lock);
 316
 317         clk_enable(data->clk_master);
 318
 319         itype = __ffs(__raw_readl(data->sfrbase + REG_INT_STATUS));
 320         for (i = 0; i < n; i++, finfo++)
 321                 if (finfo->bit == itype)
 322                         break;
 323         /* unknown/unsupported fault */
 324         BUG_ON(i == n);
 325
 326         /* print debug message */
 327         fault_addr = __raw_readl(data->sfrbase + finfo->addr_reg);
 328         show_fault_information(data, finfo, fault_addr);
 329
 330         if (data->domain)
 331                 ret = report_iommu_fault(&data->domain->domain,
 332                                         data->master, fault_addr, finfo->type);
 333         /* fault is not recovered by fault handler */
 334         BUG_ON(ret != 0);
 335
 336         __raw_writel(1 << itype, data->sfrbase + REG_INT_CLEAR);
 337
 338         sysmmu_unblock(data);
 339
 340         clk_disable(data->clk_master);
 341
 342         spin_unlock(&data->lock);
 343
 344         return IRQ_HANDLED;
 345 }
 346
 347 static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data)
 348 {
 349         clk_enable(data->clk_master);
 350
 351         __raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
 352         __raw_writel(0, data->sfrbase + REG_MMU_CFG);
 353
 354         clk_disable(data->clk);
 355         clk_disable(data->clk_master);
 356 }
 357
 358 static bool __sysmmu_disable(struct sysmmu_drvdata *data)
 359 {
 360         bool disabled;
 361         unsigned long flags;
 362
 363         spin_lock_irqsave(&data->lock, flags);
 364
 365         disabled = set_sysmmu_inactive(data);
 366
 367         if (disabled) {
 368                 data->pgtable = 0;
 369                 data->domain = NULL;
 370
 371                 __sysmmu_disable_nocount(data);
 372
 373                 dev_dbg(data->sysmmu, "Disabled\n");
 374         } else  {
 375                 dev_dbg(data->sysmmu, "%d times left to disable\n",
 376                                         data->activations);
 377         }
 378
 379         spin_unlock_irqrestore(&data->lock, flags);
 380
 381         return disabled;
 382 }
 383
 384 static void __sysmmu_init_config(struct sysmmu_drvdata *data)
 385 {
 386         unsigned int cfg = CFG_LRU | CFG_QOS(15);
 387         unsigned int ver;
 388
 389         ver = MMU_RAW_VER(__raw_readl(data->sfrbase + REG_MMU_VERSION));
 390         if (MMU_MAJ_VER(ver) == 3) {
 391                 if (MMU_MIN_VER(ver) >= 2) {
 392                         cfg |= CFG_FLPDCACHE;
 393                         if (MMU_MIN_VER(ver) == 3) {
 394                                 cfg |= CFG_ACGEN;
 395                                 cfg &= ~CFG_LRU;
 396                         } else {
 397                                 cfg |= CFG_SYSSEL;
 398                         }
 399                 }
 400         }
 401
 402         __raw_writel(cfg, data->sfrbase + REG_MMU_CFG);
 403         data->version = ver;
 404 }
 405
 406 static void __sysmmu_enable_nocount(struct sysmmu_drvdata *data)
 407 {
 408         clk_enable(data->clk_master);
 409         clk_enable(data->clk);
 410
 411         __raw_writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 412
 413         __sysmmu_init_config(data);
 414
 415         __sysmmu_set_ptbase(data, data->pgtable);
 416
 417         __raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 418
 419         clk_disable(data->clk_master);
 420 }
 421
 422 static int __sysmmu_enable(struct sysmmu_drvdata *data, phys_addr_t pgtable,
 423                            struct exynos_iommu_domain *domain)
 424 {
 425         int ret = 0;
 426         unsigned long flags;
 427
 428         spin_lock_irqsave(&data->lock, flags);
 429         if (set_sysmmu_active(data)) {
 430                 data->pgtable = pgtable;
 431                 data->domain = domain;
 432
 433                 __sysmmu_enable_nocount(data);
 434
 435                 dev_dbg(data->sysmmu, "Enabled\n");
 436         } else {
 437                 ret = (pgtable == data->pgtable) ? 1 : -EBUSY;
 438
 439                 dev_dbg(data->sysmmu, "already enabled\n");
 440         }
 441
 442         if (WARN_ON(ret < 0))
 443                 set_sysmmu_inactive(data); /* decrement count */
 444
 445         spin_unlock_irqrestore(&data->lock, flags);
 446
 447         return ret;
 448 }
 449
 450 static void __sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
 451                                               sysmmu_iova_t iova)
 452 {
 453         if (data->version == MAKE_MMU_VER(3, 3))
 454                 __raw_writel(iova | 0x1, data->sfrbase + REG_MMU_FLUSH_ENTRY);
 455 }
 456
 457 static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
 458                                             sysmmu_iova_t iova)
 459 {
 460         unsigned long flags;
 461
 462         clk_enable(data->clk_master);
 463
 464         spin_lock_irqsave(&data->lock, flags);
 465         if (is_sysmmu_active(data))
 466                 __sysmmu_tlb_invalidate_flpdcache(data, iova);
 467         spin_unlock_irqrestore(&data->lock, flags);
 468
 469         clk_disable(data->clk_master);
 470 }
 471
 472 static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 473                                         sysmmu_iova_t iova, size_t size)
 474 {
 475         unsigned long flags;
 476
 477         spin_lock_irqsave(&data->lock, flags);
 478         if (is_sysmmu_active(data)) {
 479                 unsigned int num_inv = 1;
 480
 481                 clk_enable(data->clk_master);
 482
 483                 /*
 484                  * L2TLB invalidation required
 485                  * 4KB page: 1 invalidation
 486                  * 64KB page: 16 invalidations
 487                  * 1MB page: 64 invalidations
 488                  * because it is set-associative TLB
 489                  * with 8-way and 64 sets.
 490                  * 1MB page can be cached in one of all sets.
 491                  * 64KB page can be one of 16 consecutive sets.
 492                  */
 493                 if (MMU_MAJ_VER(data->version) == 2)
 494                         num_inv = min_t(unsigned int, size / PAGE_SIZE, 64);
 495
 496                 if (sysmmu_block(data)) {
 497                         __sysmmu_tlb_invalidate_entry(data, iova, num_inv);
 498                         sysmmu_unblock(data);
 499                 }
 500                 clk_disable(data->clk_master);
 501         } else {
 502                 dev_dbg(data->master,
 503                         "disabled. Skipping TLB invalidation @ %#x\n", iova);
 504         }
 505         spin_unlock_irqrestore(&data->lock, flags);
 506 }
 507
 508 static int __init exynos_sysmmu_probe(struct platform_device *pdev)
 509 {
 510         int irq, ret;
 511         struct device *dev = &pdev->dev;
 512         struct sysmmu_drvdata *data;
 513         struct resource *res;
 514
 515         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 516         if (!data)
 517                 return -ENOMEM;
 518
 519         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 520         data->sfrbase = devm_ioremap_resource(dev, res);
 521         if (IS_ERR(data->sfrbase))
 522                 return PTR_ERR(data->sfrbase);
 523
 524         irq = platform_get_irq(pdev, 0);
 525         if (irq <= 0) {
 526                 dev_err(dev, "Unable to find IRQ resource\n");
 527                 return irq;
 528         }
 529
 530         ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,
 531                                 dev_name(dev), data);
 532         if (ret) {
 533                 dev_err(dev, "Unabled to register handler of irq %d\n", irq);
 534                 return ret;
 535         }
 536
 537         data->clk = devm_clk_get(dev, "sysmmu");
 538         if (IS_ERR(data->clk)) {
 539                 dev_err(dev, "Failed to get clock!\n");
 540                 return PTR_ERR(data->clk);
 541         } else  {
 542                 ret = clk_prepare(data->clk);
 543                 if (ret) {
 544                         dev_err(dev, "Failed to prepare clk\n");
 545                         return ret;
 546                 }
 547         }
 548
 549         data->clk_master = devm_clk_get(dev, "master");
 550         if (!IS_ERR(data->clk_master)) {
 551                 ret = clk_prepare(data->clk_master);
 552                 if (ret) {
 553                         clk_unprepare(data->clk);
 554                         dev_err(dev, "Failed to prepare master's clk\n");
 555                         return ret;
 556                 }
 557         } else {
 558                 data->clk_master = NULL;
 559         }
 560
 561         data->sysmmu = dev;
 562         spin_lock_init(&data->lock);
 563
 564         platform_set_drvdata(pdev, data);
 565
 566         pm_runtime_enable(dev);
 567
 568         return 0;
 569 }
 570
 571 #ifdef CONFIG_PM_SLEEP
 572 static int exynos_sysmmu_suspend(struct device *dev)
 573 {
 574         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 575
 576         dev_dbg(dev, "suspend\n");
 577         if (is_sysmmu_active(data)) {
 578                 __sysmmu_disable_nocount(data);
 579                 pm_runtime_put(dev);
 580         }
 581         return 0;
 582 }
 583
 584 static int exynos_sysmmu_resume(struct device *dev)
 585 {
 586         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 587
 588         dev_dbg(dev, "resume\n");
 589         if (is_sysmmu_active(data)) {
 590                 pm_runtime_get_sync(dev);
 591                 __sysmmu_enable_nocount(data);
 592         }
 593         return 0;
 594 }
 595 #endif
 596
 597 static const struct dev_pm_ops sysmmu_pm_ops = {
 598         SET_LATE_SYSTEM_SLEEP_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume)
 599 };
 600
 601 static const struct of_device_id sysmmu_of_match[] __initconst = {
 602         { .compatible   = "samsung,exynos-sysmmu", },
 603         { },
 604 };
 605
 606 static struct platform_driver exynos_sysmmu_driver __refdata = {
 607         .probe  = exynos_sysmmu_probe,
 608         .driver = {
 609                 .name           = "exynos-sysmmu",
 610                 .of_match_table = sysmmu_of_match,
 611                 .pm             = &sysmmu_pm_ops,
 612         }
 613 };
 614
 615 static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val)
 616 {
 617         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent),
 618                                 DMA_TO_DEVICE);
 619         *ent = val;
 620         dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent),
 621                                    DMA_TO_DEVICE);
 622 }
 623
 624 static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type)
 625 {
 626         struct exynos_iommu_domain *domain;
 627         dma_addr_t handle;
 628         int i;
 629
 630
 631         domain = kzalloc(sizeof(*domain), GFP_KERNEL);
 632         if (!domain)
 633                 return NULL;
 634
 635         if (type == IOMMU_DOMAIN_DMA) {
 636                 if (iommu_get_dma_cookie(&domain->domain) != 0)
 637                         goto err_pgtable;
 638         } else if (type != IOMMU_DOMAIN_UNMANAGED) {
 639                 goto err_pgtable;
 640         }
 641
 642         domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2);
 643         if (!domain->pgtable)
 644                 goto err_dma_cookie;
 645
 646         domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1);
 647         if (!domain->lv2entcnt)
 648                 goto err_counter;
 649
 650         /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */
 651         for (i = 0; i < NUM_LV1ENTRIES; i += 8) {
 652                 domain->pgtable[i + 0] = ZERO_LV2LINK;
 653                 domain->pgtable[i + 1] = ZERO_LV2LINK;
 654                 domain->pgtable[i + 2] = ZERO_LV2LINK;
 655                 domain->pgtable[i + 3] = ZERO_LV2LINK;
 656                 domain->pgtable[i + 4] = ZERO_LV2LINK;
 657                 domain->pgtable[i + 5] = ZERO_LV2LINK;
 658                 domain->pgtable[i + 6] = ZERO_LV2LINK;
 659                 domain->pgtable[i + 7] = ZERO_LV2LINK;
 660         }
 661
 662         handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE,
 663                                 DMA_TO_DEVICE);
 664         /* For mapping page table entries we rely on dma == phys */
 665         BUG_ON(handle != virt_to_phys(domain->pgtable));
 666
 667         spin_lock_init(&domain->lock);
 668         spin_lock_init(&domain->pgtablelock);
 669         INIT_LIST_HEAD(&domain->clients);
 670
 671         domain->domain.geometry.aperture_start = 0;
 672         domain->domain.geometry.aperture_end   = ~0UL;
 673         domain->domain.geometry.force_aperture = true;
 674
 675         return &domain->domain;
 676
 677 err_counter:
 678         free_pages((unsigned long)domain->pgtable, 2);
 679 err_dma_cookie:
 680         if (type == IOMMU_DOMAIN_DMA)
 681                 iommu_put_dma_cookie(&domain->domain);
 682 err_pgtable:
 683         kfree(domain);
 684         return NULL;
 685 }
 686
 687 static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain)
 688 {
 689         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 690         struct sysmmu_drvdata *data, *next;
 691         unsigned long flags;
 692         int i;
 693
 694         WARN_ON(!list_empty(&domain->clients));
 695
 696         spin_lock_irqsave(&domain->lock, flags);
 697
 698         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 699                 if (__sysmmu_disable(data))
 700                         data->master = NULL;
 701                 list_del_init(&data->domain_node);
 702         }
 703
 704         spin_unlock_irqrestore(&domain->lock, flags);
 705
 706         if (iommu_domain->type == IOMMU_DOMAIN_DMA)
 707                 iommu_put_dma_cookie(iommu_domain);
 708
 709         dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE,
 710                          DMA_TO_DEVICE);
 711
 712         for (i = 0; i < NUM_LV1ENTRIES; i++)
 713                 if (lv1ent_page(domain->pgtable + i)) {
 714                         phys_addr_t base = lv2table_base(domain->pgtable + i);
 715
 716                         dma_unmap_single(dma_dev, base, LV2TABLE_SIZE,
 717                                          DMA_TO_DEVICE);
 718                         kmem_cache_free(lv2table_kmem_cache,
 719                                         phys_to_virt(base));
 720                 }
 721
 722         free_pages((unsigned long)domain->pgtable, 2);
 723         free_pages((unsigned long)domain->lv2entcnt, 1);
 724         kfree(domain);
 725 }
 726
 727 static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain,
 728                                    struct device *dev)
 729 {
 730         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 731         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 732         struct sysmmu_drvdata *data;
 733         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 734         unsigned long flags;
 735         int ret = -ENODEV;
 736
 737         if (!has_sysmmu(dev))
 738                 return -ENODEV;
 739
 740         list_for_each_entry(data, &owner->controllers, owner_node) {
 741                 pm_runtime_get_sync(data->sysmmu);
 742                 ret = __sysmmu_enable(data, pagetable, domain);
 743                 if (ret >= 0) {
 744                         data->master = dev;
 745
 746                         spin_lock_irqsave(&domain->lock, flags);
 747                         list_add_tail(&data->domain_node, &domain->clients);
 748                         spin_unlock_irqrestore(&domain->lock, flags);
 749                 }
 750         }
 751
 752         if (ret < 0) {
 753                 dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n",
 754                                         __func__, &pagetable);
 755                 return ret;
 756         }
 757
 758         dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n",
 759                 __func__, &pagetable, (ret == 0) ? "" : ", again");
 760
 761         return ret;
 762 }
 763
 764 static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain,
 765                                     struct device *dev)
 766 {
 767         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 768         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 769         struct sysmmu_drvdata *data, *next;
 770         unsigned long flags;
 771         bool found = false;
 772
 773         if (!has_sysmmu(dev))
 774                 return;
 775
 776         spin_lock_irqsave(&domain->lock, flags);
 777         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 778                 if (data->master == dev) {
 779                         if (__sysmmu_disable(data)) {
 780                                 data->master = NULL;
 781                                 list_del_init(&data->domain_node);
 782                         }
 783                         pm_runtime_put(data->sysmmu);
 784                         found = true;
 785                 }
 786         }
 787         spin_unlock_irqrestore(&domain->lock, flags);
 788
 789         if (found)
 790                 dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n",
 791                                         __func__, &pagetable);
 792         else
 793                 dev_err(dev, "%s: No IOMMU is attached\n", __func__);
 794 }
 795
 796 static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain,
 797                 sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter)
 798 {
 799         if (lv1ent_section(sent)) {
 800                 WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova);
 801                 return ERR_PTR(-EADDRINUSE);
 802         }
 803
 804         if (lv1ent_fault(sent)) {
 805                 sysmmu_pte_t *pent;
 806                 bool need_flush_flpd_cache = lv1ent_zero(sent);
 807
 808                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 809                 BUG_ON((unsigned int)pent & (LV2TABLE_SIZE - 1));
 810                 if (!pent)
 811                         return ERR_PTR(-ENOMEM);
 812
 813                 update_pte(sent, mk_lv1ent_page(virt_to_phys(pent)));
 814                 kmemleak_ignore(pent);
 815                 *pgcounter = NUM_LV2ENTRIES;
 816                 dma_map_single(dma_dev, pent, LV2TABLE_SIZE, DMA_TO_DEVICE);
 817
 818                 /*
 819                  * If pre-fetched SLPD is a faulty SLPD in zero_l2_table,
 820                  * FLPD cache may cache the address of zero_l2_table. This
 821                  * function replaces the zero_l2_table with new L2 page table
 822                  * to write valid mappings.
 823                  * Accessing the valid area may cause page fault since FLPD
 824                  * cache may still cache zero_l2_table for the valid area
 825                  * instead of new L2 page table that has the mapping
 826                  * information of the valid area.
 827                  * Thus any replacement of zero_l2_table with other valid L2
 828                  * page table must involve FLPD cache invalidation for System
 829                  * MMU v3.3.
 830                  * FLPD cache invalidation is performed with TLB invalidation
 831                  * by VPN without blocking. It is safe to invalidate TLB without
 832                  * blocking because the target address of TLB invalidation is
 833                  * not currently mapped.
 834                  */
 835                 if (need_flush_flpd_cache) {
 836                         struct sysmmu_drvdata *data;
 837
 838                         spin_lock(&domain->lock);
 839                         list_for_each_entry(data, &domain->clients, domain_node)
 840                                 sysmmu_tlb_invalidate_flpdcache(data, iova);
 841                         spin_unlock(&domain->lock);
 842                 }
 843         }
 844
 845         return page_entry(sent, iova);
 846 }
 847
 848 static int lv1set_section(struct exynos_iommu_domain *domain,
 849                           sysmmu_pte_t *sent, sysmmu_iova_t iova,
 850                           phys_addr_t paddr, short *pgcnt)
 851 {
 852         if (lv1ent_section(sent)) {
 853                 WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 854                         iova);
 855                 return -EADDRINUSE;
 856         }
 857
 858         if (lv1ent_page(sent)) {
 859                 if (*pgcnt != NUM_LV2ENTRIES) {
 860                         WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 861                                 iova);
 862                         return -EADDRINUSE;
 863                 }
 864
 865                 kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
 866                 *pgcnt = 0;
 867         }
 868
 869         update_pte(sent, mk_lv1ent_sect(paddr));
 870
 871         spin_lock(&domain->lock);
 872         if (lv1ent_page_zero(sent)) {
 873                 struct sysmmu_drvdata *data;
 874                 /*
 875                  * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD
 876                  * entry by speculative prefetch of SLPD which has no mapping.
 877                  */
 878                 list_for_each_entry(data, &domain->clients, domain_node)
 879                         sysmmu_tlb_invalidate_flpdcache(data, iova);
 880         }
 881         spin_unlock(&domain->lock);
 882
 883         return 0;
 884 }
 885
 886 static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size,
 887                                                                 short *pgcnt)
 888 {
 889         if (size == SPAGE_SIZE) {
 890                 if (WARN_ON(!lv2ent_fault(pent)))
 891                         return -EADDRINUSE;
 892
 893                 update_pte(pent, mk_lv2ent_spage(paddr));
 894                 *pgcnt -= 1;
 895         } else { /* size == LPAGE_SIZE */
 896                 int i;
 897                 dma_addr_t pent_base = virt_to_phys(pent);
 898
 899                 dma_sync_single_for_cpu(dma_dev, pent_base,
 900                                         sizeof(*pent) * SPAGES_PER_LPAGE,
 901                                         DMA_TO_DEVICE);
 902                 for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
 903                         if (WARN_ON(!lv2ent_fault(pent))) {
 904                                 if (i > 0)
 905                                         memset(pent - i, 0, sizeof(*pent) * i);
 906                                 return -EADDRINUSE;
 907                         }
 908
 909                         *pent = mk_lv2ent_lpage(paddr);
 910                 }
 911                 dma_sync_single_for_device(dma_dev, pent_base,
 912                                            sizeof(*pent) * SPAGES_PER_LPAGE,
 913                                            DMA_TO_DEVICE);
 914                 *pgcnt -= SPAGES_PER_LPAGE;
 915         }
 916
 917         return 0;
 918 }
 919
 920 /*
 921  * *CAUTION* to the I/O virtual memory managers that support exynos-iommu:
 922  *
 923  * System MMU v3.x has advanced logic to improve address translation
 924  * performance with caching more page table entries by a page table walk.
 925  * However, the logic has a bug that while caching faulty page table entries,
 926  * System MMU reports page fault if the cached fault entry is hit even though
 927  * the fault entry is updated to a valid entry after the entry is cached.
 928  * To prevent caching faulty page table entries which may be updated to valid
 929  * entries later, the virtual memory manager should care about the workaround
 930  * for the problem. The following describes the workaround.
 931  *
 932  * Any two consecutive I/O virtual address regions must have a hole of 128KiB
 933  * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug).
 934  *
 935  * Precisely, any start address of I/O virtual region must be aligned with
 936  * the following sizes for System MMU v3.1 and v3.2.
 937  * System MMU v3.1: 128KiB
 938  * System MMU v3.2: 256KiB
 939  *
 940  * Because System MMU v3.3 caches page table entries more aggressively, it needs
 941  * more workarounds.
 942  * - Any two consecutive I/O virtual regions must have a hole of size larger
 943  *   than or equal to 128KiB.
 944  * - Start address of an I/O virtual region must be aligned by 128KiB.
 945  */
 946 static int exynos_iommu_map(struct iommu_domain *iommu_domain,
 947                             unsigned long l_iova, phys_addr_t paddr, size_t size,
 948                             int prot)
 949 {
 950         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 951         sysmmu_pte_t *entry;
 952         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
 953         unsigned long flags;
 954         int ret = -ENOMEM;
 955
 956         BUG_ON(domain->pgtable == NULL);
 957
 958         spin_lock_irqsave(&domain->pgtablelock, flags);
 959
 960         entry = section_entry(domain->pgtable, iova);
 961
 962         if (size == SECT_SIZE) {
 963                 ret = lv1set_section(domain, entry, iova, paddr,
 964                                      &domain->lv2entcnt[lv1ent_offset(iova)]);
 965         } else {
 966                 sysmmu_pte_t *pent;
 967
 968                 pent = alloc_lv2entry(domain, entry, iova,
 969                                       &domain->lv2entcnt[lv1ent_offset(iova)]);
 970
 971                 if (IS_ERR(pent))
 972                         ret = PTR_ERR(pent);
 973                 else
 974                         ret = lv2set_page(pent, paddr, size,
 975                                        &domain->lv2entcnt[lv1ent_offset(iova)]);
 976         }
 977
 978         if (ret)
 979                 pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n",
 980                         __func__, ret, size, iova);
 981
 982         spin_unlock_irqrestore(&domain->pgtablelock, flags);
 983
 984         return ret;
 985 }
 986
 987 static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain,
 988                                               sysmmu_iova_t iova, size_t size)
 989 {
 990         struct sysmmu_drvdata *data;
 991         unsigned long flags;
 992
 993         spin_lock_irqsave(&domain->lock, flags);
 994
 995         list_for_each_entry(data, &domain->clients, domain_node)
 996                 sysmmu_tlb_invalidate_entry(data, iova, size);
 997
 998         spin_unlock_irqrestore(&domain->lock, flags);
 999 }
1000
1001 static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain,
1002                                  unsigned long l_iova, size_t size)
1003 {
1004         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1005         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1006         sysmmu_pte_t *ent;
1007         size_t err_pgsize;
1008         unsigned long flags;
1009
1010         BUG_ON(domain->pgtable == NULL);
1011
1012         spin_lock_irqsave(&domain->pgtablelock, flags);
1013
1014         ent = section_entry(domain->pgtable, iova);
1015
1016         if (lv1ent_section(ent)) {
1017                 if (WARN_ON(size < SECT_SIZE)) {
1018                         err_pgsize = SECT_SIZE;
1019                         goto err;
1020                 }
1021
1022                 /* workaround for h/w bug in System MMU v3.3 */
1023                 update_pte(ent, ZERO_LV2LINK);
1024                 size = SECT_SIZE;
1025                 goto done;
1026         }
1027
1028         if (unlikely(lv1ent_fault(ent))) {
1029                 if (size > SECT_SIZE)
1030                         size = SECT_SIZE;
1031                 goto done;
1032         }
1033
1034         /* lv1ent_page(sent) == true here */
1035
1036         ent = page_entry(ent, iova);
1037
1038         if (unlikely(lv2ent_fault(ent))) {
1039                 size = SPAGE_SIZE;
1040                 goto done;
1041         }
1042
1043         if (lv2ent_small(ent)) {
1044                 update_pte(ent, 0);
1045                 size = SPAGE_SIZE;
1046                 domain->lv2entcnt[lv1ent_offset(iova)] += 1;
1047                 goto done;
1048         }
1049
1050         /* lv1ent_large(ent) == true here */
1051         if (WARN_ON(size < LPAGE_SIZE)) {
1052                 err_pgsize = LPAGE_SIZE;
1053                 goto err;
1054         }
1055
1056         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent),
1057                                 sizeof(*ent) * SPAGES_PER_LPAGE,
1058                                 DMA_TO_DEVICE);
1059         memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
1060         dma_sync_single_for_device(dma_dev, virt_to_phys(ent),
1061                                    sizeof(*ent) * SPAGES_PER_LPAGE,
1062                                    DMA_TO_DEVICE);
1063         size = LPAGE_SIZE;
1064         domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
1065 done:
1066         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1067
1068         exynos_iommu_tlb_invalidate_entry(domain, iova, size);
1069
1070         return size;
1071 err:
1072         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1073
1074         pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n",
1075                 __func__, size, iova, err_pgsize);
1076
1077         return 0;
1078 }
1079
1080 static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain,
1081                                           dma_addr_t iova)
1082 {
1083         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1084         sysmmu_pte_t *entry;
1085         unsigned long flags;
1086         phys_addr_t phys = 0;
1087
1088         spin_lock_irqsave(&domain->pgtablelock, flags);
1089
1090         entry = section_entry(domain->pgtable, iova);
1091
1092         if (lv1ent_section(entry)) {
1093                 phys = section_phys(entry) + section_offs(iova);
1094         } else if (lv1ent_page(entry)) {
1095                 entry = page_entry(entry, iova);
1096
1097                 if (lv2ent_large(entry))
1098                         phys = lpage_phys(entry) + lpage_offs(iova);
1099                 else if (lv2ent_small(entry))
1100                         phys = spage_phys(entry) + spage_offs(iova);
1101         }
1102
1103         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1104
1105         return phys;
1106 }
1107
1108 static struct iommu_group *get_device_iommu_group(struct device *dev)
1109 {
1110         struct iommu_group *group;
1111
1112         group = iommu_group_get(dev);
1113         if (!group)
1114                 group = iommu_group_alloc();
1115
1116         return group;
1117 }
1118
1119 static int exynos_iommu_add_device(struct device *dev)
1120 {
1121         struct iommu_group *group;
1122
1123         if (!has_sysmmu(dev))
1124                 return -ENODEV;
1125
1126         group = iommu_group_get_for_dev(dev);
1127
1128         if (IS_ERR(group))
1129                 return PTR_ERR(group);
1130
1131         iommu_group_put(group);
1132
1133         return 0;
1134 }
1135
1136 static void exynos_iommu_remove_device(struct device *dev)
1137 {
1138         if (!has_sysmmu(dev))
1139                 return;
1140
1141         iommu_group_remove_device(dev);
1142 }
1143
1144 static int exynos_iommu_of_xlate(struct device *dev,
1145                                  struct of_phandle_args *spec)
1146 {
1147         struct exynos_iommu_owner *owner = dev->archdata.iommu;
1148         struct platform_device *sysmmu = of_find_device_by_node(spec->np);
1149         struct sysmmu_drvdata *data;
1150
1151         if (!sysmmu)
1152                 return -ENODEV;
1153
1154         data = platform_get_drvdata(sysmmu);
1155         if (!data)
1156                 return -ENODEV;
1157
1158         if (!owner) {
1159                 owner = kzalloc(sizeof(*owner), GFP_KERNEL);
1160                 if (!owner)
1161                         return -ENOMEM;
1162
1163                 INIT_LIST_HEAD(&owner->controllers);
1164                 dev->archdata.iommu = owner;
1165         }
1166
1167         list_add_tail(&data->owner_node, &owner->controllers);
1168         return 0;
1169 }
1170
1171 static struct iommu_ops exynos_iommu_ops = {
1172         .domain_alloc = exynos_iommu_domain_alloc,
1173         .domain_free = exynos_iommu_domain_free,
1174         .attach_dev = exynos_iommu_attach_device,
1175         .detach_dev = exynos_iommu_detach_device,
1176         .map = exynos_iommu_map,
1177         .unmap = exynos_iommu_unmap,
1178         .map_sg = default_iommu_map_sg,
1179         .iova_to_phys = exynos_iommu_iova_to_phys,
1180         .device_group = get_device_iommu_group,
1181         .add_device = exynos_iommu_add_device,
1182         .remove_device = exynos_iommu_remove_device,
1183         .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
1184         .of_xlate = exynos_iommu_of_xlate,
1185 };
1186
1187 static bool init_done;
1188
1189 static int __init exynos_iommu_init(void)
1190 {
1191         int ret;
1192
1193         lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
1194                                 LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
1195         if (!lv2table_kmem_cache) {
1196                 pr_err("%s: Failed to create kmem cache\n", __func__);
1197                 return -ENOMEM;
1198         }
1199
1200         ret = platform_driver_register(&exynos_sysmmu_driver);
1201         if (ret) {
1202                 pr_err("%s: Failed to register driver\n", __func__);
1203                 goto err_reg_driver;
1204         }
1205
1206         zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL);
1207         if (zero_lv2_table == NULL) {
1208                 pr_err("%s: Failed to allocate zero level2 page table\n",
1209                         __func__);
1210                 ret = -ENOMEM;
1211                 goto err_zero_lv2;
1212         }
1213
1214         ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
1215         if (ret) {
1216                 pr_err("%s: Failed to register exynos-iommu driver.\n",
1217                                                                 __func__);
1218                 goto err_set_iommu;
1219         }
1220
1221         init_done = true;
1222
1223         return 0;
1224 err_set_iommu:
1225         kmem_cache_free(lv2table_kmem_cache, zero_lv2_table);
1226 err_zero_lv2:
1227         platform_driver_unregister(&exynos_sysmmu_driver);
1228 err_reg_driver:
1229         kmem_cache_destroy(lv2table_kmem_cache);
1230         return ret;
1231 }
1232
1233 static int __init exynos_iommu_of_setup(struct device_node *np)
1234 {
1235         struct platform_device *pdev;
1236
1237         if (!init_done)
1238                 exynos_iommu_init();
1239
1240         pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root);
1241         if (IS_ERR(pdev))
1242                 return PTR_ERR(pdev);
1243
1244         /*
1245          * use the first registered sysmmu device for performing
1246          * dma mapping operations on iommu page tables (cpu cache flush)
1247          */
1248         if (!dma_dev)
1249                 dma_dev = &pdev->dev;
1250
1251         of_iommu_set_ops(np, &exynos_iommu_ops);
1252         return 0;
1253 }
1254
1255 IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu",
1256                  exynos_iommu_of_setup);