2 * linux/arch/arm/mach-omap2/irq.c
4 * Interrupt handler for OMAP2 boards.
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
19 #include <asm/exception.h>
20 #include <linux/irqdomain.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
27 /* Define these here for now until we drop all board-files */
28 #define OMAP24XX_IC_BASE 0x480fe000
29 #define OMAP34XX_IC_BASE 0x48200000
31 /* selected INTC register offsets */
33 #define INTC_REVISION 0x0000
34 #define INTC_SYSCONFIG 0x0010
35 #define INTC_SYSSTATUS 0x0014
36 #define INTC_SIR 0x0040
37 #define INTC_CONTROL 0x0048
38 #define INTC_PROTECTION 0x004C
39 #define INTC_IDLE 0x0050
40 #define INTC_THRESHOLD 0x0068
41 #define INTC_MIR0 0x0084
42 #define INTC_MIR_CLEAR0 0x0088
43 #define INTC_MIR_SET0 0x008c
44 #define INTC_PENDING_IRQ0 0x0098
45 #define INTC_PENDING_IRQ1 0x00b8
46 #define INTC_PENDING_IRQ2 0x00d8
47 #define INTC_PENDING_IRQ3 0x00f8
48 #define INTC_ILR0 0x0100
50 #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
51 #define INTCPS_NR_ILR_REGS 128
52 #define INTCPS_NR_MIR_REGS 3
55 * OMAP2 has a number of different interrupt controllers, each interrupt
56 * controller is identified as its own "bank". Register definitions are
57 * fairly consistent for each bank, but not all registers are implemented
58 * for each bank.. when in doubt, consult the TRM.
61 /* Structure to save interrupt controller context */
62 struct omap_intc_regs {
67 u32 ilr[INTCPS_NR_ILR_REGS];
68 u32 mir[INTCPS_NR_MIR_REGS];
70 static struct omap_intc_regs intc_context;
72 static struct irq_domain *domain;
73 static void __iomem *omap_irq_base;
74 static int omap_nr_pending = 3;
75 static int omap_nr_irqs = 96;
77 /* INTC bank register get/set */
78 static void intc_writel(u32 reg, u32 val)
80 writel_relaxed(val, omap_irq_base + reg);
83 static u32 intc_readl(u32 reg)
85 return readl_relaxed(omap_irq_base + reg);
88 void omap_intc_save_context(void)
92 intc_context.sysconfig =
93 intc_readl(INTC_SYSCONFIG);
94 intc_context.protection =
95 intc_readl(INTC_PROTECTION);
97 intc_readl(INTC_IDLE);
98 intc_context.threshold =
99 intc_readl(INTC_THRESHOLD);
101 for (i = 0; i < omap_nr_irqs; i++)
102 intc_context.ilr[i] =
103 intc_readl((INTC_ILR0 + 0x4 * i));
104 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
105 intc_context.mir[i] =
106 intc_readl(INTC_MIR0 + (0x20 * i));
109 void omap_intc_restore_context(void)
113 intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
114 intc_writel(INTC_PROTECTION, intc_context.protection);
115 intc_writel(INTC_IDLE, intc_context.idle);
116 intc_writel(INTC_THRESHOLD, intc_context.threshold);
118 for (i = 0; i < omap_nr_irqs; i++)
119 intc_writel(INTC_ILR0 + 0x4 * i,
120 intc_context.ilr[i]);
122 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
123 intc_writel(INTC_MIR0 + 0x20 * i,
124 intc_context.mir[i]);
125 /* MIRs are saved and restore with other PRCM registers */
128 void omap3_intc_prepare_idle(void)
131 * Disable autoidle as it can stall interrupt controller,
132 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
134 intc_writel(INTC_SYSCONFIG, 0);
137 void omap3_intc_resume_idle(void)
139 /* Re-enable autoidle */
140 intc_writel(INTC_SYSCONFIG, 1);
143 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
144 static void omap_ack_irq(struct irq_data *d)
146 intc_writel(INTC_CONTROL, 0x1);
149 static void omap_mask_ack_irq(struct irq_data *d)
151 irq_gc_mask_disable_reg(d);
155 static void __init omap_irq_soft_reset(void)
159 tmp = intc_readl(INTC_REVISION) & 0xff;
161 pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
162 omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs);
164 tmp = intc_readl(INTC_SYSCONFIG);
165 tmp |= 1 << 1; /* soft reset */
166 intc_writel(INTC_SYSCONFIG, tmp);
168 while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
169 /* Wait for reset to complete */;
171 /* Enable autoidle */
172 intc_writel(INTC_SYSCONFIG, 1 << 0);
175 int omap_irq_pending(void)
179 for (i = 0; i < omap_nr_pending; i++)
180 if (intc_readl(INTC_PENDING_IRQ0 + (0x20 * i)))
185 void omap3_intc_suspend(void)
187 /* A pending interrupt would prevent OMAP from entering suspend */
191 static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base)
196 ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC",
197 handle_level_irq, IRQ_NOREQUEST | IRQ_NOPROBE,
200 pr_warn("Failed to allocate irq chips\n");
204 for (i = 0; i < omap_nr_pending; i++) {
205 struct irq_chip_generic *gc;
206 struct irq_chip_type *ct;
208 gc = irq_get_domain_generic_chip(d, 32 * i);
212 ct->type = IRQ_TYPE_LEVEL_MASK;
213 ct->handler = handle_level_irq;
215 ct->chip.irq_ack = omap_mask_ack_irq;
216 ct->chip.irq_mask = irq_gc_mask_disable_reg;
217 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
219 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
221 ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i;
222 ct->regs.disable = INTC_MIR_SET0 + 32 * i;
228 static void __init omap_alloc_gc_legacy(void __iomem *base,
229 unsigned int irq_start, unsigned int num)
231 struct irq_chip_generic *gc;
232 struct irq_chip_type *ct;
234 gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
237 ct->chip.irq_ack = omap_mask_ack_irq;
238 ct->chip.irq_mask = irq_gc_mask_disable_reg;
239 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
240 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
242 ct->regs.enable = INTC_MIR_CLEAR0;
243 ct->regs.disable = INTC_MIR_SET0;
244 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
245 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
248 static int __init omap_init_irq_of(struct device_node *node)
252 omap_irq_base = of_iomap(node, 0);
253 if (WARN_ON(!omap_irq_base))
256 domain = irq_domain_add_linear(node, omap_nr_irqs,
257 &irq_generic_chip_ops, NULL);
259 omap_irq_soft_reset();
261 ret = omap_alloc_gc_of(domain, omap_irq_base);
263 irq_domain_remove(domain);
268 static int __init omap_init_irq_legacy(u32 base)
272 omap_irq_base = ioremap(base, SZ_4K);
273 if (WARN_ON(!omap_irq_base))
276 irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0);
278 pr_warn("Couldn't allocate IRQ numbers\n");
282 domain = irq_domain_add_legacy(NULL, omap_nr_irqs, irq_base, 0,
283 &irq_domain_simple_ops, NULL);
285 omap_irq_soft_reset();
287 for (j = 0; j < omap_nr_irqs; j += 32)
288 omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32);
293 static int __init omap_init_irq(u32 base, struct device_node *node)
296 return omap_init_irq_of(node);
298 return omap_init_irq_legacy(base);
301 static asmlinkage void __exception_irq_entry
302 omap_intc_handle_irq(struct pt_regs *regs)
309 for (i = 0; i < omap_nr_pending; i++) {
310 irqnr = intc_readl(INTC_PENDING_IRQ0 + (0x20 * i));
319 irqnr = intc_readl(INTC_SIR);
320 irqnr &= ACTIVEIRQ_MASK;
323 irqnr = irq_find_mapping(domain, irqnr);
324 handle_IRQ(irqnr, regs);
330 * If an irq is masked or deasserted while active, we will
331 * keep ending up here with no irq handled. So remove it from
332 * the INTC with an ack.
338 void __init omap2_init_irq(void)
342 omap_init_irq(OMAP24XX_IC_BASE, NULL);
343 set_handle_irq(omap_intc_handle_irq);
346 void __init omap3_init_irq(void)
350 omap_init_irq(OMAP34XX_IC_BASE, NULL);
351 set_handle_irq(omap_intc_handle_irq);
354 void __init ti81xx_init_irq(void)
358 omap_init_irq(OMAP34XX_IC_BASE, NULL);
359 set_handle_irq(omap_intc_handle_irq);
362 static int __init intc_of_init(struct device_node *node,
363 struct device_node *parent)
374 if (of_address_to_resource(node, 0, &res)) {
375 WARN(1, "unable to get intc registers\n");
379 if (of_device_is_compatible(node, "ti,am33xx-intc")) {
384 ret = omap_init_irq(-1, of_node_get(node));
388 set_handle_irq(omap_intc_handle_irq);
393 IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init);
394 IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init);
395 IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init);