4 * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
5 * Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com
7 * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
8 * Suman Anna <s-anna@ti.com>
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/mutex.h>
23 #include <linux/slab.h>
24 #include <linux/kfifo.h>
25 #include <linux/err.h>
26 #include <linux/module.h>
27 #include <linux/of_device.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/omap-mailbox.h>
31 #include <linux/mailbox_controller.h>
32 #include <linux/mailbox_client.h>
36 #define MAILBOX_REVISION 0x000
37 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
38 #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
39 #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
41 #define OMAP2_MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
42 #define OMAP2_MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
44 #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u))
45 #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u))
46 #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
48 #define MAILBOX_IRQSTATUS(type, u) (type ? OMAP4_MAILBOX_IRQSTATUS(u) : \
49 OMAP2_MAILBOX_IRQSTATUS(u))
50 #define MAILBOX_IRQENABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE(u) : \
51 OMAP2_MAILBOX_IRQENABLE(u))
52 #define MAILBOX_IRQDISABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE_CLR(u) \
53 : OMAP2_MAILBOX_IRQENABLE(u))
55 #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
56 #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
58 #define MBOX_REG_SIZE 0x120
60 #define OMAP4_MBOX_REG_SIZE 0x130
62 #define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
63 #define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
65 /* Interrupt register configuration types */
66 #define MBOX_INTR_CFG_TYPE1 0
67 #define MBOX_INTR_CFG_TYPE2 1
69 struct omap_mbox_fifo {
71 unsigned long fifo_stat;
72 unsigned long msg_stat;
73 unsigned long irqenable;
74 unsigned long irqstatus;
75 unsigned long irqdisable;
79 struct omap_mbox_queue {
82 struct work_struct work;
83 struct omap_mbox *mbox;
87 struct omap_mbox_device {
89 struct mutex cfg_lock;
90 void __iomem *mbox_base;
95 struct omap_mbox **mboxes;
96 struct mbox_controller controller;
97 struct list_head elem;
100 struct omap_mbox_fifo_info {
116 struct omap_mbox_queue *rxq;
118 struct omap_mbox_device *parent;
119 struct omap_mbox_fifo tx_fifo;
120 struct omap_mbox_fifo rx_fifo;
121 u32 ctx[OMAP4_MBOX_NR_REGS];
123 struct mbox_chan *chan;
127 /* global variables for the mailbox devices */
128 static DEFINE_MUTEX(omap_mbox_devices_lock);
129 static LIST_HEAD(omap_mbox_devices);
131 static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE;
132 module_param(mbox_kfifo_size, uint, S_IRUGO);
133 MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)");
135 static struct omap_mbox *mbox_chan_to_omap_mbox(struct mbox_chan *chan)
137 if (!chan || !chan->con_priv)
140 return (struct omap_mbox *)chan->con_priv;
144 unsigned int mbox_read_reg(struct omap_mbox_device *mdev, size_t ofs)
146 return __raw_readl(mdev->mbox_base + ofs);
150 void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs)
152 __raw_writel(val, mdev->mbox_base + ofs);
155 /* Mailbox FIFO handle functions */
156 static mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
158 struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
160 return (mbox_msg_t)mbox_read_reg(mbox->parent, fifo->msg);
163 static void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
165 struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
167 mbox_write_reg(mbox->parent, msg, fifo->msg);
170 static int mbox_fifo_empty(struct omap_mbox *mbox)
172 struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
174 return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0);
177 static int mbox_fifo_full(struct omap_mbox *mbox)
179 struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
181 return mbox_read_reg(mbox->parent, fifo->fifo_stat);
184 /* Mailbox IRQ handle functions */
185 static void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
187 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
188 &mbox->tx_fifo : &mbox->rx_fifo;
189 u32 bit = fifo->intr_bit;
190 u32 irqstatus = fifo->irqstatus;
192 mbox_write_reg(mbox->parent, bit, irqstatus);
194 /* Flush posted write for irq status to avoid spurious interrupts */
195 mbox_read_reg(mbox->parent, irqstatus);
198 static int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
200 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
201 &mbox->tx_fifo : &mbox->rx_fifo;
202 u32 bit = fifo->intr_bit;
203 u32 irqenable = fifo->irqenable;
204 u32 irqstatus = fifo->irqstatus;
206 u32 enable = mbox_read_reg(mbox->parent, irqenable);
207 u32 status = mbox_read_reg(mbox->parent, irqstatus);
209 return (int)(enable & status & bit);
212 void omap_mbox_save_ctx(struct mbox_chan *chan)
216 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
222 nr_regs = OMAP4_MBOX_NR_REGS;
224 nr_regs = MBOX_NR_REGS;
225 for (i = 0; i < nr_regs; i++) {
226 mbox->ctx[i] = mbox_read_reg(mbox->parent, i * sizeof(u32));
228 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
232 EXPORT_SYMBOL(omap_mbox_save_ctx);
234 void omap_mbox_restore_ctx(struct mbox_chan *chan)
238 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
244 nr_regs = OMAP4_MBOX_NR_REGS;
246 nr_regs = MBOX_NR_REGS;
247 for (i = 0; i < nr_regs; i++) {
248 mbox_write_reg(mbox->parent, mbox->ctx[i], i * sizeof(u32));
249 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
253 EXPORT_SYMBOL(omap_mbox_restore_ctx);
255 static void _omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
258 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
259 &mbox->tx_fifo : &mbox->rx_fifo;
260 u32 bit = fifo->intr_bit;
261 u32 irqenable = fifo->irqenable;
263 l = mbox_read_reg(mbox->parent, irqenable);
265 mbox_write_reg(mbox->parent, l, irqenable);
268 static void _omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
270 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
271 &mbox->tx_fifo : &mbox->rx_fifo;
272 u32 bit = fifo->intr_bit;
273 u32 irqdisable = fifo->irqdisable;
276 * Read and update the interrupt configuration register for pre-OMAP4.
277 * OMAP4 and later SoCs have a dedicated interrupt disabling register.
279 if (!mbox->intr_type)
280 bit = mbox_read_reg(mbox->parent, irqdisable) & ~bit;
282 mbox_write_reg(mbox->parent, bit, irqdisable);
285 void omap_mbox_enable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq)
287 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
292 _omap_mbox_enable_irq(mbox, irq);
294 EXPORT_SYMBOL(omap_mbox_enable_irq);
296 void omap_mbox_disable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq)
298 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
303 _omap_mbox_disable_irq(mbox, irq);
305 EXPORT_SYMBOL(omap_mbox_disable_irq);
308 * Message receiver(workqueue)
310 static void mbox_rx_work(struct work_struct *work)
312 struct omap_mbox_queue *mq =
313 container_of(work, struct omap_mbox_queue, work);
317 while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
318 len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
319 WARN_ON(len != sizeof(msg));
321 mbox_chan_received_data(mq->mbox->chan, (void *)msg);
322 spin_lock_irq(&mq->lock);
325 _omap_mbox_enable_irq(mq->mbox, IRQ_RX);
327 spin_unlock_irq(&mq->lock);
332 * Mailbox interrupt handler
334 static void __mbox_tx_interrupt(struct omap_mbox *mbox)
336 _omap_mbox_disable_irq(mbox, IRQ_TX);
337 ack_mbox_irq(mbox, IRQ_TX);
338 mbox_chan_txdone(mbox->chan, 0);
341 static void __mbox_rx_interrupt(struct omap_mbox *mbox)
343 struct omap_mbox_queue *mq = mbox->rxq;
347 while (!mbox_fifo_empty(mbox)) {
348 if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
349 _omap_mbox_disable_irq(mbox, IRQ_RX);
354 msg = mbox_fifo_read(mbox);
356 len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
357 WARN_ON(len != sizeof(msg));
360 /* no more messages in the fifo. clear IRQ source. */
361 ack_mbox_irq(mbox, IRQ_RX);
363 schedule_work(&mbox->rxq->work);
366 static irqreturn_t mbox_interrupt(int irq, void *p)
368 struct omap_mbox *mbox = p;
370 if (is_mbox_irq(mbox, IRQ_TX))
371 __mbox_tx_interrupt(mbox);
373 if (is_mbox_irq(mbox, IRQ_RX))
374 __mbox_rx_interrupt(mbox);
379 static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
380 void (*work)(struct work_struct *))
382 struct omap_mbox_queue *mq;
387 mq = kzalloc(sizeof(*mq), GFP_KERNEL);
391 spin_lock_init(&mq->lock);
393 if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL))
396 INIT_WORK(&mq->work, work);
404 static void mbox_queue_free(struct omap_mbox_queue *q)
406 kfifo_free(&q->fifo);
410 static int omap_mbox_startup(struct omap_mbox *mbox)
413 struct omap_mbox_queue *mq;
415 mq = mbox_queue_alloc(mbox, mbox_rx_work);
421 ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
424 pr_err("failed to register mailbox interrupt:%d\n", ret);
425 goto fail_request_irq;
428 if (mbox->send_no_irq)
429 mbox->chan->txdone_method = TXDONE_BY_ACK;
431 _omap_mbox_enable_irq(mbox, IRQ_RX);
436 mbox_queue_free(mbox->rxq);
440 static void omap_mbox_fini(struct omap_mbox *mbox)
442 _omap_mbox_disable_irq(mbox, IRQ_RX);
443 free_irq(mbox->irq, mbox);
444 flush_work(&mbox->rxq->work);
445 mbox_queue_free(mbox->rxq);
448 static struct omap_mbox *omap_mbox_device_find(struct omap_mbox_device *mdev,
449 const char *mbox_name)
451 struct omap_mbox *_mbox, *mbox = NULL;
452 struct omap_mbox **mboxes = mdev->mboxes;
458 for (i = 0; (_mbox = mboxes[i]); i++) {
459 if (!strcmp(_mbox->name, mbox_name)) {
467 struct mbox_chan *omap_mbox_request_channel(struct mbox_client *cl,
468 const char *chan_name)
470 struct device *dev = cl->dev;
471 struct omap_mbox *mbox = NULL;
472 struct omap_mbox_device *mdev;
473 struct mbox_chan *chan;
478 return ERR_PTR(-ENODEV);
481 pr_err("%s: please use mbox_request_channel(), this API is supported only for OMAP non-DT usage\n",
483 return ERR_PTR(-ENODEV);
486 mutex_lock(&omap_mbox_devices_lock);
487 list_for_each_entry(mdev, &omap_mbox_devices, elem) {
488 mbox = omap_mbox_device_find(mdev, chan_name);
492 mutex_unlock(&omap_mbox_devices_lock);
494 if (!mbox || !mbox->chan)
495 return ERR_PTR(-ENOENT);
498 spin_lock_irqsave(&chan->lock, flags);
501 chan->active_req = NULL;
503 init_completion(&chan->tx_complete);
504 spin_unlock_irqrestore(&chan->lock, flags);
506 ret = chan->mbox->ops->startup(chan);
508 pr_err("Unable to startup the chan (%d)\n", ret);
509 mbox_free_channel(chan);
515 EXPORT_SYMBOL(omap_mbox_request_channel);
517 static struct class omap_mbox_class = { .name = "mbox", };
519 static int omap_mbox_register(struct omap_mbox_device *mdev)
523 struct omap_mbox **mboxes;
525 if (!mdev || !mdev->mboxes)
528 mboxes = mdev->mboxes;
529 for (i = 0; mboxes[i]; i++) {
530 struct omap_mbox *mbox = mboxes[i];
532 mbox->dev = device_create(&omap_mbox_class, mdev->dev,
533 0, mbox, "%s", mbox->name);
534 if (IS_ERR(mbox->dev)) {
535 ret = PTR_ERR(mbox->dev);
540 mutex_lock(&omap_mbox_devices_lock);
541 list_add(&mdev->elem, &omap_mbox_devices);
542 mutex_unlock(&omap_mbox_devices_lock);
544 ret = mbox_controller_register(&mdev->controller);
549 device_unregister(mboxes[i]->dev);
554 static int omap_mbox_unregister(struct omap_mbox_device *mdev)
557 struct omap_mbox **mboxes;
559 if (!mdev || !mdev->mboxes)
562 mutex_lock(&omap_mbox_devices_lock);
563 list_del(&mdev->elem);
564 mutex_unlock(&omap_mbox_devices_lock);
566 mbox_controller_unregister(&mdev->controller);
568 mboxes = mdev->mboxes;
569 for (i = 0; mboxes[i]; i++)
570 device_unregister(mboxes[i]->dev);
574 static int omap_mbox_chan_startup(struct mbox_chan *chan)
576 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
577 struct omap_mbox_device *mdev = mbox->parent;
580 mutex_lock(&mdev->cfg_lock);
581 pm_runtime_get_sync(mdev->dev);
582 ret = omap_mbox_startup(mbox);
584 pm_runtime_put_sync(mdev->dev);
585 mutex_unlock(&mdev->cfg_lock);
589 static void omap_mbox_chan_shutdown(struct mbox_chan *chan)
591 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
592 struct omap_mbox_device *mdev = mbox->parent;
594 mutex_lock(&mdev->cfg_lock);
595 omap_mbox_fini(mbox);
596 pm_runtime_put_sync(mdev->dev);
597 mutex_unlock(&mdev->cfg_lock);
600 static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, void *data)
604 if (!mbox_fifo_full(mbox)) {
605 _omap_mbox_enable_irq(mbox, IRQ_RX);
606 mbox_fifo_write(mbox, (mbox_msg_t)data);
608 _omap_mbox_disable_irq(mbox, IRQ_RX);
610 /* we must read and ack the interrupt directly from here */
611 mbox_fifo_read(mbox);
612 ack_mbox_irq(mbox, IRQ_RX);
618 static int omap_mbox_chan_send(struct omap_mbox *mbox, void *data)
622 if (!mbox_fifo_full(mbox)) {
623 mbox_fifo_write(mbox, (mbox_msg_t)data);
627 /* always enable the interrupt */
628 _omap_mbox_enable_irq(mbox, IRQ_TX);
632 static int omap_mbox_chan_send_data(struct mbox_chan *chan, void *data)
634 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
640 if (mbox->send_no_irq)
641 ret = omap_mbox_chan_send_noirq(mbox, data);
643 ret = omap_mbox_chan_send(mbox, data);
648 static const struct mbox_chan_ops omap_mbox_chan_ops = {
649 .startup = omap_mbox_chan_startup,
650 .send_data = omap_mbox_chan_send_data,
651 .shutdown = omap_mbox_chan_shutdown,
654 #ifdef CONFIG_PM_SLEEP
655 static int omap_mbox_suspend(struct device *dev)
657 struct omap_mbox_device *mdev = dev_get_drvdata(dev);
660 if (pm_runtime_status_suspended(dev))
663 for (usr = 0; usr < mdev->num_users; usr++) {
664 reg = MAILBOX_IRQENABLE(mdev->intr_type, usr);
665 mdev->irq_ctx[usr] = mbox_read_reg(mdev, reg);
671 static int omap_mbox_resume(struct device *dev)
673 struct omap_mbox_device *mdev = dev_get_drvdata(dev);
676 if (pm_runtime_status_suspended(dev))
679 for (usr = 0; usr < mdev->num_users; usr++) {
680 reg = MAILBOX_IRQENABLE(mdev->intr_type, usr);
681 mbox_write_reg(mdev, mdev->irq_ctx[usr], reg);
688 static const struct dev_pm_ops omap_mbox_pm_ops = {
689 SET_SYSTEM_SLEEP_PM_OPS(omap_mbox_suspend, omap_mbox_resume)
692 static const struct of_device_id omap_mailbox_of_match[] = {
694 .compatible = "ti,omap2-mailbox",
695 .data = (void *)MBOX_INTR_CFG_TYPE1,
698 .compatible = "ti,omap3-mailbox",
699 .data = (void *)MBOX_INTR_CFG_TYPE1,
702 .compatible = "ti,omap4-mailbox",
703 .data = (void *)MBOX_INTR_CFG_TYPE2,
709 MODULE_DEVICE_TABLE(of, omap_mailbox_of_match);
711 static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller *controller,
712 const struct of_phandle_args *sp)
714 phandle phandle = sp->args[0];
715 struct device_node *node;
716 struct omap_mbox_device *mdev;
717 struct omap_mbox *mbox;
719 mdev = container_of(controller, struct omap_mbox_device, controller);
721 return ERR_PTR(-EINVAL);
723 node = of_find_node_by_phandle(phandle);
725 pr_err("%s: could not find node phandle 0x%x\n",
727 return ERR_PTR(-ENODEV);
730 mbox = omap_mbox_device_find(mdev, node->name);
732 return mbox ? mbox->chan : ERR_PTR(-ENOENT);
735 static int omap_mbox_probe(struct platform_device *pdev)
737 struct resource *mem;
739 struct mbox_chan *chnls;
740 struct omap_mbox **list, *mbox, *mboxblk;
741 struct omap_mbox_fifo_info *finfo, *finfoblk;
742 struct omap_mbox_device *mdev;
743 struct omap_mbox_fifo *fifo;
744 struct device_node *node = pdev->dev.of_node;
745 struct device_node *child;
746 const struct of_device_id *match;
747 u32 intr_type, info_count;
748 u32 num_users, num_fifos;
754 pr_err("%s: only DT-based devices are supported\n", __func__);
758 match = of_match_device(omap_mailbox_of_match, &pdev->dev);
761 intr_type = (u32)match->data;
763 if (of_property_read_u32(node, "ti,mbox-num-users", &num_users))
766 if (of_property_read_u32(node, "ti,mbox-num-fifos", &num_fifos))
769 info_count = of_get_available_child_count(node);
771 dev_err(&pdev->dev, "no available mbox devices found\n");
775 finfoblk = devm_kzalloc(&pdev->dev, info_count * sizeof(*finfoblk),
782 for (i = 0; i < info_count; i++, finfo++) {
783 child = of_get_next_available_child(node, child);
784 ret = of_property_read_u32_array(child, "ti,mbox-tx", tmp,
788 finfo->tx_id = tmp[0];
789 finfo->tx_irq = tmp[1];
790 finfo->tx_usr = tmp[2];
792 ret = of_property_read_u32_array(child, "ti,mbox-rx", tmp,
796 finfo->rx_id = tmp[0];
797 finfo->rx_irq = tmp[1];
798 finfo->rx_usr = tmp[2];
800 finfo->name = child->name;
802 if (of_find_property(child, "ti,mbox-send-noirq", NULL))
803 finfo->send_no_irq = true;
805 if (finfo->tx_id >= num_fifos || finfo->rx_id >= num_fifos ||
806 finfo->tx_usr >= num_users || finfo->rx_usr >= num_users)
810 mdev = devm_kzalloc(&pdev->dev, sizeof(*mdev), GFP_KERNEL);
814 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
815 mdev->mbox_base = devm_ioremap_resource(&pdev->dev, mem);
816 if (IS_ERR(mdev->mbox_base))
817 return PTR_ERR(mdev->mbox_base);
819 mdev->irq_ctx = devm_kzalloc(&pdev->dev, num_users * sizeof(u32),
824 /* allocate one extra for marking end of list */
825 list = devm_kzalloc(&pdev->dev, (info_count + 1) * sizeof(*list),
830 chnls = devm_kzalloc(&pdev->dev, (info_count + 1) * sizeof(*chnls),
835 mboxblk = devm_kzalloc(&pdev->dev, info_count * sizeof(*mbox),
842 for (i = 0; i < info_count; i++, finfo++) {
843 fifo = &mbox->tx_fifo;
844 fifo->msg = MAILBOX_MESSAGE(finfo->tx_id);
845 fifo->fifo_stat = MAILBOX_FIFOSTATUS(finfo->tx_id);
846 fifo->intr_bit = MAILBOX_IRQ_NOTFULL(finfo->tx_id);
847 fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->tx_usr);
848 fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->tx_usr);
849 fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->tx_usr);
851 fifo = &mbox->rx_fifo;
852 fifo->msg = MAILBOX_MESSAGE(finfo->rx_id);
853 fifo->msg_stat = MAILBOX_MSGSTATUS(finfo->rx_id);
854 fifo->intr_bit = MAILBOX_IRQ_NEWMSG(finfo->rx_id);
855 fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->rx_usr);
856 fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->rx_usr);
857 fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->rx_usr);
859 mbox->send_no_irq = finfo->send_no_irq;
860 mbox->intr_type = intr_type;
863 mbox->name = finfo->name;
864 mbox->irq = platform_get_irq(pdev, finfo->tx_irq);
867 mbox->chan = &chnls[i];
868 chnls[i].con_priv = mbox;
872 mutex_init(&mdev->cfg_lock);
873 mdev->dev = &pdev->dev;
874 mdev->num_users = num_users;
875 mdev->num_fifos = num_fifos;
876 mdev->intr_type = intr_type;
879 /* OMAP does not have a Tx-Done IRQ, but rather a Tx-Ready IRQ */
880 mdev->controller.txdone_irq = true;
881 mdev->controller.dev = mdev->dev;
882 mdev->controller.ops = &omap_mbox_chan_ops;
883 mdev->controller.chans = chnls;
884 mdev->controller.num_chans = info_count;
885 mdev->controller.of_xlate = omap_mbox_of_xlate;
886 ret = omap_mbox_register(mdev);
890 platform_set_drvdata(pdev, mdev);
891 pm_runtime_enable(mdev->dev);
893 ret = pm_runtime_get_sync(mdev->dev);
895 pm_runtime_put_noidle(mdev->dev);
900 * just print the raw revision register, the format is not
901 * uniform across all SoCs
903 l = mbox_read_reg(mdev, MAILBOX_REVISION);
904 dev_info(mdev->dev, "omap mailbox rev 0x%x\n", l);
906 ret = pm_runtime_put_sync(mdev->dev);
910 devm_kfree(&pdev->dev, finfoblk);
914 pm_runtime_disable(mdev->dev);
915 omap_mbox_unregister(mdev);
919 static int omap_mbox_remove(struct platform_device *pdev)
921 struct omap_mbox_device *mdev = platform_get_drvdata(pdev);
923 pm_runtime_disable(mdev->dev);
924 omap_mbox_unregister(mdev);
929 static struct platform_driver omap_mbox_driver = {
930 .probe = omap_mbox_probe,
931 .remove = omap_mbox_remove,
933 .name = "omap-mailbox",
934 .pm = &omap_mbox_pm_ops,
935 .of_match_table = of_match_ptr(omap_mailbox_of_match),
939 static int __init omap_mbox_init(void)
943 err = class_register(&omap_mbox_class);
947 /* kfifo size sanity check: alignment and minimal size */
948 mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
949 mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size,
952 return platform_driver_register(&omap_mbox_driver);
954 subsys_initcall(omap_mbox_init);
956 static void __exit omap_mbox_exit(void)
958 platform_driver_unregister(&omap_mbox_driver);
959 class_unregister(&omap_mbox_class);
961 module_exit(omap_mbox_exit);
963 MODULE_LICENSE("GPL v2");
964 MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
965 MODULE_AUTHOR("Toshihiro Kobayashi");
966 MODULE_AUTHOR("Hiroshi DOYU");